Class / Patent application number | Description | Number of patent applications / Date published |
438654000 | Having adhesion promoting layer | 28 |
20080206987 | PROCESS FOR TUNGSTEN NITRIDE DEPOSITION BY A TEMPERATURE CONTROLLED LID ASSEMBLY - Embodiments of the invention provide processes for vapor depositing tungsten-containing materials, such as metallic tungsten and tungsten nitride. In one embodiment, a method for forming a tungsten-containing material is provided which includes positioning a substrate within a processing chamber containing a lid plate, heating the lid plate to a temperature within a range from about 120° C. to about 180° C., exposing the substrate to a reducing gas during a pre-nucleation soak process, and depositing a first tungsten nucleation layer on the substrate during a first atomic layer deposition process within the processing chamber. The method further provides depositing a tungsten nitride layer on the first tungsten nucleation layer during a vapor deposition process, depositing a second tungsten nucleation layer on the tungsten nitride layer during a second atomic layer deposition process within the processing chamber, and exposing the substrate to another reducing gas during a post-nucleation soak process. | 08-28-2008 |
20080233739 | METHOD FOR FABRICATING CONDUCTIVE LAYER - A method for fabricating a conductive layer is provided. First, a substrate is provided and a patterned adhesion layer is formed on the substrate. Next, a chemical plating process is performed to form a first metal layer on the patterned adhesion layer by placing the substrate in an electroplating solution and the electroplating solution is shocked. Thereafter, a second metal layer is formed on the first metal layer by performing a plating process. | 09-25-2008 |
20080242082 | METHOD FOR FABRICATING BACK END OF THE LINE STRUCTURES WITH LINER AND SEED MATERIALS - A sputter-etching method employed to achieve a thinned down noble metal liner layer deposited on the surface or field of an intermediate back end of the line (BEOL) interconnect structure. The noble metal liner layer is substantially thinned down to a point where the effect of the noble metal has no significant effect in the chemical-mechanical polishing (CMP) process. The noble metal liner layer may be completely removed by sputter etching to facilitate effective planarization by chemical-mechanical polishing to take place. | 10-02-2008 |
20090004849 | METHOD FOR FABRICATING AN INTER DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE - In a method for fabricating an inter dielectric layer in semiconductor device, a primary liner HDP oxide layer is formed by supplying a high density plasma (HDP) deposition source to a bit line stack formed on a semiconductor substrate. A high density plasma (HDP) deposition source is supplied to the bit line stack to form a primary liner HDP oxide layer. The primary liner HDP oxide layer is etched to a predetermined depth to form a secondary liner HDP oxide layer. An interlayer dielectric layer is formed to fill the areas defined by the bit line stack where the secondary liner HDP oxide layer is located. | 01-01-2009 |
20090149021 | SPRAY DISPENSING METHOD FOR APPLYING LIQUID METAL - Embodiments of a method for applying a thermal-interface material are described. During this method, a first surface of a heat-removal device and a second surface of a semiconductor die are prepared. Next, a region on a given surface, which is at least one of the first surface and the second surface, is defined. Then, the thermal-interface material is applied to at least the region, where the thermal-interface material includes a material that is a liquid metal over a range of operating temperatures of the semiconductor die. | 06-11-2009 |
20090155998 | Atomic layer deposited tantalum containing adhesion layer - Apparatus and methods of fabricating an atomic layer deposited tantalum containing adhesion layer within at least one dielectric material in the formation of a metal, wherein the atomic layer deposition tantalum containing adhesion layer is sufficiently thin to minimize contact resistance and maximize the total cross-sectional area of metal, including but not limited to tungsten, within the contact. | 06-18-2009 |
20090176367 | OPTIMIZED SiCN CAPPING LAYER - A back-end-of-line (BEOL) interconnect structure and a method of forming an interconnect structure. The interconnect structure comprises a conductor, such as copper, embedded in a dielectric layer, and a low-k dielectric capping layer, which acts as a diffusion barrier, on the conductor. A method of forming the BEOL interconnect structure is disclosed, where the capping layer is deposited using plasma-enhanced chemical vapor deposition (PECVD) and is comprised of Si, C, H, and N. The interconnect structure provides improved oxygen diffusion resistance and improved barrier qualities allowing for a reduction in film thickness. | 07-09-2009 |
20100178762 | MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE SUITABLE FOR FORMING WIRINGS BY DAMASCENE METHOD AND SEMICONDUCTOR DEVICE - An interlayer insulating film having a concave portion is formed on a semiconductor substrate. A tight adhesion film is formed on the inner surface of the concave portion and the upper surface of the insulating film. The surface of the adhesion layer is covered with an auxiliary film made of Cu alloy containing a first metal element. A conductive member containing a second metal element other than the first metal element is embedded in the concave portion, and deposited on the auxiliary film. Heat treatment is performed to make atoms of the first metal element in the auxiliary film segregate on the inner surface of the concave portion. The adhesion layer contains an element for enhancing tight adhesion of the auxiliary film more than if the auxiliary film is deposited directly on a surface of the interlayer insulating film. During the period until the barrier layer having also the function of enhancing tight adhesion, it becomes possible to retain sufficient tight adhesion of a wiring member and prevent peel-off of the wiring member. | 07-15-2010 |
20100323518 | METHOD FOR PRODUCING A NANOPOROUS LAYER - The invention relates to a method for producing a nanoporous layer, wherein a layer made of gold and silver is deposited onto a substrate, particularly in an electrochemical or galvanic fashion, wherein the composition of said layer lies between 20% and 40% gold and 80% to 60% silver. The silver is subsequently selectively removed in order to obtain a nanoporous gold layer. | 12-23-2010 |
20110059608 | METHOD FOR IMPROVING ADHESION OF LOW RESISTIVITY TUNGSTEN/TUNGSTEN NITRIDE LAYERS - Methods of improving the adhesion of low resistivity tungsten/tungsten nitride layers are provided. Low resistivity tungsten/tungsten nitride layers with good adhesion are formed by treating a tungsten or tungsten nitride layer before depositing low resistivity tungsten. Treatments include a plasma treatment and a temperature treatment. According to various embodiments, the treatment methods involve different gaseous atmospheres and plasma conditions. | 03-10-2011 |
20110223763 | METHODS FOR GROWING LOW-RESISTIVITY TUNGSTEN FOR HIGH ASPECT RATIO AND SMALL FEATURES - The present invention addresses this need by providing methods for depositing low resistivity tungsten films in small features and features having high aspect ratios. The methods involve depositing very thin tungsten nucleation layers by pulsed nucleation layer (PNL) processes and then using chemical vapor deposition (CVD) to deposit a tungsten layer to fill the feature. Depositing the tungsten nucleation layer involves exposing the substrate to alternating pulses of a boron-containing reducing agent and a tungsten-containing precursor without using any hydrogen gas, e.g., as a carrier or background gas. Using this process, a conformal tungsten nucleation layer can be deposited to a thickness as small as about 10 Angstroms. The feature may then be wholly or partially filled with tungsten by a hydrogen reduction chemical vapor deposition process. Resistivities of about 14 μΩ-cm for a 500 Angstrom film may be obtained. | 09-15-2011 |
20110237073 | METHOD FOR FORMING A THROUGH SILICON VIA (TSV) - A method of forming a through silicon via includes forming a via opening in a substrate using a hard mask, wherein a polymer is formed in the via opening. A first wet clean removes a first portion of the polymer and forms a first carbon containing oxide along portions of the sidewalls. A first ash process modifies the first carbon containing oxide and removes a second portion of the polymer. A first wet etch removes the modified first carbon containing oxide and a third portion of the polymer. A second ash process forms a second carbon containing oxide along at least a portion of the sidewalls. A second wet etch process removes the second carbon containing oxide and a fourth portions of the polymer. A third ash process forms a third carbon containing oxide along portions of the sidewalls and removes any remaining portions of the polymer. | 09-29-2011 |
20120064714 | CONTACT FORMATION METHOD INCORPORATING A PREVENTATIVE ETCH STEP FOR REDUCING INTERLAYER DIELECTRIC MATERIAL FLAKE DEFECTS - Disclosed are embodiments of a contact formation technique that incorporates a preventative etch step to reduce interlayer dielectric material flaking (e.g., borophosphosilicate glass (BPSG) flaking) and, thereby to reduce surface defects. Specifically, contact openings, which extend through a dielectric layer to semiconductor devices in and/or on a center portion of a substrate, can be filled with a conductor layer deposited by chemical vapor deposition (CVD). Chemical mechanical polishing (CMP) of the conductor layer can be performed to complete the contact structures. However, before the CMP process is performed (e.g., either before the contact openings are ever formed or before the contact openings are filled), a preventative etch process can be performed to remove any dielectric material from above the edge portion of the substrate. Removing the dielectric material from above the edge portion of the substrate prior to CMP reduces the occurrence of surface defects caused by dielectric material flaking. | 03-15-2012 |
20120184098 | ELECTROCHEMICAL ETCHING OF SEMICONDUCTORS - Semiconductors are electrochemically etched in solutions containing sources of bifluoride and nickel ions. The electrochemical etching may form pores in the surface of the semiconductor in the nanometer range. The etched semiconductor is then nickel plated. | 07-19-2012 |
20120220122 | NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a nitride semiconductor device and a manufacturing method thereof. The nitride semiconductor device includes an insulating layer and a metal layer formed on a nitride semiconductor layer. The insulating layer makes contact with the nitride semiconductor layer. A separation preventing layer is formed between the insulating layer and the metal layer so as to make contact with each of these layers. The separation preventing layer has, as a main component, at least one kind of oxide of a metal selected from the group consisting of tungsten, molybdenum, chromium, titanium, nickel, hafnium, zinc, indium and yttrium. | 08-30-2012 |
20120258591 | N-Type Contact Electrode Comprising a Group III Nitride Semiconductor, and Method Forming Same - A method for forming an n-type contact electrode comprising an n-type nitride semiconductor such as Al | 10-11-2012 |
20120276738 | METHOD FOR FORMING THROUGH SILICON VIA STRUCTURE - A method for forming a TSV structure includes providing a silicon substrate with an interlayer dielectric layer formed thereon, forming a hard mask structure including a first hard mask layer including a metal element on the interlayer dielectric layer and a second hard mask layer on the first hard mask layer; forming an opening through the hard mask structure and the interlayer dielectric layer, the opening has a bottom and sidewalls in the silicon substrate. The method further includes depositing an insulating material on the hard mask structure and on the bottom and the sidewalls of the opening, subsequently removing the insulating material and the second hard mask layer until the first hard mask layer is exposed, and filling a conductive material into the opening. The method also includes removing the conductive material and the first hard mask layer by a CMP process until the interlayer dielectric layer is exposed. | 11-01-2012 |
20130029486 | METHOD OF MANUFACTURING AN ELECTRONIC DEVICE HAVING A PLASTIC SUBSTRATE AND CORRESPONDING CARRIER - A method of manufacturing an electronic device on a plastic substrate includes: providing a carrier as a rigid support for the electronic device; providing a metallic layer on the carrier; forming the plastic substrate on the metallic layer, the metallic layer guaranteeing a temporary bonding of the plastic substrate to the carrier; forming the electronic device on the plastic substrate; and releasing the carrier from the plastic substrate. Releasing the carrier comprises immersing the electronic device bonded to the carrier in a oxygenated water solution that breaks the bonds between the plastic substrate and the metallic layer. | 01-31-2013 |
20130288476 | ELECTROCHEMICAL ETCHING OF SEMICONDUCTORS - Semiconductors are electrochemically etched in solutions containing sources of bifluoride and nickel ions. The electrochemical etching may form pores in the surface of the semiconductor in the nanometer range. The etched semiconductor is then nickel plated. | 10-31-2013 |
20140377947 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - When a recess is formed in a SiCOH film, C is removed from the film to form a damage layer. If the damage layer is removed by hydrofluoric acid or the like, the surface becomes hydrophobic. By supplying a boron compound gas, a silicon compound gas or a gas containing trimethyl aluminum to the SiCOH film, B, Si or Al is adsorbed on the SiCOH film. These atoms bond with Ru and a Ru film is easily formed on the SiCOH film. The Ru film is formed using, for example, Ru | 12-25-2014 |
20150140809 | INTEGRATED CIRCUIT AND INTERCONNECT, AND METHOD OF FABRICATING SAME - The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect. | 05-21-2015 |
20150380302 | SELECTIVE FORMATION OF DIELECTRIC BARRIERS FOR METAL INTERCONNECTS IN SEMICONDUCTOR DEVICES - A dielectric diffusion barrier is deposited on a substrate that has a via and an overlying trench etched into an exposed layer of inter-layer dielectric, wherein there is exposed metal from the underlying interconnect at the bottom of the via. In order to provide a conductive path from the underlying metallization layer to the metallization layer that is being formed over it, the dielectric diffusion barrier is formed selectively on the inter-layer dielectric and not on the exposed metal at the bottom of the via. In one example a dielectric SiNC diffusion barrier layer is selectively deposited on the inter-layer dielectric using a remote plasma deposition and a precursor that contains both silicon and nitrogen atoms. Generally, a variety of dielectric diffusion barrier materials with dielectric constants of between about 3.0-20.0 can be selectively formed on inter-layer dielectric. | 12-31-2015 |
20160020142 | CONDUCTIVE STRUCTURE AND METHOD OF FORMING THE SAME - Conductive structures and method of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive structure includes providing a substrate having a recess formed therein, the recess lined with a first seed layer and partially filled with a first conductive material; removing a portion of the first seed layer free from the first conductive material to form an exposed surface of the recess; lining the exposed surface of the recess with a second seed layer; and filling the recess with a second conductive material, the second conductive material covering the first conductive material and the second seed layer. | 01-21-2016 |
20160104679 | METHODS OF FORMING SUBSTRATE MICROVIAS WITH ANCHOR STRUCTURES - Methods of forming anchor structures in package substrate microvias are described. Those methods and structures may include forming a titanium layer in an opening of a package substrate using a first deposition process, wherein the opening comprises an undercut region, and wherein the first conductive layer does not substantially form in an anchor region of the undercut region. The titanium layer may then be re-sputtered using a second deposition process, wherein the titanium layer is formed in the anchor region. | 04-14-2016 |
20160133471 | ELECTROLESS PLATING PROCESS AND TIN-SILVER PLATING SOLUTION THEREIN - An electroless plating process includes providing a semiconductor substrate which has a substrate and a copper pillar disposed on the substrate; providing a tin-silver plating solution includes 0.1-50 wt % tin and 1×10 | 05-12-2016 |
20160133508 | AIR GAP STRUCTURE WITH BILAYER SELECTIVE CAP - A semiconductor substrate including one or more conductors is provided. A first layer and a second layer are deposited on the top surface of the conductors. A dielectric cap layer is formed over the semiconductor substrate and air gaps are etched into the dielectric layer. The result is a bilayer cap air gap structure with effective electrical performance. | 05-12-2016 |
20160141257 | THROUGH-PACKAGE-VIA (TPV) STRUCTURES ON INORGANIC INTERPOSER AND METHODS FOR FABRICATING SAME - Disclosed herein are, for instance, methods for producing through package vias in a glass interposer. For instance, disclosed herein is a method for producing through package vias in a glass interposer comprising laminating a polymer on at least a portion of a top surface of a glass interposer, removing at least a portion of the polymer and the glass interposer to form a through via, filling at least a portion of the through via with a metal conductor to form a metallization layer, and selectively removing a portion of the metallization layer to form a metalized through package via. Other methods are also disclosed, along with through-package-via structures in glass interposers produced therefrom. | 05-19-2016 |
20160141265 | BUMPLESS BUILD-UP LAYER PACKAGE INCLUDING A RELEASE LAYER - An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a release layer having a lower release layer surface, an upper release layer surface parallel to the lower release layer surface, and at least one release layer side, the release layer coupled with the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the release layer side and lower release layer surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface. | 05-19-2016 |