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At least one layer forms a diffusion barrier

Subclass of:

438 - Semiconductor device manufacturing: process

438584000 - COATING WITH ELECTRICALLY OR THERMALLY CONDUCTIVE MATERIAL

438597000 - To form ohmic contact to semiconductive material

438652000 - Plural layered electrode or conductor

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DocumentTitleDate
20090280640DEPOSITION AND DENSIFICATION PROCESS FOR TITANIUM NITRIDE BARRIER LAYERS - In one embodiment, a method for forming a titanium nitride barrier material on a substrate is provided which includes depositing a titanium nitride layer on the substrate by a metal-organic chemical vapor deposition (MOCVD) process, and thereafter, densifying the titanium nitride layer by exposing the substrate to a plasma process. In one example, the MOCVD process and the densifying plasma process is repeated to form a barrier stack by depositing a second titanium nitride layer on the first titanium nitride layer. In another example, a third titanium nitride layer is deposited on the second titanium nitride layer. Subsequently, the method provides depositing a conductive material on the substrate and exposing the substrate to a annealing process. In one example, each titanium nitride layer may have a thickness of about 15 Å and the titanium nitride barrier stack may have a copper diffusion potential of less than about 5×1011-12-2009
20100022087SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes an insulating film formed above an upper surface of a semiconductor substrate and including a contact hole, the contact hole including an upper portion and a lower portion located on the upper portion via a boundary as a first lower end of the upper portion and a first upper end of the lower portion, the boundary including a second inner width same as the first inner width, the lower portion including a second lower end having a third inner width narrower than the second inner width, a first conductive plug made from polycrystalline silicon and formed in the lower portion of the contact hole so that the exposed upper surface of the substrate is in contact with the first conductive plug, and a second conductive plug formed on the first conductive plug and made from a conductive material different from the polycrystalline silicon.01-28-2010
20090209099Forming Diffusion Barriers by Annealing Copper Alloy Layers - A method of forming an interconnect structure of an integrated circuit includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; and forming a copper alloy seed layer in the opening. The copper alloy seed layer physically contacts the dielectric layer. The copper alloy seed layer includes copper and an alloying material. The method further includes filling a metallic material in the opening and over the copper alloy seed layer; performing a planarization to remove excess metallic material over the dielectric layer; and performing a thermal anneal to cause the alloying material in the copper alloy seed layer to be segregated from copper.08-20-2009
20090191705Semiconductor Contact Barrier - System and method for reducing contact resistance and improving barrier properties is provided. An embodiment comprises a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer.07-30-2009
20090191706METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, including forming a dielectric film above a substrate; forming a metal containing film above the dielectric film; forming at least one carbon containing film of a silicon carbon containing film containing silicon and carbon and a nitrogen carbon containing film containing nitrogen and carbon above the metal containing film; etching the carbon containing film selectively; etching the metal containing film selectively to transfer an opening of the carbon containing film formed by etching; and etching the dielectric film using the carbon containing film and the metal containing film as masks in a state in which a surface of the carbon containing film other than the opening is exposed.07-30-2009
20100075496SURFACE PREPARATION PROCESS FOR DAMASCENE COPPER DEPOSITION - A method is disclosed for metallizing a substrate comprising an interconnect feature in the manufacture of a microelectronic device, wherein the interconnect feature comprises a bottom, a sidewall, and a top opening having a diameter, D. The method comprises the following steps: depositing a barrier layer on the bottom and the sidewall of the interconnect feature, the barrier layer comprising a metal selected from the group consisting of ruthenium, tungsten, tantalum, titanium, iridium, rhodium, and combinations thereof; contacting the substrate comprising the interconnect feature comprising the bottom and sidewall having the barrier layer thereon with an aqueous composition comprising a reducing agent and a surfactant; and depositing copper metal onto the bottom and the sidewall of the interconnect feature having the barrier layer thereon.03-25-2010
20120244698METHODS FOR FORMING COPPER DIFFUSION BARRIERS FOR SEMICONDUCTOR INTERCONNECT STRUCTURES - Embodiments of methods for forming Cu diffusion barriers for semiconductor interconnect structures are provided. The method includes oxidizing an exposed outer portion of a copper line that is disposed along a dielectric substrate to form a copper oxide layer. An oxide reducing metal is deposited onto the copper oxide layer. The copper oxide layer is reduced with at least a portion of the oxide reducing metal that oxidizes to form a metal oxide barrier layer. A dielectric cap is deposited over the metal oxide barrier layer.09-27-2012
20130078800METHOD FOR FABRICATING MOS TRANSISTOR - A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a silicide thereon; performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; and removing un-reacted platinum in the first rapid thermal process.03-28-2013
20130078799METHOD OF FORMING METAL CARBIDE BARRIER LAYERS FOR FLUOROCARBON FILMS - A method of forming metal carbide barrier layers for fluorocarbon films in semiconductor devices is described. The method includes depositing a fluorocarbon film on a substrate and depositing a metal-containing layer on the fluorocarbon film at a first temperature, where the metal-containing layer reacts with the fluorocarbon film to form a metal fluoride layer at an interface between the metal-containing layer and the fluorocarbon film. The method further includes heat-treating the metal-containing layer at a second temperature that is greater than the first temperature, wherein the heat-treating the metal-containing layer removes fluorine from the metal fluoride layer by diffusion through the metal-containing layer and forms a metal carbide barrier layer at the interface between the metal-containing layer and the fluorocarbon film, and wherein the metal-containing layer survives the heat-treating at the second temperature without blistering or pealing.03-28-2013
20130034958Method of Fabricating an Integrated Device - A method of fabricating an integrated device including a MicroElectroMechanical system (MEMS) and an associated microcircuit is provided. In one embodiment, the method comprises: forming a high temperature contact through a dielectric layer to an underlying element of a microcircuit formed adjacent to a MicroElectroMechanical System (MEMS) structure on a substrate; and depositing a layer of conducting material over the dielectric layer, and patterning the layer of conducting material to form a local interconnect (LI) for the microcircuit overlying and electrically coupled to the contact and a bottom electrode for the adjacent MEMS structure. Other embodiments are also provided.02-07-2013
20130040457POWER MOSFET CONTACT METALLIZATION - A structure includes a semiconductor device formed in a substrate; an insulator adjacent to the semiconductor device; an electrical contact electrically coupled to the semiconductor device, wherein the electrical contact includes tungsten; and an electrical connector coupled to the electrical contact, wherein the electrical connector includes aluminum. A surface of the insulator and a surface of the electrical contact form a substantially even surface.02-14-2013
20130040456METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device is provided. In the method, a groove is formed in a insulating film on a semiconductor substrate. An underlayer film is formed on the insulating film. A metal film is formed on the underlayer film. First polishing, in which the metal film is removed, is performed by supplying a first CMP slurry containing metal ions. The surfaces of the polishing pad and the semiconductor substrate are cleaned by supplying organic acid and pure water. Second polishing, in which the underlayer film is removed from the portion other than the groove, is performed by supplying a second CMP slurry different from the first CMP slurry.02-14-2013
20130040455HIGH TEMPERATURE ANNEAL FOR STRESS MODULATION - A method for modulating stress in films formed in semiconductor device manufacturing provides for high temperature annealing of an as-deposited compressive film such as titanium nitride. The high temperature annealing converts the initially compressive film to a tensile film without compromising other film qualities and characteristics. The converted tensile films are particularly advantageous as work function adjusting films in PMOS transistor devices and are advantageously used in conjunction with additional metal gate materials.02-14-2013
20100081276METHOD FOR FORMING COBALT TUNGSTEN CAP LAYERS - A method is provided for integrating cobalt tungsten cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt tungsten cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k regions, and forming a cobalt tungsten cap layer on the Cu paths.04-01-2010
20100099251METHOD FOR NITRIDATION PRETREATMENT - In one embodiment, a method for fabricating a damascene structure is provided which includes exposing a dielectric surface on a substrate to a nitrogen plasma to form a nitrided dielectric layer, wherein the dielectric surface contains a plurality of openings therein, depositing a barrier layer on the nitrided dielectric surface, and depositing a seed layer over the barrier layer. In some examples, the nitrogen plasma is formed from nitrogen gas or a mixture of nitrogen gas and hydrogen gas. The nitrogen plasma may be formed in a barrier deposition chamber or by a reactive preclean chamber. In another embodiment, a bulk layer may be deposited to fill the openings after depositing the seed layer. In one example, the bulk layer may contain copper, tungsten, or alloys thereof, and be deposited by an electrochemical plating process.04-22-2010
20090155997METHOD FOR FORMING Ta-Ru LINER LAYER FOR Cu WIRING - A method of forming a Ta—Ru metal liner layer for Cu wiring includes: (i) conducting atomic deposition of Ta X times, each atomic deposition of Ta being accomplished by a pulse of hydrogen plasma, wherein X is an integer such that a surface of an underlying layer is not covered with Ta particles; (ii) after step (i), conducting atomic deposition of Ru Y times, each atomic deposition of Ru being accomplished by a pulse of hydrogen plasma, wherein Y is an integer such that the Ta particles are not covered with Ru particles; and (iii) repeating steps (i) and (ii) Z times, thereby forming a Ta—Ru metal liner layer on a Cu wiring substrate.06-18-2009
20120164826Methods of Forming Metal Patterns in Openings in Semiconductor Devices - A method of forming a semiconductor device is disclosed. A dielectric layer having a opening therein is formed on a semiconductor substrate. An inner surface of the opening is treated by plasma. A barrier metal layer is formed on the plasma-treated inner surface of the opening. A seed layer is formed on the barrier metal layer. A metal bulk layer is formed on the seed layer. High quality semiconductor devices can be fabricated by using these methods, which may stably fill the opening formed in the dielectric layer.06-28-2012
20090197405METHOD OF FORMING A LAYER OVER A SURFACE OF A FIRST MATERIAL EMBEDDED IN A SECOND MATERIAL IN A STRUCTURE FOR A SEMICONDUCTOR DEVICE - There is described a method of forming a barrier layer (08-06-2009
20130052818Methods for Forming Interconnect Structures of Integrated Circuits - A method includes forming a hard mask over a low-k dielectric layer, and patterning the hard mask to form an opening. A stress tuning layer is formed over the low-k dielectric layer and in physical contact with the hard mask. The stress tuning layer has an inherent stress, wherein the inherent stress is a near-zero stress or a tensile stress. The low-k dielectric layer is etched to form a trench aligned to the opening, wherein the step of etching is performed using the hard mask as an etching mask.02-28-2013
20130089980MOSFET INTEGRATED CIRCUIT HAVING DOPED CONDUCTIVE INTERCONNECTS AND METHODS FOR ITS MANUFACTURE - An integrated circuit device having doped conductive contacts, and methods for its fabrication, are provided. One such method involves depositing a dielectric layer on the surface of a silicon semiconductor substrate, and photolithographically patterning a plurality of contact trenches on the dielectric layer. A tantalum barrier is deposited in the trenches, followed by a copper seed layer. The trenches are then plated with copper, including an overburden. A layer of doping material is deposited atop the overburden, and diffused into the copper by a heat treatment process. The overburden is then removed through chemical mechanical planarization, resulting in usable conductive interconnects in the trenches.04-11-2013
20090093115METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE BY ANNEALING ALUMINUM AND COPPER LAYERS TOGETHER - A metal line is formed to realize an improved electrical conductivity over the conventional aluminum metal lines. The metal line of a semiconductor device is made by forming an interlayer dielectric having a metal line forming region on a semiconductor substrate. A diffusion barrier on the interlayer dielectric is formed which includes a surface of the metal line forming region. A nucleus formation prevention layer is formed on upper ends of sidewalls of the metal line forming region and on a portion of the diffusion barrier which is placed on an upper surface of the interlayer dielectric. A laminated metal layer made of an aluminum layer and a copper layer is formed to fill the metal line forming region. A portion of the laminated metal layer, the nucleus formation prevention layer and the diffusion barrier is removed to expose the interlayer dielectric. The laminated metal layer is annealed into an annealed metal layer.04-09-2009
20120225553FORMATION OF A MASKING LAYER ON A DIELECTRIC REGION TO FACILITATE FORMATION OF A CAPPING LAYER ON ELECTRICALLY CONDUCTIVE REGIONS SEPARATED BY THE DIELECTRIC REGION - A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.09-06-2012
20130164933HYDROGEN BARRIER FOR FERROELECTRIC CAPACITORS - An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.06-27-2013
20120270392FABRICATING METHOD OF ACTIVE DEVICE ARRAY SUBSTRATE - A fabricating method of an active device array substrate is provided. The active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.10-25-2012
20100323517MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURE - Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line.12-23-2010
20130023116METHOD FOR THE FORMATION OF CO FILM AND METHOD FOR THE FORMATION OF CU INTERCONNECTION FILM - A Co film is formed by supplying cobalt alkylamidinate, and a combined gas containing H01-24-2013
20080213997SELECTIVE COPPER-SILICON-NITRIDE LAYER FORMATION FOR AN IMPROVED DIELECTRIC FILM/COPPER LINE INTERFACE - A process to form a copper-silicon-nitride layer on a copper surface on a semiconductor wafer is described. The process may include the step of exposing the wafer to a first plasma made from helium. The process may also include exposing the wafer to a second plasma made from a reducing gas, where the second plasma removes copper oxide from the copper surface, and exposing the wafer to silane, where the silane reacts with the copper surface to selectively form copper silicide. The process may further include exposing the wafer to a third plasma made from ammonia and molecular nitrogen to form the copper silicon nitride layer.09-04-2008
20110300708THROUGH-SILICON VIA STRUCTURE AND METHOD FOR MAKING THE SAME - A through-silicon via structure includes a substrate with a first side and a second side, a through-silicon hole connecting the first side and the second side and filled with a conductive material, a passivation layer disposed on and contacting the first side and covering the through-silicon hole, and a protection ring surrounding but not contacting the through-silicon hole and exposed by the first side and the second side. The protection ring is filled with an insulating material.12-08-2011
20110300707Metallization and Its Use In, In Particular, an IGBT or a Diode - A method of fabricating a power semiconductor component having a semiconductor body having at least two main surfaces includes applying a layer of a metallization on at least one of the main surfaces. The layer has a thickness of at least 15 μm and serves as a heat sink. The method also includes producing a field stop zone in the semiconductor body by implantation of protons or helium through the layer.12-08-2011
20110143533POISON-FREE AND LOW ULK DAMAGE INTEGRATION SCHEME FOR DAMASCENE INTERCONNECTS - A method of forming a dual damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using a tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.06-16-2011
20120108060SEMICONDUCTOR DEVICE HAVING SILICON-DIFFUSED METAL WIRING LAYER AND ITS MANUFACTURING METHOD - In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.05-03-2012
20120108058METHODS OF FORMING LAYERS ON SUBSTRATES - Methods for forming layers on a substrate are provided herein. In some embodiments, methods of forming layers on a substrate disposed in a process chamber may include depositing a barrier layer comprising titanium within one or more features in the substrate; and sputtering a material from a target in the presence of a plasma formed from a process gas by applying a DC power to the target, maintaining a pressure of less than about 500 mTorr within the process chamber, and providing up to about 5000 W of a substrate bias RF power to deposit a seed layer comprising the material atop the barrier layer.05-03-2012
20120108057METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED GATES - A method for fabricating a semiconductor device includes forming first plugs over a substrate, forming contact holes that expose the first plugs, ion-implanting an anti-diffusion material into the first plugs, and forming second plugs filling the contact holes.05-03-2012
20110294289Method for Producing a Connection Electrode for Two Semiconductor Zones Arranged One Above Another - A method for producing a connection electrode for a first and second adjacent and complementarily doped semiconductor zones includes a step of producing a trench extending through the first semiconductor zone into the second semiconductor zone in such a way that the first semiconductor zone is uncovered at sidewalls of the trench and the second semiconductor zone is uncovered at least at a bottom of the trench. The method also includes producing a first connection zone in the first semiconductor zone by implanting dopant atoms into the sidewalls at least at a first angle. The method further includes producing a second connection zone in the second semiconductor zone by implanting dopant atoms at least at a second, different angle. The method also includes depositing an electrode layer at least onto the sidewalls and the bottom of the trench for the purpose of producing the connection electrode.12-01-2011
20110171827Three Dimensional Integration and Methods of Through Silicon Via Creation - A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, etching the exposed planar area to form a cavity having a first depth in the structure, removing a second portion of the photoresist to expose a second planar area on the substrate layer, forming a doped portion in the second planar area, and etching the cavity to expose a first conductor in the structure and the doped portion to expose a second conductor in the structure.07-14-2011
20100035428METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing a semiconductor device according to the present invention includes: a groove forming step of forming a groove in an insulating layer made of an insulating material containing Si and O; an alloy film applying step of covering the side surface and the bottom surface of the groove with an alloy film made of an alloy material containing Cu and Mn by sputtering; a thinning step of reducing the thickness of a portion of the alloy film covering the bottom surface of the groove; a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu in the groove after the thinning step; and a barrier film forming step of forming a barrier film made of MnSiO between the Cu wire and the insulating layer by heat treatment.02-11-2010
20120088364SEMICONDUCTOR DEVICE AND THE METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate; a metal electrode wiring laminate on the semiconductor substrate, the metal electrode wiring laminate being patterned with a predetermined wiring pattern; the metal electrode wiring laminate including an undercoating barrier metal laminate and aluminum or aluminum alloy film on the undercoating barrier metal laminate; and organic passivation film covering the metal electrode wiring laminate, wherein the barrier metal laminate is a three-layered laminate including titanium films sandwiching a titanium nitride film. The semiconductor device according to the invention facilitates improving the moisture resistance of the portion of the barrier metal laminate exposed temporarily in the manufacturing process, facilitates employing only one passivation film, facilitates preventing the failures caused by cracks from occurring and the failures caused by Si nodules remaining in the aluminum alloy from increasing.04-12-2012
20090047780Method for forming composite barrier layer - Provided is a method for forming a composite barrier layer with superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer generally form boundaries with dielectric materials and crystalline layers generally form boundaries with conductive materials such as interconnect materials.02-19-2009
20100112807METHOD OF FORMING METAL WIRING OF SEMICONDUCTOR DEVICE - A method of forming a metal wiring of a semiconductor device, and devices thereof. A method of forming a metal wiring, and devices thereof, may maximize semiconductor yield by substantially removing oxide on and/or over a trench and/or by substantially removing a by-product that may remain on and/or over a surface of a wafer. A method of forming a metal wiring of a semiconductor may include forming a dielectric layer on and/or over a metal wiring. A method of forming a metal wiring of a semiconductor may include forming a contact hole, which may expose a partial surface of metal wiring, on and/or over a dielectric layer. A method of forming a metal wiring of a semiconductor may include performing an oxide removing process on and/or over an inner side of a contact hole, and/or performing a by-product removing process on and/or over an inner side wall of a trench.05-06-2010
20090149020METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A technology is provided which allows, in a coupling portion obtained by burying a conductive material within a coupling hole bored in an insulating film, the removal of a natural oxide film on the surface of a silicide layer which is present at the bottom portion of the coupling hole. A coupling hole is bored in an interlayer insulating film (first and second insulating films) to expose the surface of a nickel silicide layer at the bottom portion of the coupling hole. Then, reduction gases including a HF gas and a NH06-11-2009
20100015800METHOD FOR FORMING METAL FILM USING CARBONYL MATERIAL, METHOD FOR FORMING MULTI-LAYER WIRING STRUCTURE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A film forming method includes a first step of supplying a carbonyl material including a metallic element onto a surface of a substrate to be processed in a form of gas phase molecules along with a suppressor gas suppressing a decomposition of the carbonyl material, wherein a partial pressure of the suppressor gas is set to a first partial pressure at which the decomposition of the carbonyl material is suppressed; and a second step of changing the partial pressure of the suppressor gas in the surface of the substrate to a second partial pressure which causes the decomposition of the carbonyl material to thereby deposit the metallic element on the surface of the substrate.01-21-2010
20110263118Method of Manufacturing Semiconductor Devices - A method of manufacturing semiconductor devices includes forming a dielectric interlayer over a semiconductor substrate, wherein a wet etch rate (WER) is faster in an upper part of the dielectric interlayer than in a lower part of the dielectric interlayer, forming trenches in the dielectric interlayer, performing a cleaning process to make a width of an opening portion in an upper part of each of the trenches wider than a width of an opening portion in lower part of the trench, and filling the trenches with a metal layer.10-27-2011
20110195571SEMICONDUCTOR PROCESS - A semiconductor process is described. A substrate with at least one conductive region is provided, on which a dielectric layer is formed. An opening is formed in the dielectric layer, such that the conductive region is exposed. A first conductive layer is conformally formed on the surface of the opening. A first cleaning step is conducted using a first cleaning solution. A baking step is conducted after the first cleaning step. Afterwards, the opening is filled with a second conductive layer.08-11-2011
20100267231APPARATUS FOR UV DAMAGE REPAIR OF LOW K FILMS PRIOR TO COPPER BARRIER DEPOSITION - An apparatus and method for the ultraviolet (UV) treatment of carbon-containing low-k dielectric enables process-induced damage repair. A semiconductor substrate processing system may be configured to include degas and plasma pre-clean modules, UV process modules, copper diffusion barrier deposition modules and copper seed deposition modules such that the substrate is held under vacuum and is not exposed to ambient air after low k damage repair and before copper barrier layer deposition. Inventive methods provide for treatment of a damaged low-k dielectric on a semiconductor substrate with UV radiation to repair processing induced damage and barrier layer deposition prior breaking vacuum.10-21-2010
20100015798METHOD FOR FORMING A RUTHENIUM METAL CAP LAYER - A method for integrating ruthenium (Ru) metal cap layers and modified Ru metal cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration (EM) and stress migration (SM) in bulk Cu metal. In one embodiment, the method includes providing a planarized patterned substrate containing a Cu metal surface and a dielectric layer surface, depositing first Ru metal on the Cu metal surface, and depositing additional Ru metal on the dielectric layer surface, where the amount of the additional Ru metal is less than the amount of the first Ru metal. The method further includes at least substantially removing the additional Ru metal from the dielectric layer surface to improve the selective formation of a Ru metal cap layer on the Cu metal surface. Other embodiments further include incorporating one or more types of modifier elements into the dielectric layer surface, the Cu metal surface, the Ru metal cap layer, or a combination thereof.01-21-2010
20090087982SELECTIVE RUTHENIUM DEPOSITION ON COPPER MATERIALS - Embodiments of the invention provide processes for selectively forming a ruthenium-containing film on a copper surface over exposed dielectric surfaces. Thereafter, a copper bulk layer may be deposited on the ruthenium-containing film. In one embodiment, a method for forming layers on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a copper-containing surface and a dielectric surface, exposing the substrate to a ruthenium precursor to selectively form a ruthenium-containing film over the copper-containing surface while leaving exposed the dielectric surface, and depositing a copper bulk layer over the ruthenium-containing film.04-02-2009
20100099252Methods to completely eliminate or significantly reduce defects in copper metallization in IC manufacturing - A method for the improved electroplating of copper onto a copper seed layer provides burnishing the surface of the copper seed layer. The burnishing treatment is used to enhance the platability of the copper seed layer. The burnishing may be a reverse electroplating or a sputter etching process. Following the burnishing of the seed layer, the copper layer that is electroplated onto the seed layer exhibits improved quality.04-22-2010
20100081275METHOD FOR FORMING COBALT NITRIDE CAP LAYERS - A method is provided for integrating cobalt nitride cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt nitride cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k dielectric regions, and selectively forming a cobalt nitride cap layer on the Cu paths relative to the low-k dielectric regions.04-01-2010
20100081274METHOD FOR FORMING RUTHENIUM METAL CAP LAYERS - A method is provided for integrating ruthenium (Ru) metal deposition into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. Embodiments of the invention include treating patterned substrates containing metal layers and low-k dielectric materials with NH04-01-2010
20110201198METHOD FORMING METAL FILM AND SEMICONDUCTOR FABRICATION DEVICE HAVING METAL FILM - A method of forming metal films includes preparing a substrate, on which an insulating layer and a metal layer formed of a first metal are exposed; and forming a metal capping layer by supplying an organic precursor of a second metal onto the substrate to deposit the second metal simultaneously on the insulating layer and the metal layer, wherein the second metal capping layer has different thicknesses on the insulating layer and the metal layer.08-18-2011
20120295437METHOD FOR FABRICATING THROUGH-SILICON VIA STRUCTURE - A method for fabricating through-silicon via structure is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a through-silicon via in the semiconductor substrate; covering a liner in the through-silicon via; performing a baking process on the liner; forming a barrier layer on the liner; and forming a through-silicon via electrode in the through-silicon via.11-22-2012
20090280642SEMICONDUCTOR DEVICE HAVING MULTIPLE WIRING LAYERS AND METHOD OF PRODUCING THE SAME - A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.11-12-2009
20080206986METHOD OF FORMING A COPPER-BASED METALLIZATION LAYER INCLUDING A CONDUCTIVE CAP LAYER BY AN ADVANCED INTEGRATION REGIME - By appropriately designing a plurality of deposition steps and intermediate sputter processes, the formation of a barrier material within a via opening may be accomplished on the basis of a highly efficient process strategy that readily integrates conductive cap layers formed above metal-containing regions into well-approved process sequences.08-28-2008
20110171828SEMICONDUCTOR DEVICE WITH A LINE AND METHOD OF FABRICATION THEREOF - A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.07-14-2011
20090042385METHOD OF MANUFACTURING METAL LINE - A method of manufacturing a metal line according to embodiments includes forming an interlayer dielectric layer over a semiconductor substrate. A dielectric layer is formed over the interlayer dielectric layer. A trench may be formed by etching the dielectric layer and the interlayer dielectric layer. A metal material may be disposed over the interlayer dielectric layer including the trench. A first planarization process may be performed on the metal material using the dielectric layer as an etch stop layer. A wet etch process may be performed on the semiconductor substrate subjected the first planarization process. A second planarization process may be performed on interlayer dielectric layer subjected to the wet etch process.02-12-2009
20110269308METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a method for manufacturing a semiconductor device, a first Ti film, a titanium nitride (TiN) film, a second Ti film, a first aluminum (Al) film and a second Al film are formed sequentially in a contact hole formed in a second interlayer insulating film and on a Cu wire. The first titanium (Ti) film is formed so that a ratio of a thickness of a first portion of the first Ti film on a bottom face of the contact hole to a thickness of a second portion of the first Ti film on the second interlayer insulating film becomes equal to or smaller than 5/100. Moreover, the second Al film is formed using an aluminum reflow method, in which the second Ti film and the first Al film are alloyed with each other to form an Al—Ti alloy film.11-03-2011
20120295438COPPER INTERCONNECTION, METHOD FOR FORMING COPPER INTERCONNECTION STRUCTURE, AND SEMICONDUCTOR DEVICE - A copper interconnection structure includes an insulating layer, an interconnection body including copper and a barrier layer surrounding the interconnection body. The barrier layer includes a first barrier layer formed between a first portion of the interconnection body and the insulating layer. The first portion of the interconnection body is part of the interconnection body that faces the insulating layer. The barrier layer also includes a second barrier layer formed on a second portion of the interconnection body. The second portion of the interconnection body is part of the interconnection body not facing the insulating layer. Each of the first and the second barrier layers is formed of an oxide layer including manganese, and each of the first and the second barrier layers has a position where the atomic concentration of manganese is maximized in their thickness direction of the first and the second barrier layers.11-22-2012
20100279503Method for Producing an Electrically Conductive Connection - A method for producing an electrically conductive connection between a first surface of a semiconductor substrate and a second surface of the semiconductor substrate includes producing a hole, forming an electrically conductive layer that includes tungsten, removing the electrically conductive layer from the first surface of the semiconductor substrate, filling the hole with copper and thinning the semiconductor substrate. The hole is produced from the first surface of the semiconductor substrate into the semiconductor substrate. The electrically conductive layer is removed from the first surface of the semiconductor substrate, wherein the electrically conductive layer remains at least with reduced thickness in the hole. The semiconductor substrate is thinned starting from a surface, which is an opposite surface of the first surface of the semiconductor substrate, to obtain the second surface of the semiconductor substrate with the hole being uncovered at the second surface of the semiconductor substrate.11-04-2010
20080274610METHODS OF FORMING A SEMICONDUCTOR DEVICE INCLUDING A DIFFUSION BARRIER FILM - Methods of forming a semiconductor device that includes a diffusion barrier film are provided. The diffusion barrier film includes a metal nitride formed by using a MOCVD process and partially treated with a plasma treatment. Thus, a specific resistance of the diffusion barrier film can be decreased, and the diffusion barrier film may have distinguished barrier characteristics.11-06-2008
20100003816Method of manufacturing a semiconductor device from which damage layers and native oxide films in connection holes have been removed - An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF01-07-2010
20080311740Power composite integrated semiconductor device and manufacturing method thereof - A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for reducing ON-resistance. Furthermore, wire bonding connection of the copper electrodes is secured, and also the time-lapse degradation under high temperature which causes diffusion of copper and corrosion of copper is suppressed. Still furthermore, direct bonding connection can be established to current collecting electrodes in the power device portion, and also established to a bonding pad formed on the control circuit portion in the control circuit portion. A pad area at the device peripheral portion which has been hitherto needed is reduced, so that the area of the device is saved, and the manufacturing cost is reduced.12-18-2008
20080268634DOPANT DIFFUSION BARRIER LAYER TO PREVENT OUT DIFFUSION - A dopant diffusion barrier layer between silicon and buried oxide is disclosed. In one embodiment, the structure comprises a silicon layer and a substrate separated by an oxide layer; and a diffusion barrier layer located between the oxide layer and the silicon layer. The structure may include an oxide liner between the diffusion barrier layer and the silicon layer.10-30-2008
20110207320Noble Metal Activation Layer - Processes for minimizing contact resistance when using nickel silicide (NiSi) and other similar contact materials are described. These processes include optimizing silicide surface cleaning, silicide surface passivation against oxidation and techniques for diffusion barrier/catalyst layer deposition. Additionally, processes for generating a noble metal (for example platinum, iridium, rhenium, ruthenium, and alloys thereof) activation layer that enables the electroless barrier layer deposition on a NiSi-based contact material are described. The processes may be employed when using NiSi-based materials in other end products. The processes may be employed on silicon-based materials08-25-2011
20110207319METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing the semiconductor device includes forming an insulating film above a semiconductor substrate, forming an opening in the insulating film, forming a conductive film above the insulating film with the opening formed, removing the conductive film above the insulating film to bury the conductive film in the opening, and processing a surface of the insulating film with a silicon compound including Si—N or Si—Cl.08-25-2011
20110207318Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device, includes burying a conductive pattern in an insulating film made of SiOH, SiCOH or organic polymer, treating surfaces of the insulating film and the conductive pattern with plasma which includes a hydrocarbon gas as a treatment gas, and forming a diffusion barrier film, which is formed of an SiCH film, an SiCHN film, an SiCHO film or an SiCHON film, over the insulating film and the conductive pattern with performing a plasma CVD by adding an Si-containing gas to the treatment gas while increasing the addition amount gradually or in a step-by-step manner.08-25-2011
20110207317SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.08-25-2011
20090163024METHODS OF DEPOSITING A RUTHENIUM FILM - A method of depositing includes: loading a substrate into a reactor; and conducting a plurality of atomic layer deposition cycles on the substrate in the reactor. At least one of the cycles includes steps of: supplying a ruthenium precursor to the reactor; supplying a purge gas to the reactor; and supplying non-plasma ammonia gas to the reactor after supplying the ruthenium precursor. The method allows formation of a ruthenium layer having an excellent step-coverage at a relatively low deposition temperature at a relatively high deposition rate. In situ isothermal deposition of barrier materials, such as TaN at 200-300° C., is also facilitated.06-25-2009
20090298282Methods of Forming Interlayer Dielectrics Having Air Gaps - Methods of forming an interlayer dielectric having an air gap are provided including forming a first insulating layer on a semiconductor substrate. The first insulating layer defines a trench. A metal wire is formed in the trench such that the metal wire is recessed beneath an upper surface of the first insulating layer. A metal layer is formed on the metal wire, wherein the metal layer includes a capping layer portion filling the recess, a upper portion formed on the capping layer portion, and an overhang portion formed on the portion of the first insulating layer adjacent to the trench protruding sideward from the upper portion. The first insulating layer is removed and a second insulating layer is formed on the semiconductor substrate to cover the metal layer, whereby an air gap is formed below the overhang portion of the metal layer. A portion of the second insulating layer is removed to expose the upper portion of the metal layer. The upper portion and the overhang portion of the metal layer are removed. A third insulating layer is formed on the semiconductor substrate from which the upper portion and the overhang portion have been removed to maintain the air gap.12-03-2009
20090209098Multi-Step Cu Seed Layer Formation for Improving Sidewall Coverage - A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form a seed layer in a first chamber; and performing a first etch step to remove a portion of the seed layer. The method may further include performing a second deposition step to increase the thickness of the seed layer. At least one of the first etch step and the second deposition step is performed in a second chamber different from the first chamber.08-20-2009
20110223762Schemes for Forming Barrier Layers for Copper in Interconnect Structures - A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.09-15-2011
20110223761METHODS FOR FABRICATING CONTACTS OF SEMICONDUCTOR DEVICE STRUCTURES AND METHODS FOR DESIGNING SEMICONDUCTOR DEVICE STRUCTURES - Methods for fabricating contacts of semiconductor device structures include forming a dielectric layer over a semiconductor substrate with active-device regions spaced at a first pitch, forming a first plurality of substantially in-line apertures over every second active-device region of the active-device regions, and forming a second plurality of substantially in-line apertures laterally offset from apertures of the first plurality over active-device regions over which apertures of the first plurality are not located. Methods for designing semiconductor device structures include forming at least two laterally offset sets of contacts over a substrate including active-device regions at a first pitch, the contacts being formed at a second pitch that is about twice the first pitch.09-15-2011
20120302058METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprises forming a contact hole within an interlayer insulating film of a substrate and forming a contact plug while the substrate is heated. In forming the contact plug, the substrate is held on a stage within the chamber of a sputtering apparatus through a chuck, and an ESC voltage applied to the chuck is increased stepwise in a plurality of steps. First target power is applied to a target within the chamber to form a first Al film in the contact hole. Next, second target power higher than the first target power is applied to the target within the chamber to form a second Al film on the first Al film.11-29-2012
20090104769Semiconductor chip with coil element over passivation layer - A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.04-23-2009
20090053891Method for fabricating a semiconductor device - A method for fabricating a semiconductor device for preventing a poisoned via is provided. A substrate with a conductive layer formed thereon is provided. A composite layer is formed over the substrate and the conductive layer, wherein the composite layer comprises a dielectric layer and a spin-on-glass layer. A via hole is formed through the composite layer, wherein the via hole exposes a surface of the conductive layer. A protection layer is formed on a sidewall of the via hole so as to prevent out-gassing from the spin-on-glass layer. A barrier layer is formed on the protection layer and the conductive layer within the via hole. And a metal layer is deposited on the barrier layer within the via hole to fill the via hole.02-26-2009
20090117732METHOD OF FABRICATING SEMICONDCUTOR DEVICE - A method of fabricating a semiconductor device that may include forming an insulating interlayer on and/or over a semiconductor substrate, and then forming a damascene structure by patterning the insulating interlayer, and then forming a metal layer on and/or over the insulating interlayer and filling the damascene structure, and then forming a metal line by planarizing the metal layer until an upper surface of the insulating interlayer is exposed, and then forming pores in the insulating interlayer by performing thermal treatment of the planarized structure.05-07-2009
20100216304METHOD FOR FORMING TI FILM AND TIN FILM, CONTACT STRUCTURE, COMPUTER READABLE STORAGE MEDIUM AND COMPUTER PROGRAM - A cleaning process is performed on the surface of a nickel silicide film serving as an underlayer. Then, a Ti film is formed to have a film thickness of not less than 2 nm but less than 10 nm by CVD using a Ti compound gas. Then, the Ti film is nitrided. Then, a TiN film is formed on the Ti film thus nitrided, by CVD using a Ti compound gas and a gas containing N and H.08-26-2010
20120244699ATOMIC LAYER DEPOSITION OF TUNGSTEN MATERIALS - Embodiments of the invention provide a method for depositing tungsten-containing materials. In one embodiment, a method includes forming a tungsten nucleation layer over an underlayer disposed on the substrate while sequentially providing a tungsten precursor and a reducing gas into a process chamber during an atomic layer deposition (ALD) process and depositing a tungsten bulk layer over the tungsten nucleation layer, wherein the reducing gas contains hydrogen gas and a hydride compound (e.g., diborane) and has a hydrogen/hydride flow rate ratio of about 500:1 or greater. In some examples, the method includes flowing the hydrogen gas into the process chamber at a flow rate within a range from about 1 slm to about 20 slm and flowing a mixture of the hydride compound and a carrier gas into the process chamber at a flow rate within a range from about 50 sccm to about 500 sccm.09-27-2012
20100227474FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.09-09-2010
20100227473Methods of Forming Metal Patterns in Openings in Semiconductor Devices - A method of forming a semiconductor device is disclosed. A dielectric layer having a opening therein is formed on a semiconductor substrate. An inner surface of the opening is treated by plasma. A barrier metal layer is formed on the plasma-treated inner surface of the opening. A seed layer is formed on the barrier metal layer. A metal bulk layer is formed on the seed layer. High quality semiconductor devices can be fabricated by using these methods, which may stably fill the opening formed in the dielectric layer.09-09-2010
20110003474Germanium-Containing Dielectric Barrier for Low-K Process - A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a conductive wiring in the first dielectric layer; and a copper germanide nitride layer over the conductive wiring.01-06-2011
20100210104METHOD FOR FORMING COPPER WIRING IN A SEMICONDUCTOR DEVICE - A process for forming a copper wiring and the prevention of copper ion migration in a semiconductor device is disclosed herein. The process includes conducting a post-cleaning process for a copper layer that is to form the cooper wiring after already having undergone a CMP process. The post-cleaning process includes conducting a primary chemical cleaning using a citric acid-based chemical. A secondary chemical cleaning is then conducted on the copper layer having undergone the primary chemical cleaning using an ascorbic acid-based chemical. After the post-cleaning process is completed, the migration of copper ions over time is prevented thereby improving the reliability of the semiconductor device.08-19-2010
20100210105METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING BURIED WIRING - A method of fabricating a semiconductor device can include forming a trench in a semiconductor substrate, forming a first conductive layer on a bottom surface and side surfaces of the trench, and selectively forming a second conductive layer on the first conductive layer to be buried in the trench. The second conductive layer may be formed selectively on the first conductive layer by using an electroless plating method or using a metal organic chemical vapor deposition (MOCVD) or an atomic layer deposition (ALD) method.08-19-2010
20120196437METHODS OF FORMING COPPER WIRING AND COPPER FILM, AND FILM FORMING SYSTEM - A method of forming a Cu wiring in a trench or hole formed in a substrate is provided. The method includes forming a barrier film on the surface of the trench or hole, forming a Ru film on the barrier film, and embedding copper in the trench or hole by forming a Cu film on the Ru film using PVD while heating the substrate such that migration of copper into the trench or hole occurs.08-02-2012
20100068881Method of forming metallization in a semiconductor device using selective plasma treatment - A method of forming metallization in a semiconductor device, including forming an interlayer insulation layer on a semiconductor layer, forming a hole in the interlayer insulation layer by removing a portion of the interlayer insulation layer, forming a metal seed layer in the hole and on an upper surface of the interlayer insulation layer, such that the metal seed layer includes a first portion on the upper surface of the interlayer insulation layer, a second portion on an upper side surface of the hole, and a third portion on central and lower side surfaces of the hole, selectively plasma-treating a portion of the metal seed layer, forming a metal layer on the metal seed layer to fill the hole, and forming metallization by polishing the metal layer.03-18-2010
20100197135METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE WITH METAL-CONTAINING CAP LAYERS - A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing Cu metal surfaces and dielectric layer surfaces, forming a patterned mask layer on the patterned substrate, where the patterned mask layer contains openings that expose the Cu metal surfaces. The method further includes depositing a metal-containing layer on the Cu metal surfaces, depositing an additional metal-containing layer on the patterned mask layer, and removing the patterned mask layer and the additional metal-containing layer from the patterned substrate to selectively form metal-containing cap layers on the Cu metal surfaces.08-05-2010
20100221912Method of Manufacturing a semiconductor device - A method of manufacturing a semiconductor device includes a process of removing, by dry etching, an insulating layer which is formed on the top surface of a Ni-containing silicide layer to thereby at least partially expose the Ni-containing silicide layer; and a process of cleaning the exposed portion of the Ni-containing silicide layer using reduced water having a reductive function.09-02-2010
20090142923COPPER GATE ELECTRODE OF LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A copper gate electrode, applied in a thin-film-transistor liquid crystal display (LCD) device, at least comprises a patterned copper layer formed on a glass substrate, and a barrier layer formed on the patterned copper layer. The barrier layer comprises at least one of nitrogen and phosphorus, or comprises an alloy formularized as M06-04-2009
20090246952METHOD OF FORMING A COBALT METAL NITRIDE BARRIER FILM - A method is provided for forming a cobalt metal nitride barrier film on a substrate for semiconductor devices. According to one embodiment of the invention, the method includes depositing a plurality of metal nitride layers on the substrate, and depositing a cobalt layer between each of the plurality of metal nitride layers. According to another embodiment of the invention, the method includes simultaneously exposing the substrate to a metal nitride precursor or a metal precursor, a cobalt precursor, and a reducing gas, nitriding gas, or a combination thereof. Embodiments for integrating a cobalt metal nitride barrier film into semiconductor devices are described.10-01-2009
20110008960METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. The method includes forming a bottom electrode material layer containing aluminum and cupper over the substrate. An insulating material layer and a top electrode material layer are sequentially formed on the surface of the bottom electrode material layer. A photoresist pattern is formed on the top electrode material layer, and then the top electrode material layer is patterned to form a top electrode by using the photoresist pattern as mask. The photoresist pattern is removed by plasma ash and then an alloy process is performed to the bottom electrode material layer. Thereafter, the insulating material layer, and the bottom electrode material layer are patterned to form a patterned insulating layer and a patterned bottom electrode layer.01-13-2011
20110034026MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes forming an interlayer dielectric film above a semiconductor substrate; forming a first wiring trench with a first width and a second wiring trench with a second width that is larger than the first width inr the interlayer dielectric film; forming a first seed layer that includes a first additional element in the first wiring trench and the second wiring trench; forming a first copper layer over the first seed layer; removing the first copper layer and the first seed layer in the second wiring trench while leaving the first copper layer and the first seed layer in the first wiring trench; forming a second seed layer in the second wiring trench after removing the first copper layer and the first seed layer in the second wiring trench; and forming a second copper layer over the second seed layer.02-10-2011
20110244678SEMICONDUCTOR PROCESS - A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water. The semiconductor process can reduce the possibility of having an incomplete turning on, a leakage or a short, so that the yield of the product is increased.10-06-2011
20110244677METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS - A method of manufacturing a semiconductor device includes: forming a first conductive film on a substrate; forming an insulating film to cover the conductive film; etching the insulating film to form an opening portion to expose at least a portion of the first conductive film in the insulating film; irradiating the opening portion with ultraviolet rays in a reduction gas atmosphere; forming a barrier metal film in the opening portion; and forming a second conductive film on the barrier metal film.10-06-2011
20110237070MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device is provided which can precisely control the depth of a wiring trench pattern, and which can suppress the damage on the wiring trench pattern. A second low dielectric constant film, a third low dielectric constant film, and a film for serving as a mask layer are laminated over a diffusion preventing film in that order. The film for serving as the mask layer is etched, and a wiring trench pattern is formed which has its bottom made of a surface of the third low dielectric constant film, so that a mask layer is formed. A first resist mask is removed by asking. A wiring trench is formed using the wiring trench pattern of the mask layer such that a bottom of the trench is comprised of the second low dielectric constant film. A layer from a top surface of the copper metal to the third low dielectric constant film is removed by a CMP method. Each low dielectric constant film has a dielectric constant lower than that of FSG, and the second low dielectric constant film has the dielectric constant lower than that of the third low dielectric constant film.09-29-2011
20110237069METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first hole is formed in an insulating film. A seed layer, which covers an upper surface of the insulating film and an inner surface of the first hole, is formed. A first plating film is formed over the seed layer at a first growth rate. A second plating film is formed over the first plating film at a second growth rate that is higher than the first growth rate. A third plating film is formed over the second plating film at a third growth rate that is higher than the second growth rate.09-29-2011
20110129996THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER - A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.06-02-2011
20110212618TRENCH INTERCONNECT STRUCTURE AND FORMATION METHOD - Embodiments concern vertical interconnect structures having sub-micron widths for use in integrated circuits, and methods of their manufacture, which result in reduced interconnect resistance, I09-01-2011
20100227472METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - To solve a problem that it becomes difficult to lower contact resistance between nickel-based metal silicide and metal for contact as the result of the miniaturization of the hole. One invention of the present application is a method of manufacturing a semiconductor integrated circuit device having a MISFET subjected to silicidation of a source/drain region and the like by nickel-based metal silicide, the method performing a heat treatment for the upper surface of a silicide film in a non-plasma reducing vapor phase atmosphere containing a gas having a nitrogen-hydrogen bond as one of main gas components, before forming a barrier metal at a contact hole provided at a pre-metal insulating film.09-09-2010
20100197136COMPOSITION FOR CLEANING AND RUST PREVENTION AND PROCESS FOR PRODUCING SEMICONDUCTOR ELEMENT OR DISPLAY ELEMENT - A composition for cleaning and corrosion inhibition which is used in a step of manufacturing a semiconductor device or a display device having a copper-containing metallic wiring is provided, wherein the corrosion inhibitor component is any one of pyrazole, a pyrazole derivative such as 3,5-dimethylpyrazole, a triazole derivative such as 1,2,4-triazole, an aminocarboxylic acid such as iminodiacetic acid or ethylenediaminedipropionic acid hydrochloride, or a disulfide compound such as diisopropyl disulfide or diethyl disulfide; and the cleaning agent component is any one of ammonium fluoride, tetramethylammonium fluoride, ammonium acetate, acetic acid, glyoxylic acid, oxalic acid, ascorbic acid, 1,2-diaminopropane or dimethylacetamide. Also, a method for manufacturing a semiconductor device or the like using the composition for cleaning and corrosion inhibition is provided.08-05-2010
20110151661METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A first film containing a first metal material having a diffusion preventing function for copper, a second film containing oxygen-contained copper film, a third film containing copper and a second metal material which exhibits a diffusion preventing function for copper by bonding with oxygen, and a fourth film of copper as the main material are formed in an opening formed in an insulating film, and then a barrier layer containing the first metal material, the second metal material and oxygen is formed by thermal processing between the insulating film and the fourth film.06-23-2011
20100055898METHOD FOR FABRICATING AN INTEGRATED CIRCUIT - A method for fabricating an integrated circuit is provided. A substrate having thereon a first conductive wire and a second conductive wire is provided. A liner is formed on the first conductive wire and second conductive wire. An ashable material layer is filled into a gap between the first conductive wire and second conductive wire. The ashable material layer is then polished to expose a portion of the liner. A cap layer is formed on the ashable material layer and on the exposed liner. A through hole is etched into the cap layer to expose a portion of the ashable material layer. Thereafter, the ashable material layer is removed by way of the through hole.03-04-2010
20090093116Method for forming Zener Zap Diodes and Ohmic Contacts in the Same Integrated Circuit - A method for forming an ohmic contact and a zener zap diode in an integrated circuit includes forming a first contact opening in the insulating layer over a first diffusion region to expose the semiconductor substrate; forming a barrier metal layer on the insulating layer and in the first contact opening; forming a second contact opening in the barrier metal layer over a second diffusion region and the insulating layer to expose the semiconductor substrate; forming a third contact opening in the barrier metal layer and the insulating layer over a third diffusion region to expose the semiconductor substrate; forming an aluminum layer on the barrier metal layer and the insulating layer and in the first, second and third contact openings; and patterning the aluminum layer to form the ohmic contact over the first diffusion region and the zener zap diode over the second and third diffusion regions.04-09-2009
20090215262ATOMIC LAYER DEPOSITION SYSTEMS AND METHODS INCLUDING SILICON-CONTAINING TANTALUM PRECURSOR COMPOUNDS - The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): Ta(NR08-27-2009
20110151663METHOD TO FORM A VIA - A method for forming a via, comprising (a) providing a structure comprising a mask (06-23-2011
20110097897METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, including: forming a barrier seed Ti layer covering a recess in an insulating film; forming a first barrier TiN layer by sputtering; forming a second barrier TiN layer by sputtering with a substrate bias power higher than that in forming the first barrier TiN layer; forming a first wiring seed Ti layer by sputtering; forming a second wiring seed Ti layer by sputtering with a substrate bias power higher than that in forming the first wiring seed Ti layer; forming a first wiring seed Al layer by sputtering; forming a second wiring seed Al layer by sputtering with a substrate bias power higher than that in forming the first wiring seed Al layer; forming Ti—Al alloy in the recess by a heating; and forming an Al wiring material layer so as to fill the recess therewith by sputtering and heating.04-28-2011
20110104893METHOD FOR FABRICATING MOS TRANSISTOR - A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a gate and a source/drain region thereon; forming a Ni—Pt layer on surface of the gate and the source/drain region; performing a first rapid thermal process to react a portion of the Ni—Pt layer into a silicide layer; removing un-reacted nickel from the first rapid thermal process; removing un-reacted platinum from the first rapid thermal process; performing a second rapid thermal process for lowering the resistance of the silicide layer; and covering a contact etch stop layer (CESL) on the silicide layer after the second rapid thermal process.05-05-2011
20110070730SEQUENTIAL DEPOSITION OF TANTALUM NITRIDE USING A TANTALUM-CONTAINING PRECURSOR AND A NITROGEN-CONTAINING PRECURSOR - Embodiments of the invention provide a method for forming tantalum nitride materials on a substrate by employing an atomic layer deposition (ALD) process. The method includes heating a tantalum precursor within an ampoule to a predetermined temperature to form a tantalum precursor gas and sequentially exposing a substrate to the tantalum precursor gas and a nitrogen precursor to form a tantalum nitride material. Thereafter, a nucleation layer and a bulk layer may be deposited on the substrate. In one example, a radical nitrogen compound may be formed from the nitrogen precursor during a plasma-enhanced ALD process. A nitrogen precursor may include nitrogen or ammonia. In another example, a metal-organic tantalum precursor may be used during the deposition process.03-24-2011
20110070731METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a technology capable of improving reliability and manufacturing yield of a semiconductor device by reducing variations of electrical characteristics in connection hole portions. After a semiconductor wafer is placed over a wafer stage provided in a chamber for dry cleaning treatment of a deposition system, dry cleaning treatment is performed to a principal surface of the semiconductor wafer by supplying reducing gas, sequentially, heat treatment is performed to the semiconductor wafer at a first temperature of 100 to 150° C. by a showerhead which is maintained at 180° C. Next, after the semiconductor wafer is vacuum transferred from the chamber to a chamber for heat treatment, heat treatment is performed to the semiconductor wafer at a second temperature of 150 to 400° C. in the chamber, thereby removing a product remaining over the principal surface of the semiconductor wafer.03-24-2011
20120149192METHODS FOR DEPOSITING METAL IN HIGH ASPECT RATIO FEATURES - Methods of depositing metal in high aspect ratio features are provided herein. In some embodiments, a method of processing a substrate includes applying RF power at VHF frequency to a target comprising metal disposed in the PVD chamber above the substrate to form a plasma from a plasma-forming gas, sputtering metal atoms from the target using the plasma while maintaining a first pressure in the PVD chamber sufficient to ionize a predominant portion of the sputtered metal atoms, depositing the ionized metal atoms on a bottom surface of the opening and on a first surface of the substrate, applying a first RF power to redistribute at least some of the deposited metal atoms from the bottom surface and upper surface to sidewalls of the opening, and repeating the deposition the redistribution processes until a first layer of metal is deposited on substantially all surfaces of the opening.06-14-2012
20100311236COPPER INTERCONNECT STRUCTURE WITH AMORPHOUS TANTALUM IRIDIUM DIFFUSION BARRIER - A method of forming a diffusion barrier for use in semiconductor device manufacturing includes depositing, by a physical vapor deposition (PVD) process, an iridium doped, tantalum based barrier layer over a patterned interlevel dielectric (ILD) layer, wherein the barrier layer is deposited with an iridium concentration of at least 60% by atomic weight such that the barrier layer has a resulting amorphous structure.12-09-2010
20110256715BARRIER LAYER FOR COPPER INTERCONNECT - A copper interconnect includes a copper layer formed in a dielectric layer. A liner is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the liner and the dielectric layer. The barrier layer is a metal oxide.10-20-2011
20110212617LIQUID FOR PROTECTING COPPER WIRING SURFACE AND METHOD FOR MANUFACTURING SEMICONDUCTOR CIRCUIT ELEMENT - A copper wiring material surface protective liquid is provided that is used in production of a semiconductor circuit device containing copper wiring, and consists of an aqueous solvent and an acetylene alcohol compound containing at least 3-phenyl-2-propyn-1-ol. A method for producing a semiconductor circuit device is provided that contains: forming an insulating film and/or a diffusion preventing film on a silicon substrate; then forming a copper film by a sputtering; then forming a copper film or a copper alloy film containing 80% by mass or more of copper thereon by a plating method; and flattening the film by a chemical mechanical polishing (CMP) method, thereby providing a semiconductor substrate containing a flattened copper wiring, in which the semiconductor substrate having an exposed surface of a copper wiring material is treated by making in contact with the copper wiring material surface protective liquid.09-01-2011
20080242081POLISHING METHOD, POLISHING APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A polishing method includes a first polishing step of halfway polishing a film to be polished formed on a substrate, and a second polishing step of further polishing the polished film, wherein a first film thickness profile showing an in-plane distribution of a film thickness of the polished film after the second polishing step for a first substrate is measured, and the first polishing step for a second substrate is executed to obtain a second film thickness profile which has a size relation in a film thickness opposite to the first film thickness profile.10-02-2008
20080242080Method for implementing diffusion barrier in 3D memory - One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.10-02-2008
20110250751METHOD FOR FILLING METAL - A method for filling a metal is disclosed. First, a substrate is provided. The substrate includes a metal material layer, a dielectric layer covering the metal material layer and a hard mask layer covering the dielectric layer. The hard mask layer has at least one opening to expose the underlying dielectric layer. Second, a dry etching step is performed to etch the dielectric layer through the opening to remove part of the dielectric layer to expose the metal material layer and to form a recess and leave some residues in the recess. Then a cleaning step is performed to remove the residues and to selectively remove part of the hard mask to substantially enlarge the opening. Later, a metal fills the recess through the enlarged opening.10-13-2011
20100105204METHOD TO MODULATE COVERAGE OF BARRIER AND SEED LAYER USING TITANIUM NITRIDE - Methods for processing substrates are provided herein. In some embodiments, a method for processing substrates includes providing to a process chamber a substrate comprising an exposed dielectric layer having a feature formed therein. A mask layer comprising titanium nitride may be selectively deposited atop corners of the feature. A barrier layer may be selectively deposited atop the mask layer and into a bottom portion of the feature. The barrier layer deposited on the bottom portion of the feature may be etched to redistribute at least a portion of the barrier layer onto sidewalls of the feature.04-29-2010
20100015799SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS, COMPUTER PROGRAM AND STORAGE MEDIUM - A semiconductor device, which suppresses formation of an organic impurity layer and has excellent adhesiveness to a copper film and a metal to be a base, is manufactured. A substrate (wafer W) coated with a barrier metal layer (base film) 01-21-2010
20090325378REDUCING CONTAMINATION OF SEMICONDUCTOR SUBSTRATES DURING BEOL PROCESSING BY PERFORMING A DEPOSITION/ETCH CYCLE DURING BARRIER DEPOSITION - A conductive barrier material of a metallization system of a semiconductor device may be formed on the basis of one or more deposition/etch cycles, thereby providing a reduced material thickness in the bevel region, while enhancing overall thickness uniformity in the active region of the semiconductor substrate. In some illustrative embodiments, two or more deposition/etch cycles may be used, thereby providing the possibility to select reduced target values for the barrier thickness in the die regions, while also obtaining a significantly reduced thickness in the bevel region.12-31-2009
20090137117Method Forming Contact Plug for Semiconductor Device Using H2 Remote Plasma Treatment - Provided are methods of forming a contact plug of a semiconductor device. Methods of forming a contact plug of a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate on which a lower structure is formed, forming a contact hole in the interlayer insulating layer, the contact hole exposing the lower structure, and forming a W layer and then a WN layer to form a W/WN barrier layer in the contact hole. Methods may include H05-28-2009
20110256717METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - Provided are semiconductor devices and methods for fabricating the same. A method for fabricating a semiconductor device includes: forming an interlayer dielectric layer including an opening in which a lower conductive layer is exposed; forming a barrier layer on the interlayer dielectric layer and on the lower conductive layer the opening; forming an anti-seed generation region on a surface of the barrier layer which is provided on a top surface of the interlayer dielectric layer and an upper sidewall of the opening; and filling the opening with conductive material to form a conductive layer.10-20-2011
20090029546METHOD FOR FORMING METAL LINES OF SEMICONDUCTOR DEVICE - Methods are disclosed for forming metal lines of a semiconductor device that can reduce interconnection or contact resistance, and can reduce defects in a barrier metal layer having a column structure. The method can include forming a first metal line on a semiconductor substrate, forming an insulating film on the first metal line, forming a contact hole in the insulating film, sequentially forming a barrier metal layer and a capping layer for protecting the barrier metal layer on an entire upper surface of the resultant substrate, oxidizing the capping layer to form a capping oxide film, depositing a contact metal material on the resultant substrate, planarizing the contact metal material to expose the insulating film, and forming a second metal line on the insulating film.01-29-2009
20090029545METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides a method of manufacturing a semiconductor device which method enables a reduction in via resistance. The method of manufacturing the semiconductor device includes the steps of removing a barrier metal film from a bottom surface of a via, with the barrier metal film remaining on a bottom surface of a trench, modifying lower wiring exposed from the bottom surface of the via to form a modified layer, removing the modified layer to form an engraving (recess portion), and depositing a copper film in the engraving, the via, and the trench to form upper wiring and a via plug.01-29-2009
20080286966METHOD OF FORMING A DIELECTRIC CAP LAYER FOR A COPPER METALLIZATION BY USING A HYDROGEN BASED THERMAL-CHEMICAL TREATMENT - A new technique is disclosed in which a barrier/cap layer for a copper based metal line is formed by using a thermal-chemical treatment based on hydrogen with a surface modification on the basis of a silicon-containing precursor followed by an in situ plasma based deposition of silicon based dielectric barrier material. The thermal-chemical cleaning process is performed in the absence of any plasma ambient.11-20-2008
20100311238METHOD OF FORMING COPPER WIRING LAYER - A method of forming a copper wiring layer, which includes forming a pattern of copper seed layer on a substrate, and forming a copper wiring pattern on the pattern of copper seed layer by means of electroless plating. At least one component of semiconductor device selected from the group consisting of the gate electrode, the source electrode, the drain electrode, and a wiring connected with at least one of these electrodes is formed by a method comprising forming a pattern of copper seed layer, and forming a copper wiring pattern on the pattern of copper seed layer by means of electroless plating.12-09-2010
20100311237FORMATION OF A TANTALUM-NITRIDE LAYER - A method of forming a material on a substrate is disclosed. In one embodiment, the method includes forming a tantalum nitride layer on a substrate disposed in a plasma process chamber by sequentially exposing the substrate to a tantalum precursor and a nitrogen precursor, followed by reducing a nitrogen concentration of the tantalum nitride layer by exposing the substrate to a plasma annealing process. A metal-containing layer is subsequently deposited on the tantalum nitride layer.12-09-2010
20090117733Protection of seedlayer for electroplating - The present invention includes a method of providing a substrate; sequentially forming a seed layer over the substrate and forming a protection layer over the seed layer; and sequentially removing the protection layer and forming a conductor over the seed layer.05-07-2009
20080213998METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR MANUFACTURING APPARATUS AND STORAGE MEDIUM FOR EXECUTING THE METHOD - The semiconductor device manufacturing method includes forming an alloy film of copper and an additive metal along a wall surface of a recess portion of an interlayer insulating film in a surface of a substrate; forming a barrier layer made of a compound of the additive metal and a constituent element of the interlayer insulating film; heating the substrate under an atmosphere containing an organic acid, an organic acid anhydride, or ketones to precipitate surplus additive metal onto a surface of the alloy film; and burying copper in the recess portion after heating the substrate. Since the organic acid, the organic acid anhydride, and the ketones have a reducing power for Cu, an oxidation of Cu in the alloy film is suppressed while a barrier layer made of a compound of the additive metal and a constituent element of the insulating film is formed.09-04-2008
20100304562ELECTROLESS DEPOSITION OF COBALT ALLOYS - Systems and methods for electroless deposition of a cobalt-alloy layer on a copper surface include a solution characterized by a low pH. This solution may include, for example, a cobalt(II) salt, a complexing agent including at least two amine groups, a pH adjuster configured to adjust the pH to below 7.0, and a reducing agent. In some embodiments, the cobalt-alloy is configured to facilitate bonding and copper diffusion characteristics between the copper surface and a dielectric in an integrated circuit.12-02-2010
20110053370METAL LINE OF SEMICONDUCTOR DEVICE WITHOUT PRODUCTION OF HIGH RESISTANCE COMPOUND DUE TO METAL DIFFUSION AND METHOD FOR FORMING THE SAME - A metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is formed on the semiconductor substrate having the lower metal line, and a metal line forming region exposing at least a portion of the lower metal line is defined in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and includes a WN03-03-2011
20110136338METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a via hole in a semiconductor substrate, forming an isolation layer on an inner side of the via hole, forming a diffusion barrier layer over an upper portion of the semiconductor substrate and the inner side of the via hole where the isolation layer is formed, arranging a solvent, which contains electrically charged metal particles, on the semiconductor substrate where the diffusion barrier layer is formed, and filling the via hole with the metal particles by moving the metal particles using applied external force. The applied external force said includes a voltage causing an electric current to flow between the semiconductor substrate and the solvent, an electrical field applied between the semiconductor substrate and the solvent, or a magnetic field applied between the semiconductor substrate and the solvent.06-09-2011
20100304561FILM FORMING METHOD AND SUBSTRATE PROCESSING APPARATUS - A barrier layer including a titanium film is formed at a low temperature, and a TiSi12-02-2010
20100323516SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed is a semiconductor device including: a substrate; a wiring layer formed on the substrate and made of copper or a copper alloy; a copper diffusion barrier film formed on the wiring layer and made of an amorphous carbon film formed by CVD using a processing gas containing a hydrocarbon gas; and a low-k insulating film formed on the copper diffusion barrier film.12-23-2010
20100167530METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE - Disclosed is a method for forming a metal line of a semiconductor device. The method includes forming a first photoresist pattern on at least one interlayer dielectric provided on a semiconductor substrate, etching the interlayer dielectric using the first photoresist pattern to form a trench, removing the first photoresist pattern by ashing, and primarily removing residues left in the trench using a first cleaning solution comprising TMH, H07-01-2010
20110136339CONDUCTOR STRUCTURE INCLUDING MANGANESE OXIDE CAPPING LAYER - A microelectronic structure includes a dielectric layer located over a substrate. The dielectric layer is separated from a copper containing conductor layer by an oxidation barrier layer. The microelectronic structure also includes a manganese oxide layer located aligned upon a portion of the copper containing conductor layer not adjoining the oxidation barrier layer. A method for fabricating the microelectronic structure includes sequentially forming and sequentially planarizing within an aperture within a dielectric layer an oxidation barrier layer, a manganese containing layer (or alternatively a mobile and oxidizable material layer) and finally, a planarized copper containing conductor layer (or alternatively a base material layer comprising a material less mobile and oxidizable than the mobile and oxidizable material layer) to completely fill the aperture. The manganese layer and the planarized copper containing conductor layer are then thermally oxidized to form a manganese oxide layer self aligned to a portion of the copper containing conductor layer not adjoining the oxidation barrier layer.06-09-2011
20090197406SEQUENTIAL DEPOSITION OF TANTALUM NITRIDE USING A TANTALUM-CONTAINING PRECURSOR AND A NITROGEN-CONTAINING PRECURSOR - Embodiments of the invention provide a method for forming tantalum nitride materials on a substrate by employing an atomic layer deposition (ALD) process. The method includes heating a tantalum precursor within an ampoule to a predetermined temperature to form a tantalum precursor gas and sequentially exposing a substrate to the tantalum precursor gas and a nitrogen precursor to form a tantalum nitride material. Thereafter, a nucleation layer and a bulk layer may be deposited on the substrate. In one example, a radical nitrogen compound may be formed from the nitrogen precursor during a plasma-enhanced ALD process. A nitrogen precursor may include nitrogen or ammonia. In another example, a metal-organic tantalum precursor may be used during the deposition process.08-06-2009
20120309190COPPER INTERCONNECT FORMATION - Disclosed is a method which includes forming a copper interconnect within a trench or via in a substrate. Forming the copper interconnect includes forming a ruthenium-containing seed layer on a wall of the trench or via; forming a cobalt sacrificial layer on the ruthenium-containing layer before the ruthenium-containing seed layer being exposed to an environment that is oxidizing with respect to the seed layer; and contacting the cobalt sacrificial layer with a copper plating solution, the copper plating solution dissolving the cobalt sacrificial layer and plating out copper on the unoxidized ruthenium-containing seed layer. Alternatively, the ruthenium-containing seed layer may be replaced with platinum, tungsten nitride, titanium nitride or titanium or iridium. Further alternatively, the cobalt sacrificial layer may be replaced by tin, cadmium, copper or manganese.12-06-2012
20110189850SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first insulating film is formed on a semiconductor substrate. A first interconnection is formed in a trench formed in the first insulating film. A first barrier film is formed between the first interconnection and first insulating film. A second insulating film is formed on the upper surface of the first interconnection, and in a first hollow portion between the side surface of the first barrier film and the first insulating film. The second insulating film is formed from the upper surface of the first interconnection to a depth higher than the bottom surface of the first interconnection. The first hollow portion is formed below the bottom surface of the second insulating film.08-04-2011
20100022086METHOD OF MANUFACTURING A METAL WIRING STRUCTURE - In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitidation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole.01-28-2010
20110151662MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE HAVING IMPROVED COPPER DIFFUSION PREVENTIVE FUNCTION OF PLUGS AND WIRINGS MADE OF COPPER OR COPPER ALLOY AND SEMICONDUCTOR DEVICE OF THIS KIND - (a) A copper alloy film containing at least two types of metal elements in addition to copper is formed on the surface of an insulator containing oxygen and formed on a semiconductor substrate. (b) A metal film made of pure copper or copper alloy is formed on the copper alloy film. (c) After the step (a) or (b), heat treatment is performed under the condition that a metal oxide film is formed on a surface of the insulator through reaction between the oxygen in the insulator and the metal elements in the copper alloy film.06-23-2011
20090280641METHOD OF FORMING A CONTACT STRUCTURE - An insulation layer may be formed on an object having a contact region. The insulation layer may be partially etched to form an opening exposing the contact region. A material layer including silicon and oxygen may be formed on the exposed contact region. A metal layer may be formed on the material layer including silicon and oxygen. The material layer including silicon and oxygen may be reacted with the metal layer to form a metal oxide silicide layer at least on the contact region. A conductive layer may be formed on the metal oxide silicide layer to fill up the opening.11-12-2009
20090035937In-Situ Deposition for Cu Hillock Suppression - A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.02-05-2009
20100062598METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH METAL LINE - A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.03-11-2010
20110318919SURFACE TREATMENT FOR A FLUOROCARBON FILM - A method for manufacturing semiconductor devices includes the steps of annealing an insulating layer and forming a barrier layer including a metal element over the insulating layer. The insulating layer includes a fluorocarbon (CFx) film. The barrier layer is formed by a high-temperature sputtering process after the annealing step.12-29-2011
20120009781METHOD OF MANUFACTURING A METAL WIRING STRUCTURE - In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitridation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole.01-12-2012
20120015516ELECTRICAL CONDUCTOR LINE HAVING A MULTILAYER DIFFUSION BARRIER FOR USE IN A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - An electrical conductor having a multilayer diffusion barrier of use in a resultant semiconductor device is presented. The electrical conductor line includes an insulation layer, a diffusion barrier, and a metal line. The insulation layer is formed on a semiconductor substrate and having a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a multi-layered structure made of TaN layer, an Mo01-19-2012
20110165775THIN FILM FORMING METHOD - According to the present invention, a thin film having a desired thickness is formed on an inner sidewall of a step with excellent step coverage in a film forming step and an etching step at least once, respectively. In an embodiment of the present invention, a target material is deposited on a substrate (07-07-2011
20120028461METHODS FOR DEPOSITING METAL IN HIGH ASPECT RATIO FEATURES - Methods for depositing metal in high aspect ratio features formed on a substrate are provided herein. In some embodiments, a method includes applying first RF power at VHF frequency to target comprising metal disposed above substrate to form plasma, applying DC power to target to direct plasma towards target, sputtering metal atoms from target using plasma while maintaining pressure in PVD chamber sufficient to ionize predominant portion of metal atoms, depositing first plurality of metal atoms on bottom surface of opening and on first surface of substrate, applying second RF power to redistribute at least some of first plurality from bottom surface to lower portion of sidewalls of the opening, and depositing second plurality of metal atoms on upper portion of sidewalls by reducing amount of ionized metal atoms in PVD chamber, wherein first and second pluralities form a first layer deposited on substantially all surfaces of opening.02-02-2012
20120064713Ultra-low-k dual damascene structure and method of fabricating - A method of patterning an insulation layer is described. The method includes preparing a feature pattern in an insulation layer using at least one hard mask layer formed on the insulation layer, where the insulation layer contains a low-k material having a dielectric constant less than the dielectric constant of SiO03-15-2012
20120070983SEMICONDUCTOR DEVICE WITH GATE TRENCH - A method of manufacturing a semiconductor device is presented. The device has: a gate terminal formed from polysilicon and covered by an insulation layer; and a plug extending through an insulation layer to provide an electrical connection to the gate trench. A metal layer is deposited to cover at least a portion of the insulation layer. The metal layer is then etched to remove the metal layer from above the plug.03-22-2012
20120108059METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnO05-03-2012
20120252209PLASMA NITRIDING METHOD, PLASMA NITRIDING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A plasma nitriding method includes placing, in a processing chamber, a target object having a structure including a first portion containing a metal and a second portion containing silicon to expose surfaces of the first and the second portion; and performing a plasma process on the target object to selectively nitride the surface of the first portion such that a metal nitride film is selectively formed on the surface of the first portion. Further, the first portion contains tungsten, and a nitrogen-containing plasma is generated by supplying a nitrogen-containing gas into the processing chamber and setting an internal pressure of the processing chamber in a range from 133 Pa to 1333 Pa. The surface of the first portion is selectively nitrided without nitriding the surface of the second portion by the nitrogen-containing plasma such that a tungsten nitride film is formed on the surface of the first portion.10-04-2012
20120315753METHOD OF FORMING A THROUGH-SILICON VIA UTILIZING A METAL CONTACT PAD IN A BACK-END-OF-LINE WIRING LEVEL TO FILL THE THROUGH-SILICON VIA - A method for fabricating through-silicon vias (TSVs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill TSVs with plated-conductive material (e.g., copper) from an electroplating solution. Moreover, the method provides a way to fill high aspect ratio TSVs with minimal additional semiconductor fabrication process steps, which can increase the silicon area that is available for forming additional electronic components on integrated circuits.12-13-2012
20120315755COPPER INTERCONNECT WITH METAL HARDMASK REMOVAL - A passivation layer is formed on inlaid Cu for protection against oxidation and removal during subsequent removal of an overlying metal hardmask. Embodiments include treating an exposed upper surface of inlaid Cu with hydrofluoric acid and a copper complexing agent, such as benzene triazole, to form a passivation monolayer of a copper complex, etching to remove the metal hardmask, removing the passivation layer by heating to at least 300° C., and forming a barrier layer on the exposed upper surface of the inlaid Cu.12-13-2012
20090130844Method of Forming Metal Line of Semiconductor Device - A method of forming metal lines of a semiconductor device, comprising providing a semiconductor substrate in which a plurality of gates and junctions formed between the gates are included in a cell area and a peripheral area; forming an insulating layer over the semiconductor substrate including the gates; forming an etch protection layer over the insulating layer; etching he etch protection layer and the insulating layer, and gap-filling conductive material to form contact plugs contacting the junctions of the cell area; and, forming first metal lines contacting the contact plugs and forming second metal lines contacting the junctions of the peripheral area by etching the etch protection layer and the insulating layer.05-21-2009
20090130843METHOD OF FORMING LOW-RESISTIVITY RECESSED FEATURES IN COPPER METALLIZATION - A method is provided for forming low-resistivity recessed features containing a ruthenium (Ru) film integrated with bulk copper (Cu) metal. The method includes providing a patterned substrate containing a recessed feature, depositing a barrier film in the recessed feature in a barrier film deposition chamber, transferring the patterned substrate from the barrier film deposition chamber to a Ru metal deposition chamber, heat-treating the barrier film in the presence of a H05-21-2009
20110183516METHODS OF FORMING WIRING STRUCTURES - In a method of forming a wiring structure, a first insulation layer is formed on a substrate, the first insulation layer comprising a group of hydrocarbon (C07-28-2011
20110183515SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon.07-28-2011
20120129342METHOD FOR FABRICATING A SEMICONDUCTOR SUBSTRATE WITH A CO-PLANAR BACKSIDE METALLIZATION STRUCTURE - A method for fabricating a backside metallization structure on a semiconductor substrate including moving a printhead having at least one nozzle orifice relative to the semiconductor substrate, and feeding an Al passivation layer ink and an AgAl soldering pad ink through said printhead such that both said Al passivation layer ink and said AgAl soldering pad ink are simultaneously extruded from said at least one nozzle orifice and deposited onto the semiconductor substrate.05-24-2012
20120129341METHOD FOR FABRICATING VIA HOLE AND THROUGH-SILICON VIA - A method for fabricating a via hole includes forming a first mask pattern on a first surface of a wafer exposing a portion of the first surface of the wafer, forming a passivation region within the wafer by implanting impurities into the exposed portion of the wafer using the first mask pattern as an ion implantation barrier layer, forming an etching stop layer on the first surface of the wafer including the passivation regions, forming a second mask pattern on a second surface of the wafer faces away from the first surface of the wafer, wherein the second mask pattern exposes a portion of the second surface of the wafer over an area between the passivation regions, and forming a via hole by etching the wafer using the second mask pattern as an etching mask.05-24-2012
20120315756PROCESS FOR ELECTROLESS COPPER DEPOSITION ON A RUTHENIUM SEED - Embodiments of the invention provide methods for forming conductive materials within contact features on a substrate by depositing a seed layer within a feature and subsequently filling the feature with a copper-containing material during an electroless deposition process. In one example, a copper electroless deposition solution contains levelers to form convexed or concaved copper surfaces. In another example, a seed layer is selectively deposited on the bottom surface of the aperture while leaving the sidewalls substantially free of the seed material during a collimated PVD process. In another example, the seed layer is conformably deposited by a PVD process and subsequently, a portion of the seed layer and the underlayer are plasma etched to expose an underlying contact surface. In another example, a ruthenium seed layer is formed on an exposed contact surface by an ALD process utilizing the chemical precursor ruthenium tetroxide.12-13-2012
20120315754INTERCONNECTION BARRIER MATERIAL DEVICE AND METHOD - Interconnects containing ruthenium and methods of forming can include utilization of a sacrificial protective material. Planarization or other material removal operations can be performed on a substrate having a recess, the recess containing a ruthenium containing material along with the sacrificial protective material. The protective material is later removed, and a conductor can be filled in the remaining recess.12-13-2012
20120252208METHOD OF FORMING METAL INTERCONNECTIONS OF SEMICONDUCTOR DEVICE - A method of forming a metal interconnection of semiconductor device is provided. The method includes forming a low-k dielectric layer including an opening; forming a barrier metal pattern conformally covering a bottom surface and an inner sidewall of the opening; forming a metal pattern exposing a part of the inner sidewall of the barrier metal pattern in the opening; forming a metal capping layer on the top surfaces of the metal pattern and the low-k dielectric layer using a selective chemical vapor deposition process, wherein the thickness of the metal capping layer on the metal pattern is greater than the thickness of the metal capping layer on the low-k dielectric layer; and forming a metal capping pattern covering the top surface of the metal pattern by planarizing the metal capping layer down to the top surface of the low-k dielectric layer.10-04-2012
20120252206PROCESS FOR DAMASCENE STRUCTURE WITH REDUCED LOW-K DAMAGE - Embodiments described herein generally provide methods for reducing undesired low-k damages during a damascene process using a sacrificial dielectric material and optionally a barrier/capping layer. In one embodiment, a damascene structure is formed through a sacrificial dielectric material deposited over a dielectric base layer. The damascene structure is filled with a suitable metal such as copper. The sacrificial dielectric material filled in trench areas between the copper damascene is then removed, followed by a barrier/cap layer which conformally or selectively covers exposed surfaces of the copper damascene structure. Ultra low-k dielectric materials may then fill the trench areas that were previously filled with sacrificial dielectric material. The invention prevents the ultra low-k material between the metal lines from exposing to various damaging processes during a damascene process such as etching, stripping, wet cleaning, pre-metal cleaning or CMP process.10-04-2012
20120171862INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME - An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon.07-05-2012
20120220120METHOD FOR FABRICATING BURIED BIT LINE IN SEMICONDUCTOR DEVICE - A method for fabricating a buried bit line in a semiconductor device includes forming a liner oxide layer over the entire surface of a substrate having bodies isolated by a trench, selectively etching the liner oxide layer contacted with one side surface of the trench to a given depth, forming a sacrifice layer at a larger height than an etched surface of the liner oxide layer wherein the sacrifice layer partially fills the trench to the larger height, forming a liner nitride layer on sidewalls of the trench over the sacrifice layer, removing the sacrifice layer to expose a part of a body at the one side surface of the trench, forming a barrier layer along the entire surface of the resultant structure including the liner oxide layer, and forming a buried bit line over the barrier layer to be contacted with the exposed part of the body.08-30-2012
20120178256FORMATION OF A TANTALUM-NITRIDE LAYER - A method of forming a material on a substrate is disclosed. In one embodiment, the method includes forming a tantalum nitride layer on a substrate disposed in a plasma process chamber by sequentially exposing the substrate to a tantalum precursor and a nitrogen precursor, followed by reducing a nitrogen concentration of the tantalum nitride layer by exposing the substrate to a plasma annealing process. A metal-containing layer is subsequently deposited on the tantalum nitride layer.07-12-2012
20120178255METHOD FOR IMPROVING WITHIN DIE UNIFORMITY OF METAL PLUG CHEMICAL MECHANICAL PLANARIZATION PROCESS IN GATE LAST ROUTE - A method for improving the within die uniformity of the metal plug CMP process in the gate last route is provided. Before performing the CMP process for forming the metal plug, a metal etching process is applied, so that the step height between the metal layers in the contact hole area and the non-contact hole area is greatly reduced. Therefore, the relatively small step height will exert a significantly less effect on the following CMP process, so that the step height will be limitedly transferred to the top of metal plug after finishing CMP process. In this way, the recess on top of the metal plug is largely reduced, so that a flat top of the metal plug is obtained, and within die uniformity and electrical properties the device are improved.07-12-2012
20120238091SEMICONDUCTOR HAVING A HIGH ASPECT RATIO VIA - The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a method for forming a via structure includes forming a via in a semiconductor substrate, wherein via sidewalls of the via are defined by the semiconductor substrate; forming a dielectric layer on the via sidewalls; removing the dielectric layer from a portion of the via sidewalls; and forming a conductive layer to fill the via, wherein the conductive layer is disposed over the dielectric layer and the portion of the via sidewalls. In an example, the dielectric layer is an oxide layer.09-20-2012
20100009533Conformal Films on Semiconductor Substrates - A layer of diffusion barrier or seed material is deposited on a semiconductor substrate having a recessed feature. The method may include a series of new deposition cycles, for example, a first net deposition cycle and a second net deposition cycle. The first net deposition cycle includes depositing a first deposited amount of the diffusion barrier or seed material and etching a first etched amount of the diffusion barrier or seed material. The second net deposition cycle including depositing a second deposited amount of the diffusion barrier or seed material and etching a second etched amount of the diffusion barrier or seed material. At least one of the process parameters of the first cycle differs from that of the second allows providing a graded deposition effects to reduce a risk of damaging any under layers and dielectric. A deposited layer of diffusion barrier or seed material is generally more conformal.01-14-2010
20090061621METHOD OF FORMING A METAL DIRECTLY ON A CONDUCTIVE BARRIER LAYER BY ELECTROCHEMICAL DEPOSITION USING AN OXYGEN-DEPLETED AMBIENT - By suppressing the presence of free oxygen during a cleaning process and a subsequent electrochemical deposition of a seed layer, the quality of a corresponding interface between the barrier material and the seed layer may be enhanced, thereby also improving performance and the characteristics of the finally obtained metal region. Thus, by identifying free oxygen as a main source for negatively affecting the characteristics of metals during a “direct on barrier” plating process, efficient strategies have been developed and are disclosed herein to provide a reliable technique for volume production of sophisticated semiconductor devices.03-05-2009
20100291767MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In MOSFET having SBD as a protection element, a TiW (alloy having tungsten as a main component) film is used as an aluminum-diffusion barrier metal film below an aluminum source electrode in order to secure properties of SBD. The present inventors have found that a tungsten-based barrier metal film is in the form of columnar grains having a lower barrier property than that of a titanium-based barrier metal film such as TiN so that aluminum spikes are generated relatively easily in a silicon substrate. In the present invention, when a tungsten-based barrier metal film is formed by sputtering as a barrier metal layer between an aluminum-based metal layer and a silicon-based semiconductor layer therebelow, the lower layer is formed by ionization sputtering while applying a bias to the wafer side and the upper layer is formed by sputtering without applying a bias to the wafer side.11-18-2010
20120220121FILM FORMING METHOD AND STORAGE MEDIUM - In a film forming method for forming a Co film on a substrate provided in a processing chamber, gaseous Co08-30-2012
20120083117Method Of Forming Hardened Porous Dielectric Layer And Method Of Fabricating Semiconductor Device Having Hardened Porous Dielectric Layer - Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.04-05-2012
20120083116Cost-Effective TSV Formation - A device includes a substrate having a first surface, and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the substrate. A dielectric layer is disposed over the substrate. A metal pad is disposed in the dielectric layer and physically contacting the TSV, wherein the metal pad and the TSV are formed of a same material, and wherein no layer formed of a material different from the same material is between and spacing the TSV and the metal pad apart from each other.04-05-2012
20120264290METHOD AND APPARATUS FOR FILLING INTERCONNECT STRUCTURES - Methods, apparatus, and systems for depositing copper and other metals are provided. In some implementations, a wafer substrate is provided to an apparatus. The wafer substrate has a surface with field regions and a feature. A copper layer is plated onto the surface of the wafer substrate. The copper layer is annealed to redistribute copper from regions of the wafer substrate to the feature. Implementations of the disclosed methods, apparatus, and systems allow for void-free bottom-up fill of features in a wafer substrate.10-18-2012
20120231626FORMATION OF LINER AND BARRIER FOR TUNGSTEN AS GATE ELECTRODE AND AS CONTACT PLUG TO REDUCE RESISTANCE AND ENHANCE DEVICE PERFORMANCE - The invention provides a method of forming a film stack on a substrate, comprising performing a silicon containing gas soak process to form a silicon containing layer over the substrate, reacting with the silicon containing layer to form a tungsten silicide layer on the substrate, depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer.09-13-2012
20110124192PROCESS FOR FORMING COBALT-CONTAINING MATERIALS - Embodiments of the invention described herein generally provide methods and apparatuses for forming cobalt silicide layers, metallic cobalt layers, and other cobalt-containing materials. In one embodiment, a method for forming a cobalt silicide containing material on a substrate is provided which includes exposing a substrate to at least one preclean process to expose a silicon-containing surface, depositing a cobalt silicide material on the silicon-containing surface, depositing a metallic cobalt material on the cobalt silicide material, and depositing a metallic contact material on the substrate. In another embodiment, a method includes exposing a substrate to at least one preclean process to expose a silicon-containing surface, depositing a cobalt silicide material on the silicon-containing surface, expose the substrate to an annealing process, depositing a barrier material on the cobalt silicide material, and depositing a metallic contact material on the barrier material.05-26-2011
20110124191COMPOSITIONS FOR THE CURRENTLESS DEPOSITION OF TERNARY MATERIALS FOR USE IN THE SEMICONDUCTOR INDUSTRY - The present invention relates to the use of ternary nickel-containing metal alloys of the NiMR type (where M=Mo, W, Re or Cr, and R=B or P) deposited by an electroless process in semiconductor technology. In particular, the present invention relates to the use of these deposited ternary nickel-containing metal alloys as barrier material or as selective encapsulation material for preventing the diffusion and electromigration of copper in semiconductor components.05-26-2011
20080299766METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, includes forming a first dielectric film above a substrate, forming an opening in the first dielectric film, forming a catalytic characteristic film using at least one of a metal having catalytic characteristics and a conductive oxide having catalytic characteristics as its material on sidewalls and at a bottom of the opening, depositing a conductive material film using a conductive material in the opening in which the catalytic characteristic film is formed on the sidewalls and at the bottom, removing the catalytic characteristic film formed on the sidewalls of the opening, and forming a second dielectric film above the first dielectric film and the conductive material film after the removing.12-04-2008
20080299765Method of Fabricating a Structure for a Semiconductor Device - There is described a method of fabricating a dual damascene structure for a semiconductor device. A halogen based pre-cursor is used during vapour deposition of a diffusion barrier layer in a trench or via formed in a substrate. Residual halogen from the deposition is allowed to remain on the barrier layer and is used to catalyse growth of a metal layer on the barrier layer to fill the trench or via.12-04-2008
20120264292REDUNDANT METAL BARRIER STRUCTURE FOR INTERCONNECT APPLICATIONS - A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier layer is located within an opening that is located within a dielectric material and it is between a diffusion barrier layer and a conductive material which are also present within the opening. The redundant diffusion barrier includes a single layered or multilayered structure comprising Ru and a Co-containing material including pure Co or a Co alloy including at least one of N, B and P.10-18-2012
20120264291PROCESS FOR FORMING COBALT-CONTAINING MATERIALS - Embodiments of the invention described herein generally provide methods and apparatuses for forming cobalt silicide layers, metallic cobalt layers, and other cobalt-containing materials. In one embodiment, a method for forming a cobalt silicide containing material on a substrate is provided which includes exposing a substrate to at least one preclean process to expose a silicon-containing surface, depositing a cobalt silicide material on the silicon-containing surface, depositing a metallic cobalt material on the cobalt silicide material, and depositing a metallic contact material on the substrate. In another embodiment, a method includes exposing a substrate to at least one preclean process to expose a silicon-containing surface, depositing a cobalt silicide material on the silicon-containing surface, expose the substrate to an annealing process, depositing a barrier material on the cobalt silicide material, and depositing a metallic contact material on the barrier material.10-18-2012
20110003475SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for producing a semiconductor device including a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of the contact hole; a zirconium oxide film disposed on a side surface of the contact hole and a side surface and a bottom surface of the trench; a zirconium film disposed on the zirconium oxide film inside the contact hole and inside the trench; and a second conductor composed of Cu embedded into the contact hole and into the trench.01-06-2011
20110003473STRUCTURE FOR METAL CAP APPLICATIONS - An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material.01-06-2011
20110045670METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE FOR PREVENTING OCCURRENCE OF SHORT CIRCUIT BETWEEN BIT LINE CONTACT PLUG AND STORAGE NODE CONTACT PLUG - A method for manufacturing a semiconductor device includes the steps of forming a plug on a semiconductor substrate, forming an insulation layer over the semiconductor substrate having the plug formed thereon, defining a line type trench through a first etching of a partial thickness of the insulation layer; and defining a contact hole through a second etching of a portion of the insulation layer corresponding to the bottom of the trench so as to expose the plug.02-24-2011
20110045669METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnO02-24-2011
20120270391SCHEME FOR PLANARIZING THROUGH-SILICON VIAS - Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method disclosed herein includes forming a layer of isolation material above a via opening formed in a semiconductor device, the via opening extending into a substrate of the semiconductor device. The method also includes performing a first planarization process to remove at least an upper portion of the layer of isolation material formed outside of the via opening, and forming a conductive via element inside of the via opening after performing the first planarization process.10-25-2012
20110237072INTEGRATED CIRCUIT SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.09-29-2011
20110237071COPPER WIRING SURFACE PROTECTIVE LIQUID AND METHOD FOR MANUFACTURING SEMICONDUCTOR CIRCUIT - A copper wiring material surface protective liquid for production of a semiconductor device is provided, containing an oxyalkylene adduct of an acetylenediol containing an acetylenediol having an oxyalkylene having 2 or 3 carbon atoms added thereto. A method for producing a semiconductor circuit device is provided, containing: forming an insulating film and/or a diffusion preventing film on a silicon substrate; then forming a copper film by a sputtering method; then forming a copper wiring containing 80% by mass or more of copper thereon by a plating method; and flattening the wiring by a chemical mechanical polishing (CMP) method, thereby providing a semiconductor substrate containing a copper wiring, the semiconductor substrate having an exposed surface of a copper wiring material being treated by making in contact with the copper wiring material surface protective liquid.09-29-2011
20120276737POST-ETCHING TREATMENT PROCESS FOR COPPER INTERCONNECTING WIRES - A method for post-etching treatment of copper interconnecting wires that are used to electrically couple an upper interconnecting layer with a lower interconnecting layer includes forming the lower interconnecting layer on a substrate, and forming the upper interconnecting layer on the lower interconnecting layer. The lower interconnecting layer includes a first dielectric layer, a plurality of wire trenches formed in the first dielectric layer and being filled with copper, and a first top barrier layer overlying the first dielectric layer and the wire trenches. The upper interconnecting layer includes a second dielectric layer on the top barrier layer, and a plurality of vias extending through the second dielectric layer and the top barrier layer and exposing the copper in the wire trenches. The method further includes treating the exposed copper using a plasma process comprising NH11-01-2012
20120329272METHOD FOR FORMING SMALL DIMENSION OPENINGS IN THE ORGANIC MASKING LAYER OF TRI-LAYER LITHOGRAPHY - A method for forming small dimension openings in the organic masking layer of tri-layer lithography. The method includes forming an organic polymer layer over a semiconductor substrate; forming a silicon containing antireflective coating on the organic polymer layer; forming a patterned photoresist layer on the antireflective coating, the patterned photoresist layer having an opening therein; performing a first reactive ion etch to transfer the pattern of the opening into the antireflective coating to form a trench in the antireflective coating, the organic polymer layer exposed in a bottom of the trench; and performing a second reactive ion etch to extend the trench into the organic polymer layer, the second reactive ion etch forming a polymer layer on sidewalls of the trench, the second reactive ion etch containing a species derived from a gaseous hydrocarbon.12-27-2012
20120329273HOMOGENEOUS POROUS LOW DIELECTRIC CONSTANT MATERIALS - In one exemplary embodiment, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to an exposed surface of the first layer; heating the structure to a first temperature to enable the filling material to homogeneously fill the plurality of pores; after filling the plurality of pores, performing at least one first process on the structure; after performing the at least one first process, removing the filling material from the plurality of pores by heating the structure to a second temperature to decompose the filling material; and after removing the filling material from the plurality of pores, performing at least one second process on the structure, where the at least one second process is performed at a third temperature that is greater than the second temperature.12-27-2012
20100190335Method of manufacturing semiconductor device - In a method of manufacturing a semiconductor device according to the present invention, a wiring trench is formed on the surface of an insulating film, and the inner surface of this wiring trench is thereafter coated with an alloy film made of an alloy material containing copper and a prescribed metallic element. After this coating with the alloy film, a copper film is laminated on the insulating film to fill up the wiring trench. Then, unnecessary portions of the copper film outside the wiring trench are removed, so that the surface of the copper film remaining in the wiring trench is generally flush with the surface of the insulating film. Thereafter heat treatment is performed. The prescribed metallic element is deposited on the wiring trench due to this heat treatment. Then, the prescribed metallic element deposited on the wiring trench is removed.07-29-2010
20100167531SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same includes sequentially laminating a first dielectric film, an etch-blocking film and a second dielectric film on and/or over a semiconductor substrate, forming a photosensitive film mask to open a trench region in the second dielectric film, etching the second dielectric film using the photosensitive film mask as an etching mask until the etch-blocking film is exposed to form the trench, and then forming a copper metal layer in the trench at uniform thickness.07-01-2010
20100130006METHOD AND STRUCTURE OF A THICK METAL LAYER USING MULTIPLE DEPOSITION CHAMBERS - A thick metal layer is formed on a semiconductor integrated circuit in multiple different deposition chambers. A first portion of the metal layer is formed in a first deposition chamber, the first thickness being approximately half the target thickness. The substrate is then removed from the first chamber and transported to a second chamber. The deposition of the same metal layer continues in a second chamber, having the same grain structure and orientation. The second portion of the metal layer is grown to achieve the final thickness. By using two different deposition chambers to form the single metal layer, layers in excess of 25,000 angstroms in thickness can be obtained.05-27-2010
20080227290Semiconductor Device and Method for Fabricating the Same - A method of fabricating a semiconductor device includes forming a barrier film over a semiconductor substrate and over a gate disposed on the substrate; forming a metal layer over the barrier film; selectively etching the metal layer and the barrier film to form a contact pattern between the gates; forming a spacer over a sidewall of the contact pattern; forming an interlayer insulating film over the contact pattern and the gate; and polishing the interlayer insulating film to expose the contact pattern.09-18-2008
20110263119METHOD OF FORMING NANOSCALE THREE-DIMENSIONAL PATTERNS IN A POROUS MATERIAL - A method of forming a nanoscale three-dimensional pattern in a porous semiconductor includes providing a film comprising a semiconductor material and defining a nanoscale metal pattern on the film, where the metal pattern has at least one lateral dimension of about 100 nm or less in size. Semiconductor material is removed from below the nanoscale metal pattern to create trenches in the film having a depth-to-width aspect ratio of at least about 10:1, while pores are formed in remaining portions of the film adjacent to the trenches. A three-dimensional pattern having at least one nanoscale dimension is thus formed in a porous semiconductor, which may be porous silicon. The method can be extended to form self-integrated porous low-k dielectric insulators with copper interconnects, and may also facilitate wafer level chip scale packaging integration.10-27-2011
20080248644METHOD OF FABRICATING A SEMICONDUCTOR DEVICE WITH A POROUS DIELECTRIC FILM - In the fabrication of a semiconductor device, an SiO10-09-2008
20130178060Method for Manufacturing a Barrier Layer on a Substrate and a Multi-Layer Stack - A method for manufacturing a barrier layer (07-11-2013
20130178059MANUFACTURING METHOD AND MANUFACTURING APPARATUS OF DEVICE - A manufacturing method of a device including: a first process in which a barrier film is formed on a substrate with a concave portion provided on one surface thereof so as to cover an inner wall surface of the concave portion; a second process in which a conductive film is formed so as to cover the barrier film; and a third process in which the conductive film is melted by a reflow method, wherein the method includes a process α between the second process and the third process, in which the substrate with the barrier film and the conductive film laminated thereon in this order is exposed to an atmosphere under a pressure A for a time period B, and wherein in the process α, control is carried out such that a product of the pressure A and the time period B is not greater than 6×1007-11-2013
20120252207POST DEPOSITION TREATMENTS FOR CVD COBALT FILMS - Embodiments of the invention provide methods for forming materials on a substrate used for metal gate and other applications. In one embodiment, a method includes forming a cobalt stack over a barrier layer disposed on a substrate by depositing a cobalt layer during a deposition process, exposing the cobalt layer to a plasma to form a plasma-treated cobalt layer during a plasma process, and repeating the cobalt deposition process and the plasma process to form the cobalt stack containing a plurality of plasma-treated cobalt layers. The method further includes exposing the cobalt stack to an oxygen source gas to form a cobalt oxide layer from an upper portion of the cobalt stack during a surface oxidation process and heating the remaining portion of the cobalt stack to a temperature within a range from about 300° C. to about 500° C. to form a crystalline cobalt film during a thermal annealing crystallization process.10-04-2012
20080213996Designs and methods for conductive bumps - Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.09-04-2008
20080213995Ultrasonic electropolishing of conductive material - In one embodiment, the present invention includes a method for forming a dielectric layer on a semiconductor wafer and patterning at least one opening in the dielectric layer, depositing a barrier layer over the dielectric layer, depositing a conductive layer over the barrier layer, and electropolishing the conductive layer while ultrasonically agitating the semiconductor wafer until a predetermined amount of the conductive layer remains over the barrier layer. Other embodiments are described and claimed.09-04-2008
20130102148Interconnect Structure for Semiconductor Devices - A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.04-25-2013
20080200027METHOD OF FORMING METAL WIRE IN SEMICONDUCTOR DEVICE - The present invention discloses a method of forming a metal wire in a semiconductor device and comprises the steps of forming a first insulating layer, a conductive layer and a capping layer on a semiconductor substrate, forming hard mask patterns on the capping layer, etching the capping layer and the conductive layer through an etching process utilizing the hard mask patterns to form metal wires, removing the hard mask patterns and forming a second insulating layer on the semiconductor substrate including the metal wires to insulate the metal wires from each other.08-21-2008
20110223760 CONFORMALITY OF OXIDE LAYERS ALONG SIDEWALLS OF DEEP VIAS - A method for improving conformality of oxide layers along sidewalls of vias in semiconductor substrates includes forming a nitride layer over an upper surface of a semiconductor substrate and forming a via extending through the nitride layer and into the semiconductor substrate. The via may have a depth of at least about 50 μm from a top surface of the nitride layer and an opening of less than about 10 μm at the top surface of the nitride layer. The method also includes forming an oxide layer over the nitride layer and along sidewalls and bottom of the via. The oxide layer may be formed using a thermal chemical vapor deposition (CVD) process at a temperature of less than about 450° C., where a thickness of the oxide layer at the bottom of the via is at least about 50% of a thickness of the oxide layer at the top surface of the nitride layer.09-15-2011
20130203250SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes: modifying a surface of a burying recess, of which surface is hydrophobic and which is formed in a dielectric film, to a hydrophilic state by supplying a plasma containing H ions and H radicals or a plasma containing NHx (x being 1, 2 or 3) ions and NHx radicals to the dielectric film formed on a substrate and containing silicon, carbon, hydrogen and oxygen, a bottom portion of the burying recess being exposed with a lower conductive layer; and directly forming an adhesion film formed of a Ru film on the hydrophilic surface of the recess. The method further includes burying copper forming a conductive path in the recess.08-08-2013
20100081277METHOD FOR PASSIVATING EXPOSED COPPER SURFACES IN A METALLIZATION LAYER OF A SEMICONDUCTOR DEVICE - When forming sophisticated metallization systems, surface integrity of an exposed metal surface, such as a copper-containing surface, may be enhanced by exposing the surface to a vapor of a passivation agent. Due to the corresponding interaction with the metal surface, enhanced integrity may be accomplished, while at the same time damage of exposed dielectric surface portions may be significantly reduced compared to conventional aggressive wet chemical cleaning processes that are typically used in conventional patterning regimes.04-01-2010
20110256716Method of depositing a uniform barrier layer and metal seed layer with reduced overhang over a plurality of recessed semiconductor features - A method of depositing a metal seed layer with underlying barrier layer on a wafer substrate comprising a plurality of recessed device features. A first portion of the barrier layer is deposited on the wafer substrate without excessive build-up of barrier layer material on the openings to the plurality of recessed device features, while obtaining bottom coverage without substantial sputtering of the bottom surface. Subsequently, a metal seed layer is deposited using the same techniques used to deposit the barrier layer, to avoid excessive build up of metal seed layer material on the openings to the features, with minimal sputtering of the barrier layer surface.10-20-2011
20080274611METHOD AND PROCESS FOR FORMING A SELF-ALIGNED SILICIDE CONTACT - The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO11-06-2008
20120258590CHEMICAL MECHANICAL POLISHING (CMP) PROCESSING OF THROUGH-SILICON VIA (TSV) AND CONTACT PLUG SIMULTANEOUSLY - A method includes forming conductive material in a contact hole and a TSV opening, and then performing one step to remove portions of the conductive material outside the contact hole and the TSV opening to leave the conductive material in the contact hole and the TSV opening, thereby forming a contact plug and a TSV structure, respectively. In some embodiments, the removing step is performed by a CMP process.10-11-2012
20120258589METHOD OF FABRICATING COAXIAL THROUGH-SILICON VIA - A method of fabricating a through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage.10-11-2012
20100317189METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a method for manufacturing a semiconductor device which is decreased in resistance of a copper wiring containing a ruthenium-containing film and a copper-containing film, thereby having improved reliability. Also disclosed is an apparatus for manufacturing a semiconductor device. Specifically, an Ru film is formed on a substrate having a recessed portion by a CVD method using a raw material containing an organic ruthenium complex represented by the general formula and a reducing gas (step S12-16-2010
20120282768Schemes for Forming Barrier Layers for Copper in Interconnect Structures - A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.11-08-2012
20130157458SEMICONDUCTOR DEVICE HAVING A COPPER PLUG - Disclosed is a process of making a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. There may also be a cap layer over the copper plug to protect it from oxidation. There may also be a dielectric layer over the cap layer.06-20-2013
20130183824METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a first layer including a first metal, forming a second layer including a second metal, the second layer being adjacent to the first layer, polishing top surfaces of the first and second layers, and cleaning the first and second layers using a cleaning solution. The cleaning solution may include an etching solution etching the first and second layers and an inhibitor suppressing the second layer from being over etched.07-18-2013
20110306203INTERCONNECT STRUCTURE AND METHOD OF MANUFACTURING A DAMASCENE STRUCTURE - An interconnect structure is provided, including a layer of dielectric material having at least one opening and a first barrier layer on sidewalls defining the opening. A ruthenium-containing second barrier layer overlays the first barrier layer, the second barrier layer having a ruthenium zone, a ruthenium oxide zone, and a ruthenium-rich zone. The ruthenium zone is interposed between the first barrier layer and the ruthenium oxide zone. The ruthenium oxide zone is interposed between the ruthenium zone and the ruthenium-rich zone.12-15-2011
20120028463MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS - A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.02-02-2012
20120028462METHOD FOR FORMING CU FILM AND STORAGE MEDIUM - In a method for forming a Cu film, a CVD Cu film is formed on a CVD-Ru film that is formed on a wafer W. In the method, the wafer W having the CVD-Ru film is loaded into a chamber 1, and a film-forming source material in a vapor state is introduced into the chamber 1. The film-forming source material includes Cu(hfac)TMVS that is a Cu complex having a vapor pressure higher than that of Cu(hfac)02-02-2012
20130196502SELECTIVE FORMATION OF METALLIC FILMS ON METALLIC SURFACES - Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In some embodiments, a first precursor forms a layer on the first surface and is subsequently reacted or converted to form a metallic layer. The deposition temperature may be selected such that a selectivity of above about 50% or even about 90% is achieved.08-01-2013
20130196503SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first conductor formed over a semiconductor device; an insulation film formed over the semiconductor substrate and the first conductor and having an opening arriving at the first conductor; a first film formed in the opening and formed of a compound containing Zr; a second film formed over the first film in the opening and formed of an oxide containing Mn; and a second conductor buried in the opening and containing Cu.08-01-2013
20090075475METHOD OF SUBSTRATE TREATMENT, PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE, SUBSTRATE TREATING APPARATUS, AND RECORDING MEDIUM - Substrate processing apparatus 03-19-2009
20120070982METHODS FOR FORMING LAYERS ON A SUBSTRATE - Methods for forming layers on a substrate having one or more features formed therein are provided herein. In some embodiments, a method for forming layers on a substrate having one or more features formed therein may include depositing a seed layer within the one or more features; and etching the seed layer to remove at least a portion of the seed layer proximate an opening of the feature such that the seed layer comprises a first thickness disposed on a lower portion of a sidewall of the feature proximate a bottom of the feature and a second thickness disposed on an upper portion of the sidewall proximate the opening of the feature and wherein the first thickness is greater than the second thickness.03-22-2012
20120070981ATOMIC LAYER DEPOSITION OF A COPPER-CONTAINING SEED LAYER - The present disclosure relates to the field of microelectronic device fabrication and, more particularly, to the formation of copper-containing seed layers for the fabrication of interconnects in integrated circuits. The copper-containing seed layers may be formed in an atomic layer deposition process with a copper pre-cursor and organometallic co-reagent.03-22-2012
20120094483FILM FORMING METHOD, FILM FORMING APPARATUS AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for forming a film includes the steps of: placing an object to be processed into a processing container; and generating M(BH04-19-2012
20130210225METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes etching a substrate to form a pillar isolated by a trench, forming a buffer layer along the entire structure including the pillar, forming a diffusion barrier layer that exposes a portion of the buffer layer at a first sidewall of the pillar, forming a liner layer along the entire structure including the diffusion barrier layer, selectively ion-implanting dopants into the liner layer, and forming a junction in the first sidewall of the pillar by diffusing the dopants through a thermal process.08-15-2013

Patent applications in class At least one layer forms a diffusion barrier