Class / Patent application number | Description | Number of patent applications / Date published |
438629000 | Diverse conductive layers limited to viahole/plug | 12 |
20090098728 | STRUCTURE CU LINER FOR INTERCONNECTS USING A DOUBLE-BILAYER PROCESSING SCHEME - The disclosed method forms a via between metallization layers in a semiconductor structure by patterning an insulator layer overlying a first metallization layer to include a via opening. The method lines the via opening with TaN and Ta liners and then sputter etches the via opening deeper through the TaN and Ta liners into the first metallization layer. After sputter etching, the method then lines the via opening with second TaN and Ta liners. Next, the method deposits a conductor into the via opening, thereby connecting the first and second metallization layers. | 04-16-2009 |
20090111262 | MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION - A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated. | 04-30-2009 |
20100136782 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a manufacturing process of a semiconductor device, electroplating and CMP have had a problem of increase in manufacturing costs for forming a wiring. Correspondingly, an opening is formed in a porous insulating film after a mask is formed thereover, and a conductive material containing Ag is dropped into the opening. Further, a first conductive layer is formed by baking the conductive material dropped into the opening by selective irradiation with laser light. Subsequently, a metal film is formed over the entire surface by sputtering, and the mask is removed thereafter to have only the metal film remain over the first conductive layer, thereby forming an embedded wiring layer formed with a stack of the first conductive layer containing Ag and the second conductive layer (metal film). | 06-03-2010 |
20110129995 | MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION - A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated. | 06-02-2011 |
20120156871 | METHODS FOR FORMING CONDUCTIVE VIAS IN SEMICONDUCTOR DEVICE COMPONENTS - A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer, may be formed on surfaces of each hole. Surfaces within each hole may be coated with a seed layer, which facilitates adhesion of conductive material within each hole. Conductive material is introduced into each hole. Introduction of the conductive material may be effected by deposition or plating. Alternatively, conductive material in the form of solder may be introduced into each hole. | 06-21-2012 |
20140154879 | METHODS OF FORMING INTERCONNECTS AND SEMICONDUCTOR STRUCTURES - A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed. | 06-05-2014 |
20160197010 | SEMICONDUCTOR DEVICE WITH REDUCED VIA RESISTANCE | 07-07-2016 |
20180025943 | ALIGNING CONDUCTIVE VIAS WITH TRENCHES | 01-25-2018 |
438630000 | Silicide formation | 4 |
20090317972 | METHOD OF FORMING A METAL SILICIDE LAYER, DEVICES INCORPORATING METAL SILICIDE LAYERS AND DESIGN STRUCTURES FOR THE DEVICES - Methods of forming metal silicide layers. The methods include: forming a silicon-rich layer between dielectric layers; contacting the silicon-rich layer with a metal layer and heating the silicon rich-layer and the metal layer to diffuse metal atoms from the metal layer into the silicon layer to form a metal silicide layer. | 12-24-2009 |
20090317973 | METHOD OF FORMING A METAL SILICIDE LAYER, DEVICES INCORPORATING METAL SILICIDE LAYERS AND DESIGN STRUCTURES FOR THE DEVICES - Electronic devices and design structures of electronic devices containing metal silicide layers. The devices include: a thin silicide layer between two dielectric layers, at least one metal wire abutting a less than whole region of the silicide layer and in electrical contact with the silicide layer. | 12-24-2009 |
20130130495 | Method For Fabricating A Metal Silicide Interconnect In 3D Non-Volatile Memory - A method for fabricating a metal silicide interconnect in a stacked 3D non-volatile memory array. A stack of alternating layers of undoped/lightly doped polysilicon and heavily doped polysilicon is formed on a substrate. Memory holes are etched in cell areas of the stack while an interconnect area is protected. Slits are etched in the cell areas and the interconnect areas. A wet etch is performed via the slits or the memory holes in the cell area to remove portions of the undoped/lightly doped polysilicon layers in the cell area, and dielectric is deposited. Silicidation transforms portions of the heavily doped polysilicon layers in the cell area to metal silicide, and transforms portions of the heavily doped and undoped/lightly doped polysilicon layers in the interconnect area to metal silicide. The metal silicide interconnect can be used for routing power and control signals from below the stack to above the stack. | 05-23-2013 |
20130252416 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. | 09-26-2013 |