| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438614000 | Plural conductive layers | 59 |
| 20110177686 | Stable Gold Bump Solder Connections - A metallic interconnect structure ( | 07-21-2011 |
| 20100041226 | Process For Through Silicon Via Filing - A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. Low copper concentration and high acidity electroplating solution is used for deposition copper into the through silicon vias. | 02-18-2010 |
| 20090124075 | Method of manufacturing a wafer level package - A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved. | 05-14-2009 |
| 20130052817 | METHOD FOR THE FABRICATION OF BONDING SOLDER LAYERS ON METAL BUMPS WITH IMPROVED COPLANARITY - A method for fabrication of bonding solder layers on metal bumps with improved coplanarity, applicable to the flip-chip bump bonding technique for semiconductor IC packaging. When metal bumps have different sizes, the bonding solders thereon may have different heights after high-temperature reflows. The present invention can improve the coplanarity of bonding solders, and mitigating or even eliminating the difficulties in downstream packaging and testing caused by the inconsistent height of bonding solders. To achieve this purpose, the present invention proposes a two-step fabrication method for controlling the surface areas of the metal bumps and the bonding solder layers thereon separately, and thereby improving the coplanarity of the bonding solders after high-temperature reflows. The two-step fabrication method includes: a first-step process for forming metal bumps on the semiconductor devices; and a second-step process for forming bonding solder layers of different sizes on the metal bumps. | 02-28-2013 |
| 20090093111 | SPROCKET OPENING ALIGNMENT PROCESS AND APPARATUS FOR MULTILAYER SOLDER DECAL - A process for aligning at least two layers in an abutting relationship with each other comprises forming a plurality of sprocket openings in each of the layers for receiving a sprocket of diminishing diameters as the sprocket extends outwardly from a base, with the center axes of the sprocket openings in each layer being substantially alignable with one another, the diameter of the sprocket openings in an abutting layer for first receiving the sprocket being greater than the diameter of the sprocket openings in an abutted layer. This is followed by forming a plurality of reservoir openings in each of at least two of the layers and positioning the sprocket openings in the layers to correspond with one another and the reservoir openings in the layers to correspond with one another so that substantial alignment of the center axes of the corresponding sprocket openings in the layers effects substantial alignment of the center axes of the corresponding reservoir openings in the layers. Engaging the sprocket openings with the sprocket by inserting the end of the sprocket having the smallest diameter into the sprocket openings having the largest diameter in the layers and continuing through to the sprocket opening having the smallest diameter in the layers effects substantial alignment of the center axes of the corresponding sprocket openings and substantial alignment of the center axes of the corresponding reservoir openings in the layers. The invention also comprises apparatus-for performing this process. | 04-09-2009 |
| 20090017610 | Junction structure of terminal pad and solder, semiconductor device having the junction structure, and method of manufacturing the semiconductor device - The present invention provides a semiconductor device which comprises a terminal pad ( | 01-15-2009 |
| 20090098724 | Method Of Forming Metallic Bump And Seal For Semiconductor Device - The method mainly contains the following steps. First, an UBM is formed on a top side of a semiconductor's I/O pad. An isolative layer and a metallic foil are sequentially arranged in this order on the UBM. Then, a via is formed to expose the top surface of the UBM. Subsequently, a thin metallic layer is formed in the via and a resist is formed on the metallic foil. Then, by using the metallic foil and the thin metallic layer as an electrode to conduct electrical current, a metallic bump is formed using electroplating in the via on the top side of the UBM. Finally, the resist and the metallic foil are removed and the formation of the metallic bump is completed. Optionally coating on bump may be needed for certain chosen bump materials. | 04-16-2009 |
| 20090098723 | Method Of Forming Metallic Bump On I/O Pad - The method mainly contains the following steps. First, an UBM is formed on a top side of a semiconductor's I/O pad. An isolative layer and a metallic foil are sequentially arranged in this order on the UBM. Then, a via is formed to expose the top surface of the UBM. Subsequently, a thin metallic layer is formed in the via and a resist is formed on the metallic foil. Then, by using the metallic foil and the thin metallic layer as an electrode to conduct electrical current, a metallic bump is formed using electroplating in the via on the top side of the UBM. Finally, the resist and the metallic foil are removed and the formation of the metallic bump is completed. | 04-16-2009 |
| 20100087058 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first electronic circuit component and a second electronic circuit component are electrically connected to an electro-conductive member via a first solder and a second solder, respectively. The electro-conductive member is formed in a resin film. The electro-conductive member is configured as containing a second diffusion barrier metal film. The second diffusion barrier metal film prevents diffusion of the second solder. Between the electro-conductive member and the first solder, a first diffusion barrier metal film is provided. The first diffusion barrier metal film prevents diffusion of the first solder. On the first surface of the resin film and on the electro-conductive member, an adhesive metal film is formed so as to contact with the resin film and the electro-conductive member. The adhesive metal film has stronger adhesiveness to the resin film than either of those of the first solder and the first diffusion barrier metal film. | 04-08-2010 |
| 20100099250 | Methods of Forming Integrated Circuit Contact Pads Using Electroless Plating of Diffusion Barrier Layers - Methods of forming a contact pad include forming a copper pattern on a semiconductor substrate and forming a passivation layer on the copper pattern. The passivation layer is defined to have an opening therein that exposes at least a portion of an upper surface of the copper pattern. A diffusion barrier layer is formed in the opening by electroless plating the diffusion barrier layer onto the exposed portion of the upper surface of the copper pattern. This diffusion barrier layer operates as a barrier to copper out-diffusion from the copper pattern. These methods further include conformally depositing an underbump metallization layer onto at least a sidewall of the opening in the passivation layer and onto an upper surface of the diffusion barrier layer. A step is then performed to plate a contact bump (e.g., solder bump) onto a portion of the underbump metallization layer extending opposite the diffusion barrier layer. | 04-22-2010 |
| 20110201196 | METHOD FOR PRODUCING A METAL CONTACT ON A SEMICONDUCTOR SUBSTRATE PROVIDED WITH A COATING - A method for producing an electrically conducting metal contact on a semiconductor component having a coating on the surface of a semiconductor substrate. In order to keep transfer resistances low while maintaining good mechanical strength, the invention proposes applying a particle-containing fluid onto the coating, where the particles contain at least metal particles and glass frits, curing the fluid while simultaneously forming metal areas in the substrate through heat treatment, removing the cured fluid and the areas of the coating covered by the fluid, and depositing, for the purposes of forming the contact without using intermediate layers, electrically conducting material from a solution onto areas of the semiconductor component in which the coating is removed while at the same time conductively connecting the metal areas present in said areas on the substrate. | 08-18-2011 |
| 20080206979 | INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION BARRIER LAYERS - An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. | 08-28-2008 |
| 20110171822 | METHOD OF MANUFACTURING AN INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE - A method of manufacturing an interconnect structure for a semiconductor device having a device substrate is provided. The semiconductor device includes an electrically-conductive pad formed overlying the device substrate and an electrically-conductive platform formed overlying the electrically-conductive pad and enclosing a cavity. The electrically-conductive platform has a perimeter portion extending away from the electrically-conductive pad and a capping portion atop the perimeter portion. The semiconductor device also includes a cushioning material disposed in the cavity. | 07-14-2011 |
| 20090137110 | LOW FABRICATION COST, HIGH PERFORMANCE, HIGH RELIABILITY CHIP SCALE PACKAGE - The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed. | 05-28-2009 |
| 20090291554 | SEMICONDUCTOR CHIP AND METHOD FOR FABRICATING THE SAME - A semiconductor chip includes a silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure, a polymer bump over said passivation layer, wherein said polymer bump has a thickness of between 5 and 25 micrometers, an adhesion/barrier layer on said pad exposed by said opening, over said passivation layer and on a top surface and a portion of sidewall(s) of said polymer bump, a seed layer on said adhesion/barrier layer; and a third metal layer on said seed layer. | 11-26-2009 |
| 20120295434 | SOLDER COLLAPSE FREE BUMPING PROCESS OF SEMICONDUCTOR DEVICE - A method of forming bumps of a semiconductor device with reduced solder bump collapse. The method includes preparing a semiconductor substrate in which pads are exposed externally from a passivation layer; forming a seed layer on the semiconductor substrate; forming a photoresist pattern to expose the seed layer on the pads; forming pillars by performing a primary electroplating on a region exposed by the photoresist pattern; forming a solder layer by performing a secondary electroplating on the pillars; removing the photoresist pattern; forming solder bumps, in which solders partially cover surfaces of the pillars, by performing a reflow process on the semiconductor substrate; and removing portions of the seed layer formed in regions other than the solder bumps. | 11-22-2012 |
| 20090061614 | METHOD FOR FORMING BUMPS ON UNDER BUMP METALLURGY - A method for forming a bump on under bump metallurgy according to the present invention is provided. A bonding pad is first formed on the active surface of a wafer. Subsequently, a passivation layer is formed on the active surface of the wafer and exposes the bonding pad. An under bump metallurgy is formed on the bonding pad. A layer of film is formed on the passivation layer and overlays the under bump metallurgy. Afterward, the portion of the film on the under bump metallurgy is exposed to a UV light and the exposed portion of the film is removed to expose the under bump metallurgy. A solder paste is applied to the under bump metallurgy and the remaining film on the wafer is removed. Finally, the solder paste is reflowed to form a spherical bump. | 03-05-2009 |
| 20090221142 | Method of forming a metal bump on a semiconductor device - An uppermost one of multilayered electrode pads, on which a bump and a plating coat will be formed, is made of metal having high ionization tendency, particularly, Al. On the other hand, an uppermost one of multilayered electrode pads, on which none of the bump and the plating coat will be formed, is made of metal having low ionization tendency, particularly, Cu. | 09-03-2009 |
| 20100190332 | Method of Forming a Copper Topped Interconnect Structure that has Thin and Thick Copper Traces - A copper-topped interconnect structure allows the combination of high density design areas, which have low current requirements that can be met with tightly packed thin and narrow copper traces, and low density design areas, which have high current requirements that can be met with more widely spaced thick and wide copper traces, on the same chip. | 07-29-2010 |
| 20090111260 | ELECTRONIC COMPONENT, SEMICONDUCTOR DEVICE, METHODS OF MANUFACTURING THE SAME, CIRCUIT BOARD, AND ELECTRONIC INSTRUMENT - The present invention is a method of manufacturing a semiconductor device, by forming a wiring on or above a wafer so that the wiring is electrically connected to a first electrode disposed on a first surface of the wafer, forming a first resin layer on or above the wafer such that the wiring is disposed between the wafer and the first resin layer, forming an opening in the first resin layer such that the opening overlaps the wiring, forming a conductive member in the opening such that the conductive member being electrically connected to the wiring, forming a second electrode on the conductive member such that the second electrode is electrically connected to the wiring via the conductive member, and separating the wafer into individual elements after the forming of the first resin layer. | 04-30-2009 |
| 20090149016 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor device and a method of fabricating the same. The method of fabricating the semiconductor device includes forming a mask pattern having an opening corresponding to an electrode pad formed on a semiconductor substrate; forming a bump by filling the opening with a conductive first material; forming a sidewall film on sidewalls of the bump using a second material; forming a connection member between an upper surface of the bump and a wire substrate using a conductive third material in order to electrically connect the bump and the wire substrate; and forming an underfill resin between the wire substrate and the semiconductor substrate, wherein a wetting angle between the second material and the third material is greater than that between the first material and the third material. | 06-11-2009 |
| 20100297842 | CONDUCTIVE BUMP STRUCTURE FOR SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A conductive bump structure for a semiconductor device and a method for fabricating the same are provided. A metal bump is formed on an under bump metallurgy (UBM) structure electrically connected to and formed on a connection pad of the semiconductor device, wherein the metal bump is sized smaller than the UBM structure. Subsequently, a solder bump is mounted on the UBM structure and encapsulates the metal bump, so as to increase the bonding area and simultaneously allow the solder bump to be sufficiently wetted on the UBM structure to enhance bonding stress of the solder bump. | 11-25-2010 |
| 20100297841 | Method for providing a redistribution metal layer in an integrated circuit - A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability. | 11-25-2010 |
| 20110244675 | Structure and method of forming pillar bumps with controllable shape and size - A structure and method of forming pillar bumps with controllable shape and size are provided, which use polishing planarization technology to eliminate shape difference among pillar bumps on a wafer and die, thus yield the pillar bumps with design shape and size. | 10-06-2011 |
| 20110143531 | PACKAGING CONDUCTIVE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A packaging conductive structure for a semiconductor substrate and a method for manufacturing the structure are provided. The structure comprises an under bump metal (UBM) that overlays a pad of the semiconductor substrate. At least one auxiliary component is disposed on the UBM. Then, a bump conductive layer is disposed thereon and a bump is subsequently formed on the bump conductive layer. Thus, the bump can electrically connect to the pad of the semiconductor substrate through the UBM and the bump conductive layer and can provide better junction buffer capabilities and conductivity. | 06-16-2011 |
| 20100015796 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD AND APPARATUS FOR THE SAME - A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting. | 01-21-2010 |
| 20090215259 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a semiconductor package and a method of manufacturing the same. The semiconductor package includes a semiconductor chip that includes metal pads provided on a predetermined area of an upper side of a semiconductor substrate, where element structures used to manufacture a semiconductor element are formed, and bump electrodes connected to the metal pads; and a passivation film that is provided on an entire surface of the semiconductor chip other than upper surface of the bump electrodes. Therefore, it is possible to avoid difficulties in performing an epoxy underfill process used in a conventional flip chip bonding, and complexity and high cost resulting from the use of a molding compound process and a solder ball process. It is also possible to prevent damages to the lateral surface of the semiconductor chip due to an absence of the passivation film on the lateral surface of the semiconductor chip in a conventional wafer level package. | 08-27-2009 |
| 20090215258 | Semiconductor device manufacturing method - There is provide a semiconductor device manufacturing method, including: preparing a substrate; laminating an insulation layer on the substrate; laminating a first underlying metal layer on the insulation layer; forming rewiring on the first underlying metal layer; removing exposed portions of the first underlying metal layer; laminating a second underlying metal layer on the rewiring and the insulation layer; forming a column electrode on the rewiring via the second underlying metal layer; and removing exposed portions of the second underlying metal layer. | 08-27-2009 |
| 20110070728 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE HAVING CONDUCTIVE BUMPS - A semiconductor device having conductive bumps and a fabrication method thereof is proposed. The fabrication method includes the steps of forming a first metallic layer on a substrate having solder pads and a passivation layer formed thereon, and electrically connecting it to the solder pads; applying a second covering layer over exposed parts of the first metallic layer; subsequently, forming a second metallic layer on the second covering layer, and electrically connecting it to the exposed parts of the first metallic layer; applying a third covering layer, and forming openings for exposing parts of the second metallic layer to form thereon a conductive bump having a metallic standoff and a solder material. The covering layers and the metallic layers can provide a buffering effect for effectively absorbing the thermal stress imposed on the conductive bumps to prevent delamination caused by the UBM layers. | 03-24-2011 |
| 20120202343 | METHOD OF FORMING UNDERBUMP METALLURGY STRUCTURE EMPLOYING SPUTTER-DEPOSITED NICKEL COPPER ALLOY - A metallic adhesion layer is formed on a last level metal plate exposed in an opening of a passivation layer. A Ni—Cu alloy in which the weight percentage of Ni is from about 50% to about 70% is deposited by sputtering onto the metallic adhesion layer to form an underbump metallic layer. Optionally, a wetting layer comprising Cu or Au may be deposited by sputtering. A C4 ball is applied to a surface of the underbump metallic layer comprising the Ni—Cu alloy or the wetting layer for C4 processing. The sputter deposition of the Ni—Cu alloy offers economic advantages relative to known methods in the art since the Ni—Cu alloy in the composition of the present invention is non-magnetic and easy to sputter, and the consumption of the inventive Ni—Cu alloy is limited during C4 processing. | 08-09-2012 |
| 20110212615 | MANUFACTURING METHOD OF A BUMP STRUCTURE HAVING A REINFORCEMENT MEMBER - A manufacturing method of a bump structure having a reinforcement member is disclosed. First, a substrate including pads and a passivation layer is provided. The passivation layer has first openings, and each first opening exposes a portion of the corresponding pad respectively. Next, an under ball metal (UBM) material layer is formed on the substrate to cover the passivation layer and the pads exposed by the passivation layer. Bumps are formed on the UBM material layer and the lower surface of each bump is smaller than that of the opening. Each reinforcement member formed on the UBM material layer around each bump contacts with each bump, and the material of the reinforcement member is a polymer. The UBM material layer is patterned to form UBM layers and the lower surface of each UBM layer is larger than that of each corresponding opening. Hence, the bump has a planar upper surface. | 09-01-2011 |
| 20100105200 | Semiconductor Package with Passivation Island for Reducing Stress on Solder Bumps - A flip chip style semiconductor package has a substrate with a plurality of active devices formed thereon. A contact pad is formed over the substrate. An under bump metallization (UBM) layer is in electrical contact with the contact pad. A passivation layer is formed over the substrate. In one case, the UBM layer is disposed above the passivation layer. Alternatively, the passivation layer is disposed above the UBM layer. A portion of the passivation layer is removed to create a passivation island. The passivation island is centered with respect to the contact pad with its top surface devoid of the UBM layer. A solder bump is formed over the passivation island in electrical contact with the UBM layer. The passivation island forms a void in the solder bump for stress relief. The UBM layer may include a redistribution layer such that the passivation island is offset from the contact pad. | 04-29-2010 |
| 20110086505 | METALLIC BUMP STRUCTURE WITHOUT UNDER BUMP METALLURGY AND A MANUFACTURING METHOD THEREOF - The metallic bump is directly formed on a semiconductor wafer's I/O pad without UBM. First, a zinc layer is formed on the I/O pad or an anti-oxidation layer of the I/O pad is selectively etched off. Then, an isolative layer and a copper foil are arranged sequentially in this order above the I/O pad. The isolative layer is originally in a liquid state or in a temporarily solid state and later permanently solidified. Then, a via above the I/O pad is formed by removing part of the isolative layer and the cooper foil. Subsequently, a thin metallic layer connecting the copper foil and the I/O pad is formed in the via and a plating resist on the copper foil is formed. Then, a metallic bump is formed from the via whose height is controlled by the plating resist. Finally, the plating resist and the copper foil are removed. | 04-14-2011 |
| 20090176364 | SEMICONDUCTOR DEVICE HAVING A REFRACTORY METAL CONTAINING FILM AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO | 07-09-2009 |
| 20110111587 | METHOD FOR FORMING POST BUMP - Disclosed is a method for forming post bumps, the method including the steps of: forming a seed layer for metal plating on a substrate; forming a resist layer having openings provided as positions where the seed layer is subjected to metal plating; forming a dummy sheet, exposing the openings, on the resist layer; forming a post by performing metal plating of the openings; forming solder balls on the post; and removing the dummy sheet and the resist layer. | 05-12-2011 |
| 20120040524 | PROCESS FOR MAKING CONDUCTIVE POST WITH FOOTING PROFILE - A process for making a copper post with footing profile employs dual photoresist films of different photosensitivities and thicknesses on an under-bump-metallurgy (UBM) layer. After an exposure lithography process, a first opening with a substantially vertical sidewall is formed in a first photoresist film, and a second opening with a sloped sidewall is formed in a second photoresist film. The second opening has a top diameter and a bottom diameter greater than the top diameter, and the bottom diameter is greater than the diameter of the first opening. A conductive layer is then formed in the first opening and the second opening followed by removing the dual photoresist films. | 02-16-2012 |
| 20110318918 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE ALLOWING SMOOTH BUMP SURFACE - A method of fabricating a semiconductor device, includes: removing, after forming solder for forming a plurality of bumps on a semiconductor substrate, an oxide film formed on a surface of the solder while heating the semiconductor substrate with first radiant heat; and heating the semiconductor substrate with an amount of second radiant heat that is greater than the amount of the first radiant heat by holding the semiconductor substrate at a position apart from a front surface of a heater stage at a predetermined distance to reflow the solder from which the oxide film is removed. | 12-29-2011 |
| 20120009777 | UBM Etching Methods - A method of forming a device includes forming an under-bump metallurgy (UBM) layer including a barrier layer and a seed layer over the barrier layer; and forming a mask over the UBM layer. The mask covers a first portion of the UBM layer, and a second portion of the UBM layer is exposed through an opening in the mask. The first portion of the UBM layer includes a barrier layer portion and a seed layer portion. A metal bump is formed in the opening and on the second portion of the UBM layer. The mask is then removed. A wet etch is performed to remove the seed layer portion. A dry etch is performed to remove the barrier layer portion. | 01-12-2012 |
| 20120064712 | Method for Reducing UBM Undercut in Metal Bump Structures - A method of forming a device includes providing a wafer including a substrate; and forming an under-bump metallurgy (UBM) layer including a barrier layer overlying the substrate and a seed layer overlying the barrier layer. A metal bump is formed directly over a first portion of the UBM layer, wherein a second portion of the UBM layer is not covered by the metal bump. The second portion of the UBM layer includes a seed layer portion and a barrier layer portion. A first etch is performed to remove the seed layer portion, followed by a first rinse step performed on the wafer. A second etch is performed to remove the barrier layer portion, followed by a second rinse step performed on the wafer. At least a first switch time from the first etch to the first rinse step and a second switch time from the second etch to the second rinse step is less than about 1 second. | 03-15-2012 |
| 20090233436 | Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP Coating - An interconnect structure for a semiconductor device is made by forming a contact pad on a substrate, forming an under bump metallization layer over the contact pad, forming a photoresist layer over the substrate, removing a portion of the photoresist layer to form an opening which exposes the UBM, depositing a first conductive material into the opening of the photoresist, removing the photoresist layer, depositing a second conductive material over the first conductive material, and coating the second conductive material with an organic solderability preservative. The interconnect structure is formed without solder reflow. The first conductive layer is nickel and the second conductive layer is copper. The organic solderability preservative is made with benzotriazole, rosin, rosin esters, benzimidazole compounds, or imidazole compounds. The interconnect structure decreases the pitch between the core pillars in the interconnect array and increases the density of I/O contacts on the semiconductor device. | 09-17-2009 |
| 20110104887 | Semiconductor element and method of manufacturing the same - A method of manufacturing a semiconductor element including a semiconductor substrate, a conductive post portion provided on the semiconductor substrate to protrude therefrom, and a solder layer provided on the conductive post portion, includes forming on the semiconductor substrate the conductive post portion having a distal end surface curved in a substantially arc shape by electrolytic plating, forming an intermediate solder layer on the distal end surface of the conductive post portion, and reflowing the intermediate solder layer to form the solder layer which has a thickest portion at a top of the distal end surface of the conductive post portion. | 05-05-2011 |
| 20090130840 | Protected Solder Ball Joints in Wafer Level Chip-Scale Packaging - Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress. | 05-21-2009 |
| 20120129336 | STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES - Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire. | 05-24-2012 |
| 20120129335 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask. | 05-24-2012 |
| 20120178252 | Dummy Metal Design for Packaging Structures - A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern. | 07-12-2012 |
| 20120220118 | CHIP AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature. | 08-30-2012 |
| 20120083114 | DIMENSIONALLY DECOUPLED BALL LIMITING METALURGY - A method for reducing stress on under ball metallurgy (UBM) is disclosed. A collar is disposed around the ball to provide support, and prevent solder interaction in the undercut areas of the UBM. In one embodiment, the collar is comprised of photosensitive polyimide. | 04-05-2012 |
| 20100323513 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE HAVING CONDUCTIVE BUMPS - A semiconductor device having conductive bumps and a fabrication method thereof are provided. The fabrication method mainly including steps of: providing a semiconductor substrate having a solder pad and a passivation layer formed thereon with a portion of the solder pads exposed from the passivation layer; disposing a first metal layer on the solder pad and a portion of the passivation layer around the solder pad; disposing a covering layer on the first metal layer and the passivation layer, and forming an aperture in the covering layer to expose a portion of the first metal layer, wherein a center of the aperture is deviated from that of the solder pad; deposing a metal pillar on the portion of the first metal layer; and deposing a solder material on an outer surface of the metal pillar for providing a better buffering effect. | 12-23-2010 |
| 20080299757 | Wafer structure and method for fabricating the same - A wafer structure and a method for fabricating the same are provided. First, a wafer having a pad and a first protection layer with a first opening is provided. Next, a second protection layer with a second opening is formed on the first protection layer. Part of the pad and the first protection layer are exposed from the openings. The edges of the openings construct a step structure. Following that, an adhesion layer is formed on the pad, the step structure and the second protection layer. Afterwards, a photo-resist layer with a third opening is formed on the adhesion layer. Then, a barrier layer is electroplated onto part of the adhesion layer. Further, a wetting layer is formed on the barrier layer, and then the photo-resist layer and part of the adhesion layer exposed outside the barrier layer are removed. Finally, a solder layer is printed onto the wetting layer. | 12-04-2008 |
| 20110003470 | METHODS AND STRUCTURES FOR A VERTICAL PILLAR INTERCONNECT - In wafer-level chip-scale packaging and flip-chip packaging and assemblies, a solder cap is formed on a vertical pillar. In one embodiment, the vertical pillar overlies a semiconductor substrate. A solder paste, which may be doped with at least one trace element, is applied on a top surface of the pillar structure. A reflow process is performed after applying the solder paste to provide the solder cap. | 01-06-2011 |
| 20120329264 | Reflow System and Method for Conductive Connections - A system and method for forming conductive connections is disclosed. An embodiment comprises forming conductive material on to contacts of a semiconductor substrate. The semiconductor substrate is then inverter such that the conductive material is beneath the semiconductor substrate, and the conductive material is reflowed to form a conductive bump. The reflow is performed using gravity in order to form a more uniform shape for the conductive bump. | 12-27-2012 |
| 20120329265 | METHODS AND STRUCTURES FOR CONTROLLING WAFER CURVATURE - Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers. | 12-27-2012 |
| 20130012014 | UBM Etching Methods for Eliminating Undercut - A method includes forming an under-bump metallurgy (UBM) layer overlying a substrate, and forming a mask overlying the UBM layer. The mask covers a first portion of the UBM layer, and a second portion of the UBM layer is exposed through an opening in the mask. A metal bump is formed in the opening and on the second portion of the UBM layer. The mask is then removed. A laser removal is performed to remove a part of the first portion of the UBM layer and to form an UBM. | 01-10-2013 |
| 20100167522 | STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES - Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming a plurality of trenches in a dielectric layer extending to an underlying metal layer. The method further includes depositing metal in the plurality of trenches to form discrete metal line islands in contact with the underlying metal layer. The method also includes forming a solder bump in electrical connection to the plurality of metal line islands. | 07-01-2010 |
| 20130012015 | SEMICONDUCTOR DEVICE FOR IMPROVING ELECTRICAL AND MECHANICAL CONNECTIVITY OF CONDUCTIVE PILLERS AND METHOD THEREFOR - A semiconductor device has a semiconductor die having a first surface and a second surface wherein at least one bond pad is formed on the first surface. A passivation layer is formed on the first surface of the semiconductor device, wherein a central area of the at least one bond is exposed. A seed layer is formed on exposed portions of the bond pad and the passivation layer. A conductive pillar is formed on the seed layer. The conductive pillar has a base portion wherein the base portion has a diameter smaller than the seed layer and a stress relief portion extending from a lateral surface of a lower section of the base portion toward distal ends of the seed layer. A solder layer is formed on the conductive pillar. | 01-10-2013 |
| 20130017681 | Solder Bump Cleaning Before ReflowAANM Willeke; ReinerAACI DresdenAACO DEAAGP Willeke; Reiner Dresden DEAANM Zenner; SorenAACI DresdenAACO DEAAGP Zenner; Soren Dresden DE - Generally, the subject matter disclosed herein relates to methods for forming modern sophisticated semiconductor devices, and more specifically, methods wherein substantially lead-free solder bumps may be formed above a contact layer of a semiconductor chip. One illustrative method disclosed herein includes forming a solder bump above a metallization layer of a semiconductor device, removing an oxide film from a surface of the solder bump, and, after removing the oxide film, performing a solder bump reflow process in a reducing ambient to reflow the solder bump. | 01-17-2013 |
| 20080254611 | INTERCONNECTION DESIGNS AND MATERIALS HAVING IMPROVED STRENGTH AND FATIGUE LIFE - Methods and designs for increasing interconnect areas for interconnect bumps are disclosed. An interconnect bump may be formed on a substrate such that the interconnect bump extends beyond a contact pad onto a substrate. An interconnect bump may be formed on a larger contact pad, the bump having a large diameter. | 10-16-2008 |
| 20130143400 | METAL-CONTAMINATION-FREE THROUGH-SUBSTRATE VIA STRUCTURE - A through-substrate via (TSV) structure that is immune to metal contamination due to a backside planarization process is provided. After forming a through-substrate via (TSV) trench, a diffusion barrier liner is conformally deposited on the sidewalls of the TSV trench. A dielectric liner is formed by depositing a dielectric material on vertical portions of the diffusion barrier liner. A metallic conductive via structure is formed by subsequently filling the TSV trench. Horizontal portions of the diffusion barrier liner are removed. The diffusion barrier liner protects the semiconductor material of the substrate during the backside planarization by blocking residual metallic material originating from the metallic conductive via structure from entering into the semiconductor material of the substrate, thereby protecting the semiconductor devices within the substrate from metallic contamination. | 06-06-2013 |
| 20130149858 | METHOD OF MANUFACTURING BUMP - A bump manufacturing method may be provided. The bump manufacturing method may include forming a bump on an electrode pad included in a semiconductor device, and controlling a shape of the bump by reflowing the bump formed on the semiconductor device under an oxygen atmosphere. | 06-13-2013 |
