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Bump electrode

Subclass of:

438 - Semiconductor device manufacturing: process

438584000 - COATING WITH ELECTRICALLY OR THERMALLY CONDUCTIVE MATERIAL

438597000 - To form ohmic contact to semiconductive material

438612000 - Forming solder contact or bonding pad

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
438614000 Plural conductive layers 60
438615000 Including fusion of conductor 27
Entries
DocumentTitleDate
20100055895Electrically conductive structure on a semiconductor substrate formed from printing - Provided are methods for forming an electrically conductive structure of a desired three-dimensional shape on a substantially planar surface of a substrate, e.g., a semiconductor wafer. Typically, the particulate matter is deposited in a layer-by-layer manner and adhered to selected regions on the substrate surface. The particulate matter may be deposited to produce a mold for forming the structure and/or to produce the structure itself. A three-dimensional printer with associated electronic data may be used without the need of a lithographic mask or reticle.03-04-2010
20090104766Method of Forming Micro Metal Bump - The present invention provides a method of forming a micro metal bump, which is capable of stably and industrially forming a micro metal bump, by a gas deposition process, at a prescribed position of a metal part formed on one side surface of a substrate. The method comprises the steps of: forming a straight hole (04-23-2009
20100159691PHOTOSENSITIVE RESIN COMPOSITION AND LAMINATE - Disclosed is a photosensitive resin composition showing excellent contrast performance after exposure to light. Also disclosed is a photosensitive resin laminate using the composition. The photosensitive resin composition comprises (a) 20 to 90% by mass of a binder having a carboxyl group, (b) 5 to 75% by mass of an addition-polymerizable monomer having at least one ethylenically unsaturated terminal group, (c) 0.01 to 30% by mass of a photopolymerization initiator, and (d) 0.01 to 10% by mass of a leuco dye, wherein a specific binder is contained as the binder (a) and a specific monomer is contained as the addition-polymerizable monomer (b).06-24-2010
20100151670Methods Of Adding Pads And One Or More Interconnect Layers To The Passivated Topside Of A Wafer Including Connections To At Least A Portion Of The Integrated Circuit Pads Thereon - A pattern of conductive ink is disposed on the topside of the unsingulated integrated circuits of a wafer, and, typically after wafer probing, the pattern of conductive ink is removed. The conductive ink pattern provides an electrical pathway between bond pads on an integrated circuit and large contact pads disposed on the topside of the integrated circuit. Each of the large contact pads is much greater in area than the corresponding bond pads, and are spaced apart so that the pitch of the large contact pads is much greater than that of the bond pads. In one aspect of the present invention, the conductive ink includes a mixture of conductive particles and wafer bonding thermoset plastic. In another aspect of the present invention, the conductive ink is heated and disposed on a wafer by an ink jet printing system.06-17-2010
20090191701MICROELECTRONIC DEVICES AND METHODS FOR FORMING INTERCONNECTS IN MICROELECTRONIC DEVICES - Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.07-30-2009
20110195568SEMICONDUCTOR STRUCTURE, METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR PACKAGE - A semiconductor structure, a method for manufacturing a semiconductor structure and a semiconductor package are provided. The method for manufacturing a semiconductor structure includes the following steps. Firstly, a silicon substrate is provided. Next, a part of the silicon substrate is removed to form a ring hole and a silicon pillar surrounded by the silicon pillar. Then, a photosensitive material is disposed in the ring hole, wherein the photosensitive material is insulating. After that, the silicon pillar is removed, such that the ring hole forms a through hole and the photosensitive material covers a lateral wall of the through hole. Lastly, the conductive material is disposed in the through hole, wherein the outer surface of the conductive material is surrounded by the photosensitive material.08-11-2011
20100075493METHOD OF FORMING ELECTRODE CONNECTING PORTION - A manufacturing method for an electrode connecting portion includes covering an electrode forming surface with a solder sheet, rolling a heating roller on the solder sheet that covers the electrode forming surface, and removing the solder sheet after the heating roller has passed over the solder sheet.03-25-2010
20130034956CLEANING RESIDUAL MOLDING COMPOUND ON SOLDER BUMPS - A method of forming wafer-level chip scale packaging solder bumps on a wafer substrate involves cleaning the surface of the solder bumps using a laser to remove any residual molding compound from the surface of the solder bumps after the solder bumps are reflowed and a liquid molding compound is applied and cured.02-07-2013
20080261390METHOD FOR FORMING BUMPS ON UNDER BUMP METALLURGY - A method for forming metal bumps is provided. A bonding pad is first formed on the active surface of a chip and then a passivation layer is formed on the active surface of the chip and exposes the bonding pad. An under bump metallurgy is formed on the active surface of the chip to overlay the bonding pad. A layer of patterned photoresist is formed on the under bump metallurgy and exposes the portion of the under bump metallurgy on the bonding pad. A layer of copper is plated on the exposed portion of the under bump metallurgy and then a layer of solder is printed on the copper layer. Afterward the solder is reflowed to form a spherical metal bump. Finally, the photoresist layer is removed and the exposed portion of the under bump metallurgy is etched out.10-23-2008
20130040453Through Silicon Via Layout - A system and method for forming under bump metallization layers that reduces the overall footprint of UBMs, through silicon vias, and trace lines is disclosed. A preferred embodiment comprises forming an under bump metallization layer over a plurality of through silicon vias, whereas the UBM is connected to only a portion of the total number of through silicon vias over which it is located. The trace lines connected to the through silicon vias may additionally be formed beneath the UBM to save even more space on the surface of the die.02-14-2013
20090149014METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE06-11-2009
20090124074WAFER LEVEL SENSING PACKAGE AND MANUFACTURING PROCESS THEREOF - A wafer level sensing package and manufacturing process thereof are described. The process includes providing a wafer having sensing chips, in which each sensing chip has a sensing area and pads; forming a stress release layer on a wafer surface; cladding a photoresist layer on the stress release layer; patterning the photoresist layer to expose the pads and a portion of the stress release layer, without exposing opening areas of the sensing areas; forming a conductive metal layer of re-distributed pads on the portion of the stress release layer exposed by the photoresist layer; removing the photoresist layer; forming a re-cladding photoresist layer on the stress release layer and the conductive metal layer; forming holes in the re-cladding photoresist layer above the re-distributed pad area; and forming conductive bumps in the holes to electrically connect to the conductive metal layer.05-14-2009
20130089977METHOD FOR FORMING HIGH DENSITY PATTERNS - In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in an integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.04-11-2013
20090305494Bump structure for a semiconductor device and method of manufacture - A semiconductor device employing the bump structure includes a plurality of bump structures arrayed along a substrate in a first direction. Each bump structure has a width in the first direction greater than a pitch gap between successively arrayed bump structures, and at least one bump structure has a sidewall facing in the first direction that is non-conductive.12-10-2009
20130072012Method For Forming Package Substrate With Ultra-Thin Seed Layer - A method for forming a package substrate with a seed layer is provided, which includes a step of etching away the metal foil laminated on the substrate, so that the substrate has a rough surface, and a step of forming an ultra-thin seed layer on the rough surface of the substrate, wherein the ultra-thin seed layer is formed along the rough surface of the substrate, and thereby the ultra-thin seed layer has a rough surface. Consequently, the adhesion between the metal bumps or circuits formed on the ultra-thin rough seed layer and the substrate can be increased. Furthermore, because the seed layer is ultra thin, the metal bumps or the circuit lines formed on the package substrate can be made finer in line widths and line pitches, and the good yield of the package substrate with fine circuit lines can be increased.03-21-2013
20110014785Method for manufacturing semiconductor device, and semiconductor manufacturing apparatus used in said method - This method includes an electrode pad forming process for forming an electrode pad on a substrate, a solder bump forming process for forming a solder bump on the electrode pad, at least part of the surface of the solder bump being covered with a flux, and an oxygen exposure process for supplying an oxygen gas having reactive properties, such as an ozone (O01-20-2011
20130065388SUBSTRATE STRUCTURE WITH COMPLIANT BUMP AND MANUFACTURING METHOD THEREOF - A substrate structure with compliant bump comprises a substrate, a plurality of bumps, and a metallic layer, wherein the substrate comprises a surface, a trace layer, and a protective layer. The trace layer comprises a plurality of conductive pads, and each of the conductive pads comprises an upper surface. The protective layer comprises a plurality of openings. The bumps are formed on the surface, and each of the bumps comprises a top surface, an inner surface and an outer surface and defines a first body and a second body. The first body is located on the surface. The second body is located on top of the first body. The metallic layer is formed on the top surface, the inner surface, and the upper surface.03-14-2013
20090117729Electrostatic Discharge (ESD) Protection Structure - A semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate. A solder bump is formed on the contact pad. An electrostatic discharge (ESD) bump electrode is formed on the contact pad. The ESD bump electrode has a tip. The ESD bump electrode is made with gold. A chip carrier substrate has a contact pad metallurgically connected to the solder bump. The chip carrier substrate also has a ground plate. The ground plate is a low impedance ground point. The tip of the ESD bump electrode is separated from the ground plate by a distance according to ESD sensitivity of the active devices. The distance is determined by a ratio of a discharging threshold voltage for ESD sensitivity of the active device to be protected to an atmosphere discharging voltage.05-07-2009
20100159692ATTACHMENT USING MAGNETIC PARTICLE BASED SOLDER COMPOSITES - Electronic devices and methods for fabricating electronic devices are described. One method includes providing a first body with a plurality of composite bumps thereon, the composite bumps comprising a solder and magnetic particles. The method also includes applying a magnetic field to the magnetic particles to generate sufficient heat to melt the solder and form molten bump regions containing the magnetic particles therein. The method also includes coupling a second body to the first body through the molten bump regions, and cooling the molten bump regions to form solidified composite bumps coupling the second body to the first body. Other embodiments are described and claimed.06-24-2010
20110300705MANUFACTURING METHOD OF BUMP STRUCTURE WITH ANNULAR SUPPORT - A manufacturing method of a bump structure with an annular support includes the following steps. A substrate including pads and a passivation layer is provided. The passivation has first openings exposing a portion of the pads. An UBM material layer is formed to cover the passivation layer and the pads. A patterned photoresist layer, having second openings respectively exposing the UBM material layer over the pads, is formed on the UBM material layer. A diameter of each second opening located on a lower surface of the patterned photoresist layer is less than that located on an upper surface of the patterned photoresist layer. Bumps are formed in the second openings. A portion of the patterned photoresist layer is removed to form an annular support at a periphery of each bump. The UBM material layer is patterned using the annular supports and the bumps as masks to form UBM layers.12-08-2011
20120289042Arrangement for solder bump formation on wafers - An apparatus and a process for the manufacture of a solder-bump adhered wafer substrate for use in the semiconductor industry, comprising one or more of the following steps including: arranging a first compressive member and a second compressive member in an opposed, compressibly displaceable, spaced-apart relationship, with a pattern plate disposed therebetween with the pattern plate having a plurality of aligned through-holes arranged thereon; filling the through-holes with a molten solder; compressing the solder and the pattern plate between the first and second opposed compressive members to compact the solder therein and cleans the pattern plate of excess solder; chilling the pattern plate to solidify the molten solder in the through-holes; and removing the pattern plate from the spaced-apart compressive members to produce a wafer with solder bumps thereon.11-15-2012
20110195567METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises: immersing a semiconductor substrates in a Pd activating solution containing Pd ions and adhering a Pd catalyst to a surface of the semiconductor substrate; and immersing the semiconductor substrate, to which the Pd catalyst is adhered, in a Pd electroless plating solution and forming an electroless-plated Pd film on the semiconductor substrate.08-11-2011
20090149015MANUFACTURING METHOD OF CONTACT STRUCTURE - A manufacturing method of a contact structure includes first providing a substrate on which a contact pad has already been formed. Afterwards, a polymer bump is formed on the contact pad. Next, a conductive layer is formed on the polymer bump. The conductive layer covers the polymer bump and extends to the outside of the polymer bump. The portion of the conductive layer extending to the outside of the polymer bump serves as a test pad.06-11-2009
20110201194Direct IMS (Injection Molded Solder) Without a Mask for Forming Solder Bumps on Substrates - An assembly is obtained; it includes a substrate; a plurality of wet-able pads formed on a surface of the substrate; and a solder resist layer deposited on the surface of the substrate and having an outer surface. At least the solder resist layer is formed with recessed regions defining volumes adjacent the wet-able pads. Molten solder is directly injected into the volumes adjacent the wet-able pads, such that the volumes adjacent the wet-able pads are filled with solder. The solder is allowed to solidify. It forms a plurality of solder structures adhered to the wet-able pads. The substrate and the solder are re-heated after the solidification, to re-flow the solder into generally spherical balls extending above the outer surface of the solder resist layer. The volumes adjacent the wet-able pads are configured and dimensioned to receive sufficient solder in the injecting step such that the generally spherical balls extend above the outer surface of the solder resist layer as a result of the re-heating step. In an alternative approach, solder injection and solidification are carried out in a nitrogen environment or a forming gas environment, and the reflow step may be omitted.08-18-2011
20110136336METHODS OF FORMING CONDUCTIVE VIAS - Methods of forming a conductive via may include forming a blind via hole partially through a substrate, forming an aluminum film on surfaces of the substrate, removing a first portion of the aluminum film from some surfaces, selectively depositing conductive material onto a second portion of the aluminum film, and exposing the blind via hole through a back side of the substrate. Methods of fabricating a conductive via may include forming at least one via hole through at least one unplated bond pad, forming a first adhesive over at least one surface of the at least one via hole, forming a dielectric over the first adhesive, forming a base layer over the dielectric and the at least one unplated bond pad, and plating nickel onto the base layer.06-09-2011
20090093110BGA package having half-etched bonding pad and cut plating line and method of fabricating same - A ball grid array (BGA) package having a half-etched bonding pad and a cut plating line and a method of fabricating the same. In the BGA package, the plating line is cut to form a predetermined uneven bonding pad using half-etching, thereby increasing the contact area between the bonding pad and a solder ball. The BGA package includes a first external layer having a first circuit pattern and a wire bonding pad pattern wherein a chip is connected to a wire bonding pad using wire bonding. A second external layer includes a second circuit pattern, a cut plating line pattern, and a half-etched uneven solder ball pad pattern. In the second external layer, another chip is mounted on a solder ball pad. An insulating layer having a through hole interposed between the first and second external layers and electrically connects the first and second external layers therethrough.04-09-2009
20120142184MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE - A manufacturing method of a semiconductor structure includes providing a substrate having an upper surface and a bottom surface. First openings are formed in the substrate. An oxidization process is performed to oxidize the substrate having the first openings therein to form an oxide-containing material layer, and the oxide-containing material layer has second openings therein. A conductive material is filled into the second openings to form conductive plugs. A first device layer is formed a first surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. A second device layer is formed on a second surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs.06-07-2012
20090275192MOLDED DIELECTRIC LAYER IN PRINT-PATTERNED ELECTRONIC CIRCUITS - A method forms a first active electronic layer, prints an array of pillars on the first active electronic layer, dispenses a curable polymer over the array of pillars, molds the curable polymer by contacting the curable polymer with a mold structure to displace the curable polymer from upper surfaces of the pillars, cures the curable polymer to produce a hardened polymer, and removes the array of pillars to leave an array of holes in the hardened polymer. Another method provides a substrate having selected areas, prints an array of pillars on the substrate, dispenses a curable polymer over the array of pillars, molds the curable polymer by contacting the array of pillars with a mold structure to displace the curable polymer from upper surfaces of the pillars, cures the curable polymer to produce a hardened polymer, and removes the array of pillars to leave an array of holes in the hardened polymer corresponding to the selected areas. Another method forms a first active electronic layer on a substrate, prints an array of conductive pillars on the active electronic layer on a substrate, dispenses a curable polymer on the array of conductive pillars, molds the curable polymer by contacting the array of pillars with a mold structure to displace the curable polymer from the upper surfaces of the conductive pillars, curing the curable polymer to produce a hardened polymer, and forms a second active electronic layer on the hardened polymer such that the second active electronic layer is in electrical connection with the first active electronic layer through the conductive pillars.11-05-2009
20090286390METHOD OF PACKAGING A SEMICONDUCTOR DEVICE AND A PREFABRICATED CONNECTOR - A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer over the first major surface of the first device, forming a via in the first dielectric layer, forming a seed layer within the via and over a portion of the first dielectric layer, physically coupling a connector to the seed layer, and plating a conductive material over the seed layer to form a first interconnect in the first via and over a portion of the first dielectric layer.11-19-2009
20090042382Device packages - Low volume production of electronic devices having ball attachments, e.g. solder ball arrays, is advantageously achieved using a specific method. In particular a stencil having holes in, for example, the ball grid array pattern is formed by laser ablation of the holes in materials such as paper and polymers. The stencil holes are aligned with corresponding pads on the electronic device. Balls such as solder balls are introduced into the holes and heated to induce adhesion of the balls to the corresponding pads.02-12-2009
20110201195FLIP CHIP MOUNTING METHOD AND BUMP FORMING METHOD - The invention involves mounting a solder resin composition (08-18-2011
20080293234Semiconductor device and manufacturing method of the same - A semiconductor device includes a plurality of electrode layers provided at designated positions of a semiconductor substrate, an organic insulation film formed on the semiconductor substrate by selectively exposing designated areas of the electrode layers, and projection electrodes for outside connection, the projection electrodes being formed on the designated areas of the electrode layers. Thickness of the organic insulation film situated in the vicinity of the periphery of the projection electrodes is greater than thickness of the organic insulation film situated between the projection electrodes.11-27-2008
20090155993TERMINAL PAD STRUCTURES AND METHODS OF FABRICATING SAME - Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.06-18-2009
20100144136SEMICONDUCTOR DEVICE WITH SOLDER BALLS HAVING HIGH RELIABILITY - A semiconductor device includes a substrate, a metal layer, an alloy layer and a Sn—Ag—Cu-based solder ball. The metal layer is configured to be formed on the substrate. The alloy layer is configured to be formed on the metal layer. The Sn—Ag—Cu-based solder ball is configured to be placed on the alloy layer. The alloy layer includes Ni and Zn as essential elements.06-10-2010
20090325375REDUCING LEAKAGE IN DIELECTRIC MATERIALS INCLUDING METAL REGIONS INCLUDING A METAL CAP LAYER IN SEMICONDUCTOR DEVICES - By introducing an additional heat treatment prior to and/or after contacting a sensitive dielectric material with wet chemical agents, such as an electrolyte solution, enhanced performance with respect to leakage currents or dielectric strength may be accomplished during the fabrication of advanced semiconductor devices. For example, metal cap layers for metal lines may be provided on the basis of electroless deposition techniques, wherein the additional heat treatment(s) may provide the required electrical performance.12-31-2009
20090023282CONDUCTIVE BALL MOUNTING METHOD AND APPARATUS - There is provided a method of mounting conductive balls on pads on a substrate. The method includes: (a) placing the substrate having the pads coated with an adhesive over a container for containing the conductive balls therein and whose top surface is open such that the pads faces the top surface of the container; and (b) throwing up the conductive balls in the container by moving the container up and down at a given stroke, thereby allowing the conductive balls to adhere to the adhesive coated on the pads. Step (b) is repeatedly performed.01-22-2009
20090081861MANUFACTURING METHOD OF SOLDER BALL DISPOSING SURFACE STRUCTURE OF PACKAGE SUBSTRATE - A manufacturing method of a solder ball disposing surface structure on a core board including: providing a core board with a first metal layer and an opposing metal bump-equipped second metal layer; forming resists on the first and second metal layers respectively; forming third, fourth and fifth openings in the resists; removing the first and second metal layers in the third and fourth openings to form first and second circuit layers and metal pads respectively; removing the metal bumps in the fifth openings to form metal flanges; removing the resists; forming first and second insulative protection layers on the first and second circuit layers and metal pads respectively; forming first and second openings in the first and second insulative protection layers to expose the first circuit layer as electrical connecting pads and expose the metal flanges respectively. Accordingly, increased contact surface area for mounting conductive elements prevents detachment thereof.03-26-2009
20090075469THERMO-COMPRESSION BONDED ELECTRICAL INTERCONNECT STRUCTURE AND METHOD - An electrical structure and method for forming electrical interconnects. The method includes positioning a sacrificial carrier substrate such that a first surface of a non-solder metallic core structure within the sacrificial carrier substrate is in contact with a first electrically conductive pad. The first surface is thermo-compression bonded to the first electrically conductive pad. The sacrificial carrier substrate is removed from the non-solder metallic core structure. A solder structure is formed on a second electrically conductive pad. The first substrate comprising the non-solder metallic core structure is positioned such that a second surface of the non-solder metallic core structure is in contact with the solder structure. The solder structure is heated to a temperature sufficient to cause the solder structure to melt and form an electrical and mechanical connection between the second surface of the non-solder metallic core structure and the second electrically conductive pad.03-19-2009
20110230043TAPE RESIDUE-FREE BUMP AREA AFTER WAFER BACK GRINDING - Organic-adhesive tapes are often used to secure and protect the bumps during wafer processing after bump formation. While residual organic-adhesive tape may remain on the wafer after tape de-lamination, applying a bump template layer on the bumps before laminating the tape allows any residue to be removed afterwards and results in a residue-free wafer.09-22-2011
20090117730MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED DEVICE - Manufacture of semiconductor products such as LCD driver requires a bump plating step for forming a gold bump electrode having a size of from about 15 to 20 μm. This bump plating step is performed by electroplating with a predetermined plating solution, but projections intermittently appear on the bump electrode during a mass production process. In the invention, abnormal growth of projections over the gold bump electrode is prevented by adding, prior to the gold bump plating step, a step of circulating and stirring a plating solution while erecting a plating cup and efficiently dissolving/discharging a precipitate. This step is performed for each wafer to be treated.05-07-2009
20090253259Solder ball attachment jig and method for manufacturing semiconductor device using the same - Disclosed are a solder attachment jig and a method of manufacturing a semiconductor device using the same. The solder ball attachment jig, which arranges a solder ball to be aligned with a conductive post of a semiconductor wafer, can include a body and a receiving hole, which is formed on the body to hold the solder ball. Internal walls of the receiving hole that face each other are symmetrically inclined. Using the solder ball attachment jig in accordance with an embodiment of the present invention, the alignment of the solder ball can be improved while reducing the cost and simplifying the processes.10-08-2009
20090258486SEMICONDUCTOR DEVICE FABRICATION METHOD - A method of forming a semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. This surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is deposited on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer having openings exposing part of the conductive pattern is formed. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The method enables the thickness of the protective layer, which may function as a package of the semiconductor device, to be reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.10-15-2009
20100015795SEMICONDUCTOR DEVICE HAVING PROJECTING ELECTRODE FORMED BY ELECTROLYTIC PLATING, AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate, and a plurality of wiring lines provided on one side of the semiconductor substrate, each of the wiring lines having a connection pad portion. An overcoat film is provided on the wiring lines and the one side of the semiconductor substrate. The overcoat film has a plurality of openings in parts corresponding to the connection pad portions of the wiring lines. A plurality of foundation metal layers are respectively provided on inner surfaces of the openings of the overcoat film and electrically connected to the pat portions of the wiring lines. A plurality of projecting electrodes are respectively provided on the foundation metal layers in the openings of the overcoat film.01-21-2010
20090298277Maskless Process for Solder Bumps Production - Methods of producing a solder bump are presented. Preferred methods lack a requirement for photoresist processing or masking a target substrate. Contemplated methods include forming a well around one or more bond pads on a wafer where the walls of the well are formed by a passivation layer material. Contact material can comprise a solder paste or an under bump metallization layer, which can be placed within the wells as a contact bed for solder balls. A priori prepared solder balls, in solid form or in molten form, can deposited on the contact material to produce the solder bump.12-03-2009
20100178761Stacked Integrated Chips and Methods of Fabrication Thereof - Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion.07-15-2010
20110059606METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND MASK - A photosensitive resin film is formed on a protective insulating film. Next, a plurality of bump cores is formed on the protective insulating film along a first straight line by exposing and developing the photosensitive resin film. Next, a plurality of bumps, and a plurality of interconnects that connects each of the plurality of bumps to any of the electrode pads are formed by selectively forming conductive films on a plurality of bump cores, a plurality of electrode pads, and the protective insulating film. In the step of forming a plurality of bump cores, a region bordering on the interconnect on the lateral faces of the bump core is formed to have a gentler slope than that of a region intersecting the first straight line, by exposing the photosensitive resin film only one time using a multi-gradation mask.03-10-2011
20100216302Lead-free tin alloy electroplating compositions and methods - Disclosed are electrolyte compositions for depositing a tin alloy on a substrate. The electrolyte compositions include tin ions, ions of one or more alloying metals, a flavone compound and a dihydroxy bis-sulfide. The electrolyte compositions are free of lead and cyanide. Also disclosed are methods of depositing a tin alloy on a substrate and methods of forming an interconnect bump on a semiconductor device.08-26-2010
20100221909METHOD FOR MAKING AN ELECTRIC INTERCONNECTION BETWEEN TWO CONDUCTING LAYERS - This method for making an electric interconnection between two conducting layers separated by at least one insulation or semi-conducting layer, comprises forming a stud extending at least between the lower conducting layer and the upper conducting layer, wherein the nature and/or the shape of said stud impart non-wettability properties relative to the material used for the separating layer.09-02-2010
20100221910METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having an internal circuit; an electrode pad electrically connected to the internal circuit; an insulating film having a through hole exposing the electrode pad; and a re-distribution wiring pattern formed on the insulating film and electrically connected to the electrode pad. The semiconductor device further includes a recess groove formed in the insulating film around and adjacent to the re-distribution wiring pattern.09-02-2010
20100221908Manufacturing method of semiconductor device - Disclosed is a method of manufacturing a semiconductor device that does not have a defect, such as wire breakage, due to an uplifted portion created at a rewiring pattern in a multilayer wire structure. Before a wiring layer is formed on an insulation layer, the insulation layer is exposed via a mask. The mask has a weak exposure part and a strong exposure part. The mask is positioned such that the weak exposure part corresponds to an arrangement position of a wire line of an underlying wiring layer, and such that the strong exposure part corresponds to an arrangement position of a via part of the underlying wiring layer. The underlying wiring layer is a layer immediately below the insulation layer.09-02-2010
20090111259METHODS FOR FORMING CONNECTIVE ELEMENTS ON INTEGRATED CIRCUITS FOR PACKAGING APPLICATIONS - Methods for forming connective elements on integrated circuits for packaging applications are provided herein. In some embodiments, a method of forming connective elements on an integrated circuit for flipchip packaging may include providing a resist layer on the integrated circuit; forming a plurality of holes through the resist layer; filling the plurality of holes with conductive material; and stripping at least a portion of the resist layer using a stripping solution containing acetic anhydride and ozone to expose the connective elements.04-30-2009
20110129994Method of manufacturing a dual face package - A method of manufacturing a dual face package, including: preparing an upper substrate composed of an insulating layer including a post via-hole; forming a filled electrode in a semiconductor substrate, the filled electrode being connected to a die pad; applying an adhesive layer on one side of the semiconductor substrate including the filled electrode, and attaching the upper substrate to the semiconductor substrate; cutting another side of the semiconductor substrate in a thickness direction, thus making the filled electrode into a through-electrode; and forming a post electrode in the post via-hole, forming an upper redistribution layer connected to the post electrode of the semiconductor substrate, and forming a lower redistribution layer connected to the through-electrode on the other side of the semiconductor substrate.06-02-2011
20110117736MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - When relatively hard Au bump electrodes are mass-produced by electrolytic plating while ensuring usually required properties such as a non-glossy property and shape-flatness, combination of conditions, such as low liquid temperature, high current density, and low concentration of added Tl (thallium) that is an adjuvant, will be selected by itself. However, in such conditions, there is a problem that it is difficult to maintain the Tl concentration in a plating solution and, when the Tl concentration is reduced, defective appearance of the Au bump electrodes is generated by anomalous deposition. Conventionally, there has been no means to directly monitor minute Tl concentration and the Tl concentration has been controlled by analyzing the plating solution periodically. However, this cannot prevent generation of a lot of defective products.05-19-2011
20130130494EMBEDDED SEMICONDUCTOR DEVICE SUBSTRATE AND PRODUCTION METHOD THEREOF - An embedded semiconductor device substrate having a semiconductor device integrated therein is formed by disposing a semiconductor device in an opening provided on an insulating resin, and sandwiching the semiconductor device and the insulating resin with a front surface wiring layer and a rear surface wiring layer and performing heat pressing. Connection between bumps of the semiconductor device and the front surface wiring layer is made with a connection wiring pattern. The connection wiring pattern is formed by patterning a resist film by direct exposure thereof with a light beam, and then performing etching. Thereby, it becomes possible to absorb a mounting error of a semiconductor device to a printed wiring board and a positional error of electrodes between semiconductor devices accompanying the tendency of reduction of the pitch of a semiconductor device, and to perform electric connection with a wiring pattern securely.05-23-2013
20090035929Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device includes: (a) forming an insulating layer having a contact hole on a semiconductor section in which an element is formed; (b) forming an electrode pad on the insulating layer so that a depression or a protrusion remains at a position at which the electrode pad overlaps the contact section; (c) forming a passivation film to have an opening on a first section of the electrode pad and to be positioned on a second section of the electrode pad; (d) forming a barrier layer on the electrode pad; and (e) forming a bump to be larger than the opening in the passivation film and to be partially positioned on the passivation film. The contact section is connected with the second section at a position within a range in which the contact section overlaps the bump while avoiding the first section of the electrode pad.02-05-2009
20110027984PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A CONDUCTIVE STUD OVER A BONDING PAD REGION - An electronic device can include an interconnect level including a bonding pad region. An insulating layer can overlie the interconnect level and include an opening over the bonding pad region. In one embodiment, a conductive stud can lie within the opening and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer lying along a side and a bottom of the opening and a conductive stud lying within the opening. The conductive stud can substantially fill the opening. A majority of the conductive stud can lie within the opening. In still another embodiment, a process for forming an electronic device can include forming a conductive stud within the opening wherein from a top view, the conductive stud lies substantially completely within the opening. The process can also include forming a second barrier layer overlying the conductive stud.02-03-2011
20110034022SEMICONDUCTOR PACKAGE AND FABRICATION METHOD - A semiconductor package and a fabrication method thereof are disclosed, whereby an environmental problem is solved by using external connection terminals or semiconductor element-mounting terminals containing a smaller amount of lead, while at the same time achieving a fine pitch of the terminals. The semiconductor package includes a board (02-10-2011
20100062597Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers - An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.03-11-2010
20100015794PACKAGING CONDUCTIVE STRUCTURE AND METHOD FOR FORMING THE SAME - A packaging conductive structure for a semiconductor substrate and a method for forming the structure are provided. The dielectric layer of the packaging conductive structure partially overlays the metallic layer of the semiconductor substrate and has a receiving space. The lifting layer and conductive layer are formed in the receiving space, wherein the conductive layer extends for connection to a bump. The lifting layer is partially connected to the dielectric layer. As a result, the conductive layer can be stably deposited on the edge of the dielectric layer for enhancing the reliability of the packaging conductive structure.01-21-2010
20090317969METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD AND STRUCTURE FOR IMPLEMENTING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming an electrode; forming a projection projecting with respect to the electrode by melting a resin; and providing a conductive layer electrically connected to the electrode. The conductive layer is extended to an upper surface of the projection. Therefore, productivity of the semiconductor is improved.12-24-2009
20090176363Etching composition for an under-bump metallurgy layer and method of forming a bump structure using the same - In an etching composition for an under-bump metallurgy (UBM) layer and a method of forming a bump structure, the etching composition includes about 40% by weight to about 90% by weight of hydrogen peroxide (H07-09-2009
20120309187Conformal Coining of Solder Joints in Electronic Packages - Thermal deformation of a substrate and the substrate's warp at room temperature are used to determine the expected profile of the substrate at reflow. A contact surface profile of a coining pressure plate is selected based on the expected substrate profile. A solder surface is shaped on the substrate or a die to be joined to the substrate by the coining pressure plate, thereby facilitating the chip-joining process.12-06-2012
20100029074Maskless Process for Solder Bump Production - Methods of producing a solder bump are presented. Preferred methods lack a requirement for masking a target substrate. Contemplated methods include forming a well around one or more bond pads on a wafer where the walls of the well are formed by a covering layer material, possibly comprising photoresist or passivation material. The well can be filled with a contact material. Contact material can comprise a solder paste or an under bump metallization layer, which can be placed within the wells as a contact bed for solder balls. A priori prepared solder balls, in solid form or in molten form, can deposited on the contact material to produce the solder bump.02-04-2010
20120231621Manufacturing Method Of A Semiconductor Load Board - A manufacturing method of a semiconductor load board is disclosed. The manufacturing method includes a first conductive layer forming step, a first patterning step, a dielectric layer forming step, a drilling step, a second conductive layer forming step, a second patterning step or a two-times patterning step, and a solder connecting step. In a second patterning step or a two-times patterning step, a solder pads is formed in the opening of the dielectric layer, wherein each solder pad has a height higher than the height of the dielectric, and the width of each solder pad is equal to or smaller than the maximum width of the opening, such that wider intervals are provided in the same area and the problems of short circuit failure and electrical interference can be reduced.09-13-2012
20120009776SEMICONDUCTOR SUBSTRATES WITH UNITARY VIAS AND VIA TERMINALS, AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate.01-12-2012
20120009775SEMICONDUCTOR PACKAGE WITH A REDUCED VOLUME AND THICKNESS AND CAPABLE OF HIGH SPEED OPERATION AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes a semiconductor chip provided with a bonding pad disposed over a surface thereof; a through electrode passing from the surface to a second surface opposing the first surface and connected electrically with the bonding pad; and a redistribution disposed at the second surface and connected electrically with the through electrode. An embodiment of the present invention is capable of significantly reducing the thickness and volume of the semiconductor package. It is also capable of high speed operation since the path of the signal inputted and/or outputted from the semiconductor package is is shortened. It is capable of stacking easily at least two semiconductor packages having a wafer level, and it is capable of significantly reducing parasitic capacitance.01-12-2012
20120058636COMPOSITION FOR REMOVING A PHOTORESIST AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE COMPOSITION - Provided are a composition for removing a photoresist and a method of manufacturing a semiconductor device using the composition. The composition includes about 60-90 wt % of dimethyl sulfoxide, about 10-30 wt % of a polar organic solvent, about 0.5-1.5 wt % of hydroxy alkyl ammonium and about 1-10 wt % of an amine containing no hydroxyl group.03-08-2012
20110092065SEMICONDUCTOR DEVICE SUITABLE FOR A STACKED STRUCTURE - A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.04-21-2011
20090130839MANUFACTURING METHOD OF REDISTRIBUTION CIRCUIT STRUCTURE - A method of manufacturing a redistribution circuit structure is provided. First, a substrate is provided. The substrate has a plurality of pads and a passivation layer. The passivation layer has a plurality of first openings exposing a portion of each of the pads, respectively. A first patterned photoresist layer is formed on the passivation layer. The first patterned photoresist layer has a plurality of second openings exposing a portion of each of the pads. A plurality of first bumps is formed in the second openings, respectively. An under ball metal (UBM) material layer is formed over the substrate to cover the first patterned photoresist layer and the first bumps. A plurality of conductive lines is formed on the UBM material layer. The UBM material layer is patterned to form a plurality of UBM layers using the conductive lines as a mask.05-21-2009
20090130838METHOD OF FORMING CONDUCTIVE BUMPS - A method of forming a conductive bump of the present invention, includes the steps of, preparing a substrate including a connection pad and a protection insulating layer, in which an opening portion is provided on the connection pad, on a surface layer side, arranging a first conductive ball, at least an outer surface portion of which is made of solder, on the connection pad in the opening portion of the protection insulating layer, filling a solder layer in the opening portion by applying a reflow heating to the first conductive ball, arranging a second conductive ball on the solder layer, and obtaining a conductive bump which protrudes from an upper surface of the protection insulating layer, by joining the solder layer and the second conductive ball by a reflow heating.05-21-2009
20120129334SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME - Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.05-24-2012
20120129333METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE MANUFACTURED USING THE SAME - Provided are a method for manufacturing a semiconductor package and a semiconductor package manufactured using the method. The method includes providing a substrate having a first region and a second region having a higher step difference than the first region, i.e., having a difference in height, forming a mask pattern having a first opening exposing a portion of the first region and a second opening exposing a portion of the second region on the substrate, forming first and second bump material films filling the first and second openings, respectively, and forming the first and second bumps by performing a reflow process on the first and second bump material films, wherein the first opening has a lower portion having the same width with the second opening and a top portion having a width greater than the second opening.05-24-2012
20120164825SEMICONDUCTOR PACKAGE WITH A METAL POST AND MANUFACTURING METHOD THEREOF - Disclosed are a semiconductor package and a manufacturing method thereof. The semiconductor package can include a semiconductor substrate, having one surface on which a conductive pad is formed; an insulating layer, being formed on one surface of the semiconductor substrate; a metal post, penetrating through the conductive pad, the semiconductor substrate, and the insulating layer; and an outer-layer circuit, being electrically connected to the metal post. With the present invention, it can become unnecessary to form an additional via for electrically connecting both surfaces of the semiconductor substrate, thereby simplifying the manufacturing process, reducing the manufacturing cost, and improving the coupling reliability.06-28-2012
20100330798Formation of TSV Backside Interconnects by Modifying Carrier Wafers - An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×1012-30-2010
20120214302SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating a semiconductor device is provided. The method may include preparing a substrate having a first surface and a second surface, forming a via hole exposing at least a portion of the substrate from the first surface of the substrate, forming a first insulating film on an inner wall of the via hole, forming a conductive connection part filling an inside of the via hole including the first insulating film, polishing the second surface of the substrate until the conductive connection part is exposed, and selectively forming a second insulating film on the second surface of the substrate using an electrografting method to expose the conductive connection part.08-23-2012
20120178251METHOD OF FORMING METAL PILLAR - The disclosure relates to fabrication of to a metal pillar. An exemplary method of fabricating a semiconductor device comprises the steps of providing a substrate having a contact pad; forming a passivation layer extending over the substrate having an opening over the contact pad; forming a metal pillar over the contact pad and a portion of the passivation layer; forming a solder layer over the metal pillar; and causing sidewalls of the metal pillar to react with an organic compound to form a self-assembled monolayer or self-assembled multi-layers of the organic compound on the sidewalls of the metal pillar.07-12-2012
20120083113CREATION OF LEAD-FREE SOLDER JOINT WITH INTERMETALLICS - A method of coupling an integrated circuit to a substrate includes providing the substrate, forming a contact pad in the substrate, contacting the contact pad with a solder ball, and repeatedly exposing the solder ball to a thermal process to cause intermetallics based on a metal in the contact pad to be formed in the thermal ball.04-05-2012
20120270388ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE - A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress.10-25-2012
20110212614MICROELECTRONIC WORKPIECES AND METHOD FOR MANUFACTURING MICROELECTRONIC DEVICES USING SUCH WORKPIECES - Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces are disclosed. In one embodiment, a microelectronic assembly comprises a support member having a first side and a projection extending away from the first side. The assembly also includes a plurality of conductive traces at the first side of the support member. Some of the conductive traces include bond sites carried by the projection and having an outer surface at a first distance from the first side of the support member. The assembly further includes a protective coating deposited over the first side of the support member and at least a portion of the conductive traces. The protective coating has a major outer surface at a second distance from the first side of the support member. The second distance is approximately the same as the first distance such that the outer surface of the protective coating is generally co-planar with the outer surface of the bond sites carried by the projection. In several embodiments, a microelectronic die can be coupled to the corresponding bond sites carried by the projection in a flip-chip configuration.09-01-2011
20120322255Metal Bump Formation - A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.12-20-2012
20120276733METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In order to provide a semiconductor device that includes a conductive layer on one surface of a semiconductor substrate with an insulating layer therebetween, a bump on the other surface of the semiconductor substrate, and a through-electrode through the semiconductor substrate connecting the conductive layer with the bump, a through-hole is formed from the other surface of the semiconductor substrate to be connected to the conductive layer, a seed metal film is formed on the through-hole and the other surface, a photoresist is formed thereon, a mask layer is formed by processing the photoresist with a pattern larger than the through-hole, a plated film is grown by electrolytic plating so as to integrally form the through-electrode and a part of the bump.11-01-2012
20110269306SOLDER BUMP, ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE ELECTRONIC COMPONENT - An electronic component includes a plurality of first electrode pads arranged on a first substrate, a plurality of second electrode pads arranged at positions corresponding to the first electrode pads on a second substrate and a plurality of solder bumps which join together the first electrode pads and the second electrode pads. Here, the first substrate is located over the second substrate so that the first electrode pads and the second electrode pads are at positions which are shifted from opposite positions where the first electrode pads opposite to the second electrode pads, and at least a part of the solder bumps are solidified into hourglass-shaped.11-03-2011
20100203720SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME FOR DECREASING NUMBER OF PROCESSES - A semiconductor package and a method for manufacturing the same. The semiconductor package includes a semiconductor chip having bonding pads; a first insulation layer pattern; redistribution line patterns; a second insulation layer pattern; and conductive balls. The first insulation layer pattern having first openings exposing the bonding pads. The redistribution line patterns are located on the first insulation layer pattern and are electrically connected with the bonding pads. The second insulation layer pattern covering the redistribution line patterns and having second openings having first open areas which expose portions of the redistribution line patterns and having second open areas which extend from the first open areas along the semiconductor chip. The conductive balls are electrically connected with the portions of the redistribution line patterns which are exposed through the first open areas of the second insulation layer pattern.08-12-2010
20100203721MULTI-COMPONENT INTEGRATED CIRCUIT CONTACTS - An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g., metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.08-12-2010
20130171816APPARATUS AND METHOD FOR PLACING SOLDER BALLS - A system and process for forming a ball grid array on a substrate includes defining a plurality of openings in a resist layer on the substrate, and forming a plurality of openings in the resist layer, each positioned over a contact pad of the substrate. Flux is then deposited in the openings, and solder balls are positioned in each opening with the flux. Solder bumps are formed by reflowing the solder balls in the respective openings. The resist layer is then removed, leaving an array of solder bumps on the substrate. The flux can be deposited by depositing a layer of flux, then removing the flux, except a portion that remains in each opening. Solder balls can be positioned by moving a ball feeder across the resist layer and dropping a solder ball each time an aperture in the ball feeder aligns with an opening in the resist layer.07-04-2013
20120252203CONTROLLED ELECTROPLATED SOLDER BUMPS - The uniformity of the composition of plated solder bumps from one batch of wafers to another is improved by controlling the rotational speed of the wafers based on the particular solder bump pattern. Embodiments include sequentially horizontal fountain electroplating a pattern of solder bumps, e.g., SnAg solder bumps, on a plurality batches of wafers and controlling the rotational speed of each batch of wafers during electroplating based on a calibration plot of the concentration of a solder bump component, e.g., Ag, as a function of rotational speed for each solder bump pattern, such that the uniformity of the Ag concentration in the patterns of solder bumps is greater than 95%, e.g., greater than 98%. Embodiments further include electroplating in the same plater sequential batches of wafers having both different patterns and different solder bump compositions at the same high throughput.10-04-2012
20080213992SEMICONDUCTOR PACKAGE HAVING ENHANCED HEAT DISSIPATION AND METHOD OF FABRICATING THE SAME - A semiconductor package comprising a semiconductor chip and a first heat spreader adhered to the upper surface of the semiconductor chip is provided. The first heat spreader comprises a flat metal plate and a plurality of metal balls adhered to the flat metal plate. A method of fabricating the semiconductor chip package is also provided.09-04-2008
20110230044CONTACT STRUCTURE HAVING A COMPLIANT BUMP AND A TESTING AREA AND MANUFACTURING METHOD FOR THE SAME - A contact structure having both a compliant bump and a testing area and a manufacturing method for the same is introduced. The compliant bump is formed on a conductive contact of the silicon wafer or a printed circuit board. The core of the bump is made of polymeric material, and coated with a conductive material. In particular, the compliant bump is disposed on the one side of the conductive contact structure that includes both the bump and the testing area, wherein the testing area allows the area to be functionality tested, so as to prevent damage of the coated conductive material over the compliant bump during a probe testing.09-22-2011
20130149856Interface Structure for Copper-Copper Peeling Integrity - An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers. The interface includes a flat zone interface region and an intergrowth interface region, wherein the flat zone interface region is less than or equal to 50% of the interface.06-13-2013
20130149857SOLDER INTERCONNECT BY ADDITION OF COPPER - A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process.06-13-2013
20120282767METHOD FOR PRODUCING A TWO-SIDED FAN-OUT WAFER LEVEL PACKAGE WITH ELECTRICALLY CONDUCTIVE INTERCONNECTS, AND A CORRESPONDING SEMICONDUCTOR PACKAGE - A semiconductor packaging process includes drilling apertures in a reconstituted wafer, then filling the apertures with conductive paste by wiping a quantity of the paste across a back surface of the wafer so that paste is forced into the apertures. The paste is cured to form conductive posts. The wafer is thinned, and redistribution layers are formed on front and back surfaces of the wafer, with the posts acting as interconnections between the redistribution layers. In an alternative process, blind apertures are drilled. A dry film resist is applied to the front surface of the wafer, and patterned to expose the apertures. Conductive paste is applied from the front. To prevent paste from trapping air pockets in the apertures, the wiping process is performed under vacuum. After curing the paste, the wafer is thinned to expose the cured paste in the apertures, and redistribution layers are formed.11-08-2012
20130157455Electrical Contact Alignment Posts - An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.06-20-2013
20130183823BUMPING PROCESS - A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots corresponded to the first areas of the titanium-containing metal layer, forming a plurality of copper bumps at the opening slots, proceeding a heat procedure, forming a plurality of bump isolation layers on the copper bumps, forming a plurality of connective layers on the bump isolation layers, removing the photoresist layer, removing the second areas and enabling each the first areas to form an under bump metallurgy layer.07-18-2013
20130122700Multi-Die Stacking Using Bumps with Different Sizes - A device includes a first die having a first side and a second side opposite to first side, the first side includes a first region and a second region, and a first metal bump of a first horizontal size formed on the first region of the first side of the first die. A second die is bonded to the first metal bump at the first side of the first die. A dielectric layer is formed over the first side of the first die and includes a first portion directly over the second die, a second portion covering the second die. A second metal bump of a second horizontal size greater than the first horizontal size is formed on the second region of the first side of the first die. An electrical component is bonded to the first side of the first die through the second metal bump.05-16-2013
20130196498BUMPING PROCESS AND STRUCTURE THEREOF - A bumping process includes providing a silicon substrate; forming a titanium-containing metal layer on silicon substrate, the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas; forming a first photoresist layer on titanium-containing metal layer; patterning the first photoresist layer to form a plurality of first opening slots; forming a plurality of copper bumps within first opening slots, said copper bump comprises a first top surface and a first ring surface; removing the first photoresist layer; forming a second photoresist layer on titanium-containing metal layer; patterning the second photoresist layer to form a plurality of second opening slots; forming a plurality of bump isolation layers at spaces, the first top surfaces and the first ring surfaces; forming a plurality of connective layers on bump isolation layers; removing the second photoresist layer, removing the second areas to form an under bump metallurgy layer.08-01-2013

Patent applications in class Bump electrode

Patent applications in all subclasses Bump electrode