Class / Patent application number | Description | Number of patent applications / Date published |
438607000 | With epitaxial conductor formation | 8 |
20080286957 | METHOD FORMING EPITAXIAL SILICON STRUCTURE - A method of forming an epitaxial silicon structure is disclosed. The method includes performing a first epitaxial growth process using a first source gas including silicon (Si) and hydrogen chloride (HCl) to form a first epitaxial silicon layer on a substrate, and performing a second epitaxial growth process using a second source gas including silicon (Si) and chlorine (Cl) to form a second epitaxial silicon layer on the first epitaxial silicon layer. | 11-20-2008 |
20090068830 | Microelectronic package interconnect and method of fabrication thereof - A method of interconnecting and an interconnect is provided to connect a first component and a second component of an integrated circuit. The interconnect includes a plurality of Carbon Nanotubes (CNTs), which provide a conducting path between the first component and the second component. The interconnect further includes a passivation layer to fill the gaps between adjacent CNTs. A method of producing Anisotropic Conductive Film (ACF) and an ACF is provided. The ACF includes a plurality of CNTs, which provide a conducting path between a first side of the ACF and a second side of the ACF. The sides of the ACF can also include a conductive curable adhesive layer. In an embodiment, the conductive curable adhesive layer can incorporate a B-stage cross-linkable polymer and silver particles. | 03-12-2009 |
20100159689 | SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS WITH STRESS BUFFER SPACERS AND METHODS OF FABRICATING THE SAME - A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate. | 06-24-2010 |
20110300704 | SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS WITH STRESS BUFFER SPACERS AND METHODS OF FABRICATING THE SAME - A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate. | 12-08-2011 |
20140134837 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for manufacturing the semiconductor device may include forming a capping layer including a bit line contact hole on a substrate, forming a spacer on inner walls of the bit line contact hole, forming a bit line contact in the bit line contact hole, forming a bit line layer on the substrate, exposing the spacer by etching the bit line layer, and etching the spacer. | 05-15-2014 |
20150037970 | Silicon Film Forming Method, Thin Film Forming Method and Cross-Sectional Shape Control Method - The present disclosure provides a silicon film forming method for forming a silicon film on a workpiece having a processed surface, including: forming a seed layer by supplying a high-order aminosilane-based gas containing two or more silicon atoms in a molecular formula onto the processed surface and by having silicon adsorbed onto the processed surface; and forming a silicon film by supplying a silane-based gas not containing an amino group onto the seed layer and by depositing silicon onto the seed layer, wherein, when forming a seed layer, a process temperature is set within a range of 350 degrees C. or lower and a room temperature or higher. | 02-05-2015 |
20160126103 | RECESS FILLING METHOD AND PROCESSING APPARATUS - There is provided a method of filling a recess of a workpiece, which includes: forming a first thin film made of a semiconductor material along a wall surface defining a recess in a semiconductor substrate; annealing the workpiece within a vessel whose internal process is set to a first pressure, and forming an epitaxial region which is generated by crystallizing the semiconductor material of the first thin film, along a surface defining the recess, without moving the first thin film; forming a second thin film made of the semiconductor material along the wall surface defining the recess; and annealing the workpiece within the vessel whose internal pressure is set to a second pressure lower than the first pressure, and forming a further epitaxial region which is generated by crystallizing the semiconductor material of the second thin film which is moved toward a bottom of the recess. | 05-05-2016 |
20190148131 | APPARATUS AND METHOD FOR SELECTIVE DEPOSITION | 05-16-2019 |