Class / Patent application number | Description | Number of patent applications / Date published |
438598000 | Selectively interconnecting (e.g., customization, wafer scale integration, etc.) | 61 |
20090104765 | SEMICONDUCTOR DEVICE HAVING DIFFUSION LAYERS AS BIT LINES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films formed between the respective adjacent bit line diffusion layers on the semiconductor region; and a plurality of word lines each formed on the semiconductor region in a column direction and each intersecting with the bit line insulating films and the gate insulating films. Memory cells are formed at intersections of the gate insulating films and the word lines. A plurality of connection diffusion layers including connection parts electrically connected to the bit line diffusion layers are formed in the upper portion of the semiconductor region, and a level of upper faces of the connection parts is lower than a level of upper faces of the connection diffusion layers in the semiconductor region. | 04-23-2009 |
20090142916 | APPARATUS AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT - On aspect is a method to manufacture an integrated circuit including a reshaping process of the wafer edge region and an apparatus to perform the reshaping process. | 06-04-2009 |
20090239369 | Method of Forming Electrical Interconnects within Insulating Layers that Form Consecutive Sidewalls - Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect. | 09-24-2009 |
20090311858 | PROGRAMMABLE VIA STRUCTURE AND METHOD OF FABRICATING SAME - A programmable via structure is provided as well as a method of fabricating the same. The inventive programmable via a semiconductor substrate. An oxide layer such as a thermal oxide is located on a surface of the semiconductor substrate. A patterned heating material is located on a surface of the oxide layer. The inventive structure also includes a patterned dielectric material having a least one via filled with a phase change material (PCM). The patterned dielectric material including the PCM filled via is located on a surface of the patterned heating material. A patterned diffusion barrier is located on an exposed surface of said at least one via filled with the phase change material. The inventive structure also includes contact vias that extend through the patterned dielectric material. The contact vias are filled with a conductive material which also extends onto the upper surface of the patterned dielectric material. A conductive material which serves as the input of the device is located atop the patterned diffusion barrier that is located directly above the via that is filled with the phase change material. | 12-17-2009 |
20100159688 | Device fabrication - Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes. | 06-24-2010 |
20110263116 | ULTRAHIGH DENSITY PATTERNING OF CONDUCTING MEDIA - A reconfigurable device and a method of creating, erasing, or reconfiguring the device are provided. At an interface between a first insulating layer and a second insulating layer, an electrically conductive, quasi one- or zero-dimensional electron gas is present such that the interface presents an electrically conductive region that is non-volatile. The second insulating layer is of a thickness to allow metal-insulator transitions upon the application of a first external electric field. The electrically conductive region is subject to erasing upon application of a second external electric field. | 10-27-2011 |
20120009774 | DEVICE FOR DETECTING AN ATTACK AGAINST AN INTEGRATED CIRCUIT - An integrated circuit including an intrusion attack detection device. The device includes a single-piece formed of a conductive material and surrounded with an insulating material and includes at least one stretched or compressed elongated conductive track, connected to a mobile element, at least one conductive portion distant from said piece and a circuit for detecting an electric connection between the piece and the conductive portion. A variation in the length of said track in an attack by removal of the insulating material, causes a displacement of the mobile element until it contacts the conductive portion. | 01-12-2012 |
20120156870 | Chip Pad Resistant to Antenna Effect and Method - A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC. | 06-21-2012 |
20120302054 | CONDUCTIVE STRUCTURES FOR MICROFEATURE DEVICES AND METHODS FOR FABRICATING MICROFEATURE DEVICES - Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method for fabricating interposer devices having substrates includes forming a plurality of conductive sections on a first substrate in a first pattern. The method continues by forming a plurality of conductive sections on a second substrate in a second pattern. The method further includes constructing a plurality of conductive lines in a common third pattern on both the first substrate and the second substrate. The conductive lines can be formed on the first and second substrates either before or after forming the first pattern of conductive sections on the first substrate and/or forming the second pattern of conductive sections on the second substrate. | 11-29-2012 |
20130059436 | DEVICE FABRICATION - Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes. | 03-07-2013 |
20140248764 | METHODS OF FORMING STRUCTURES ON AN INTEGRATED CIRCUIT PRODUCT - One illustrative method disclosed herein includes forming a seed layer above a substrate that includes a conductive region, wherein the seed layer is comprised of a metal-containing material, forming a nucleation layer on the seed layer, wherein the nucleation layer is comprised of a transition metal oxide ceramic material, and performing a thermal treatment process at a temperature so as to generate a plurality of spaced-apart, vertically oriented alloy structures, wherein the alloy structures are comprised of at least one material from the seed layer and at least one material from the nucleation layer. | 09-04-2014 |
20150126026 | ELECTRICAL COMPONENTS AND METHODS AND SYSTEMS OF MANUFACTURING ELECTRICAL COMPONENTS - A method of manufacturing an electrical component includes providing a substrate, applying an insulating layer on the substrate, applying a circuit layer on the insulating layer, irradiating the insulating layer with an electron beam to transform the insulating layer, and irradiating the circuit layer with an electron beam to transform the circuit layer. The substrate may be a metallic substrate that is highly thermally conductive. The insulating layer provides electrical isolation and effective heat transfer between the circuit layer and the substrate. The method may include coupling a light emitting diode module or other active circuits requiring thermal management to the circuit layer resident on the electrically insulating/thermally conducting layer. | 05-07-2015 |
438599000 | With electrical circuit layout | 7 |
20080233732 | METHOD OF PLACING WIRES - A method of placing wires for placing a shield wire with respect to a shield subject wire placed on a chip, a method includes setting a plurality of wire tracks on the chip, dividing the chip into at least a first area and a second area according to a division boundary, confirming whether the shield subject wire exists around the division boundary in the second area when the division boundary is not laid on top of the wire track, and determining whether to place the shield wire on a wire track being adjacent to division boundary in the first area based on the confirming. | 09-25-2008 |
20090111257 | Techniques for Impeding Reverse Engineering - Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer. | 04-30-2009 |
20110159682 | METHODS OF MANUFACTURING MEMORY DEVICES - A method of manufacturing a memory device is disclosed. The method includes providing a substrate, forming a number of memory sectors on the substrate, wherein each of the memory sectors is coupled to an adjacent one via a first diffused region in the substrate and is coupled to another adjacent one via at least one second diffused region in the substrate, forming a first dielectric layer on the memory sectors, forming a first conductive structure through the first dielectric layer to the first diffused region, and at least one second conductive structure through the first dielectric layer to the at least one second diffused region, forming a patterned first mask layer on the first dielectric layer, the first conductive structure and the at least one second conductive structure, the patterned first mask layer exposing the first conductive structure, and etching back the first conductive structure. | 06-30-2011 |
20110171821 | Semiconductor Devices and Methods of Manufacturing Thereof - Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features. | 07-14-2011 |
20130295761 | Three-Dimensional Semiconductor Device and Method for Fabricating the Same - Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes. | 11-07-2013 |
20160161843 | INTELLIGENT UNIFORM MASKS FOR SEMICONDUCTOR FABRICATION - A method for reducing pattern density effects in semiconductor fabrication includes forming a first mask that includes one or more arrays of uniformly distributed pattern. Each array of the uniformly distributed pattern includes similar pattern elements having similar dimensions, orientations, and distances. Using the first mask allows forming a layer of semiconductor devices based on the first mask with reduced pattern density effects. A second mask is formed for the layer based on the first mask. The second mask includes undesired portions, for which the pattern is not uniform. Using the second mask allows removing the undesired portions of the formed layer of the semiconductor devices to create desired structures on the formed layer without a need for using optical proximity correction (OPC). | 06-09-2016 |
20160197068 | Power Gating for Three Dimensional Integrated Circuits (3DIC) | 07-07-2016 |
438600000 | Using structure alterable to conductive state (i.e., antifuse) | 14 |
20080318407 | Method for Forming Storage Electrode of Semiconductor Memory Device - In order to form a storage electrode of a semiconductor memory device, an interlayer dielectric layer is formed on a semiconductor substrate having a bit line thereon. A contact hole exposing the semiconductor substrate is formed by patterning the interlayer dielectric layer. A polysilicon layer is etched to a predetermined thickness using polysilicon etching gas after the polysilicon layer is deposited. An over-etch process is performed relative to the polysilicon layer, and then a storage node contact having a planarized surface is formed in the contact hole by performing an etching process for planarizing the surface of the polysilicon layer. A mold insulating layer is formed on the resultant structure, in which the mold insulating layer exposes an area where the storage node contact is formed. A storage electrode coupled to the storage node contact is formed. | 12-25-2008 |
20090029541 | METHOD OF FABRICATING ANTI-FUSE AND METHOD OF PROGRAMMING ANTI-FUSE - A method of fabricating an anti-fuse includes firstly forming a dielectric layer on a substrate having a first conductive type. Next, a conductive layer is formed on the dielectric layer. A first ion implantation process is then performed, such that the conductive layer has the first conductive type. Thereafter, the conductive layer and the dielectric layer are patterned to form a gate and a gate dielectric layer. The gate and the gate dielectric layer together construct a gate structure. Finally, two source/drain regions having a second conductive type are formed in the substrate at respective sides of the gate. Besides, a method of programming an anti-fuse includes firstly applying a voltage to a gate to break down a gate dielectric layer. The gate and a substrate are then electrically conducted or a P/N forward bias is then formed in a P/N junction after the breakdown of the gate dielectric layer. | 01-29-2009 |
20090163018 | Method to prevent alloy formation when forming layered metal oxides by metal oxidation - The present method of fabricating a resistive memory device includes the steps of providing a first electrode, oxidizing a portion of the first electrode with an oxidizing agent, providing a metal body on the oxidized portion of the first electrode, oxidizing the entire metal body with an oxidizing agent, and providing a second electrode on the oxidized metal body. | 06-25-2009 |
20090239370 | Methods Of Forming An Antifuse And A Conductive Interconnect, And Methods Of Forming DRAM Circuitry - A first via opening is formed to a first conductor and a second via opening is formed to a second conductor. The first and second via openings are formed through insulative material. Then, the first conductor is masked from being exposed through the first via opening and to leave the second conductor outwardly exposed through the second via opening. An antifuse dielectric is formed within the second via opening over the exposed second conductor while the first conductor is masked. Then, the first conductor is unmasked to expose it through the first via opening. Then, conductive material is deposited to within the first via opening in conductive connection with the first conductor to form a conductive interconnect within the first via opening to the first conductor and to within the second via opening over the antifuse dielectric to form an antifuse comprising the second conductor, the antifuse dielectric within the second via opening and the conductive material deposited to within the second via opening. Other aspects are contemplated. | 09-24-2009 |
20090305493 | ADOPTING FEATURE OF BURIED ELECTRICALLY CONDUCTIVE LAYER IN DIELECTRICS FOR ELECTRICAL ANTI-FUSE APPLICATION - An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature. | 12-10-2009 |
20090317968 | Method for Manufacturing Memory Element - A conductive paste including conductive particles each of which has a size of greater than or equal to 0.1 μm and less than or equal to 10 μm, a resin, and a solvent is placed over a first conductor and the solvent is vaporized. In this manner, a second conductor having the conductive particles and a memory layer including the resin between the first conductor and the conductive particles is formed. | 12-24-2009 |
20100081268 | DAMASCENE PROCESS FOR CARBON MEMORY ELEMENT WITH MIIM DIODE - Forming a metal-insulator diode and carbon memory element in a single damascene process is disclosed. A trench having a bottom and a sidewall is formed in an insulator. A first diode electrode is formed in the trench during a single damascene process. A first insulating region comprising a first insulating material is formed in the trench during the single damascene process. A second insulating region comprising a second insulating material is formed in the trench during the single damascene process. A second diode electrode is formed in the trench during the single damascene process. The first insulating region and the second insulating region reside between the first diode electrode and the second diode electrode to form a metal-insulator-insulator-metal (MIIM) diode. A region of carbon is formed in the trench during the single damascene process. At least a portion of the carbon is electrically in series with the MIIM diode. | 04-01-2010 |
20100203719 | Method of Forming an Antifuse and a Conductive Interconnect, and Methods of Forming DRAM Circuitry - A first via opening is formed to a first conductor and a second via opening is formed to a second conductor. The first and second via openings are formed through insulative material. Then, the first conductor is masked from being exposed through the first via opening and to leave the second conductor outwardly exposed through the second via opening. An antifuse dielectric is formed within the second via opening over the exposed second conductor while the first conductor is masked. Then, the first conductor is unmasked to expose it through the first via opening. Then, conductive material is deposited to within the first via opening in conductive connection with the first conductor to form a conductive interconnect within the first via opening to the first conductor and to within the second via opening over the antifuse dielectric to form an antifuse comprising the second conductor, the antifuse dielectric within the second via opening and the conductive material deposited to within the second via opening. Other aspects are contemplated. | 08-12-2010 |
20100233874 | METHOD FOR FORMING FUNCTIONAL ELEMENT USING METAL-TO-INSULATOR TRANSITION MATERIAL, FUNCTIONAL ELEMENT FORMED BY METHOD, METHOD FOR PRODUCING FUNCTIONAL DEVICE, AND FUNCTIONAL DEVICE PRODUCED BY METHOD - A method for forming a functional element includes a first step of forming an insulating layer composed of an insulator phase of a transition metal oxide serving as a metal-to-insulator transition material, the transition metal oxide being mainly composed of vanadium dioxide, and a second step of causing part of the insulating layer to transition to a metallic phase, in which the insulator phase differs from the metallic phase in terms of electrical resistivity and/or light transmittance. | 09-16-2010 |
20110034021 | PROGRAMMABLE THROUGH SILICON VIA - Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack. | 02-10-2011 |
20110217836 | Programmable Via Devices in Back End of Line Level - Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; at least one isolation layer over the first dielectric layer; a heater within the isolation layer; a capping layer over a side of the isolation layer opposite the first dielectric layer; at least one programmable via extending through the capping layer and at least a portion of the isolation layer and in contact with the heater, the programmable via comprising at least one phase change material; a conductive cap over the programmable via; a second dielectric layer over a side of the capping layer opposite the isolation layer; a first conductive via and a second conductive via, each extending through the second dielectric layer, the capping layer and at least a portion of the isolation layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive cap. | 09-08-2011 |
20110312175 | METHODS FOR FORMING ANTIFUSES WITH CURVED BREAKDOWN REGIONS - Methods are disclosed for forming an antifuse that includes first and second conductive regions having spaced-apart curved portions, with a first dielectric region therebetween, forming in combination with the curved portions a curved breakdown region adapted to switch from a substantially non-conductive initial state to a substantially conductive final state in response to a predetermined programming voltage. A sense voltage less than the programming voltage is used to determine the state of the antifuse as either OFF (high impedance) or ON (low impedance). A shallow trench isolation (STI) region is desirably provided adjacent the breakdown region to inhibit heat loss from the breakdown region during programming. Lower programming voltages and currents are observed compared to antifuses using substantially planar dielectric regions. In a further embodiment, a resistive region is inserted in one lead of the antifuse with either planar or curved breakdown regions to improve post-programming sense reliability. | 12-22-2011 |
20130065387 | METHOD AND STRUCTURE OF MONOLITHICALLY INTEGRATED ESD SUPPERSSION DEVICE - A method of fabricating ESD suppression device includes forming conductive pillars dispersed in a dielectric material. The gaps formed between each pillar in the device behave like spark gaps when a high voltage ESD pulse occurs. When the voltage of the pulse reaches the “trigger voltage” these gaps spark over, creating a very low resistance path. In normal operation, the leakage current and the capacitance is very low, due to the physical gaps between the conductive pillars. The proposed method for fabricating an ESD suppression device includes micromachining techniques to be on-chip with device ICs. | 03-14-2013 |
20140024210 | LOW COST ANTI-FUSE STRUCTURE AND METHOD TO MAKE SAME - An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure. | 01-23-2014 |
438601000 | Using structure alterable to nonconductive state (i.e., fuse) | 28 |
20080206978 | ELECTRONIC FUSES IN SEMICONDUCTOR INTEGRATED CIRCUITS - A structure fabrication method. The method includes providing a structure. The structure includes (a) a substrate layer, (b) a first fuse electrode in the substrate layer, and (c) a fuse dielectric layer on the substrate layer and the first fuse electrode. The method further includes (i) forming an opening in the fuse dielectric layer such that the first fuse electrode is exposed to a surrounding ambient through the opening, (ii) forming a fuse region on side walls and bottom walls of the opening such that the fuse region is electrically coupled to the first fuse electrode, and (iii) after said forming the fuse region, filling the opening with a dielectric material. | 08-28-2008 |
20080254609 | APPARATUS AND METHOD FOR ELECTRONIC FUSE WITH IMPROVED ESD TOLERANCE - Method of making an electronic fuse blow resistor structure. In one embodiment, the method includes forming an insulator film, depositing a conductor on the insulator film, and after the depositing, etching the conductor to form a plurality of spaced apart non-conductive regions and a plurality of spaced-apart conductive regions. In another embodiment, the method includes forming the insulator film, forming a conductive sheet, and sub-dividing the conductive sheet into the plurality of conductive regions. | 10-16-2008 |
20080293230 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A silicon-rich oxide (SRO) film is arranged over an uppermost third-level wiring in a semiconductor device. Then, a silicon oxide film and a silicon nitride film lying over the third-level wiring are dry-etched to expose part of the third-level wiring to thereby form a bonding pad and to form an opening over the fuse. In this procedure, the SRO film serves as an etch stopper. This optimizes the thickness of the dielectric films lying over the fuse. | 11-27-2008 |
20090017609 | RECTANGULAR CONTACT USED AS A LOW VOLTAGE FUSE ELEMENT - A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse elements. In one embodiment, the fuse element is constructed with a rectangular-shaped contact. The contact is made long enough so that it makes contact at each end with a metal layer, but design rule spacing is still maintained between the connections with the metal layer. The overlapping areas between the rectangular contact and the metal layers are asymmetrical. Alternatively, these overlapping areas are smaller than the design rule overlap requirements. In a second embodiment, a fuse element is constructed with a plurality of rectangular-shaped contacts. As a result, a current value that is significantly lower than conventional fuse current values, can be used to melt such a contact or blow the fuse. | 01-15-2009 |
20090149013 | METHOD OF FORMING A CRACK STOP LASER FUSE WITH FIXED PASSIVATION LAYER COVERAGE - A crack stop void is formed in a low-k dielectric or silicon oxide layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The passivation layer is fixed in place by using an etch stop shape of conducting material which is formed simultaneously with the formation of the interconnect structure. This produces a reliable and repeatable fuse structure that has controllable passivation layer over the fuse structure that is easily manufactured. | 06-11-2009 |
20090275191 | METHOD AND APPARATUS FOR ELECTROSTATIC DISCHARGE PROTECTION USING A TEMPORARY CONDUCTIVE COATING - A method and apparatus for providing ESD protection of an integrated circuit using a temporary conductive coating. The method deposits a temporary conductive coating upon a chip die between contacts to be protected such that a conductive path is created between contacts, provides a carrier substrate that is then bonded to the chip die and then the conductive coating is deactivated to ready the device for use. The deactivation of the conductive coating may involve physical removal of the conductive coating (or a portion thereof), oxidation of the conductive coating to form a non-conductive coating, or some other process to interrupt the conductive path between contacts. The apparatus of the invention is a chip having a temporary conductive coating deposited thereon to protect the integrated circuit from ESD events. | 11-05-2009 |
20100178760 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - A semiconductor device includes a first interlayer insulating film formed on a semiconductor substrate; a second interlayer insulating film formed on the first interlayer film and including a plurality of grooves; a first barrier metal formed on inner surfaces of the grooves; a first interconnect part and a first bonding electrode part including a copper film formed on the first barrier metal; a second barrier metal formed on the first interconnect part and the first bonding electrode part; a second interconnect part including a metal film formed on the first interconnect part via the second barrier metal; a second bonding electrode part including a metal film formed on the first bonding electrode part via the second barrier metal; and a third interlayer insulating film formed on the second interlayer insulating film, the second interconnect part, and the second bonding electrode part, and including an opening that allows exposure of the surface of the second bonding electrode part. | 07-15-2010 |
20100221907 | Method of Fabricating a Fuse for Use in a Semiconductor Device - A fuse in a semiconductor device includes: first and second fuse patterns, each being in the shape of a bar, separated from each other in a blowing region; first and second contact plugs respectively coupled to the first and the second fuse patterns; and a third fuse pattern coupled to the first and the second fuse patterns through the first and the second contact plugs. | 09-02-2010 |
20100240210 | STRAPPING CONTACT FOR CHARGE PROTECTION - A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area. | 09-23-2010 |
20100279500 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device having increased reliability includes a fuse region and a monitoring region. Fuses are located on an insulation film in the fuse region and are exposed through fuse windows. A monitoring pattern is located on the insulation film in the monitoring region. The monitoring pattern includes sub-patterns that are exposed through a monitoring window. | 11-04-2010 |
20110212613 | SEMICONDUCTOR DEVICES HAVING A FUSE AND METHODS OF CUTTING A FUSE - A semiconductor device and methods of cutting a fuse of a semiconductor device are provided, the semiconductor device includes a semiconductor substrate that includes a fuse region, a plurality of fuse patterns disposed in the fuse region of the semiconductor substrate, and an insulating layer that insulates the fuse patterns from the semiconductor substrate. The fuse patterns each include a fuse. The fuse patterns are linked to the semiconductor substrate. | 09-01-2011 |
20110256709 | LEVEL POSTURE SENSING CHIP AND ITS MANUFACTURING METHOD, LEVEL POSTURE SENSOR - The present invention discloses a gas pendulum style level posture sensing chip and its manufacturing method and a level posture sensor. The gas pendulum style level posture sensing chip includes: a semiconductor substrate; two sets of arm thermosensitive fuses formed on the surface of the semiconductor substrate, each set of the thermosensitive fuses including two thermosensitive fuses in parallel to each other, the two sets of thermosensitive fuses being vertical to each other; electrodes formed at the two ends of the thermosensitive fuses. For the level posture sensing chip and sensor provided by the present invention, the parallelism and verticality of the thermosensitive fuses is high in precision such that the more accurate measurement can be implemented. | 10-20-2011 |
20110256710 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - When a metal cap film is provided on an electric fuse, the break-ability of the electric fuse is reduced. A semiconductor device | 10-20-2011 |
20120088361 | FUSE PART IN SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of the first conductive pattern are spaced apart by the space part along the first direction. The fuse part includes a first insulation pattern formed over the space part, the first insulation pattern having a width smaller than a width of the first conductive pattern along the second direction and a thickness greater than a thickness of the first conductive pattern, and a second conductive pattern formed over the first insulation pattern, the second conductive pattern having a width greater than the width of the first insulation pattern along the second direction. | 04-12-2012 |
20120171857 | ELECTRICALLY PROGRAMMABLE FUSE USING ANISOMETRIC CONTACTS AND FABRICATION METHOD - A fabrication method for fabricating an electrically programmable fuse method includes depositing a polysilicon layer on a substrate, patterning an anode contact region, a cathode contact region and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, depositing a silicide layer on the polysilicon layer, and forming a plurality of anisometric contacts on the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively. | 07-05-2012 |
20120196434 | E-fuse Structure Design in Electrical Programmable Redundancy for Embedded Memory Circuit - An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer. | 08-02-2012 |
20120214301 | STRUCTURE AND METHOD TO FORM E-FUSE WITH ENHANCED CURRENT CROWDING - An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region. | 08-23-2012 |
20120276732 | PROTECTION LAYER FOR PREVENTING LASER DAMAGE ON SEMICONDUCTOR DEVICES - A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy. | 11-01-2012 |
20120289041 | BALLASTED POLYCRYSTALLINE FUSE - A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to form first and second terminal portions of a first width joined along a length of the fuse by a fuse portion of a second width narrower than the first width. First and second contacts are connected to the first and second terminal portions respectively. The silicide material being discontinuous in a terminal region of the second layer along the length of the fuse. | 11-15-2012 |
20130089976 | FUSE STRUCTURE FOR HIGH INTEGRATED SEMICONDUCTOR DEVICE - The present invention provides a technology capable of improving an operation reliability of a semiconductor device. Particularly, a fuse material which constitutes the copper can be prevented from migrating being locked in the recesses or the grooves after a blowing process. A semiconductor device includes an insulating layer including a concave-convex-shaped upper part; and a fuse formed on the insulating layer. | 04-11-2013 |
20130102146 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME - A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via. | 04-25-2013 |
20130109167 | NANOWIRE EFUSES | 05-02-2013 |
20130316526 | VOLTAGE SWITCHABLE DIELECTRIC FOR DIE-LEVEL ELECTROSTATIC DISCHARGE (ESD) PROTECTION - A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC. A method includes depositing a voltage-switchable dielectric layer on a first die between a first terminal and a second terminal. | 11-28-2013 |
20140065813 | SIZE-FILTERED MULTIMETAL STRUCTURES - A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width. | 03-06-2014 |
20140106559 | SYSTEM AND METHOD FOR FORMING AN ALUMINUM FUSE FOR COMPATIBILITY WITH COPPER BEOL INTERCONNECT SCHEME - A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse. | 04-17-2014 |
20140127895 | Semiconductor Device Comprising a Fuse Structure and a Method for Manufacturing such Semiconductor Device - A semiconductor device comprises a semiconductor substrate, an anorganic isolation layer on the semiconductor substrate and a metallization layer on the anorganic isolation layer. The metallization layer comprises a fuse structure. At least in an area of the fuse structure the metallization layer and the anorganic isolation layer have a common interface. | 05-08-2014 |
20140349474 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention includes fuse patterns spaced apart from each other by a predetermined distance over a first interlayer insulation film; a second interlayer insulation film disposed between the fuse patterns over the first interlayer insulation film; and a capping film pattern formed over the fuse patterns and the second interlayer insulation films, the capping film pattern including a slot exposing the second interlayer insulation film. | 11-27-2014 |
20150099356 | E-FUSES CONTAINING AT LEAST ONE UNDERLYING TUNGSTEN CONTACT FOR PROGRAMMING - Semiconductor structures are provided containing an electronic fuse (E-fuse) that includes a fuse element and at least one underlying tungsten contact that is used for programming the fuse element. In some embodiments, a pair of neighboring tungsten contacts is used for programming the fuse element. In another embodiment, an overlying conductive region can be used in conjunction with one of the underlying tungsten contacts to program the fuse element. In the disclosed structures, the fuse element is in direct contact with upper surfaces of a pair of underlying tungsten contacts. In one embodiment, the semiconductor structures may include an interconnect level located atop the fuse element. The interconnect level has a plurality of conductive regions embedded therein. In other embodiments, the fuse element is located within an interconnect level that is located atop the tungsten contacts. | 04-09-2015 |