Entries |
Document | Title | Date |
20080200020 | Semiconductor device and method of fabricating a semiconductor device - A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation. The second deposition, with an associated ion implant for doping, completes the gate electrode. With the two-deposition process, it is possible to maximize the doping at the gate electrode/gate dielectric interface while minimizing risk of boron penetration of the gate dielectric. A further development of this method includes the patterning of both gate electrode layers with the advantage of utilizing the drain extension and source/drain implants as the gate doping implants and the option of offsetting the two patterns to create an asymmetric device. A method is also provided for the formation of shallow junctions in a semiconductor substrate by diffusion of dopant from an implanted layer contained within a dielectric layer into the semiconductor surface. Further, the ion implanted layer is provided with a second implanted species, such as hydrogen, in addition to the intended dopant species, wherein said species enhances the diffusivity of the dopant in the dielectric layer. | 08-21-2008 |
20080200021 | SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK - A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO | 08-21-2008 |
20080220604 | AIR BREAK FOR IMPROVED SILICIDE FORMATION WITH COMPOSITE CAPS - Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is formed on an n-FET structure. However, prior to the deposition of the second metal layer, the protective layer is exposed to air. This air break step alters the adhesion between the protective cap layer and the second metal layer and thereby, effects the stress imparted upon the first metal layer during silicide formation. The result is a more tensile silicide that is optimal for n-FET performance. Additionally, the method allows such a tensile silicide region to be formed using a relatively thin first metal layer-protective cap layer-second metal layer stack, and particularly, a relatively thin second metal layer, to minimize mechanical energy build up at the junctions between the gate conductor and the sidewall spacers to avoid silicon bridging. | 09-11-2008 |
20080242072 | PLASMA DRY ETCH PROCESS FOR METAL-CONTAINING GATES - A method of manufacturing a semiconductor device. The method comprises forming a gate stack layer. The gate stack has an insulating layer on a substrate, a metal-containing layer on the insulating layer, a metal nitride barrier layer on the metal-containing layer, and a silicon-containing layer on the metal nitride barrier layer. The method also comprises patterning the gate stack layer. Pattering includes a plasma etch of the metal nitride barrier layer. The plasma etch has a chloride-containing feed gas and a physical etch component. The physical etch component includes a high-mass species having a molecular weight of greater than about 71 gm/mol. | 10-02-2008 |
20080268631 | Method of Forming a Silicided Gate Utilizing a CMP Stack - A method for fabricating a semiconductor device includes forming a silicided gate utilizing a CMP stack. The CMP stack includes a first liner formed over the underlying semiconductor device and a first dielectric layer formed over the first liner layer. The first dielectric layer is formed to approximately the height of the gate. A second liner layer is formed over the first dielectric layer. Since the first dielectric layer is formed to approximately the height of the gate, the second liner over the moat regions is at approximately the height of the first liner over the gate. A CMP process is performed to expose the first liner over the top of the gate. Since the first dielectric layer is formed to the height of the gate, a portion of the second liner remains over the moat regions after the CMP process. Afterwards, the gate is exposed and a silicidation is performed to create a silicided gate. | 10-30-2008 |
20080299754 | Methods for forming MOS devices with metal-inserted polysilicon gate stack - A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a metal-containing layer on the gate dielectric; and forming a composite layer over the metal-containing layer. The step of forming the composite layer includes forming an un-doped silicon layer substantially free from p-type and n-type impurities; and forming a silicon layer adjoining the un-doped silicon layer. The step of forming the silicon layer comprises in-situ doping a first impurity. (or need to be change to: forming a silicon layer first & then forming un-doped silicon layer) The method further includes performing an annealing to diffuse the first impurity in the silicon layer into the un-doped silicon layer. | 12-04-2008 |
20090011587 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. The method of fabricating the semiconductor device comprises providing a substrate. Next, an insulating layer, a conductive layer and a silicide layer are formed on the substrate in sequence. Next, a hard masking layer is formed on the silicide layer exposing a portion of the silicide layer. A first etching step is performed to remove the silicide layer and the underlying conductive layer which are not covered by the hard masking layer, thereby forming a gate stack. And next, a second etching step is performed to remove any remaining conductive layer not covered by the hard masking layer after the first etching step. The second etching step is performed with an etchant comprising ammonium hydroxide. | 01-08-2009 |
20090029538 | PROCESS FOR MAKING A SEMICONDUCTOR DEVICE USING PARTIAL ETCHING - A method including partially etching a first portion of a first layer, wherein the first layer is a conductive layer, is provided. The method further includes removing at least a portion of a second layer. The method further includes completing etching of said first portion of the conductive layer so that said first portion of the conductive layer is removed. The method further includes completing formation of the semiconductor device. | 01-29-2009 |
20090029539 | METHOD FOR FABRICATING TUNGSTEN LINE AND METHOD FOR FABRICATING GATE OF SEMICONDUCTOR DEVICE USING THE SAME - A method for fabricating a tungsten (W) line includes forming a silicon-containing layer, forming a diffusion barrier layer over the silicon-containing layer, forming a tungsten layer over the diffusion barrier layer, and performing a thermal treatment process on the tungsten layer to increase a grain size of the tungsten layer. | 01-29-2009 |
20090042380 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gate dielectric film, a poly-silicon film, a film of a refractory metal such as tungsten, and a gate cap dielectric film are sequentially laminated on a semiconductor substrate. The gate cap dielectric film and the refractory metal film are selectively removed by etching. Thereafter, a double protection film including a silicon nitride film and a silicon oxide film is formed on side surfaces of the gate cap dielectric film, the refractory metal film, and the poly-silicon film. The poly-silicon film is etched using the double protection film as a mask. Thereafter, the semiconductor substrate is light oxidized to form a silicon oxide film on side surfaces of the poly-silicon film. Accordingly, a junction leakage of a MOSFET having a gate electrode of a poly-metal structure, particularly, a memory cell transistor of a DRAM, can be further reduced. | 02-12-2009 |
20090053882 | KRYPTON SPUTTERING OF THIN TUNGSTEN LAYER FOR INTEGRATED CIRCUITS - A method of depositing a bilayer of tungsten over tungsten nitride by a plasma sputtering process in which krypton is used as the sputter working gas during the tungsten deposition. Argon may be used as the sputtering working gas during the reactive sputtering deposition of tungsten nitride. The beneficial effect of reduction of tungsten resistivity is increased when the thickness of the tungsten layer is less than 50 nm and further increased when less than 35 nm. The method may be used in forming a gate stack including a polysilicon layer over a gate oxide layer over a silicon gate region of a MOS transistor in which the tungsten nitride acts as a barrier. A plasma sputter chamber in which the invention may be practiced includes gas sources of krypton, argon, and nitrogen. | 02-26-2009 |
20090053883 | METHOD OF SETTING A WORK FUNCTION OF A FULLY SILICIDED SEMICONDUCTOR DEVICE, AND RELATED DEVICE - A method of setting a work function of a fully silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a silicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the silicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction. | 02-26-2009 |
20090061611 | FABRICATING DUAL LAYER GATE ELECTRODES HAVING POLYSILICON AND A WORKFUNCTION METAL - A method for fabricating a dual layer gate electrode having a polysilicon layer and a workfunction metal layer comprises depositing a layer of a workfunction metal on a semiconductor substrate, depositing a layer of polysilicon on the workfunction metal layer, depositing a hard mask layer on the polysilicon layer, etching the hard mask layer to form a hard mask structure defining a gate electrode, etching the polysilicon layer to remove a portion of the polysilicon layer not protected by the hard mask structure, thereby forming a polysilicon structure beneath the hard mask structure, applying a mixture of ozone and water to exposed sidewalls of the polysilicon structure, thereby forming a silicon dioxide layer on the sidewalls, and etching the workfunction metal layer to remove a portion of the workfunction metal layer not protected by the hard mask structure, thereby forming a workfunction metal structure beneath the polysilicon structure. | 03-05-2009 |
20090068828 | DUAL WORK FUNCTION CMOS DEVICES UTILIZING CARBIDE BASED ELECTRODES - Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region. | 03-12-2009 |
20090087974 | METHOD OF FORMING HIGH-K GATE ELECTRODE STRUCTURES AFTER TRANSISTOR FABRICATION - A sophisticated high-k metal gate electrode structure may be formed after the deposition of a first part of an interlayer dielectric material, thereby providing a high degree of process compatibility with conventional CMOS techniques. Thus, sophisticated strain-inducing mechanisms may be readily implemented in the overall process flow, while nevertheless avoiding any high temperature processes during the formation of the sophisticated high-k dielectric gate stack. | 04-02-2009 |
20090093108 | SEMICONDUCTOR FABRICATION PROCESS INCLUDING SILICIDE STRINGER REMOVAL PROCESSING - A semiconductor fabrication process includes forming a gate electrode ( | 04-09-2009 |
20090111256 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a pattern including a first layer including tungsten, performing a gas flowing process on the pattern in a gas ambience including nitrogen, and forming a second layer over the pattern using a source gas including nitrogen, wherein the purge is performed at a given temperature for a given period of time in a manner that a reaction between the first layer and the nitrogen used when forming the second layer is controlled. | 04-30-2009 |
20090117726 | Integration Scheme for an NMOS Metal Gate - A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate electrode of the NMOS transistor. The method also includes depositing a NMOS-metal layer over the semiconductor substrate, depositing a fill-metal layer over the NMOS-metal layer, and then reducing the thickness of the NMOS metal layer and the fill metal layer to expose the gate electrodes of the NMOS transistor and the PMOS transistor. | 05-07-2009 |
20090130833 | INSULATING BUFFER FILM AND HIGH DIELECTRIC CONSTANT SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: an n-transistor including a first gate insulating film made of a high-dielectric-constant material and a first gate electrode fully silicided with a metal, the first gate insulating film and the first gate electrode being formed in this order over a semiconductor region; and a p-transistor including a second gate insulating film made of the high-dielectric-constant material and a second gate electrode fully silicided with the metal, the second gate insulating film and the second gate electrode being formed in this order over the semiconductor region. If the metal has a work function larger than a Fermi level in potential energy of electrons of silicon, a metal concentration of the second gate electrode is higher than that of the first gate electrode whereas if the metal has a work function smaller than the Fermi level of silicon, a metal concentration of the second gate electrode is lower than that of the first gate electrode. | 05-21-2009 |
20090142913 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof that can prevent mutual diffusion of impurity in a silicide layer and can decrease sheet resistance of an N-type polymetal gate electrode and a P-type polymetal gate electrode, respectively in the semiconductor device having gate electrodes of a polymetal gate structure and a dual gate structure are provided. The P-type polymetal gate electrode includes a P-type silicon layer containing P-type impurity, a silicide layer formed on the P-type silicon layer and having a plurality of silicide grains which are discontinuously disposed in a direction substantially parallel with the surface of the semiconductor substrate, a silicon film continuously formed on the surface of the P-type silicon layer exposed on the discontinuous part of the silicide layer and on the surface of the silicide layer, a second metal nitride layer formed on the silicon film, and a metal layer formed on the metal nitride layer. | 06-04-2009 |
20090163016 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING METAL GATE ELECTRODE AND ELECTRONIC FUSE - A method of fabricating a semiconductor device including a metal gate electrode and an electronic fuse. The method may include forming a gate dielectric layer on a semiconductor substrate, forming a first metal layer on the gate dielectric layer, forming a portion of the first metal layer in a first device region, forming a second metal layer on the semiconductor substrate comprising the portion of the first metal layer, forming a portion of the second metal layer in a second device region, forming a low-resistance layer on the semiconductor substrate comprising the portion of the first metal layer and the portion of the second metal layer, and patterning the low-resistance layer to form gate electrodes, and a fuse pattern of the low-resistance layer in a fuse region. | 06-25-2009 |
20090191699 | METHODS FOR FORMING SILICIDE CONDUCTORS USING SUBSTRATE MASKING - A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers. | 07-30-2009 |
20090233433 | Semiconductor device having silicon layer in a gate electrode - A method for forming a semiconductor device includes, in order, consecutively depositing a gate insulating film and a silicon layer on a semiconductor substrate, implanting boron into the silicon layer, diffusing the boron by heat-treating the silicon layer, implanting phosphorous into the silicon layer, diffusing at least the phosphorous by heat-treating the silicon layer, and patterning the silicon layer by using a dry etching technique. | 09-17-2009 |
20090239368 | Methods of Forming an Oxide Layer and Methods of Forming a Gate Using the Same - An oxide layer is selectively formed on a layer including silicon by a plasma process using hydrogen gas and a gas including oxygen. The hydrogen gas is controlled to have a flow rate less than about 50 percent of an overall flow rate by adding helium gas to the plasma process. | 09-24-2009 |
20090253257 | METHODS OF FABRICATING MULTI-LAYER NONVOLATILE MEMORY DEVICES - A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions. | 10-08-2009 |
20090258484 | METHODS FOR FABRICATING DUAL MATERIAL GATE IN A SEMICONDUCTOR DEVICE - A method for fabricating dual material gate structures in a device is provided. The dual material gate structures have different gate electrode materials in different regions of the device. In one embodiment, the method includes providing a substrate having a patterned first gate electrode and a patterned first gate dielectric layer disposed on the substrate, removing a portion of the first gate electrode from the substrate to define a trench on the substrate, and filling the trench to form a second gate electrode. | 10-15-2009 |
20090286387 | Modulation of Tantalum-Based Electrode Workfunction - A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer ( | 11-19-2009 |
20100015790 | TiC AS A THERMALLY STABLE p-METAL CARBIDE ON HIGH k SiO2 GATE STACKS - A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (pMOS) device. | 01-21-2010 |
20100041225 | STRUCTURE, DESIGN STRUCTURE AND METHOD OF MANUFACTURING DUAL METAL GATE VT ROLL-UP STRUCTURE - A structure, design structure and method of manufacturing is provided for a dual metal gate Vt roll-up structure, e.g., multi-work function metal gate. The method of manufacturing the multi-work function metal gate structure comprises forming a first type of metal with a first work function in a central region and forming a second type of metal with a second work function in at least one edge region adjacent the central region. The first work-function is different from the second work function. | 02-18-2010 |
20100055891 | DUAL GATE STRUCTURE, FABRICATION METHOD FOR THE SAME, SEMICONDUCTOR DEVICE HAVING THE SAME, AND SEMICONDUCTOR DEVICE FABRICATION METHOD - In one embodiment, a semiconductor device includes at least two stacked gate structures formed on a substrate. The two stacked gate structures each include a semiconductor layer and a metal layer over the semiconductor layer. The two stacked gate structures on the substrate are characterized by differential intermediate layers, one of the two structures including an ohmic layer and the other of the two structures not including an ohmic layer. | 03-04-2010 |
20100062596 | Semiconductor device and manufacturing method for the same - In a semiconductor substrate on which are formed an N-type MOS transistor and a P-type MOS transistor, the gate electrode of the N-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the gate electrode of the P-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the concentration of carbon contained in the former tungsten film is less than the concentration of carbon contained in the latter tungsten film. | 03-11-2010 |
20100068877 | METHOD FOR TUNING A WORK FUNCTION OF HIGH-K METAL GATE DEVICES - The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming first and second transistors in the substrate, the first transistor having a first gate structure that includes a first dummy gate, the second transistor having a second gate structure that includes a second dummy gate, removing the first and second dummy gates thereby forming a first trench and a second trench, respectively, forming a first metal layer to partially fill in the first and second trenches, removing the first metal layer within the first trench, forming a second metal layer to partially fill in the first and second trenches, forming a third metal layer to partially fill in the first and second trenches, reflowing the second metal layer and the third metal layer, and forming a fourth metal layer to fill in the remainder of the first and second trenches. | 03-18-2010 |
20100099249 | SELECTIVE SILICIDE FORMATION USING RESIST ETCH BACK - Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device. | 04-22-2010 |
20100112800 | CMOS STRUCTURE AND METHOD FOR FABRICATION THEREOF USING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND GATE MATERIALS - Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates. | 05-06-2010 |
20100144134 | Methods of Forming Integrated Circuit Devices Having Different Gate Electrode Cross Sections - A semiconductor device includes a first conductive structure and a second conductive structure. The first conductive structure is formed in a first region of a substrate, and includes a first polysilicon layer pattern, a first conductive layer pattern having a resistance smaller than that of the first polysilicon layer pattern, and a first hard mask. The second conductive structure is formed in a second region of the substrate and has a thickness substantially the same as that of the first conductive structure. The second conductive structure includes a second polysilicon layer pattern, a second conductive layer pattern having a resistance smaller than that of the second polysilicon layer pattern and having a thickness different from that of the first conductive layer pattern, and a second hard mask. | 06-10-2010 |
20100184283 | Method of Manufacturing Flash Memory Device - A method of manufacturing a flash memory device comprises forming a gate insulating layer on a semiconductor substrate, forming silicon seed crystals on a surface of the gate insulating layer by reacting a nitrogen or oxygen atmosphere gas and a silicon source gas, forming a first layer for a floating gate over the gate insulating layer and the silicon seed crystals by increasing an amount of the silicon source gas, and forming a second layer for a floating gate on the first layer for a floating gate. | 07-22-2010 |
20100203717 | CUT FIRST METHODOLOGY FOR DOUBLE EXPOSURE DOUBLE ETCH INTEGRATION - A multiple etch process for forming a gate in a semiconductor structure in which a cut area is first formed followed by the forming of the gate conductor lines. | 08-12-2010 |
20100279498 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING THE SAME - A method for forming a semiconductor structure is provided. The method includes providing a substrate; forming a dielectric layer on the substrate; forming a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and performing a selective atomic layer deposition (ALD) process to selectively deposit a conformal metal layer onto the top surface and sidewalls of the conductor pattern, but without depositing onto the main surface of the dielectric layer substantially. | 11-04-2010 |
20100291765 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - An aspect of the present disclosure, there is provided a method for fabricating a semiconductor device, including, forming a gate insulating film on a semiconductor substrate, forming a metal film on the gate insulating film, depositing a metal-silicon compound film on the metal film without exposing the semiconductor substrate into atmosphere after forming the metal film, forming a silicon film on the metal-silicon compound film, and etching the metal film, the metal-silicon compound film, and the silicon film. | 11-18-2010 |
20100297840 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, sequentially forming a silicon layer and a metal layer over the gate insulation layer, performing a first gate etching process to etch the metal layer using a gate hard mask layer, formed on the metal layer, as an etch barrier, and then partially etch the silicon layer, thereby forming a first pattern, performing a second gate etching process to partially etch the silicon layer, thereby forming an undercut beneath the metal layer, forming a capping layer on both sidewalls of the first pattern including the undercut, performing a third gate etching process to etch the silicon layer to expose the gate insulation layer using the gate hard mask layer and the capping layer as an etch barrier, thereby forming a second pattern, and performing a gate re-oxidation process. | 11-25-2010 |
20100330794 | METHOD FOR CLEANING A SEMICONDUCTOR DEVICE - There is provided a method for cleaning a semiconductor device capable of making compatible the inhibition of dissolution of a gate metal material and the acquisition of a favorable contact resistance. A method for cleaning a semiconductor device includes steps: a semiconductor substrate including silicon, and having a main surface is prepared; a multilayer gate including a metal layer and a silicon layer stacked sequentially from the bottom is formed over the main surface; a silicide layer is formed over the main surface and the silicon layer surface; an insulation layer is formed over the silicide layer in each of the main surface and the multilayer gate surface; a shared contact hole is formed in the insulation layer in such a manner that the silicide layer in the main surface of the semiconductor substrate and the surface of the multilayer gate is exposed from the insulation layer; and the shared contact hole is subjected to sulfuric acid cleaning, aqueous hydrogen peroxide cleaning, and APM cleaning separately, respectively, thereby to remove an altered layer formed in the shared contact hole. | 12-30-2010 |
20100330795 | Krypton Sputtering of Low Resistivity Tungsten - A method of depositing a bilayer of tungsten over tungsten nitride by a plasma sputtering process in which krypton is used as the sputter working gas during the tungsten deposition. Argon may be used as the sputtering working gas during the reactive sputtering deposition of tungsten nitride. The beneficial effect of reduction of tungsten resistivity is increased when the thickness of the tungsten layer is less than 50 nm and further increased when less than 35 nm. The method may be used in forming a gate stack including a polysilicon layer over a gate oxide layer over a silicon gate region of a MOS transistor in which the tungsten nitride acts as a barrier. A plasma sputter chamber in which the invention may be practiced includes gas sources of krypton, argon, and nitrogen. | 12-30-2010 |
20110034019 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE - A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening. | 02-10-2011 |
20110059604 | METHODS FOR FABRICATING STEP GATE ELECTRODE STRUCTURES FOR FIELD-EFFECT TRANSISTORS - A method is disclosed for forming at least two semiconductor devices with different gate electrode thicknesses. After forming a gate dielectric region, and determining whether a first or second device formed on the gate dielectric region expects a relatively faster gate dopant diffusion rate, a gate electrode layer is formed on the gate dielectric region wherein the gate electrode layer has a step-structure in which a portion thereof for the first device has a relatively larger thickness than that for the second device if the first device has a relatively faster gate dopant diffusion rate. | 03-10-2011 |
20110111585 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The invention provides a technique to manufacture a highly reliable semiconductor device and a display device at high yield. As an exposure mask, an exposure mask provided with a diffraction grating pattern or an auxiliary pattern formed of a semi-transmissive film with a light intensity reducing function is used. With such an exposure mask, various light exposures can be more accurately controlled, which enables a resist to be processed into a more accurate shape. Therefore, when such a mask layer is used, the conductive film and the insulating film can be processed in the same step into different shapes in accordance with desired performances. As a result, thin film transistors with different characteristics, wires in different sizes and shapes, and the like can be manufactured without increasing the number of steps. | 05-12-2011 |
20110111586 | Method of Setting a Work Function of a Fully Silicided Semiconductor Device, and Related Device - A method of setting a work function of a fully silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a silicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the silicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction. | 05-12-2011 |
20110124188 | METHODS OF FABRICATING ELECTRODES AND USES THEREOF - The present invention relates to methods for fabricating nanoscale electrodes separated by a nanogap, wherein the gap size may be controlled with high precision using a self-aligning aluminum oxide mask, such that the gap width depends upon the thickness of the aluminum oxide mask. The invention also provides methods for using the nanoscale electrodes. | 05-26-2011 |
20110136331 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a first gate insulating film on a first region of a semiconductor substrate; a first gate electrode on the first gate insulating film; a second gate insulating film on a second region of the semiconductor substrate; and a second gate electrode on the second gate insulating film. The first gate insulating film includes a first insulating film composed of a first material containing a first metal, and the second gate insulating film includes a second insulating film composed of the first material and a second material containing a second metal. | 06-09-2011 |
20110171820 | METHOD OF FORMING A METAL GATE - The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a substrate. A dummy gate is formed over the substrate. A dielectric material is formed around the dummy gate. The dummy gate is then removed to form an opening in the dielectric material. Thereafter, a work function metal layer is formed to partially fill the opening. The remainder of the opening is then filled with a conductive layer using one of a polysilicon substitute method and a spin coating method. | 07-14-2011 |
20110177685 | Method of Fabricating a Semiconductor Device - The present invention discloses a method of fabricating a semiconductor memory device including forming sequentially a gate insulating layer and a first conductive pattern on a semiconductor substrate; forming a protective layer on surfaces of the first conductive pattern and the gate insulating layer; performing an etching process to form a trench, the etching process being performed such that the protective layer remains on side walls of the first conductive pattern to form a protective pattern; forming an isolation layer in the trench; etching the isolation layer; removing the protective pattern above a surface of the isolation layer; and forming sequentially a dielectric layer and a second conductive layer on surfaces of the isolation layer, the protective pattern and the first conductive pattern. | 07-21-2011 |
20110207314 | Methods to Enhance Effective Work Function of Mid-Gap Metal by Incorporating Oxygen and Hydrogen at a Low Thermal Budget - A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed. | 08-25-2011 |
20110237061 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention improves the performance of a semiconductor device wherein a metal silicide layer is formed through a salicide process. A metal silicide layer is formed over the surfaces of first and second gate electrodes, n | 09-29-2011 |
20110237062 | Semiconductor Device And Method Of Fabricating The Same - A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; fondling a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening. | 09-29-2011 |
20110237063 | METHODS OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a gate dielectric layer and a first gate layer sequentially on an overall surface of a substrate including a first region and a second region, forming a lanthanum-oxide (La | 09-29-2011 |
20110256706 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for example, transistors, which include a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the polysilicon/gate oxide interface and a relatively small nitrogen concentration within the gate oxide and at the gate oxide/substrate interface. Additionally, the present invention provides a method for fabricating a semiconductor device having a metal gate strap (e.g., a metal silicide layer) disposed over the polysilicon layer thereof, which device includes a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the silicide/polysilicon interface to substantially prevent cross-diffusion. | 10-20-2011 |
20110275212 | Integrated High-K/Metal Gate in CMOS Process Flow - A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench. | 11-10-2011 |
20110300702 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - An insulating film is formed on a semiconductor substrate. A metal sacrificial film is formed on the insulating film. Then, the sacrificial film is selectively etched to form a trench pattern in the sacrificial film. The insulating film is irradiated with ultraviolet light or an electron beam using the sacrificial film having the trench pattern as a mask. After that, an interconnect formation groove is formed in the insulating film using the sacrificial film having the trench pattern as a mask. A metal film is formed in the interconnect formation groove. | 12-08-2011 |
20120009773 | SELECTIVE DEPOSITION OF NOBLE METAL THIN FILMS - Processes are provided for selectively depositing thin films comprising one or more noble metals on a substrate by vapor deposition processes. In some embodiments, atomic layer deposition (ALD) processes are used to deposit a noble metal containing thin film on a high-k material, metal, metal nitride or other conductive metal compound while avoiding deposition on a lower k insulator such as silicon oxide. The ability to deposit on a first surface, such as a high-k material, while avoiding deposition on a second surface, such as a silicon oxide or silicon nitride surface, may be utilized, for example, in the formation of a gate electrode. | 01-12-2012 |
20120034773 | TRANSISTOR HAVING AN ETCH STOP LAYER INCLUDING A METAL COMPOUND THAT IS SELECTIVELY FORMED OVER A METAL GATE, AND METHOD THEREFOR - In one aspect, an apparatus may include a metal gate of a transistor. An etch stop layer may be selectively formed over the metal gate. The etch stop layer may include a metal compound. An insulating layer may be over the etch stop layer. A conductive structure may be included through the insulating layer to the metal gate. Methods of making such transistors are also disclosed. | 02-09-2012 |
20120045892 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A gate insulating film is formed on a semiconductor substrate having a first region in which a first conductivity type transistor is formed and a second region in which a second conductivity type transistor is formed. Next, a metal film and a first metal nitride film are sequentially formed on the gate insulating film. Next, part of each of the metal film and the first metal nitride film that is located in the second region is removed, thereby exposing part of the gate insulating film that is located in the second region. Next, a second metal nitride film made of a same metal nitride as the first metal nitride film is formed on the part of the gate insulating film that is located in the second region. | 02-23-2012 |
20120088360 | Methods of Fabricating Semiconductor Devices - Methods of manufacturing a semiconductor device including a multi-layer of dielectric layers may include forming a metal oxide layer on a semiconductor substrate and forming a multi-layer of silicate layers including metal atoms and silicon atoms, on the metal oxide layer. The multi-layer of silicate layers may include at least two metallic silicate layers having different silicon concentrations, which are a ratio of silicon atoms among all metal atoms and silicon atoms included in the metallic silicate layer. | 04-12-2012 |
20120129331 | METHODS OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING METAL GATE ELECTRODES - A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region. | 05-24-2012 |
20120171855 | METHODS TO ADJUST THRESHOLD VOLTAGE IN SEMICONDUCTOR DEVICES - Methods for forming a device on a substrate are provided herein. In some embodiments, a method of forming a device on a substrate may include providing a substrate having a partially fabricated first device disposed on the substrate, the first device including a first film stack comprising a first dielectric layer and a first high-k dielectric layer disposed atop the first dielectric layer; depositing a first metal layer atop the first film stack; and modifying a first upper surface of the first metal layer to adjust a first threshold voltage of the first device, wherein the modification of the first upper surface does not extend through to a first lower surface of the first metal layer. | 07-05-2012 |
20120171856 | NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory includes a memory cell string having a plurality of memory cell transistors connected in series, a selection gate transistor connected in series with one end of the memory cell string, and having a gate electrode provided on a gate insulating film on a semiconductor substrate, and an element isolation insulating layer which is provided in the semiconductor substrate. The gate electrode includes a first gate electrode provided on the gate insulating film, a first and second insulating films provided on the first gate electrode, and a second gate electrode provided on the second insulating film and the element isolation insulating layer, and electrically connected to the first gate electrode. An first upper surface portion of the element isolation insulating layer below the second gate electrode is leveled with an upper surface of the first gate electrode. | 07-05-2012 |
20120184096 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si<31/12 above the first gate insulating film, and a second nickel silicide having a composition of Ni/Si≧31/12 on the second gate insulating film; and segregating aluminum at an interface between the first nickel silicide and the first gate insulating film by diffusing aluminum through the first nickel silicide. | 07-19-2012 |
20120238088 | FABRICATION METHOD OF METAL GATES FOR GATE-LAST PROCESS - A method for fabricating metal gates using a gate-last process, comprising: providing a substrate ( | 09-20-2012 |
20120252202 | SEMICONDUCTOR MEMORY DEVICES AND METHOD OF MANUFACTURING THE SAME - The semiconductor memory devices include an interfacial improvement resistance layer is formed between a polysilicon layer and a conductive layer in order to improve interfacial resistance between the polysilicon layer and the conductive layer. The method of manufacturing semiconductor memory devices includes forming a polysilicon layer over a semiconductor substrate, amorphizing the polysilicon layer, and stacking an interfacial improvement resistance layer and conductive layers over the amorphized polysilicon layer. | 10-04-2012 |
20120264284 | MANUFACTURING METHOD FOR METAL GATE STRUCTURE - A manufacturing method for a metal gate structure includes providing a substrate having a gate trench formed thereon, forming a work function metal layer in the gate trench, and performing an annealing process to the work function metal layer. The annealing process is performed at a temperature between 400° C. and 500° C., and in a bout 20 seconds to about 180 seconds. | 10-18-2012 |
20120264285 | RECESSED WORKFUNCTION METAL IN CMOS TRANSISTOR GATES - A transistor gate comprises a substrate having a pair of spacers disposed on a surface, a high-k dielectric conformally deposited on the substrate between the spacers, a recessed workfunction metal conformally deposited on the high-k dielectric and along a portion of the spacer sidewalls, a second workfunction metal conformally deposited on the recessed workfunction metal, and an electrode metal deposited on the second workfunction metal. The transistor gate may be formed by conformally depositing the high-k dielectric into a trench between the spacers on the substrate, conformally depositing a workfunction metal atop the high-k dielectric, depositing a sacrificial mask atop the workfunction metal, etching a portion of the sacrificial mask to expose a portion of the workfunction metal, and etching the exposed portion of the workfunction metal to form the recessed workfunction metal. The second workfunction metal and the electrode metal may be deposited atop the recessed workfunction metal. | 10-18-2012 |
20120309185 | METHOD OF FORMING METAL GATE STRUCTURE - A method of forming metal gate structure includes providing a substrate; forming a gate dielectric layer, a material layer and a polysilicon layer stacked on the substrate; forming a first mask layer, a second mask layer and a patterned photoresist on the polysilicon layer; removing portions of the second mask layer and the first mask layer to form a hard mask by utilizing the patterned photoresist as an etching mask; removing the patterned photoresist, and next utilizing the hard mask as an etching mask to remove parts of the polysilicon layer and parts of the material layer. Thus, a gate stack is formed. Since the patterned photoresist is removed before forming the gate stack, the gate stack is protected from damages of the photoresist-removing process. The photoresist-removing process does not attack the sidewalls of the gate stack, so a bird's beak effect of the gate dielectric layer is prevent. | 12-06-2012 |
20130102144 | METHODS FOR FORMING A METAL GATE STRUCTURE ON A SUBSTRATE - Methods for forming a metal gate structure on a substrate are provided herein. In some embodiments, a method for forming a metal gate structure on a substrate having a dielectric layer formed on the substrate may include depositing a metal layer while providing a process gas comprising oxygen to form an oxygen doped work function layer atop the dielectric layer; and depositing a metal gate layer atop dielectric layer. | 04-25-2013 |
20130130489 | SEALED AIR GAP FOR SEMICONDUCTOR CHIP - A method for forming a sealed air gap for a semiconductor chip including forming a gate over a substrate; forming a sacrificial spacer adjacent to the gate; forming a first dielectric layer about the gate and the sacrificial spacer; forming a contact to the gate; substantially removing the sacrificial spacer, wherein a space is formed between the gate and the first dielectric layer; and forming a sealed air gap in the space by depositing a second dielectric layer over the first dielectric layer. | 05-23-2013 |
20130164928 | Semiconductor Device and Method for Forming the Same - Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed. | 06-27-2013 |
20130183821 | METHOD FOR MANUFACTURING DOUBLE-LAYER POLYSILICON GATE - The invention discloses a method for manufacturing a dual-layer polysilicon gate. The method includes: depositing silicon nitride on silicon oxide of an integrated circuit to be processed; performing anisotropic etching on the silicon nitride to form sidewalls of silicon nitride on sidewalls of a first layer of polysilicon gate of the integrated circuit to be processed; manufacturing a second layer of polysilicon gate; and rinsing the sidewalls of silicon nitride. | 07-18-2013 |
20130189835 | METHOD FOR CLEANING A SEMICONDUCTOR DEVICE - A method of cleaning a semiconductor device that both inhibits dissolution of gate metal material and acquires favorable contact resistance. The gate of the device is multilayered, with stacked layers of metal and silicide beneath an insulation layer and atop a silicon substrate. A shared contact hole formed in the insulation layer exposes the silicide layer and multilayer gate from the insulation layer. The shared contact hole is subjected to sulfuric acid, aqueous hydrogen peroxide and APM cleaning processes, separately, to remove an altered layer that tends to form in the shared contact hole. | 07-25-2013 |
20130217220 | REPLACEMENT GATE ELECTRODE WITH A TANTALUM ALLOY METAL LAYER - A tantalum alloy layer is employed as a work function metal for field effect transistors. The tantalum alloy layer can be selected from TaC, TaAl, and TaAlC. When used in combination with a metallic nitride layer, the tantalum alloy layer and the metallic nitride layer provides two work function values that differ by 300 mV˜500 mV, thereby enabling multiple field effect transistors having different threshold voltages. The tantalum alloy layer can be in contact with a first gate dielectric in a first gate, and the metallic nitride layer can be in contact with a second gate dielectric having a same composition and thickness as the first gate dielectric and located in a second gate. | 08-22-2013 |
20130260548 | TECHNIQUES FOR USING MATERIAL SUBSTITUTION PROCESSES TO FORM REPLACEMENT METAL GATE ELECTRODES OF SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS - Generally, the present disclosure is directed to techniques for using material substitution processes to form replacement metal gate electrodes, and for forming self-aligned contacts to semiconductor devices made up of the same. One illustrative method disclosed herein includes removing at least a dummy gate electrode to define a gate cavity, forming a work-function material in said gate cavity, forming a semiconductor material above said work-function material, and performing a material substitution process on said semiconductor material to substitute a replacement material for at least a portion of said semiconductor material. | 10-03-2013 |
20130260549 | REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT - Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material, which provides, in combination with other layer, a work function about 4.4 eV or less, and can include a material selected from tantalum carbide, metallic nitrides, and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. Optionally, carbon doping can be introduced in the channel. | 10-03-2013 |
20130273729 | HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY SEPARATE REMOVAL OF PLACEHOLDER MATERIALS IN TRANSISTORS OF DIFFERENT CONDUCTIVITY TYPE - In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence. | 10-17-2013 |
20140024208 | INTEGRATED CIRCUIT DEVICE INCLUDING LOW RESISTIVITY TUNGSTEN AND METHODS OF FABRICATION - An integrated circuit device includes a semiconductor substrate and a gate electrode on the semiconductor substrate. The gate electrode structure includes an insulating layer of a dielectric material on the semiconductor substrate, an oxygen barrier layer on the insulating layer, and a tungsten (W) metal layer on the oxygen barrier layer. Also disclosed are methods for fabricating the device. | 01-23-2014 |
20140030884 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE INCLUDING SILICON-CONTAINING LAYER AND METAL-CONTAINING LAYER, AND CONDUCTIVE STRUCTURE OF THE SAME - A method for fabricating a semiconductor device includes forming a silicon-containing layer; forming a metal-containing layer over the silicon-containing layer; forming an undercut prevention layer between the silicon containing layer and the metal containing layer; etching the metal-containing layer; and forming a conductive structure by etching the undercut prevention layer and the silicon-containing layer. | 01-30-2014 |
20140051240 | METHODS OF FORMING A REPLACEMENT GATE STRUCTURE HAVING A GATE ELECTRODE COMPRISED OF A DEPOSITED INTERMETALLIC COMPOUND MATERIAL - Disclosed herein are various methods of forming a replacement gate structure with a gate electrode comprised of a deposited intermetallic compound material. In one example, the method includes removing at least a sacrificial gate electrode structure to define a gate cavity, forming a gate insulation layer in the gate cavity, performing a deposition process to deposit an intermetallic compound material in the gate cavity above the gate insulation layer, and performing at least one process operation to remove portions of intermetallic compound material positioned outside of the gate cavity. | 02-20-2014 |
20140065811 | REPLACEMENT METAL GATE SEMICONDUCTOR DEVICE FORMATION USING LOW RESISTIVITY METALS - Embodiments of the present invention relate to approaches for forming RMG FinFET semiconductor devices using a low-resistivity metal (e.g., W) as an alternate gap fill metal. Specifically, the semiconductor will typically comprise a set (e.g., one or more) of dielectric stacks formed over a substrate to create one or more trenches/channels (e.g., short/narrow and/or long/wide trenches/channels). A work function layer (e.g., TiN) will be provided over the substrate (e.g., in and around the trenches). A low-resistivity metal gate layer (e.g., W) may then be deposited (e.g., via chemical vapor deposition) and polished (e.g., via chemical-mechanical polishing). Thereafter, the gate metal layer and the work function layer may be etched after the polishing to provide a trench having the etched gate metal layer over the etched work function layer along a bottom surface thereof. | 03-06-2014 |
20140080298 | NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern. | 03-20-2014 |
20140106556 | METHOD FOR MANUFACTURING A DUAL WORK FUNCTION SEMICONDUCTOR DEVICE - A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method includes providing a substrate having first and second areas for forming first and second transistor types. The method additionally includes forming a dielectric layer on the substrate, which extends to cover at least parts of the first and second areas. The method additionally includes forming a first metal layer/stack on the dielectric layer in the first area, where the first metal layer/stack comprises a first work function-shifting element. The method additionally includes forming a second metal layer/stack on the first metal layer in the first area and on the dielectric layer in the second area, where the second metal layer/stack comprises a second work function-shifting element. The method additionally includes annealing to diffuse the first work function-shifting element and the second work function-shifting element into the dielectric layer, and subsequently removing the first metal layer/stack and the second metal layer/stack. The method further includes forming a third metal layer/stack in the first and second predetermined areas. | 04-17-2014 |
20140106557 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE - A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench. | 04-17-2014 |
20140120711 | METHOD OF FORMING METAL GATE - Provided is a method of forming a metal gate including the following steps. A dielectric layer is formed on a substrate, wherein a gate trench is formed in the dielectric layer and a gate dielectric layer is formed in the gate trench. A first metal layer is formed in the gate trench by applying a AC bias between a target and the substrate during physical vapor deposition. A second metal layer is formed in the gate trench by applying a DC bias between the target and the substrate during physical vapor deposition. | 05-01-2014 |
20140120712 | NMOS METAL GATE MATERIALS, MANUFACTURING METHODS, AND EQUIPMENT USING CVD AND ALD PROCESSES WITH METAL BASED PRECURSORS - Embodiments provide methods for depositing metal-containing materials. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. A method for processing a substrate is provided which includes depositing a dielectric material forming a feature definition in the dielectric material, depositing a work function material conformally on the sidewalls and bottom of the feature definition, and depositing a metal gate fill material on the work function material to fill the feature definition, wherein the work function material is deposited by reacting at least one metal-halide precursor having the formula MX | 05-01-2014 |
20140213048 | Method of Making a FinFET Device - A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate, fins on the substrate, isolation regions on sides of the fins and dummy gate stacks on the substrate including wrapping a portion of the fin, which is referred to as a gate channel region. The dummy gate stacks is removed to form a gate trench and a gate dielectric layer is deposited in the gate trench. A metal stressor layer (MSL) is conformably deposited on the gate dielectric layer. A capping layer is deposited on the MSL. A thermal treatment is applied to the MSL to achieve a volume expansion. Then the capping layer is removed and a metal gate (MG) is formed on the MSL. | 07-31-2014 |
20140235047 | METHODS OF FORMING GATES OF SEMICONDUCTOR DEVICES - Methods of forming gates of semiconductor devices are provided. The methods may include forming a first recess in a first substrate region having a first conductivity type and forming a second recess in a second substrate region having a second conductivity type. The methods may also include forming a high-k layer in the first and second recesses. The methods may further include providing a first metal on the high-k layer in the first and second substrate regions, the first metal being provided within the second recess. The methods may additionally include removing at least portions of the first metal from the second recess while protecting materials within the first recess from removal. The methods may also include, after removing at least portions of the first metal from the second recess, providing a second metal within the second recess. | 08-21-2014 |
20140242790 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A metal-containing film capable of adjusting a work function is formed. A first source containing a first metal element and a halogen element and a second source containing a second metal element different from the first metal element and an amino group are alternately supplied onto a substrate having a high-k dielectric film to form a composite metal nitride film on the high-k dielectric film. | 08-28-2014 |
20140273428 | SILANE OR BORANE TREATMENT OF METAL THIN FILMS - The negative effect of oxygen on some metal films can be reduced or prevented by contacting the films with a treatment agent comprising silane or borane. In some embodiments, one or more films in an NMOS gate stack are contacted with a treatment agent comprising silane or borane during or after deposition. | 09-18-2014 |
20140287576 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device manufacturing method includes: forming a film to be a first metal layer on a substrate where an element portion is formed; forming a first insulating layer provided with an opening on the film to be the first metal layer; forming a second metal layer in the opening of the first insulating layer; eliminating the first insulating layer; eliminating the film to be the first metal layer with the second metal layer used as a mask so as to form the first metal layer; and forming an electrode portion by covering exposed surfaces of the first metal layer and the second metal layer with a third metal layer including a metal of a smaller ionization tendency than the metal of the second metal layer. | 09-25-2014 |
20140377944 | FinFETs with Multiple Threshold Voltages - A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A gate electrode is spaced apart from the semiconductor fin by the gate dielectric layer. The gate electrode includes a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer. The top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function. | 12-25-2014 |
20150037969 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device including: preparing a semiconductor substrate with a gate oxide layer on the top thereof; depositing a polycrystalline silicon layer on the top of the semiconductor substrate; depositing a protection layer overlying the top of the polycrystalline silicon layer; etching the protection layer and the polycrystalline silicon layer to form a gate body block; forming an oxide layer overlying the gate body block and the semiconductor substrate; polishing the oxide layer through Chemical Mechanical Polishing (CMP) until the top of the gate body block; removing the protection layer on the top of the gate body block; and forming a metal silicide layer on the gate body block. | 02-05-2015 |
20150044861 | GATE SILICIDATION - A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed. | 02-12-2015 |
20150303062 | Method Of Forming A Singe Metal That Performs N and P Work Functions In High-K/Metal Gate Devices - The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate with a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a metal layer over the high-k dielectric layer, the metal layer having a first work function, protecting the metal layer in the first region, treating the metal layer in the second region with a de-coupled plasma that includes carbon and nitrogen, and forming a first gate structure in the first region and a second gate structure in the second region. The first gate structure includes the high-k dielectric layer and the untreated metal layer. The second gate structure includes the high-k dielectric layer and the treated metal layer. | 10-22-2015 |
20150303279 | Method of Forming Tungsten Nitride Layer of Tungsten Gate - A method for manufacturing a semiconductor device includes providing a front-end device containing a dummy gate, removing the dummy gate, and forming a gate structure including a tungsten gate in a location previously occupied by the dummy gate that has been removed. The method also includes etching back a portion of the tungsten gate, forming a laminate structure having at least one layer of tungsten and one layer of tungsten nitride on the etched back tungsten gate, and forming a silicon nitride cap layer on the laminate structure. | 10-22-2015 |
20150311126 | STRUCTURE AND METHOD FOR METAL GATE STACK OXYGEN CONCENTRATION CONTROL USING AN OXYGEN DIFFUSION BARRIER LAYER AND A SACRIFICIAL OXYGEN GETTERING LAYER - A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed. | 10-29-2015 |
20150332975 | METHOD FOR FABRICATING METAL GATE ELECTRODE - Exemplary methods for fabricating a metal gate electrode include forming a dielectric layer on a substrate, and forming a first trench having a first width and a second trench having a second width in the dielectric layer where the first width is less than the second width. Also included is depositing a work-function metal layer over the dielectric layer and into the first and second trenches where the deposited work-function layer is in direct contact with the top surface of the dielectric layer. A first signal metal layer is deposited over the work-function metal layer filling the second trench and a second signal metal layer is deposited filling the first trench. | 11-19-2015 |
20150332976 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench. | 11-19-2015 |
20150340286 | Preventing Over-Polishing of Poly Gate in Metal-Gate CMP - A method for manufacturing a semiconductor device includes providing a substrate containing a front-end device that includes a first gate in a first-type transistor region and a second gate in a second-type transistor region, forming an interlayer dielectric layer on the semiconductor substrate, and planarizing the interlayer dielectric layer to expose the surface of the first and second gates. The method also includes forming a hard mask layer on the second gate, removing the first gate using the hard mask layer as a mask to form a trench, forming sequentially a work function metal layer and a metal gate layer in the trench, and removing a portion of the first work function metal layer and a portion of the metal gate layer that are higher than the interlayer dielectric layer to form a metal gate. | 11-26-2015 |
20150357435 | METHOD OF MAKING A GATE STRUCTURE - A method of making a gate structure includes forming a gate electrode in an opening defined by a gate dielectric layer having a top surface. Forming the gate electrode includes filling a width of a bottom portion of the opening with a first metal material having a first resistance. Forming the gate electrode further includes defining a recess in the first metal material. Forming the gate electrode further includes filling an entire width of a top portion of the opening and the recess with a homogeneous second metal material having a second resistance less than the first resistance, wherein a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material, and the top surface of the gate dielectric layer is co-planar with a top surface of the homogeneous second metal material. | 12-10-2015 |
20160013107 | METHODS OF FORMING SEMICONDUCTOR DEVICES, INCLUDING PERFORMING A HEAT TREATMENT AFTER FORMING A METAL LAYER AND A HIGH-K LAYER | 01-14-2016 |
20160013288 | METHOD OF FORMING A METAL GATE STRUCTURE | 01-14-2016 |
20160020118 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are methods for fabricating semiconductor devices. The methods for fabricating the semiconductor devices may include forming a first interlayer insulation film including a trench on a substrate, forming a high-k layer along an inner sidewall and a bottom surface of the trench, forming a first work function control film including impurities along the high-k layer, removing the impurities from the first work function control film to reduce surface resistance of the first work function control film by about 30% to about 60% and forming a gate metal in the trench. | 01-21-2016 |
20160020151 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device may include a first metal gate electrode provided in a NMOS region of a substrate; and a second metal gate electrode provided in a PMOS region of the substrate, wherein the first and second metal gate electrodes may be formed of TiN material or TiAlN material. Here, the first metal gate electrode may have a higher titanium (Ti) content than the second metal gate electrode, and the second metal gate electrode may have a higher nitrogen (N) content than the first metal gate electrode. | 01-21-2016 |
20160049301 | Method of Tuning Work Function for A Semiconductor Device - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes forming pre-tuned-work-function (preTWF) layer over a substrate, applying an angular-doping process to the preTWF layer to change a work function of the preTWF layer (referred to as a tuned work function (TWF) layer). The angular-doping process includes injecting a doping species beam to the preTWF layer with a distribution of injecting angle and forming a metal fill layer over the TWF layer. | 02-18-2016 |
20160049510 | REPLACEMENT METAL GATES TO ENHANCE TRANISTOR STRAIN - Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain. | 02-18-2016 |
20160056255 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device is provided including a substrate and a plurality of gate stacks. The gate stack includes a dielectric layer disposed on the substrate, a first capping layer disposed on the dielectric layer, a second capping layer disposed on the first capping layer, and a gate electrode layer covering the second capping layer. The first capping layer having a roughened surface may enhance the formation of the second capping layer. The second capping layer has a bottom portion and a sidewall portion, and the thickness of the bottom portion is formed to be greater than the thickness of the sidewall portion, so that the dielectric property of the second capping layer may be significantly improved. Further, a method for manufacturing the semiconductor device also provides herein. | 02-25-2016 |
20160086860 | METHODS FOR MAKING ROBUST REPLACEMENT METAL GATES AND MULTI-THRESHOLD DEVICES IN A SOFT MASK INTEGRATION SCHEME - A method of fabricating advanced multi-threshold field effect transistors using a replacement metal gate process. A first method includes thinning layers composed of multilayer film stacks and incorporating a portion of the remaining thinned film in some transistors. A second method includes patterning dopant materials for a high-k dielectric by using thinning layers composed of multilayer thin film stacks, or in other embodiments, by a single thinning layer. | 03-24-2016 |
20160093710 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a junction region on both sides of a trench in a semiconductor substrate, a first gate electrode with a first workfunction buried in the trench, and a second gate electrode formed of a polycide layer having a second workfunction overlapping with the junction region at an upper part of the first gate electrode. | 03-31-2016 |
20160111543 | Metal Gate with Silicon Sidewall Spacers - A method includes forming an opening in a dielectric to reveal a protruding semiconductor fin, forming a gate dielectric on sidewalls and a top surface of the protruding semiconductor fin, and forming a conductive diffusion barrier layer over the gate dielectric. The conductive diffusion barrier layer extends into the opening. The method further includes forming a silicon layer over the conductive diffusion barrier layer and extending into the opening, and performing a dry etch on the silicon layer to remove horizontal portions and vertical portions of the silicon layer. After the dry etch, a conductive layer is formed over the conductive diffusion barrier layer and extending into the opening. | 04-21-2016 |
20160118261 | TITANIUM ALUMINUM AND TANTALUM ALUMINUM THIN FILMS - A process for depositing titanium aluminum or tantalum aluminum thin films comprising nitrogen on a substrate in a reaction space can include at least one deposition cycle. The deposition cycle can include alternately and sequentially contacting the substrate with a vapor phase Ti or Ta precursor and a vapor phase Al precursor. At least one of the vapor phase Ti or Ta precursor and the vapor phase Al precursor may contact the substrate in the presence of a vapor phase nitrogen precursor. | 04-28-2016 |
20160155673 | SEMICONDUCTOR DEVICE HAVING TUNGSTEN GATE ELECTRODE AND METHOD FOR FABRICATING THE SAME | 06-02-2016 |
20160181107 | METHOD FOR ETCHING HIGH-K METAL GATE STACK | 06-23-2016 |
20160190013 | METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH GATE - A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The method includes forming a gate material layer in the trench. The method includes forming a planarization layer over the gate material layer. The planarization layer includes a first material that is different from a second material of the gate material layer and a third material of the dielectric layer. The method includes performing an etching process to remove the planarization layer and a first upper portion of the gate material layer so as to form a gate in the trench. | 06-30-2016 |
20160190019 | METHOD OF FORMING INTEGRATED CIRCUIT HAVING PLURAL TRANSISTORS WITH WORK FUNCTION METAL GATE STRUCTURES - The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer. | 06-30-2016 |
20160196977 | SILANE AND BORANE TREATMENTS FOR TITANIUM CARBIDE FILMS | 07-07-2016 |
20160196978 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING DEVICE, AND RECORDING MEDIUM | 07-07-2016 |
20160197016 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 07-07-2016 |
20160197162 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING METAL GATE | 07-07-2016 |
20160254157 | Metal Gate Stack Having TaAlCN Layer | 09-01-2016 |