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Gate insulator structure constructed of plural layers or nonsilicon containing compound

Subclass of:

438 - Semiconductor device manufacturing: process

438584000 - COATING WITH ELECTRICALLY OR THERMALLY CONDUCTIVE MATERIAL

438585000 - Insulated gate formation

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DocumentTitleDate
20080261388Semiconductor assemblies, methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates - The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 Å above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer.10-23-2008
20100159687SEMICONDUCTOR DEVICE HAVING ELECTRODE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.06-24-2010
20100009528Method for Rapid Thermal Treatment Using High Energy Electromagnetic Radiation of a Semiconductor Substrate for Formation of Dielectric Films - A method for fabricating semiconductor devices, e.g., SONOS cell. The method includes providing a semiconductor substrate (e.g., silicon wafer, silicon on insulator) having a surface region, which has a native oxide layer. The method includes treating the surface region to a wet cleaning process to remove a native oxide layer from the surface region. In a specific embodiment, the method includes subjecting the surface region to an oxygen bearing environment and subjecting the surface region to a high energy electromagnetic radiation having wavelengths ranging from about 300 to about 800 nanometers for a time period of less than 10 milli-seconds to increase a temperature of the surface region to greater than 1000 Degrees Celsius. In a specific embodiment, the method causes formation of an oxide layer having a thickness of less than 10 Angstroms. In a preferred embodiment, the oxide layer is substantially free from pinholes and other imperfections. In a specific embodiment, the oxide layer is a gate oxide layer.01-14-2010
20120244693METHOD FOR PATTERNING A FULL METAL GATE STRUCTURE - A method of patterning a gate structure on a substrate is described. The method includes preparing a metal gate structure on a substrate, wherein the metal gate structure includes a high dielectric constant (high-k) layer, a first gate layer formed on the high-k layer, and a second gate layer formed on the first gate layer, and wherein the first gate layer comprises one or more metal-containing layers. The method further includes preparing a mask layer with a pattern overlying the metal gate structure, transferring the pattern to the second gate layer, transferring the pattern to the first gate layer, and transferring the pattern in the first gate layer to the high-k layer, and prior to the transferring of the pattern to the high-k layer, passivating an exposed surface of the first gate layer using a nitrogen-containing and/or carbon-containing environment to reduce under-cutting of the first gate layer relative to the second gate layer, wherein the passivating is performed separately from or in addition to the transferring of the pattern to the first gate layer.09-27-2012
20130078792SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. An interdielectric layer is formed on a substrate and the interdielectric layer has a first recess and a second recess. A metal layer is formed to cover the surface of the interdielectric layer, the first recess and the second recess. Partially fills a sacrificed material into the first recess and the second recess so that a portion of the metal layer in each of the recesses is respectively covered. The uncovered metal layer in each of the recesses is removed. The sacrificed material is removed. An etching process is performed to remove the remaining metal layer in the first recess and reserve the remaining metal layer in the second recess.03-28-2013
20130078793METHOD FOR DEPOSITING A GATE OXIDE AND A GATE ELECTRODE SELECTIVELY - The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method for depositing a gate oxide and a gate electrode selectively. The present invention makes use of Octadecyltriethoxysilane's (ODTS') easy attachment to the Si—OH interface and difficult attachment to the Si—H interface, and selectively deposits the gate oxide and gate electrode materials, which avoids the unnecessary waste of materials and saves cost. Meanwhile, the present invention will transfer the etching of the gate oxide and gate electrode into the etching of SiO03-28-2013
20130084697SPLIT GATE MEMORY DEVICE WITH GAP SPACER - A method for forming a split gate device includes forming a first sidewall of a first conductive gate layer, wherein the semiconductor layer includes a tunnel region laterally adjacent the first sidewall, forming a dielectric layer along the first sidewall to provide for increased thickness of a gap spacer, forming a charge storage layer over a portion of a top surface of the first conductive layer and over the tunnel region, and forming a second conductive gate layer over the charge storage layer.04-04-2013
20130078794CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - There is provided a charge trap type non-volatile memory device and a method for fabricating the same, the charge trap type non-volatile memory device including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; a charge barrier layer formed over the charge trap layer; a gate electrode formed over the charge barrier layer; and an oxide-based spacer formed over sidewalls of the charge trap layer and provided to isolate the charge trap layer.03-28-2013
20130084698NONVOLATILE STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is an excellent nonvolatile storage device having advantageous in miniaturization and less variation in initial threshold value, and exhibiting a high writing efficiency, without an erasing failure and a retention failure. The nonvolatile storage device is characterized by including a film stack extending from between a semiconductor substrate and a gate electrode onto at least a surface of the gate electrode lying on a first impurity diffusion region side, the film stack including a charge accumulating layer and a tunnel insulating film sequentially from a gate electrode side.04-04-2013
20130034954INTEGRATED CIRCUIT SYSTEM INCLUDING NITRIDE LAYER TECHNOLOGY - An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.02-07-2013
20100099247FLASH MEMORY WITH TREATED CHARGE TRAP LAYER - A methods of forming a flash memory device are provided. The flash memory device comprises a silicon dioxide layer on a substrate and a silicon nitride layer that is formed on the silicon dioxide layer. The properties of the silicon nitride layer can be modified by any of: exposing the silicon nitride layer to ultraviolet radiation, exposing the silicon nitride layer to an electron beam, and by plasma treating the silicon nitride layer. A dielectric material is deposited on the silicon nitride layer and a conductive date is formed over the dielectric material. The flash memory device with modified silicon nitride layer provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.04-22-2010
20120264283METHODS OF FABRICATING FIELD EFFECT TRANSISTORS INCLUDING TITANIUM NITRIDE GATES OVER PARTIALLY NITRIDED OXIDE AND DEVICES SO FABRICATED - A gate of an integrated circuit field effect transistor is fabricated by fabricating a gate insulating layer on an integrated circuit substrate, fabricating a metal nitride layer on the gate insulating layer, annealing the metal nitride layer in a nitridizing ambient and fabricating a cap on the metal nitride layer that has been annealed. Thereafter, the cap on the metal nitride layer may be etched to expose sidewalls thereof and another anneal in a nitridizing ambient may take place. Related integrated circuit field effect transistors are also described.10-18-2012
20100323509Nonvolatile semiconductor memory device and method of manufacturing the same - Provided is a nonvolatile semiconductor memory device and a method of manufacturing the same. The nonvolatile semiconductor memory device may include a tunnel insulating layer formed on a semiconductor substrate, a charge trap layer including a dielectric layer doped with a transition metal formed on the tunnel insulating layer, a blocking insulating layer formed on the charge trap layer, and a gate electrode formed on the blocking insulating layer. The dielectric layer may be a high-k dielectric layer, for example, a HfO12-23-2010
20090155992HIGH K STACK FOR NON-VOLATILE MEMORY - A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.06-18-2009
20100041224Non-volatile memory device and method of manufacturing the same - The non-volatile memory device may include a semiconductor substrate having a body and a pair of fins. A bridge insulating layer may non-electrically connect upper portions of the pair of fins to define a void between the pair of fins. Outer surfaces of the pair of fins are the surfaces of the pair of fins that do not face the void and inner surfaces of the pair of fins are the surfaces of the pair of fins that do face the void. The non-volatile memory device may further include at least one control gate electrode that may cover at least a portion of outer surfaces of the pair of fins, may extend over the bridge insulating layer, and may be isolated from the semiconductor substrate. At least one pair of gate insulating layers may be between the at least one control gate electrode and the pair of fins, and at least one pair of storage nodes may be between the at least one pair of gate insulating layers and the at least one control gate electrode.02-18-2010
20100041223METHOD OF INTEGRATING HIGH-K/METAL GATE IN CMOS PROCESS FLOW - The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer over the high-k dielectric layer, the first metal layer having a first work function, removing a portion of the first metal layer in the second active region, thereafter, forming a semiconductor layer over the first metal layer in the first active region and over the partially removed first metal layer in the second active region, forming a first gate stack in the first active region and a second gate stack in the second active region, removing the semiconductor layer from the first gate stack and from the second gate stack, and forming a second metal layer on the first metal layer in the first gate stack and on the partially removed first metal layer in the second gate stack, the second metal layer having a second work function.02-18-2010
20100041222SONOS Type Stacks for Nonvolatile ChangeTrap Memory Devices and Methods to Form the Same - A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias.02-18-2010
20120214299METHOD AND STRUCTURE FOR WORK FUNCTION ENGINEERING IN TRANSISTORS INCLUDING A HIGH DIELECTRIC CONSTANT GATE INSULATOR AND METAL GATE (HKMG) - Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.08-23-2012
20130052815SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.02-28-2013
20130052814DIFFUSED CAP LAYERS FOR MODIFYING HIGH-K GATE DIELECTRICS AND INTERFACE LAYERS - Method of forming a semiconductor device includes providing a substrate with defined NMOS and PMOS device regions and an interface layer on the NMOS and PMOS device regions, depositing a high-k film on the interface layer, depositing a first cap layer on the high-k film, and removing the first cap layer from the high-k film in the PMOS device region. The method further includes depositing a second cap layer on the first cap layer in the NMOS device region and on the high-k film in the PMOS device region, performing a heat-treating process to diffuse a first chemical element into the high-k film in the NMOS device region and to reduce or eliminate the interface layer by oxygen diffusion from the interface layer into the second cap layer, removing the first and second cap layers from the high-k film, and depositing a gate electrode film over the high-k film.02-28-2013
20130164926METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming first and second gate lines over a semiconductor substrate, wherein each second gate line has a greater width than each of the first gate lines, forming a first insulating layer surrounding the top and side walls of the first and the second gate lines so that first air gaps are formed between the first and second gate lines and between the first gate lines, forming a first reaction region in the first insulating layer by diffusing an etchant to a depth less than a target depth from a surface of the first insulating layer, removing the first reaction region, forming second reaction regions in the first insulating layer by diffusing the etchant to the target depth from the surface of the first insulating layer, and removing the second reaction regions exposing a portion of each first and second gate lines.06-27-2013
20130164927SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - A lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed over a semiconductor substrate. A memory gate electrode is formed adjacent to the lamination pattern. A gate insulation film is formed between the control gate and the semiconductor substrate. A fourth insulation film, including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film, is formed between the memory gate electrode and the semiconductor substrate and between the lamination pattern and the memory gate electrode. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.06-27-2013
20110039406Methods of Etching Nanodots, Methods of Removing Nanodots From Substrates, Methods of Fabricating Integrated Circuit Devices, Methods of Etching a Layer Comprising a Late Transition Metal, and Methods of Removing a Layer Comprising a Late Transition Metal From a Substrate - Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated circuit devices. In one embodiment, a method of etching nanodots that include a late transition metal includes exposing such nanodots to a gas comprising a phosphorus and halogen-containing compound and an oxidizing agent. After the exposing, the nanodots which are remaining and were exposed are etched (either partially or completely) with an aqueous solution comprising HF.02-17-2011
20120309183SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming an oxidation film over a first and a second device region, forming an first etching preventing film extending over a first and a second area, removing the first etching preventing film over the first area; removing the oxidation film over the first device region, forming a first gate insulating film over the first device region, removing the oxidation film over the second device region, forming a second gate insulating film over the second device region, forming a first gate electrode over the first gate insulating film, forming a second gate electrode over the second gate insulating film, forming first source and drain regions in the first device region at both sides of the first gate electrode, and forming second source and drain regions in the second device region at both sides of the second gate electrode.12-06-2012
20090269919SPLIT GATE TYPE NON-VOLATILE MEMORY DEVICE - Embodiments relate to a gate structure of a split gate-type non-volatile memory device and a method of manufacturing the same. In embodiments, the split gate-type non-volatile memory device may include a device isolation layer formed on a semiconductor substrate in the direction of a bit line to define an active region, a pair of first conductive layer patterns formed on the active region, a charge storage layer interposed between the pair of first conductive layer patterns and the active region, a pair of second conductive layer pattern formed on the active region and extended along the one sidewalls of the pair of first conductive layer patterns in the direction parallel to a word line, and a gate insulating layer interposed between the pair of second conductive layer patterns and the active region. The pair of second conductive layer patterns may be formed on one sidewalls of the pair of first conductive layer patterns in the form of spacers.10-29-2009
20090269918METHODS FOR FABRICATING MEMORY CELLS HAVING FIN STRUCTURES WITH SMOOT SIDEWALLS AND ROUNDED TOP CORNERS AND EDGES - Methods for fabricating a semiconductor FIN structure with smooth sidewalls and rounded top corners and edges is disclosed. A method includes forming a plurality of semiconductor FIN structures. A sacrificial oxide layer is formed on the top surface and the sidewall surfaces of the plurality of semiconductor FIN structures for rounding the corners and edges between the top surfaces and the sidewall surfaces of the plurality of semiconductor FIN structures. The sacrificial oxide layer is removed with a high selectivity oxide etchant. The plurality of semiconductor FIN structures are annealed in a hydrogen environment. A tunnel oxide is formed over the plurality of semiconductor FIN structures.10-29-2009
20120225546METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A method of manufacturing a nonvolatile semiconductor storage device includes applying a first mask lying across a line pattern located in a first region for forming a first gate electrode and a line pattern located in a second region for forming a second gate electrode; slimming sidewalls of unmasked line patterns; forming a blanket film across the first region and the second region and partially removing the blanket film so as to remain along the slimmed sidewalls of the line patterns; applying a second mask above the line patterns located in the first region and removing the line patterns in the second region such that the masked line patterns in the first region remain; anisotropically etching the first film using the blanket film and the remaining line patterns as a mask; and etching a charge storage layer using the first film as a mask.09-06-2012
20130065385METHOD FOR PREPARING SPACER TO REDUCE COUPLING INTERFERENCE IN MOSFET - The present invention provides a method for preparing spacer to reduce coupling interference in MOSFET, which includes the steps of: forming a gate oxide layer on the semiconductor substrate; forming a gate on the gate oxide layer; and depositing a low-K dielectric material on the gate and the semiconductor substrate, and doping with carbon during deposition to form a carbon-containing low-K dielectric layer and then forming the spacer by an etching process.03-14-2013
20130065386MULTIPLE MOLD STRUCTURE METHODS OF MANUFACTURING VERTICAL MEMORY DEVICES - A first insulating interlayer is formed on a substrate including first and second regions. The first insulating interlayer has top surface, a height of which is greater in the first region than in the second region. A first planarization stop layer and a second insulating interlayer are formed. The second insulating interlayer is planarized until the first planarization stop layer is exposed. The first planarization stop layer and the first and second insulating interlayers in the second region are removed to expose the substrate. A lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern is formed. The first insulation layer patterns and the first sacrificial layer patterns are alternately and repeatedly formed on the substrate, and a second planarization stop layer pattern is formed on the first insulation layer pattern.03-14-2013
20090233432METHODS FOR FABRICATING FLASH MEMORY DEVICES - Methods for fabricating flash memory devices are disclosed. A disclosed method comprises: forming a polysilicon layer on a semiconductor substrate; injecting dopants having stepped implantation energy levels into the polysilicon layer; forming a photoresist pattern on the polysilicon layer; and etching the polysilicon layer to form a floating gate.09-17-2009
20090233430SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS, AND SEMICONDUCTOR DEVICE MANUFACTURING SYSTEM - Provided is a method of forming a high-k gate insulating film to reduce nitrogen leakage and suppress gate leakage current. A method of manufacturing a semiconductor device comprises: forming a high-k gate insulating film on a silicon substrate in a first process unit; carrying the silicon substrate to a second process unit; nitrogenizing the high-k gate insulating film using gas comprising nitrogen gas and rare gas; and annealing the silicon substrate in the second process unit.09-17-2009
20120115321METHOD FOR REMOVING POLYMER AFTER ETCHING GATE STACK STRUCTURE OF HIGH-K GATE DIELECTRIC/METAL GATE - The present invention provides a method for removing polymer after etching a gate stack structure of high-K gate dielectric/metal gate. The method mainly comprises the following steps: 1): forming a gate stack structure of interface SiO05-10-2012
20090011586NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a first insulating film provided on a surface of a semiconductor substrate, a charge accumulation layer provided on the first insulating film, a second insulating film provided above the charge accumulation layer and contains silicon and nitrogen, a third insulating film provided on the second insulating film, and composed of a single-layer insulating film containing oxygen or a plural-layer stacked insulating film at least whose films on a top layer and a bottom layer contain oxygen, relative dielectric constant thereof being larger than it of a silicon oxide film, a fourth insulating film provided on the third insulating film and contains silicon and nitrogen, a control gate provided above the fourth insulating film, and a fifth insulating film provided between the charge accumulation layer and the second insulating film or between the fourth insulating film and the control gate, and contains silicon and oxygen.01-08-2009
20090011585Methods of Etching Nanodots, Methods of Removing Nanodots From Substrates, Methods of Fabricating Integrated Circuit Devices, Methods of Etching a Layer Comprising a Late Transition Metal, and Methods of Removing a Layer Comprising a Late Transition Metal From a Substrate - Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated circuit devices. In one embodiment, a method of etching nanodots that include a late transition metal includes exposing such nanodots to a gas comprising a phosphorus and halogen-containing compound and an oxidizing agent. After the exposing, the nanodots which are remaining and were exposed are etched (either partially or completely) with an aqueous solution comprising HF.01-08-2009
20100087057SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a conductive layer formed on the insulating film, and an etch-stop insulating film formed within the conductive layer to stop etching.04-08-2010
20110143529METHOD OF FABRICATING HIGH-K/METAL GATE DEVICE - The present disclosure provides a method that includes providing a semiconductor substrate; forming a gate structure over the semiconductor substrate, first gate structure including a dummy dielectric and a dummy gate disposed over the dummy dielectric; removing the dummy gate and the dummy dielectric from the gate structure thereby forming a trench; forming a high-k dielectric layer partially filling the trench; forming a barrier layer over the high-k dielectric layer partially filling the trench; forming an capping layer over the barrier layer partially filling the trench; performing an annealing process; removing the capping layer; forming a metal layer over the barrier layer filling in a remainder of the trench; and performing a chemical mechanical polishing (CMP) to remove the various layers outside the trench.06-16-2011
20120238087NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory according to examples of the present invention comprises a memory cell and a peripheral transistor. The memory cell has a first intergate insulating film having a multilayer structure and provided on a floating gate electrode and an isolation insulating layer. The peripheral transistor has a second intergate insulating film having a multilayer structure and provided on a first gate electrode and a second isolation insulating layer. The first and second intergate insulating films have the same structure, and a lowermost insulating layer of the first intergate insulating film on the first isolation insulating layer is thinner than a lowermost insulating layer of the second intergate insulating film on the second isolation insulating layer.09-20-2012
20120238086REDUCING EQUIVALENT THICKNESS OF HIGH-K DIELECTRICS IN FIELD EFFECT TRANSISTORS BY PERFORMING A LOW TEMPERATURE ANNEAL - When forming sophisticated high-k metal gate electrode structures, for instance on the basis of a replacement gate approach, superior interface characteristics may be obtained on the basis of using a thermally grown base material, wherein the electrically effective thickness may be reduced on the basis of a low temperature anneal process. Consequently, the superior interface characteristics of a thermally grown base material may be provided without requiring high temperature anneal processes, as are typically applied in conventional strategies using a very thin oxide layer formed on the basis of a wet oxidation chemistry.09-20-2012
20110027981NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor storage device includes: a plurality of stacked units juxtaposed on a major surface of a substrate, each stacked unit aligning in a first direction parallel to the major surface of the substrate; and a gate electrode aligning parallel to the major surface in a second direction non-parallel to the first direction. Each of the plurality of stacked units includes a plurality of stacked semiconductor layers via an insulating layer. The plurality of stacked units are juxtaposed so that the spacings between adjacent stacked units are alternately a first spacing and a second spacing larger than the first spacing. The second spacing is provided at a periodic interval four times a size of a half pitch F of the bit line. The gate electrode includes a protruding portion that enters into a gap of the second spacing between the stacked units. A first insulating film, a charge storage layer, and a second insulating film are provided between a side face of the semiconductor layer and the protruding portion.02-03-2011
20110143530SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device according to the present invention includes: a first transistor formed on a semiconductor substrate 06-16-2011
20110281429Multi-Layer Charge Trap Silicon Nitride/Oxynitride Layer Engineering with Interface Region Control - A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.11-17-2011
20100120239MEMORY DEVICE ETCH METHODS - A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane (CF05-13-2010
20110300701APPARATUS HAVING A DIELECTRIC CONTAINING SCANDIUM AND GADOLINIUM - Apparatus having a dielectric containing scandium and gadolinium can provide a reliable structure with a high dielectric constant (high k). In an embodiment, a monolayer or partial monolayer sequence process, such as for example atomic layer deposition (ALD), can be used to form a dielectric containing gadolinium oxide and scandium oxide. In an embodiment, a dielectric structure can be formed by depositing gadolinium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing scandium oxide onto the substrate using precursor chemicals, and repeating to form a thin laminate structure. A dielectric containing scandium and gadolinium may be used as gate insulator of a MOSFET, a capacitor dielectric in a DRAM, as tunnel gate insulators in flash memories, as a NROM dielectric, or as a dielectric in other electronic devices, because the high dielectric constant (high k) of the film provides the functionality of a much thinner silicon dioxide film.12-08-2011
20120289040FABRICATION METHODS OF INTEGRATED SEMICONDUCTOR STRUCTURE - An integrated circuit device and method for manufacturing an integrated circuit device is disclosed. The integrated circuit device comprises a core device and an input/output circuit. Each of the core device and input/output circuit includes a PMOS structure and an NMOS structure. Each of the PMOS includes a p-type metallic work function layer over a high-k dielectric layer, and each of the NMOS structure includes an n-type metallic work function layer over a high-k dielectric layer. There is an oxide layer under the high-k dielectric layer in the input/output circuit.11-15-2012
20110287623Three-Dimensional Nonvolatile Memory Devices Having Sub-Divided Active Bars and Methods of Manufacturing Such Devices - Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.11-24-2011
20110287621SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - To improve a charge retention characteristic of a nonvolatile memory transistor. A first insulating film, a charge trapping film, and a second insulating film are formed between a semiconductor substrate and a conductive film. The charge trapping film is formed of a silicon nitride film including an upper region having a low concentration of hydrogen and a lower region having a high concentration of hydrogen. Such a silicon nitride film is formed in such a manner that a silicon nitride film including 15 atomic % or more hydrogen is formed by a chemical vapor deposition method and an upper portion of the silicon nitride film is nitrided. The nitridation treatment is performed by nitriding the silicon nitride film by nitrogen radicals produced in plasma of a nitrogen gas.11-24-2011
20110287620METHOD OF ADJUSTING METAL GATE WORK FUNCTION OF NMOS DEVICE - The present invention provides a method of adjusting a metal gate work function of an NMOS device, comprising: depositing a layer of metal nitride film or metal film on a high K dielectric as a metal gate electrode by a physical vapor deposition process; implanting elements such as Tb, Er, Yb or Sr into the metal gate electrode by an ion implantation process; performing a high temperature annealing so that the doped metal ions are driven to and accumulate on the interface between the metal gate electrode and the high K gate dielectric, or form dipoles by an interface reaction on the interface between the high K gate dielectric and SiO11-24-2011
20110287622Transistors with Multilayered Dielectric Films and Methods of Manufacturing Such Transistors - Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.11-24-2011
20100136780METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, wherein forming the second insulating film comprises forming an insulating film containing silicon using source gas not containing chlorine, and forming an insulating film containing oxygen and a metal element on the insulating film containing silicon.06-03-2010
20090298275Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, And Process To Fabricate Same - A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.12-03-2009
20110217833METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING AN ETCHANT - In an etchant for etching a capping layer having etching selectivity with respect to a dielectric layer, the capping layer changes compositions of the dielectric layer, to thereby control a threshold voltage of a gate electrode including the dielectric layer. The etchant includes about 0.01 to 3 percent by weight of an acid, about 10 to 40 percent by weight of a fluoride salt and a solvent. Accordingly, the dielectric layer is prevented from being damaged by the etching process for removing the capping layer and the electric characteristics of the gate electrode are improved.09-08-2011
20090098720SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A manufacturing method of a semiconductor device of the present invention includes the steps of forming a first insulating film over a substrate, forming a semiconductor film over the first insulating film, oxidizing or nitriding the semiconductor film by conducting a plasma treatment to the semiconductor film under a condition of an electron density of 1×1004-16-2009
20090181531METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES HAVING INSULATING LAYERS TREATED USING NEUTRAL BEAM IRRADIATION - Methods of manufacturing non-volatile memory devices that can reduce or prevent loss of charges stored in a charge storage layer and/or that can improve charge storage capacity by neutral beam irradiation of an insulating layer are disclosed. The methods include forming a tunneling insulating layer on a substrate, forming a charge storage layer on the tunneling insulating layer, forming a blocking insulating layer on the charge storage layer, irradiating the blocking insulating layer and/or the tunneling insulating layer with a neutral beam, and forming a gate conductive layer on the blocking insulating layer.07-16-2009
20120034772Nonvolatile Semiconductor Memory Device Having Multi-Layered Oxide/(OXY) Nitride Film as Inter-Electrode Insulating Film and Manufacturing Method Thereof - A nonvolatile semiconductor memory device includes a first insulator, first conductor, element isolation insulator, second insulator and second conductor. The first insulator is formed on the main surface of a substrate and the first conductor is formed on the first insulator. The element isolation insulator is filled into at least part of both side surfaces of the first insulator in a gate width direction thereof and both side surfaces of the first conductor in a gate width direction thereof and is so formed that the upper surface thereof will be set with height between those of the upper and bottom surfaces of the first conductor. The second insulator includes a three-layered insulating film formed of a silicon oxide film, a silicon oxynitride film and a silicon oxide film formed on the first conductor and element isolation insulator. The second conductor is formed on the second insulator.02-09-2012
20110021014Semiconductor memory devices performing erase operation using erase gate and methods of manufacturing the same - A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one erase gate may be formed below the charge trap layer. A second charge transfer medium, which has a second polarity opposite to the first polarity, may be stored in the at least one erase gate. During the erase operation, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium.01-27-2011
20120142180METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device according to an embodiment, includes: forming a stack structure by alternately stacking control gate electrodes and interlayer insulating films; forming a through-hole that penetrates through the stack structure in a stacking direction of the control gate electrodes and the interlayer insulating films; forming a first insulating film that covers an inner surface of the through-hole; forming a charge storage layer that covers an inner surface of the first insulating film; forming a second insulating film that covers an inner surface of the charge storage layer; forming a semiconductor layer that covers an inner surface of the second insulating film; and oxidizing an interface between the semiconductor layer and the second insulating film by performing a heat treatment in an atmosphere containing O06-07-2012
20090263961HARDWARE SET FOR GROWTH OF HIGH K & CAPPING MATERIAL FILMS - The present invention generally includes a method and an apparatus for depositing both a high k layer and a capping layer within the same processing chamber by coupling gas precursors, liquid precursors, and solid precursors to the same processing chamber. By coupling gas precursors, liquid precursors, and solid precursors to the same processing chamber, a high k dielectric layer, a capping layer for a PMOS section, and a different capping layer for a NMOS may be deposited within the same processing chamber. The capping layer prevents the metal containing electrode from reacting with the high k dielectric layer. Thus, the threshold voltage for the PMOS and NMOS may be substantially identical.10-22-2009
20100099246METHOD OF MAKING A SPLIT GATE MEMORY CELL - A method includes forming a first layer of gate material over a semiconductor substrate; forming a hard mask layer over the first layer; forming an opening; forming a charge storage layer over the hard mask layer and within the opening; forming a second layer of gate material over the charge storage layer; removing a portion of the second layer and a portion of the charge storage layer which overlie the hard mask layer, wherein a second portion of the second layer remains within the opening; forming a patterned masking layer over the hard mask layer and over the second portion, wherein the patterned masking layer defines both a first and second bitcell; and forming the first and second bitcell using the patterned masking layer, wherein each of the first and second bitcell comprises a select gate made from the first layer and a control gate made from the second layer.04-22-2010
20100099248Methods of fabricating a semiconductor device - Methods of fabricating a semiconductor device are provided, the methods include forming a first dielectric layer, a data storage layer, and a second dielectric layer, which are sequentially stacked, on a semiconductor substrate. A mask having a first opening exposing a first region of the second dielectric layer is formed on the second dielectric layer. A gate electrode filling at least a portion of the first opening is formed. A second opening exposing a second region of the second dielectric layer is formed by etching the mask such that the second region is spaced apart from the first region. A second dielectric pattern and a data storage pattern are formed by sequentially etching the exposed second region of the second dielectric layer and the data storage layer. The second dielectric pattern is formed to have a greater width than a lower surface of the gate electrode.04-22-2010
20090170303METHODS FOR FORMING QUANTUM DOTS AND FORMING GATE USING THE QUANTUM DOTS - Methods for forming a gate using quantum dots are disclosed. More particularly, the present invention relates to a method for forming quantum dots for fabrication of an ultrafine semiconductor device comprising a gate with quantum dots. The present invention is capable of forming quantum dots in uniform sizes and at uniform intervals so as to achieve an electrically stable device.07-02-2009
20110171819SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF - A silicon nitride film, which is a second hard mask, is dry etched to be removed completely. The silicon nitride film, which is formed on a sidewall of a silicon nitride film used as a first hard mask, has a relatively low etching rate. Therefore, if the silicon nitride film is continued etching until the corresponding portion thereof is removed, polysilicon is etched in a direction of depth in trench shape. Then, floating gates in adjacent cells are separated and a step portion of the polysilicon is formed. Consequently, a remaining portion of the silicon nitride film used as the first hard mask is removed, an ONO film is laminated on a whole surface of the poly silicon having the step portion on an edge that has been etched, and then, a polysilicon for a control gate is laminated on the ONO film.07-14-2011
20110269304METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a multilayer, forming a plurality of patterns by etching the multilayer and a portion of the substrate, forming a supporter to support the plurality of patterns, and removing residues formed during the etching.11-03-2011
20080206975METHOD OF MANUFACTURING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, AND A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.08-28-2008
20090298274METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming core material patterns comprising first films separated from each other above a substrate, modifying surfaces of the core material patterns so that a second film is formed so as to be selectively etchable with the first films internally remaining, covering an upper surface and sides of the second film and forming a third film on the substrate, etching back the third film so that an upper surface of the second film is exposed and a base layer of the core material patterns is exposed between the patterns, and causing the third film to selectively remain, removing the second film more rapidly than the first and third films, and patterning the base layer with the first and third films remaining on the base layer serving as a mask after the second film has been removed, thereby forming a base layer pattern.12-03-2009
20100136779Sidewall SONOS Gate Structure with Dual-Thickness Oxide and Method of Fabricating the Same - A SONOS gate structure has an oxide structure on a substrate having gate pattern thereon. The oxide structure has a relatively thinner oxide portion on the substrate for keeping good program/erase efficiency, and a relatively thicker oxide portion on sidewalls of the gate pattern for inhibiting gate disturb. Trapping dielectric spacers are on formed the oxide structure laterally adjacent to said sidewalls of said gate pattern respectively.06-03-2010
20080242071METHOD FOR PASSIVATING GATE DIELECTRIC FILMS - The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate, forming a dielectric layer over the semiconductor substrate, treating the dielectric layer with a carbon containing group, forming a conductive layer over the treated dielectric layer, and patterning and etching the dielectric layer and conductive layer to form a gate structure. The carbon containing group includes an OCH10-02-2008
20080293229Semiconductor device and manufacturing method of the same - An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor are simultaneously formed by patterning ruthenium film deposited on a gate insulator. Next, by introducing oxygen into each of the gate electrodes, the gate electrodes are transformed into those having high work function. Thereafter, by selectively reducing the gate electrode of the n channel MIS transistor, it is transformed into a gate electrode having low work function.11-27-2008
20080318403METHOD FOR FABRICATING SEMICONDUCTOR TRANSISTOR - A method for fabricating a semiconductor transistor which eliminates device defects generated during an etching process for forming gates. The method may include laminating an ONO layer on and/or over a semiconductor substrate, and then coating a polysilicon layer on and/or over the ONO layer, and then forming a photoresist pattern on and/or over the polysilicon layer, and then sequentially performing a first etching of the polysilicon layer using the photoresist pattern as an etching mask so as to maintain a predetermined thickness of the polysilicon layer and then a second etching to remove the polysilicon layer remaining from the first etching.12-25-2008
20090124070Methods of Manufacturing Semiconductor Devices Including Metal Oxide Layers - Methods of manufacturing a semiconductor device are provided including forming a charge storage layer on a gate insulating layer that is on a semiconductor substrate. A blocking insulating layer is formed on the charge storage layer and an electrode layer is formed on the blocking insulating layer. The blocking insulating layer may be formed by forming a lower metal oxide layer at a first temperature and forming an upper metal oxide layer on the lower metal oxide layer at a second temperature, lower than the first temperature.05-14-2009
20120196433METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Provided is a manufacturing method for a semiconductor device having reduced leakage current and increased capacitance while improving interface characteristics. The manufacturing method includes forming a silicon oxide layer on a base layer including silicon, forming a silicon oxynitride layer by implanting nitrogen into the silicon oxide layer, and forming hydroxy groups on a surface of the silicon oxynitride layer while etching the silicon oxynitride layer.08-02-2012
20090087973RETENTION IMPROVEMENT IN DUAL-GATE MEMORY - A manufacturing process improves retention capabilties of dual-gate non-volatile memory cells by limiting the effects of lateral charge movement. The process limits lateral extents of the charge storage medium that is an integral part of the memory device within the dual-gate device.04-02-2009
20090181530 High-K Dielectric Stack And Method Of Fabricating Same - A method for improving the reliability of a high-k dielectric layer or a high-k dielectric stack by forming an amorphous high-k dielectric layer over an insulating layer, doping the amorphous high-k dielectric layer with nitrogen atoms, and subsequently heating the resulting structure at a temperature greater than or equal to the crystallization temperature of the high-k dielectric material, thereby transforming the high-k dielectric material from an amorphous state to a crystalline state, and causing nitrogen atoms to diffuse into the insulating layer.07-16-2009
20090163015Method of Fabricating Flash Memory Device - The present invention relates to a method of fabricating a flash memory device. According to a method of fabricating a flash memory device in accordance with an aspect of the present invention, a semiconductor substrate over which a tunnel insulating layer and a first conductive layer are formed is provided. A first oxide layer is formed on the first conductive layer using a plasma oxidization process in a state where a back bias voltage is applied. A nitride layer is formed on the first oxide layer. A second oxide layer is formed on the nitride layer. A second conductive layer is formed on the second oxide layer.06-25-2009
20090163013Method for Forming Gate of Non-Volatile Memory Device - Provided is a method for forming a gate of a non-volatile memory device. A tunneling layer, a charge trapping layer, a blocking layer, and a control gate layer are formed on a semiconductor substrate. A hard mask is formed on the control gate layer. The hard mask defines a region on which a gate is formed. A gate pattern is formed by etching the control gate layer, the blocking layer, the charge trapping layer, and the tunneling layer. A damage compensation layer on a side of the gate pattern is formed using ultra low pressure plasma of a pressure range from approximately 1 mT to approximately 100 mT.06-25-2009
20090142912Method of Manufacturing Thin Film Semiconductor Device and Thin Film Semiconductor Device - A method of manufacturing a thin film semiconductor device that includes forming a thin film transistor on a substrate, forming a layer insulation film on the substrate, the layer insulation film containing no hydroxyl group in at least a film constituting a lowermost layer in the state of covering said thin film transistor and linking oxygen or hydrogen to dangling bonds in the semiconductor thin film constituting the thin film transistor by a heat treatment in a moisture atmosphere after the formation of the layer insulation film.06-04-2009
20090004838METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of: forming an etching layer (01-01-2009
20090325373SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor memory device according to the present invention includes a charge storage layer 12-31-2009
20110223756Method of Enhancing Photoresist Adhesion to Rare Earth Oxides - A method and apparatus are described for fabricating metal gate electrodes (09-15-2011
20110223758METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING DUAL GATE - A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.09-15-2011
20130217219REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT - Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.08-22-2013
20090023278METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A method of manufacturing a flash memory device that may include forming a dielectric film pattern on a semiconductor substrate; etching the semiconductor substrate using the dielectric film pattern as a mask to form a trench; forming a first dielectric film on the semiconductor substrate including the trench; performing a wet etching process on the semiconductor substrate formed with the first dielectric film; forming a second dielectric film on the semiconductor substrate; performing a planarization process on the first and second dielectric films; and removing the dielectric film pattern. Therefore, a generation of void may be prevented when forming a device isolation film and also when forming an interlayer dielectric film.01-22-2009
20100248465METHODS OF FABRICATING SILICON OXIDE LAYERS USING INORGANIC SILICON PRECURSORS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING THE SAME - Methods of fabricating a silicon oxide layer using an inorganic silicon precursor and methods of fabricating a semiconductor device using the same are provided. The methods of fabricating a semiconductor device include forming a tunnel insulating layer and a charge storage layer on a substrate; forming a dielectric layer structure on the charge storage layer using an atomic layer deposition (ALD) method, the dielectric layer structure including a first dielectric layer formed of silicon oxide, a second dielectric layer on the first dielectric layer formed of a material different from the material forming the first dielectric layer, and a third dielectric layer formed of the silicon oxide on the second dielectric layer; and forming a control gate on the dielectric layer structure. The first and third dielectric layers formed of the silicon oxide are formed using a first gas including an inorganic silicon precursor, a second gas including hydrogen gas or a hydrogen component, and a third gas including an oxide gas.09-30-2010
20100248464METHOD FOR FORMING A HIGH-k GATE STACK WITH REDUCED EFFECTIVE OXIDE THICKNESS - A method is provided for forming a high-k gate stack with a reduced effective oxide thickness (EOT) for a semiconductor device. The method includes providing a silicon-containing substrate, forming an interface layer on the silicon-containing substrate, where the interface layer has a first equivalent oxide thickness, depositing a first high-k film on the interface layer, and heat-treating the first high-k film and the interface layer at a temperature that forms a modified interface layer, where the modified interface layer has a second equivalent oxide thickness that is equal to or lower than the first equivalent oxide thickness. The method further includes depositing a second high-k film on the modified interface layer. According to one embodiment, the first high-k film includes lanthanum oxide and the second high-k film includes hafnium silicate.09-30-2010
20090163014Method for Fabricating Non-Volatile Memory Device with Charge Trapping Layer - A method for fabricating a non-volatile memory device with a charge trapping layer wherein a tunneling layer, a charge trapping layer, a blocking layer, and a control gate electrode are formed on a semiconductor substrate. A temperature of the control gate electrode is increased by applying a magnetic field to the control gate electrode. The blocking layer is densified by allowing the increased temperature to be transferred to the blocking layer contacting the control gate electrode.06-25-2009
20100003813Semiconductor device and method of fabricating the same - According to the present invention, there is provided a semiconductor device comprising: 01-07-2010
20090075466Method of manufacturing a non-volatile memory device - A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.03-19-2009
20090053881METHOD OF FORMING DIELECTRIC LAYER OF SEMICONDUCTOR MEMORY DEVICE - A method of forming a dielectric layer of a semiconductor memory device is provided. The method includes forming a first insulating layer over a semiconductor substrate, performing a first plasma treatment process in order to densify a film of the first insulating layer, and forming a high-k insulating layer, which has a dielectric constant higher than that of the first insulating layer, on the first insulating layer. After second insulating layer is formed on the high-k insulating layer. A second plasma treatment process is performed in order to densify a film of the second insulating layer.02-26-2009
20080318404Semiconductor device and method for manufacturing the same - A semiconductor device includes a silicon substrate; an insulation layer formed on the silicon substrate, the insulation layer containing an oxide of an element of at least one kind selected from at least Hf, Zr, Ti and Ta; an electrode formed on the insulation layer; and a metal oxide layer containing La and Al, the metal oxide layer being provided at at least one of an interface between the silicon substrate and the insulation layer and an interface between the insulation layer and the electrode.12-25-2008
20090221140Method of fabricating non-volatile memory device having separate charge trap patterns - A non-volatile memory device prevents charge spreading. The non-volatile memory device includes an isolation trench in a semiconductor substrate, an isolation layer partially filling the isolation trench between first and second fins defined by the isolation trench, a control gate electrode crossing the first and second fins, a first charge trap pattern between the first fin and the control gate electrode, and a second charge trap pattern between the second fin and the control gate electrode.09-03-2009
20090117725METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A method of manufacturing a flash memory device includes forming a line pattern over a semiconductor substrate, and then forming a first dielectric spacer having a vertically extending portion formed on sidewalls of the line pattern and a horizontally extending portion formed over and contacting the semiconductor substrate, and then removing the horizontally extending portion of the first dielectric spacer, and then forming a second dielectric spacer layer on the sidewall of the vertically extending portion of the first dielectric spacer and on the area of the semiconductor substrate where the horizontally extending portion of the first dielectric spacer was removed.05-07-2009
20090239367Nonvolatile memory device and method of fabricating the same - A method of fabricating a nonvolatile memory device includes forming a tunnel insulating layer on a semiconductor substrate, forming a charge storage layer on the tunnel insulating layer, forming a dielectric layer on the charge storage layer, the dielectric layer including a first aluminum oxide layer, a silicon oxide layer, and a second aluminum oxide layer sequentially stacked on the charge storage layer, and forming a gate electrode on the dielectric layer, the gate electrode directly contacting the second aluminum oxide layer of the dielectric layer.09-24-2009
20100261342SEMICONDUCTOR DEVICE CONTAINING A BURIED THRESHOLD VOLTAGE ADJUSTMENT LAYER AND METHOD OF FORMING - A method is provided for forming a semiconductor device containing a buried threshold voltage adjustment layer. The method includes providing a substrate containing an interface layer, depositing a first high-k film on the interface layer, depositing a threshold voltage adjustment layer on the first high-k film, and depositing a second high-k film on the threshold voltage adjustment layer such that the threshold voltage adjustment layer is interposed between the first and second high-k films. The semiconductor device containing a patterned gate stack is described.10-14-2010
20100184281METHOD FOR TREATING LAYERS OF A GATE STACK - A method for fabricating a semiconductor device with improved performance is disclosed. The method comprises providing a semiconductor substrate; forming one or more gate stacks having an interfacial layer, a high-k dielectric layer, and a gate layer over the substrate; and performing at least one treatment on the interfacial layer, wherein the treatment comprises a microwave radiation treatment, an ultraviolet radiation treatment, or a combination thereof.07-22-2010
20100184282METHODS OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICES - A method of manufacturing a semiconductor memory device, the method including forming a tunnel insulation layer on a substrate, forming a preliminary charge trapping layer on the tunnel insulation layer, forming an etch stop layer on the preliminary charge trapping layer, wherein a portion of the preliminary charge trapping layer is not covered by the etch stop layer, removing the exposed portion of the preliminary charge trapping layer to form a charge trapping layer having a uniform thickness, forming a dielectric layer on the charge trapping layer, and forming a gate electrode on the dielectric layer.07-22-2010
20110059603SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a method of manufacturing a semiconductor device, which includes exposing a photoresist using an exposing mask provided with a light-shielding pattern having two or more narrow width portions, developing the photoresist to form a plurality of stripe-shaped resist patterns, selectively etching a first conductive film using the resist pattern as a mask, forming an intermediate insulating film on the first conductive film, forming a second conductive film on the intermediate insulating film, and forming, by patterning the first conductive film, the intermediate insulating film, and the second conductive film, a flash memory cell and a structure constructed by forming a lower conductor pattern, a segment of the intermediate insulating film, and a dummy gate electrode in this stacking order.03-10-2011
20110059602Methods of Forming Semiconductor Devices - A method of forming a semiconductor device may include forming a first pattern on a substrate, and forming a first dielectric layer on the first pattern. The first pattern may be between portions of the first dielectric layer and the substrate. A second dielectric layer may be formed on the first dielectric layer, and the first dielectric layer may be between the first pattern and the second dielectric layer. A second pattern may be formed on the second dielectric layer. Portions of the second dielectric layer may be exposed by the second pattern, and the first and second dielectric layers may be between portions of the first and second patterns. The exposed portions of the second dielectric layer may be isotropically etched.03-10-2011
20100159686Semiconductor device and method of manufacturing the same - A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO06-24-2010
20100240206METHOD OF ANNEALING A DIELECTRIC LAYER - A method includes forming a first dielectric layer over a substrate; forming nanoclusters over the first dielectric layer; forming a second dielectric layer over the nanoclusters; annealing the second dielectric layer using nitrous oxide; and after the annealing the second dielectric layer, forming a gate electrode over the second dielectric layer.09-23-2010
20120244694MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Provided is a manufacturing method of semiconductor integrated circuit, which is effective when applied to a processing technique for a gate electrode or the like. In the patterning of a gate stack film having a high-k gate insulating film and a metal electrode film in a memory region, etching for a cut region between adjacent gate electrodes is performed first using a first resist film and, after the first resist film that is no longer needed is removed, etching for a line and space pattern is performed using a second resist film.09-27-2012
20100240207METHODS OF MANUFACTURING CHARGE TRAP TYPE MEMORY DEVICES - Manufacturing of a charge trap type memory device can include forming a tunnel insulating layer on a substrate. A charge-trapping layer can be formed on the tunnel insulating layer. A blocking layer can be formed on the charge-trapping layer. Gate electrodes can be formed on the blocking layer and divided by a trench. A portion of the charge-trapping layer aligned with the trench may be converted into a charge-blocking pattern with a vertical side profile by an anisotropic oxidation process.09-23-2010
20100227466Nonvolatile Memory Array Having Modified Channel Region Interface - The technology relates to nonvolatile memory with a modified channel region interface, such as a raised source and drain or a recessed channel region.09-09-2010
20100240209SEMICONDUCTOR DEVICES INCLUDING HYDROGEN IMPLANTATION LAYERS AND METHODS OF FORMING THE SAME - Provided are semiconductor devices and methods of forming the same. The semiconductor devices include a substrate further including a hydrogen implantation layer and a gate structure formed on the hydrogen implantation layer to include a first insulating layer, a charge storage layer, a second insulating layer and a conductive layer.09-23-2010
20090042379Method for Fabricating Semiconductor Device Capable of Adjusting the Thickness of Gate Oxide Layer - The present invention provides a method for fabricating semiconductor device, which is capable of adjusting a gate oxide layer thickness, including: providing a semiconductor substrate; growing a first oxide layer on a surface of the semiconductor substrate; patterning the first oxide layer to expose the first oxide layer corresponding to a gate to be formed; removing the exposed first oxide layer; immersing the substrate into deionized water to grow a second oxide layer; forming a polysilicon layer on the surfaces of the first oxide layer and the second oxide layer; and etching the polysilicon layer to form a gate. The method for fabricating semiconductor device according to the present invention, which is capable of adjusting the thickness of gate oxide layer, can control the thickness of gate oxide layer precisely to satisfy the requirement for different threshold voltages.02-12-2009
20100221906ENHANCING INTEGRITY OF A HIGH-K GATE STACK BY CONFINING A METAL CAP LAYER AFTER DEPOSITION - During a manufacturing sequence for forming a sophisticated high-k metal gate structure, a cover layer, such as a silicon layer, may be deposited on a metal cap layer in an in situ process in order to enhance integrity of the metal cap layer. The cover layer may provide superior integrity during the further processing, for instance in view of performing wet chemical cleaning processes and the subsequent deposition of a silicon gate material.09-02-2010
20100112799Method of Manufacturing Flash Memory Device - A method of manufacturing a flash memory device according to an embodiment includes forming a second oxide layer pattern having a mask pattern buried therein on a first nitride layer pattern and a first oxide layer stack on a semiconductor substrate; forming first polysilicon patterns at sidewalls of the buried mask pattern; removing portions of the first oxide layer, the first nitride layer pattern, and the second oxide layer pattern to form a third oxide layer pattern, a second nitride layer pattern, and a fourth oxide layer pattern at lower portions of the first polysilicon patterns and the mask pattern; forming a fifth oxide layer pattern surrounding each of the first polysilicon patterns; forming second polysilicon patterns on sidewalls of the fifth oxide layer pattern; and removing the mask pattern and parts of the third oxide layer pattern and the second nitride layer pattern between the first polysilicon patterns.05-06-2010
20100221905MATERIAL INFUSION IN A TRAP LAYER STRUCTURE USING GAS CLUSTER ION BEAM PROCESSING - A method of preparing a floating trap type device on a substrate is described. The method comprises forming a trap layer structure on a substrate, and modifying a composition of one or more layers in the trap layer structure by exposing the trap layer structure to a gas cluster ion beam (GCIB).09-02-2010
20100022081NON-VOLATILE SONOS-TYPE MEMORY DEVICE - A semiconductor memory device with the thickness of both a tunnel film and a top film provided thereon configured to be in the FN tunneling region (4 nm or more). Data retention characteristics can be improved by configuring both a tunnel film and a top film to have a thickness in the FN tunneling region. Secondly, a high-concentration impurity region of a conductivity type the same as that of the substrate is provided in a substrate region arranged between assist gates provided adjacently to each other. The aforementioned high-concentration impurity region makes a depletion layer extremely thin when bias is applied to the assist gates. Hot holes generated between bands in the depletion region are injected into a charge storage region and the holes and electrons make pairs and disappear, enabling easy data erasing.01-28-2010
20110027979DIELECTRIC FILM, METHOD OF MANUFACUTRING SEMICONDUCTOR DEVICE USING DIELECTRIC FILM, AND SEMICONDUCTOR MANUFACTURING APPARATUS - To provide a method of manufacturing a dielectric film having a high dielectric constant. In an embodiment of the present invention, an HfN/Hf laminated film is formed on a substrate on which a thin silicon oxide film is formed and a dielectric film of a metal nitride made of a mixture of Hf, Si, O and N is manufactured by annealing treatment. According to the present invention, it is possible to (1) reduce an EOT, (2) reduce a leak current to Jg=1.0×1002-03-2011
20100197128CMOS Integration with Metal Gate and Doped High-K Oxides - A method and apparatus are described for fabricating single metal gate electrodes (08-05-2010
20100197129METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: forming a stacked body of a dielectric layer including a silicon oxide and a conductive layer including silicon above a substrate; and forming a hole penetrating through the dielectric layer and the conductive layer in the stacked body, the forming the hole including: forming a first mask layer including a silicon oxide above the stacked body; etching the conductive layer while using the first mask layer as a mask; and forming a second mask layer having more silicon content than the dielectric layer above the first mask layer to etch the dielectric layer while using the second mask layer as a mask.08-05-2010
20090325372Method of manufacturing semiconductor device and substrate processing apparatus - A manufacturing method of a semiconductor device of the present invention includes the step of forming an insulating film on a substrate, and the step of forming a high dielectric constant insulating film on the insulating film, and the step of forming a titanium aluminium nitride film on the high dielectric constant insulating film, wherein in the step of forming the titanium aluminum nitride film, formation of an aluminium nitride film and formation of a titanium nitride film are alternately repeated, and at that time, the aluminium nitride film is formed firstly and/or lastly.12-31-2009
20090233431SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME - Manufacturing technique for an IC device which includes forming the first conductor film over a memory cell forming region and over a peripheral circuit forming region of a semiconductor substrate, patterning the first conductive film lying over the memory cell forming region to form a first conductive pattern which serves as a first or control gate electrode of a memory cell and leaving the first conductive film over the peripheral circuit forming region, forming a second conductive film over both the memory cell forming region and the first conductive film in the peripheral circuit forming region, etching the second conductive film to form a second or memory gate electrode of the memory cell on at least a side wall of the first conductive pattern, and followed by the formation of a gate electrode of a peripheral circuit transistor by etching the first conductive film in the peripheral circuit forming region.09-17-2009
20080318405METHOD OF FABRICATING GATE STRUCTURE - A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.12-25-2008
20090163012METHOD OF FORMING HIGH-DIELECTRIC CONSTANT FILMS FOR SEMICONDUCTOR DEVICES - A method is provided for forming high dielectric constant (high-k) films for semiconductor devices. According to one embodiment, a metal-carbon-oxygen high-k film is deposited by alternately and sequentially exposing a substrate to a metal-carbon precursor and near saturation exposure level of an oxidation source containing ozone. The method is capable of forming a metal-carbon-oxygen high-k film with good thickness uniformity while impeding growth of an interface layer between the metal-carbon-oxygen high-k film and the substrate. According to one embodiment, the metal-carbon-oxygen high-k film may be treated with an oxidation process to remove carbon from the film.06-25-2009
20110117734Method of Fabricating High-K Poly Gate Device - The present disclosure provides a semiconductor device that includes a semiconductor substrate, and a transistor formed in the substrate. The transistor has a gate structure that includes an interfacial layer formed on the substrate, a high-k dielectric layer formed on the interfacial layer, a capping layer formed on the high-k dielectric layer, the capping layer including a silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof, and a polysilicon layer formed on the capping layer.05-19-2011
20100297839METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING MULTIPLE GATE INSULATING LAYER - A method of fabricating a semiconductor device is provided. The method includes preparing a semiconductor substrate having first and second regions, forming a mask layer pattern on the second region, growing an oxidation retarding layer on the first region and removing the mask layer pattern. The method further includes growing a silicon oxide layer on the semiconductor substrate to form gate insulating layers having different thicknesses from one another on the first and second regions.11-25-2010
20100311233Semiconductor device manufacturing method - In an MIS-type GaN-FET, a base layer made of a conductive nitride including no oxygen, here, TaN, is provided on a surface layer as a nitride semiconductor layer to cover at least an area of a lower face of a gate insulation film made of Ta12-09-2010
20100317185SUBSTRATE TREATING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A substrate treating method comprising a step of preparing a semiconductor substrate (W, 12-16-2010
20090035928METHOD OF PROCESSING A HIGH-K DIELECTRIC FOR CET SCALING - A method of making a semiconductor device includes making a gate dielectric with an overlying gate electrode. The semiconductor device is made over a semiconductor layer. A high-k dielectric comprising hafnium zirconate is deposited over the semiconductor layer. The high-k dielectric is annealed at a temperature between 650 degrees Celsius and 850 degrees Celsius in an ambient comprising hydrogen and nitrogen. The gate electrode is formed on the high-k dielectric. The high-k dielectric function is for use in the gate dielectric. One affect is to improve the transistor performance while retaining or even improving the level of gate leakage.02-05-2009
20110008954INSULATING BUFFER FILM AND HIGH DIELECTRIC CONSTANT SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: an n-transistor including a first gate insulating film made of a high-dielectric-constant material and a first gate electrode fully silicided with a metal, the first gate insulating film and the first gate electrode being formed in this order over a semiconductor region; and a p-transistor including a second gate insulating film made of the high-dielectric-constant material and a second gate electrode fully silicided with the metal, the second gate insulating film and the second gate electrode being formed in this order over the semiconductor region. If the metal has a work function larger than a Fermi level in potential energy of electrons of silicon, a metal concentration of the second gate electrode is higher than that of the first gate electrode whereas if the metal has a work function smaller than the Fermi level of silicon, a metal concentration of the second gate electrode is lower than that of the first gate electrode.01-13-2011
20100178758METHODS FOR FABRICATING DIELECTRIC LAYER AND NON-VOLATILE MEMORY - The method for fabricating the dielectric layer of the present invention is described as follows. A substrate is provided in a chamber, wherein the chamber is a single-wafer LPCVD chamber. A silicon source gas, an oxidation source gas and a nitridation source gas are then introduced into the chamber, wherein a volumetric flow rate ratio of the oxidation source gas to a total amount of the oxidation source gas and the nitridation source gas is varied within a range of 0.0245 to 0.375. Afterwards, the dielectric layer with a dielectric constant within a range of 4.8 to 7.6 is formed on the substrate.07-15-2010
20100178759Method of fabricating semiconductor device - A method of fabricating a semiconductor device including forming a charge storage layer, and forming a first tunnel insulating layer covering the charge storage layer, the forming of the first tunnel insulating layer including heat treating the charge storage layer.07-15-2010
20110111584SRAM CELL HAVING A RECTANGULAR COMBINED ACTIVE AREA FOR PLANAR PASS GATE AND PLANAR PULL-DOWN NFETS - A planar pass gate NFET is designed with the same width as a planar pull-down NFET. To optimize a beta ratio between the planar pull-down NFET and an adjoined planar pass gate NFET, the threshold voltage of the planar pass gate NFET is increased by providing a different high-k metal gate stack to the planar pass gate NFET than to the planar pull-down NFET. Particularly, a threshold voltage adjustment dielectric layer, which is formed over a high-k dielectric layer, is preserved in the planar pass gate NFET and removed in the planar pull-down NFET. The combined NFET active area for the planar pass gate NFET and the planar pull-down NFET is substantially rectangular, which enables a high fidelity printing of the image of the combined NFET active area by lithographic means.05-12-2011
20110244674Method Of Forming A Plurality Of Spaced Features - A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.10-06-2011
20100055889Composite Charge Storage Structure Formation In Non-Volatile Memory Using Etch Stop Technologies - Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.03-04-2010
20110250746NONVOLATILE MEMORY DEVICE WITH MULTIPLE BLOCKING LAYERS AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blocking layer, wherein the first blocking layer has a greater energy band gap than the second blocking layer and the second blocking layer has a greater permittivity than the first blocking layer.10-13-2011
20090311857METHOD TO FORM ULTRA HIGH QUALITY SILICON-CONTAINING COMPOUND LAYERS - Multiple sequential processes are conducted in a reaction chamber to form ultra high quality silicon-containing compound layers, including silicon nitride layers. In a preferred embodiment, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. A silicon nitride layer is then formed by nitriding the silicon layer. By repeating these steps, a silicon nitride layer of a desired thickness is formed.12-17-2009
20100009529METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching from a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region; forming gate insulating films, polysilicon film and cap insulating film over the semiconductor substrate, forming a gate electrode in the low breakdown voltage MISFET formation region and high breakdown voltage MISFET formation region, and then forming a gate electrode in a memory cell formation region. By the manufacturing technology of a semiconductor device for forming the gate electrodes of a first MISFET and a second MISFET in different steps, the present invention makes it possible to provide the first MISFET and the second MISFET each having improved reliability.01-14-2010
20100062592METHOD FOR FORMING GATE SPACERS FOR SEMICONDUCTOR DEVICES - A method for forming gate spacers for semiconductor devices includes forming a patterned gate structure on substrate, where the patterned gate structure contains an interface layer on the substrate, a high-k film on the interface layer, and a gate electrode on the high-k film. The method further includes depositing a nitride barrier layer on the patterned gate structure using processing conditions that minimize or prevent oxidation of the substrate and the gate electrode, depositing a spacer material on the nitride barrier layer, and anisotropically etching the spacer material to form a gate spacer on the patterned gate structure.03-11-2010
20100062593METHOD FOR PREPARING MULTI-LEVEL FLASH MEMORY DEVICES - A method for preparing a multi-level flash memory device comprises forming a dielectric stack including a charge-trapping layer on a semiconductor substrate, forming an insulation structure having a depression on the charge-trapping layer, removing a portion of the charge-trapping layer from the depression such that the charge-trapping layer is segmented to form a plurality of storage nodes, forming a gate oxide layer isolating the storage nodes and forming a damascene gate including a polysilicon layer filling the depression.03-11-2010
20100062594METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - In accordance with an embodiment of the invention the method of manufacturing a semiconductor device is capable of forming a semiconductor substrate having an embossing structure. The method includes forming a layer having a plurality of hemispherical single crystal silicon elements, and forming one or more carbon nano tubes between adjacent hemispherical single crystal silicon elements, thereby, increasing a length of an effective channel of a transistor.03-11-2010
20100055890METHOD FOR FABRICATING NON-VOLATILE MEMORY - A method for fabricating a non-volatile memory is provided. The method includes a stacked structure and a consuming layer are formed in sequence over a substrate. A converting process is performed at a peripheral region of the consuming layer to form a first insulating layer. A conductive layer is formed over the stacked layer and the first insulating layer.03-04-2010
20090215255Methods Of Forming Dispersions Of Nanoparticles, And Methods Of Forming Flash Memory Cells - Some embodiments include methods of forming dispersions of nanoparticles. The nanoparticles are incorporated into first coordination complexes in which the nanoparticles are coordinated to hydrophobic ligands, and the first coordination complexes are dispersed within a non-polar solvent. While the first coordination complexes are within the non-polar solvent, the ligands are reacted with one or more reactants to convert the first coordination complexes into second coordination complexes that contain hydrophilic ligands. The second coordination complexes are then extracted from the non-polar solvent into water, to form a mixture of the second coordination complexes and the water. In some embodiments, the mixture may be dispersed across a semiconductor substrate to form a uniform distribution of the nanoparticles across the substrate. In some embodiments, the nanoparticles may then be incorporated into flash memory devices as charge-trapping centers.08-27-2009
20100068876METHODS OF FABRICATING HIGH-K METAL GATE DEVICES - Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.03-18-2010
20110081775METHOD FOR ADJUSTING THE THRESHOLD VOLTAGE OF A GATE STACK OF A PMOS DEVICE - A method for fabricating a semiconductor device comprising a gate stack of a gate dielectric and a gate electrode, the method including forming a gate dielectric layer over a semiconductor substrate the gate dielectric layer being a metal oxide or semimetal oxide having a first electronegativity; forming a dielectric V04-07-2011
20110081774METHODS FOR A GATE REPLACEMENT PROCESS - A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.04-07-2011
20110104882METHOD FOR PROCESSING SEMICONDUCTOR DEVICE - The present invention relates to a method for processing semiconductor devices with a fine structure, and more particularly, to a processing method suitable for miniaturizing semiconductor devices with a so-called high-k/metal gate structure. In an embodiment of the present invention, a deposited film, which includes an insulating film made of Hf or Zr and a material of Mg, Y or Al existing on, under or in the insulating film, is formed on a Si substrate and is removed by repeating a dry etching process and a wet etching process at least one time. The wet etching process is performed prior to the dry etching process.05-05-2011
20110070725Method For Making Semiconductor Device - One or more embodiments relate to a method of forming a semiconductor device, including: providing a substrate; forming a gate stack over the substrate, the gate stack including a control gate over a charge storage layer; forming a conductive layer over the gate stack; etching the conductive layer to remove a portion of the conductive layer; and forming a select gate, the forming the select gate comprising etching a remaining portion of the conductive layer.03-24-2011
20110070726Method For Making Semiconductor Device - One or more embodiments may relate to a method for making a semiconductor device, including: a method for making a semiconductor device, comprising: providing a substrate; forming a charge storage layer over the substrate; forming a control gate layer over the charge storage layer; forming a mask over the control gate layer; using the mask, etching the control gate layer and the charge storage layer; forming a select gate layer over the etched control gate layer and the etched charge storage layer; forming an additional layer over the select gate layer; etching the additional layer to form sidewall spacers over the select gate layer; and etching the select gate layer.03-24-2011
20110256705METHOD FOR FORMING A SPLIT GATE DEVICE - A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer. The method further includes etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer.10-20-2011
20110212612MEMORY DEVICES INCLUDING DIELECTRIC THIN FILM AND METHOD OF MANUFACTURING THE SAME - A memory device including a dielectric thin film having a plurality of dielectric layers and a method of manufacturing the same are provided. The memory device includes: a bottom electrode; at least one dielectric thin film disposed on the bottom electrode and having a plurality of dielectric layers with different charge trap densities from each other; and an top electrode disposed on the dielectric thin film. Therefore, a memory device, which can be readily manufactured by a simple process and can be highly integrated using its simple structure, can be provided.09-01-2011
20100112798METHOD FOR GAP FILLING IN A GATE LAST PROCESS - A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the substrate, forming a silicon layer over the high-k dielectric layer, forming a hard mask layer over the silicon layer, patterning the hard mask layer, silicon layer, and high-k dielectric layer to form first and second gate structures over the first and second regions, respectively, forming a contact etch stop layer (CESL) over the first and second gate structures, modifying a profile of the CESL by an etching process, forming an inter-layer dielectric (ILD) over the modified CESL, performing a chemical mechanical polishing (CMP) on the ILD to expose the silicon layer of the first and second gate structures, respectively, and removing the silicon layer from the first and second gate structures, respectively, and replacing it with metal gate structures.05-06-2010
20090291553Threshold Adjustment for High-K Gate Dielectric CMOS - A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a thicker oxide liner. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have differing thickness liners, and the threshold values of the differing type of FET devices is set independently from one another.11-26-2009
20100311232Method of Manufacturing Nonvolatile Memory Device - A method of manufacturing a nonvolatile memory device comprises providing a semiconductor substrate defining active regions and isolation regions with a gate insulating layer and a floating gate formed over each active region and isolation layer formed in the respective isolation regions, forming a dielectric layer on a surface of the isolation layers and the floating gates, forming a polysilicon layer over the dielectric layer through a polysilicon deposition process using a nitrogen source gas, a silicon source gas, and an impurity doping gas, and patterning the polysilicon layer to form a control gate.12-09-2010
20100317184METHOD FOR REDUCING INTERFACIAL LAYER THICKNESS FOR HIGH-K AND METAL GATE STACK - A method for reducing interfacial layer (IL) thickness for high-k dielectrics and metal gate stack is provided. In one embodiment, the method includes forming an interfacial layer on a semiconductor substrate, etching back the interfacial layer, depositing a high-k dielectric material over the interfacial layer, and forming a metal gate over the high-k dielectric material. The IL can be chemical oxide, ozonated oxide, thermal oxide, or formed by ultraviolet ozone (UVO) oxidation process from chemical oxide, etc. The etching back of IL can be performed by a Diluted HF (DHF) process, a vapor HF process, or any other suitable process. The method can further include performing UV curing or low thermal budget annealing on the interfacial layer before depositing the high-k dielectric material.12-16-2010
20110027980SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The semiconductor device has a semiconductor layer, a gate electrode which covers an end portion of the semiconductor layer, and an insulating layer for insulating the semiconductor layer and the gate electrode. The film thickness of the insulating layer which insulates a region where an end portion of the semiconductor layer and the gate electrode overlap each other is thicker than the film thickness of the insulating layer which covers the central portion of the semiconductor layer.02-03-2011
20100323510Methods of Forming Dispersions of Nanoparticles, and Methods of Forming Flash Memory Cells - Some embodiments include methods of forming dispersions of nanoparticles. The nanoparticles are incorporated into first coordination complexes in which the nanoparticles are coordinated to hydrophobic ligands, and the first coordination complexes are dispersed within a non-polar solvent. While the first coordination complexes are within the non-polar solvent, the ligands are reacted with one or more reactants to convert the first coordination complexes into second coordination complexes that contain hydrophilic ligands. The second coordination complexes are then extracted from the non-polar solvent into water, to form a mixture of the second coordination complexes and the water. In some embodiments, the mixture may be dispersed across a semiconductor substrate to form a uniform distribution of the nanoparticles across the substrate. In some embodiments, the nanoparticles may then be incorporated into flash memory devices as charge-trapping centers.12-23-2010
20100323511NONVOLATILE MEMORIES WITH LATERALLY RECESSED CHARGE-TRAPPING DIELECTRIC - Charge-trapping dielectric (12-23-2010
20110097887Semiconductor storage device and method for manufacturing the same - A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.04-28-2011
20090176358Discrete Trap Memory (DTM) Mediated by Fullerenes - A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical or endohedral Fullerenes that act as charge traps.07-09-2009
20120309184SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of forming a semiconductor device includes forming an interfacial layer on a semiconductor substrate, forming a high-k dielectric on the interfacial layer, forming a barrier metal on the high-k dielectric, forming a poly-silicon layer on the barrier metal, patterning the interfacial layer, the high-k dielectric, the barrier metal and the poly-silicon to form a gate stack forming spacers, extension regions, sidewalls and source/drain regions, forming an interlayer dielectric on the gate stack, etching off a portion of the interlayer dielectric to expose the poly-silicon layer, forming an impurity metal layer, which includes an impurity metal having a barrier effect to the diffusive material, and a metal layer including a diffusive material, on the poly-silicon layer and converting the poly-Si layer into a silicide containing the impurity metal. The barrier metal includes a titanium nitride (TiN) or a tantalum nitride (TaN).12-06-2012
20110263114METHOD FOR ETCHING MO-BASED METAL GATE STACK WITH ALUMINIUM NITRIDE BARRIER - The present application discloses a method for etching a Mo-based metal gate stack with an aluminum nitride barrier, comprising the steps of forming a SiO10-27-2011
20110189846METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES - A method of manufacturing a non-volatile memory device including a tunnel oxide layer, a preliminary charge storing layer and a dielectric layer on a semiconductor layer is disclosed. A first polysilicon layer is formed on the dielectric layer. A barrier layer and a second polysilicon layer are formed on the first polysilicon layer. The second polysilicon layer, the barrier layer, the first polysilicon layer, the dielectric layer, the preliminary charge storing layer and the tunnel oxide layer are patterned to form a tunnel layer pattern, a charge storing layer pattern, a dielectric layer pattern, a first control gate pattern, a barrier layer pattern and a second polysilicon pattern. A nickel layer is formed on the second polysilicon layer. Heat treatment is performed with respect to the second polysilicon pattern and the nickel layer to form a second control gate pattern including NiSi on the barrier layer pattern.08-04-2011
20100022080METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing the semiconductor device includes nitridizing a silicon substrate with ammonia while heating the silicon substrate, then heating the silicon substrate in an atmosphere containing nitrogen and oxygen to form a gate insulating film including a silicon-based insulating film containing nitrogen and oxygen, then annealing the silicon substrate in an oxygen atmosphere, and forming a gate electrode on the gate insulating film.01-28-2010
20100167518CROSS-CONTAMINATION CONTROL FOR SEMICONDUCTOR PROCESS FLOWS HAVING METAL COMPRISING GATE ELECTRODES - A method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor including wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface. A gate dielectric layer is formed on at least the topside semiconductor surface. A metal including gate electrode material including at least a first metal is deposited on the gate dielectric layer on the topside semiconductor surface and on at least a portion of the bevel semiconductor surface and at least a portion of the backside semiconductor surface. The metal including gate electrode material on the bevel semiconductor surface and the backside semiconductor surface are selectively removed to form substantially first metal free bevel and backside surfaces while protecting the metal gate electrode material on the topside semiconductor surface. The selective removing includes a first wet etch that etches the metal gate electrode material highly selectively as compared to the semiconductor, wherein the first wet etch includes a strong oxidizing acid, a weak acid that generally include an organic acid, and a fluoride. The fabrication of the IC including is completed including forming at least one metal interconnect layer after the selectively removing step.07-01-2010
20110306196METHOD TO FORM A SEMICONDUCTOR DEVICE HAVING GATE DIELECTRIC LAYERS OF VARYING THICKNESS - A method for fabricating an integrated circuit device is disclosed which includes providing a substrate having first, second, and third regions; and forming first, second, and third gate structures in the first, second, and third regions, respectively. The first, second, and third gate structures include a gate dielectric layer, the gate dielectric layer being a first thickness in the first gate structure, a second thickness in the second gate structure, and a third thickness in the third gate structure. Forming the gate dielectric layer of the first, second, and third thicknesses can include forming an etching barrier layer over the gate dielectric layer in at least one of the first, second, or third regions while forming the first, second, and third gate structures, and/or prior to forming the gate dielectric layer in at least one of the first, second, or third regions, performing an implantation process on the at least one region.12-15-2011
20110306195METHOD OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES - In a vertical semiconductor device and a method of manufacturing a vertical semiconductor device, sacrificial layers and insulating interlayers are repeatedly and alternately stacked on a substrate. The sacrificial layers include boron (B) and nitrogen (N) and have an etching selectivity with respect to the insulating interlayers. Semiconductor patterns are formed on the substrate through the sacrificial layers and the insulating interlayers. The sacrificial layers and the insulating interlayers are at least partially removed between the semiconductor patterns to form sacrificial layer patterns and insulating interlayer patterns on sidewalls of the semiconductor patterns. The sacrificial layer patterns are removed to form grooves between the insulating interlayer patterns. The grooves expose portions of the sidewalls of the semiconductor patterns. A gate structure is formed in each of the grooves.12-15-2011
20110318916SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - An object is to suppress deterioration of element characteristics even when an oxide semiconductor is formed after a gate insulating layer, a source electrode layer, and a drain electrode layer are formed. A gate electrode layer is formed over a substrate. A gate insulating layer is formed over the gate electrode layer. A source electrode layer and a drain electrode layer are formed over the gate insulating layer. Surface treatment is performed on surfaces of the gate insulating layer, the source electrode layer, and the drain electrode layer which are formed over the substrate. After the surface treatment is performed, an oxide semiconductor layer is formed over the gate insulating layer, the source electrode layer, and the drain electrode layer.12-29-2011
20110318915PROCESS TO MAKE HIGH-K TRANSISTOR DIELECTRICS - A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.12-29-2011
20110086504METHODS FOR FORMING INTEGRATED CIRCUITS - A method for forming an integrated circuit is provided. The method includes forming a gate dielectric structure over a substrate. A titanium-containing sacrificial layer is formed, contacting the gate dielectric structure. The whole titanium-containing sacrificial layer is substantially removed.04-14-2011
20100167519POST HIGH-K DIELECTRIC/METAL GATE CLEAN - A method for fabricating a CMOS integrated circuit (IC) includes the step of providing a substrate having a semiconductor surface. A gate stack including a metal gate electrode on a metal including high-k dielectric layer is formed on the semiconductor surface. Dry etching is used to pattern the gate stack to define a patterned gate electrode stack having exposed sidewalls of the metal gate electrode. The dry etching forms post etch residuals some of which are deposited on the substrate. The substrate including the patterned gate electrode stack is exposed to a solution cleaning sequence including a first clean step including a first acid and a fluoride for removing at least a portion of the post etch residuals, wherein the first clean step has a high selectivity to avoid etching the exposed sidewalls of the metal gate electrode. A second clean after the first clean consists essentially of a fluoride which removes residual high-k material on the semiconductor surface.07-01-2010
20120045891Methods Of Forming Patterns, And Methods Of Forming Integrated Circuits - Some embodiments include methods of forming patterns in substrates by utilizing block copolymer assemblies as patterning materials. A block copolymer assembly may be formed over a substrate, with the assembly having first and second subunits arranged in a pattern of two or more domains. Metal may be selectively coupled to the first subunits relative to the second subunits to form a pattern of metal-containing regions and non-metal-containing regions. At least some of the block copolymer may be removed to form a patterned mask corresponding to the metal-containing regions. A pattern defined by the patterned mask may be transferred into the substrate with one or more etches. In some embodiments, the patterning may be utilized to form integrated circuitry, such as, for example, gatelines.02-23-2012
20120045890Methods Of Forming Non-Volatile Memory Devices Including Dummy Word Lines - A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed.02-23-2012
20120003827METHOD FOR MANUFACTURING METAL GATE STACK STRUCTURE IN GATE-FIRST PROCESS - A method for manufacturing a metal gate stack structure in gate-first process comprises the following steps after making conventional LOCOS and STI isolations: growing an untra-thin interface layer of oxide or oxynitride on a semiconductor substrate by rapid thermal oxidation or chemical process; depositing a high dielectric constant (K) gate dielectric on the untra-thin interface oxide layer and then performing rapid thermal annealing; depositing a TiN metal gate; depositing a barrier layer of AlN or TaN; depositing a poly-silicon film and a hard mask, and performing photo-lithography and the etching of the hard mask; after photo-resist removing, etching the poly-silicon film/metal gate/high-K gate dielectric sequentially to form the metal gate stack structure. The manufacturing method of the present invention is suitable for integration of high-K dielectric/metal gate in nano-scale CMOS devices, and removes obstacles of implementing high-K/metal gate integration.01-05-2012
20120003828SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME - A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate, forming a penetration region penetrating the laminated structure, forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region, and forming an active pattern in the penetration region. The method also includes exposing a portion of the active pattern by removing the sacrificial layers and forming an information storage layer on the exposed portion of the active pattern.01-05-2012
20110097888Semiconductor memory device and method of manufacturing the same - A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.04-28-2011
20110165770Non-volatile memory device - A non-volatile memory device includes a memory cell region which is formed on a semiconductor substrate to store predetermined information, and a peripheral circuit region which is formed on the semiconductor substrate. The memory cell region includes a gate electrode; and a charge storage layer, the charge storage layer being formed to be a notch or wedge shape having an edge extending into both sides of a bottom end of the gate electrode. The peripheral circuit region includes no charge storage layer therein.07-07-2011
20110165769NONVOLATILE MEMORY DEVICE WITH MULTIPLE BLOCKING LAYERS AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blocking layer, wherein the first blocking layer has a greater energy band gap than the second blocking layer and the second blocking layer has a greater permittivity than the first blocking layer.07-07-2011
20120058634METHOD OF FABRICATING COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) DEVICE - A method of fabricating a CMOS device having high-k dielectric layer and metal gate electrode is provided. First, an isolation structure is formed in a substrate to define a first-type and a second-type MOS regions; an interfacial layer and a high-k dielectric layer are sequentially formed over the substrate; a first and a second cover layers are respectively formed over a portion of the high-k dielectric layer at the first-type MOS region and another portion of the high-k dielectric layer at the second-type MOS region; afterwards, an in-situ etching step is performed to sequentially etch the first and second cover layers using a first etching solution and to etch both the high-k dielectric layer and the interfacial layer using a second etching solution until the substrate is exposed. Wherein, the second etching solution is a mixed etching solution containing the first etching solution.03-08-2012
20120064708FILM FORMING METHOD, SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF AND SUBSTRATE PROCESSING APPARATUS THEREFOR - In a method for forming a stacked substrate of a MOS (Metal Oxide Semiconductor) structure including an oxide film serving as a gate insulating film formed on a semiconductor material layer having a film or substrate shape; and a conductive film serving as a gate electrode formed on the oxide film, a polysilane film on the semiconductor material layer is formed by coating a polysilane solution on a surface of a substrate to which the semiconductor material layer is exposed. A film containing metal ions is formed on the polysilane film by coating a metal salt solution thereon, and the polysilane film and the film containing metal ions are respectively modified into a polysiloxane film and a film containing fine metal particles to form the stacked substrate.03-15-2012
20120108050WORK FUNCTION ENGINEERING FOR EDRAM MOSFETS - Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD05-03-2012
20110104881METHOD OF REDUCING WORDLINE SHORTING - A method of fabricating a memory device includes providing a substrate having an insulating layer, forming first, second, and third conductive layers on the insulating layer, forming a mask on the third conductive layer, etching through the third conductive layer and a first portion thickness of the second conductive layer using the mask to provide an etched sidewall portions of the third conductive layer and an etched upper surface of the second polysilicon layer, and forming a liner layer along the etched sidewall portions and the etched upper surface.05-05-2011
20120122309METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING A WORK FUNCTION CONTROL FILM - A method of fabricating a semiconductor device may include: preparing a substrate in which first and second regions are defined; forming an interlayer insulating film, which includes first and second trenches, on the substrate; forming a work function control film, which contains Al and N, along a top surface of the interlayer insulating film, side and bottom surfaces of the first trench, and side and bottom surfaces of the second trench; forming a mask pattern on the work function control film formed in the second region; injecting a work function control material into the work function control film formed in the first region to control a work function of the work function control film formed in the first region; removing the mask pattern; and forming a first metal gate electrode to fill the first trench and forming a second metal gate electrode to fill the second trench.05-17-2012
20110183510SEMICONDUCTOR DEVICE HAVING LAMINATED ELECTRONIC CONDUCTOR ON BIT LINE - There are provided a semiconductor device and a fabrication method therefor including an ONO film (07-28-2011
20110183509Non-Volatile Memory Device with Improved Immunity to Erase Saturation and Method for Manufacturing Same - A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate.07-28-2011
20110183508REPLACEMENT GATE FinFET DEVICES AND METHODS FOR FORMING THE SAME - A structure and method for replacement metal gate technology is provided for use in conjunction with semiconductor fins or other devices. An opening is formed in a dielectric by removing a sacrificial gate material such as polysilicon. The surfaces of the semiconductor fin within which a transistor channel is formed, are exposed in the opening. A replacement metal gate is formed by forming a diffusion barrier layer within the opening and over a gate dielectric material, the diffusion barrier layer formation advantageously followed by an in-situ plasma treatment operation. The treatment operation utilizes at least one of argon and hydrogen and cures surface defects in the diffusion barrier layer enabling the diffusion barrier layer to be formed to a lesser thickness. The treatment operation decreases resistivity, densifies and alters the atomic ratio of the diffusion barrier layer, and is followed by metal deposition.07-28-2011
20120129330SEMICONDUCTOR DEVICES EMPLOYING HIGH-K DIELECTRIC LAYERS AS A GATE INSULATING LAYER AND METHODS OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a nitrogen-containing lower gate insulating layer on the semiconductor substrate, forming an upper gate insulating layer on the nitrogen containing lower gate insulating layer, forming a lower metal layer on the upper gate insulating layer; and selectively removing the lower metal layer in the first region such that a lower metal layer pattern remains in the second region, wherein the upper gate insulating layer in the first region prevents the lower gate insulating layer in the first region from being etched during removing of the lower metal layer in the first region. A semiconductor device fabricated by the method is also provided.05-24-2012
20120164822METHODS OF FABRICATING HIGH-K METAL GATE DEVICES - Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.06-28-2012
20100210100Semiconductor device and method for manufacturing the same - It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si<08-19-2010
20120315750SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - A semiconductor device includes bit lines (12-13-2012
20120315749Metal Gate Stack Formation for Replacement Gate Technology - Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a reduced threshold voltage (V12-13-2012
20120135594METHOD FOR FORMING A GATE ELECTRODE - A method for forming a gate electrode includes: providing a substrate; forming a gate dielectric layer and forming a sacrificial layer, the sacrificial layer including doping ions, a density of the doping ions in the sacrificial layer decreasing with increasing distance from the substrate; forming a hard mask layer; patterning the sacrificial layer and the hard mask layer; removing part of the patterned sacrificial layer by wet etching with the patterned hard mask layer as a mask, to form a dummy gate electrode which has a top width bigger than a bottom width, and removing the patterned hard mask layer; removing the dummy gate electrode and filling a gate trench with gate material to form a gate electrode which has a top width bigger than a bottom width, which facilitates the filling of the gate material and can avoid or reduce cavity forming in the gate material.05-31-2012
20120135595NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer.05-31-2012
20100173487Semiconductor apparatus and method of manufacturing the semiconductor apparatus - A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO07-08-2010
20120252201METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - According to one embodiment, a method for fabricating a semiconductor device including a memory cell portion and a select gate portion, the method includes etching a charge accumulation layer, a tunnel insulating film, and a semiconductor substrate to make a trench, burying a first insulating film in the trench to contact with a side surface of the charge accumulation layer, performing heat processing to compress the first insulating film, forming a second insulating film on the charge accumulation layer and the first insulating film, etching the second insulating film in the select gate portion to expose a surface of the charge accumulation layer, forming a silicon layer to contact with the exposed surface of the charge accumulation layer, forming a metal layer on the silicon layer, and performing heat processing to silicide an entire boundary region between the charge accumulation layer and the tunnel insulating film.10-04-2012
20120171854METHOD FOR FORMING METAL GATE - A method for forming a metal gate includes providing a substrate, subsequently forming a dummy gate on the substrate, forming spacers on sidewalls of the dummy gate, forming a stop layer on the substrate, the dummy gate and spacers of the dummy gate, and forming a sacrificial dielectric layer on the dummy gate and the stop layer. The method further includes removing a part of the sacrificial dielectric layer and the stop layer until the dummy gate is exposed and, removing a residual sacrificial dielectric layer, depositing an interlayer dielectric layer on the dummy gate and the stop layer, polishing the interlayer dielectric layer until the dummy gate is exposed, removing the dummy gate to form a trench, and forming a metal gate in the trench. The interlayer dielectric layer is flat and substantially flush with the dummy gate, so that no recesses are formed thereon.07-05-2012
20120220116Dry Chemical Cleaning For Semiconductor Processing - A deposition process including a dry etch process, followed by a deposition process of a high-k dielectric is disclosed. The dry etch process involves placing a substrate to be cleaned into a processing chamber to remove surface oxides. A gas mixture is energized to form a plasma of reactive gas which reacts with an oxide on the substrate, forming a thin film. The substrate is heated to vaporize the thin film and expose a substrate surface. The substrate surface is substantially free of oxides. Deposition is then used to form a layer on the substrate surface.08-30-2012
20100062595Nonvolatile memory device and method of forming the same - A nonvolatile memory device and a method of forming the nonvolatile memory device, the method including forming a tunnel insulating layer on a substrate, wherein forming the tunnel insulating layer includes forming a multi-element insulating layer by a process including sequentially supplying a first element source, a second element source, and a third element source to the substrate, forming a charge storage layer on the tunnel insulating layer, forming a blocking insulating layer on the charge storage layer, and forming a control gate electrode on the blocking insulating layer.03-11-2010
20100048009METHOD OF FORMING ALUMINUM-DOPED METAL CARBONITRIDE GATE ELECTRODES - A method for forming an aluminum-doped metal (tantalum or titanium) carbonitride gate electrode for a semiconductor device is described. The method includes providing a substrate containing a dielectric layer thereon, and forming the gate electrode on the dielectric layer in the absence of plasma. The gate electrode is formed by depositing a metal carbonitride film, and adsorbing an atomic layer of an aluminum precursor on the metal carbonitride film. The steps of depositing and adsorbing may be repeated a desired number of times until the aluminum-doped metal carbonitride gate electrode has a desired thickness.02-25-2010
20100048010SEMICONDUCTOR DEVICE GATE STRUCTURE INCLUDING A GETTERING LAYER - A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth.02-25-2010
20100048013NOVEL HIGH-K METAL GATE CMOS PATTERNING METHOD - The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.02-25-2010
20100048012Method for fabricating nonvolatile memory device - Provided is a method for fabricating a nonvolatile memory device capable of improving charge retention characteristics. The method for fabricating a nonvolatile memory device includes forming a charge trapping layer with a memory region and a charge blocking region on a semiconductor substrate, and trapping charges in the charge blocking region of the charge trapping layer.02-25-2010
20100048011METHOD OF PATTERNING A METAL GATE OF SEMICONDUCTOR DEVICE - Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.02-25-2010
20090061610Semiconductor device and method of manufacturing the same - A semiconductor device includes a plate of semiconductor layer, an insulator layer formed on the plate of semiconductor layer and brought into contact with the plate of semiconductor layer by at least two adjacent faces, a thickness of the insulator layer in the vicinity of a boundary line between the two adjacent faces being larger than that of the insulator layer in a region other than the vicinity of the boundary line, and a band of conductor layer formed facing a middle portion of the plate-like semiconductor layer via the insulator layer.03-05-2009
20090061608METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A SILICON DIOXIDE LAYER - A method of depositing a silicon dioxide layer for a semiconductor device. The method includes depositing the silicon dioxide layer to have a silicon concentration of greater than 30 atomic percent and a nitrogen concentration of less than 5 atomic percent. The depositing includes flowing nitric oxide gas with a silicon precursor over a substrate. In one example, the silicon precursor and nitric oxide are flowed over a substrate with the substrate being at a temperature in a range of approximately 600 to approximately 900 degrees Celsius. In one example, the silicon dioxide layer is formed on a layer including charge storage memory material.03-05-2009
20090061609METHODS OF FORMING NITRIDE READ ONLY MEMORY AND WORD LINES THEREOF - A method of forming word lines of a memory includes providing a substrate and forming a conductive layer on the substrate. A metal silicide layer is formed on the conductive layer, and a mask pattern is formed on the metal silicide layer. A mask liner covering the mask pattern and the surface of the metal silicide layer is formed on the substrate to shorten distances between the word line regions. An etching process is performed on the mask liner and the mask pattern until the partial surface of the metal silicide layer is exposed. The metal silicide layer and the conductive layer are etched to form word lines by utilizing the mask liner and the mask pattern as a mask. A silicon content of the metal silicide layer must be less than or equal to 2 for reducing a bridge failure rate between the word lines.03-05-2009
20120083112METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY WITH BACKING WIRINGS - A nonvolatile semiconductor memory comprises a first memory cell transistor, a second memory cell transistor, a connection layer, protrusion portions and a contact portion. The first memory cell transistor comprises a first gate electrode formed above a first channel region, and a second gate electrode formed on a side of the first gate electrode through an insulating film. The second memory cell transistor comprises a third gate electrode formed above a second channel region, and a fourth gate electrode formed on a side of the third gate electrode through an insulating film and facing the second gate electrode. The connection layer connects the second gate electrode and the fourth gate electrode. The protrusion portions are formed of a material different than that of the second and fourth gate electrodes, and are formed on both ends of the connection layer. The contact portion is formed on the connection layer.04-05-2012
20120083111Methods of Manufacturing a Semiconductor Device - There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.04-05-2012
20120083110METHOD FOR MANUFACTURING MOS TRANSISTORS WITH DIFFERENT TYPES OF GATE STACKS - A method for manufacturing three types of MOS transistors in three regions of a same substrate, including the steps of: forming a first insulating layer, removing the first insulating layer from the first and second regions, forming a silicon oxide layer, depositing an insulating layer having a dielectric constant which is at least twice greater than that of silicon oxide, depositing a first conductive oxygen scavenging layer, removing the first conductive layer from the second and third regions, and annealing.04-05-2012
20120264281METHOD OF FABRICATING A PLURALITY OF GATE STRUCTURES - The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a plurality of gate structures. An exemplary method of fabricating the plurality of gate structures comprises providing a silicon substrate; depositing a dummy oxide layer over the substrate; depositing a dummy gate electrode layer over the dummy oxide layer; patterning the layers to define a plurality of dummy gates; forming nitrogen-containing sidewall spacers on the plurality of dummy gates; forming an interlayer dielectric layer between the nitrogen-containing sidewall spacers; selectively depositing a hard mask layer on the interlayer dielectric layer by an atomic layer deposition (ALD) process; removing the dummy gate electrode layer; removing the dummy oxide layer; depositing a gate dielectric; and depositing a gate electrode.10-18-2012
20120264282METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING NANOCRYSTALS - A method is provided for forming a semiconductor device having nanocrystals. The method includes: forming a first insulating layer over a surface of a substrate; forming a first plurality of nanocrystals on the first insulating layer; implanting a first material into the first insulating layer; and annealing the first material to form a second plurality of nanocrystals in the first insulating layer. The method may be used to provide a charge storage layer for a non-volatile memory having a greater nanocrystal density.10-18-2012
20080299753Peripheral Gate Stacks and Recessed Array Gates - Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array.12-04-2008
20110003469Methods Of Forming Memory Cells; And Methods Of Forming Vertical Structures - Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.01-06-2011
20120322253METHOD FOR REDUCING INTERFACIAL LAYER THICKNESS FOR HIGH-K AND METAL GATE STACK - This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer.12-20-2012
20110039405METHOD FOR FABRICATING A SONOS MEMORY - The present invention provides a method for making SONOS memory, comprising the following steps: depositing silicon oxide layer and silicon oxynitride layer in sequence on underlayer; coating a layer of photoresist on the silicon oxynitride layer; removing part of the photoresist and form the logic area; removing silicon oxynitride layer in the logic area; removing the bottom oxide layer in the logic area; growing top oxide layer on the silicon oxynitride layer and logic area; removing the top oxide layer in the logic area; growing gate oxide layer; forming device structure of SONOS and logic area. The present invention can avoid the damage of top oxide layer and lateral etching in wet etching so as to improve the defect-free rate of devices.02-17-2011
20110230042METHOD FOR IMPROVING THERMAL STABILITY OF METAL GATE - The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure on the substrate, the gate structure including a dummy gate, removing the dummy gate from the gate structure thereby forming a trench, forming a work function metal layer partially filling the trench, forming a fill metal layer filling a remainder of the trench, performing a chemical mechanical polishing (CMP) to remove portions of the metal layers outside the trench, and implanting Si, C, or Ge into a remaining portion of the fill metal layer.09-22-2011
20110237060SACRIFICIAL NITRIDE AND GATE REPLACEMENT - Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.09-29-2011
20110237059Non-volatile memory devices with multiple layers having band gap relationships among the layers - A nonvolatile memory device may include: a tunnel insulating layer on a semiconductor substrate; a charge storage layer on the tunnel insulating layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer. The tunnel insulating layer may include a first tunnel insulating layer and a second tunnel insulating layer. The first tunnel insulating layer and the second tunnel insulating layer may be sequentially stacked on the semiconductor substrate. The second tunnel insulating layer may have a larger band gap than the first tunnel insulating layer. A method for fabricating a nonvolatile memory device may include: forming a tunnel insulating layer on a semiconductor substrate; forming a charge storage layer on the tunnel insulating layer; forming a blocking insulating layer on the charge storage layer; and forming a control gate electrode on the blocking insulating layer.09-29-2011
20100240208FLOATING GATE HAVING MULTIPLE CHARGE STORING LAYERS, METHOD OF FABRICATING THE FLOATING GATE, NON-VOLATILE MEMORY DEVICE USING THE SAME, AND FABRICATING METHOD THEREOF - Provided is a floating gate having multiple charge storage layers, a non-volatile memory device using the same, and a method of fabricating the floating gate and the non-volatile memory device, in which the multiple charge storage layers using metallic/semiconducting nano-particles is formed to thereby enhance a charge storage capacity of the memory device. The floating gate includes a polymer electrolytic film which is deposited on a tunneling oxide film, and is formed of at least one stage in which at least one thin film is deposited on each stage, and at least one metal nano-particle layer which is self-assembled on the upper surface of each stage of the polymer electrolytic film and on which a number of nano-particles for trapping charges are formed. The floating gate is made by self-assembling the nano-particles on the polymer electrolytic film, and thus can be fabricated without undergoing a heat treatment process at high temperature.09-23-2010
20120276731METHOD FOR FABRICATING A GATE DIELECTRIC LAYER AND FOR FABRICATING A GATE STRUCTURE - A method for fabricating a gate dielectric layer comprises the steps of: forming a dielectric layer on a semiconductor substrate; performing a nitrogen treating process to form a nitride layer on the dielectric layer; and performing a thermal treating process at 1150-1400° C. for a period of 400-800 milliseconds, to form a gate dielectric layer. A step of forming a gate layer on the gate dielectric layer may be performed to form a gate structure.11-01-2012
20120276730METHODS FOR FABRICATING A GATE DIELECTRIC LAYER AND FOR FABRICATING A GATE STRUCTURE - A method for fabricating a gate dielectric layer comprises the steps of: forming a dielectric layer on a semiconductor substrate; performing a nitrogen treating process to form a nitride layer on the dielectric layer; performing an oxygen treating process to implant oxygen into the nitride layer; and performing a thermal treating process to form a gate dielectric layer. A step of forming a gate layer on the gate dielectric layer may be performed to form a gate structure.11-01-2012
20120322252SEMICONDUCTOR MEMORY DEVICE COMPRISING THREE-DIMENSIONAL MEMORY CELL ARRAY - A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.12-20-2012
20100203716METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING DUAL GATE - A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.08-12-2010
20120100706Microelectronic Fabrication Methods Using Composite Layers for Double Patterning - Some embodiments provide microelectronic fabrication methods in which a sacrificial pattern is formed on a substrate. A spacer formation layer is formed on the substrate, the spacer formation layer covering the sacrificial pattern. The spacer formation layer is etched to expose an upper surface of the sacrificial pattern and to leave at least one spacer on at least one sidewall of the sacrificial pattern. A first portion of the sacrificial pattern having a first width is removed while leaving intact a second portion of the sacrificial pattern having a second width greater than the first width to thereby form a composite mask pattern including the at least one spacer and a portion of the sacrificial layer. An underlying portion of the substrate is etched using the composite mask pattern as an etching mask.04-26-2012
20100167517CROSS-CONTAMINATION CONTROL FOR PROCESSING OF CIRCUITS COMPRISING MOS DEVICES THAT INCLUDE METAL COMPRISING HIGH-K DIELECTRICS - A cross method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface, wherein the bevel semiconductor surface and backside semiconductor surface include silicon or germanium. A metal including high-k gate dielectric layer is formed on at least the topside semiconductor surface and on at least a portion of the bevel semiconductor surface and backside semiconductor surface. The high-k dielectric material on the bevel semiconductor surface and the backside semiconductor surface are selectively removed while protecting the high-k dielectric layer on the topside semiconductor surface. The selective removing includes a first oxidizing treatment, and a fluoride including wet etch follows the first oxidizing treatment. The fabrication of the IC is completed including forming at least one metal gate layer on the high-k gate dielectric layer after the selectively removing step.07-01-2010
20130012012SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate having an oxide layer thereon is provided. A high temperature process higher than 1000° C. is performed to form a melting layer between the substrate and the oxide layer. A removing process is performed to remove the oxide layer and the melting layer.01-10-2013
20130012013Methods Of Forming Transistor Gates - Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.01-10-2013
20100129998NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A charge holding insulating film in a memory cell is constituted by a laminated film composed of a bottom insulating film, a charge storage film, and a top insulating film on a semiconductor substrate. Further, by performing a plasma nitriding treatment to the bottom insulating film, a nitride region whose nitrogen concentration has a peak value and is 1 atom % or more is formed on the upper surface side in the bottom insulating film. The thickness of the nitride region is set to 0.5 nm or more and 1.5 nm or less, and the peak value of nitrogen concentration is set to 5 atom % or more and 40 atom % or less, and a position of the peak value of nitrogen concentration is set within 2 nm from the upper surface of the bottom insulating film, thereby suppressing an interaction between the bottom insulating film and the charge storage film.05-27-2010
20120149187NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a non-volatile semiconductor memory device including previously forming a recess in a first peripheral region on a semiconductor substrate, forming a first gate insulator having a first thickness in the recess, forming a second gate insulator having a second thickness less than the first thickness in an array region and a second peripheral region on the semiconductor substrate, successively depositing first and second gate electrode films and first and second mask insulators on each of the first and second gate insulators, forming an isolation trench on a surface of the semiconductor substrate to correspond to each position between the array region and the first and second regions of the peripheral region, depositing a buried insulator on the entire surface, and polishing an upper surface of the buried insulator so that the upper surface can be planarized.06-14-2012
20120149186FORMATION OF GATE DIELECTRICS WITH UNIFORM NITROGEN DISTRIBUTION - The present invention provides a method for manufacturing a gate dielectric (06-14-2012
20130017678METHODS OF ANNEAL AFTER DEPOSITION OF GATE LAYERSAANM TSAI; Chun HsiungAACI Xinpu TownshipAACO TWAAGP TSAI; Chun Hsiung Xinpu Township TWAANM YU; Xiong-FeiAACI HsinchuAACO TWAAGP YU; Xiong-Fei Hsinchu TWAANM HUANG; Yu-LienAACI Jhubei CityAACO TWAAGP HUANG; Yu-Lien Jhubei City TWAANM LIN; Da-WenAACI Hsinchu CityAACO TWAAGP LIN; Da-Wen Hsinchu City TW - Multi-stage preheat high-temperature anneal processes after the deposition of the gate dielectric layer(s) reduce the number of interfacial sites and improve the negative bias temperature instability (NTBI) performance of a p-type metal-oxide-semiconductor transistor (PMOS). The gate dielectric layers may include an interfacial oxide layer and a high-k dielectric layer. The multi-stage preheat is designed to reduce dopant deactivation and to improve inter-mixing between the interfacial oxide layer and the high-k dielectric layer. The high-temperature anneal is used to reduce the number of interfacial sites at the interface between the silicon substrate and the interfacial oxide layer.01-17-2013
20130017679WORK FUNCTION ADJUSTMENT IN HIGH-K METAL GATE ELECTRODE STRUCTURES BY SELECTIVELY REMOVING A BARRIER LAYER - Generally, the present disclosure is directed work function adjustment in high-k metal gate electrode structures. In one illustrative embodiment, a method is disclosed that includes removing a placeholder material of a first gate electrode structure and a second gate electrode structure, and forming a first work function adjusting material layer in the first and second gate electrode structures, wherein the first work function adjusting material layer includes a tantalum nitride layer. The method further includes removing a portion of the first work function adjusting material layer from the second gate electrode structure by using the tantalum nitride layer as an etch stop layer, removing the tantalum nitride layer by performing a wet chemical etch process, and forming a second work function adjusting material layer in the second gate electrode structure and above a non-removed portion of the first work function adjusting material layer in the first gate electrode structure.01-17-2013
20110159680METHOD OF FORMING A DIELECTRIC LAYER AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - In a method of forming an aluminum oxide layer, an aluminum source gas and a dilution gas can be supplied into a chamber through a common gas supply nozzle so that the aluminum source gas may be adsorbed on a substrate in the chamber. A first purge gas can be supplied into the chamber to purge the physically adsorbed aluminum source gas from the substrate. An oxygen source gas may be supplied into the chamber to form an aluminum oxide layer on the substrate. A second purge gas may be supplied into the chamber to purge a reaction residue and the physically adsorbed remaining gas from the substrate. The operations can be performed repeatedly to form an aluminum oxide layer having a desired thickness.06-30-2011
20080227282METHOD OF MANUFACTURING NON-VOLATILE MEMORY - A non-volatile memory is provided. A substrate having a number of trenches and a number of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A number of select gate dielectric layers are disposed between the select gates and the substrate. A number of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A number of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.09-18-2008
20130171813FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION - A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device.07-04-2013
20080220603METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An embodiment of the present invention is a method of manufacturing a semiconductor device, for forming transistors of first and second conductivity types in first and second regions on a substrate respectively. The method includes: depositing a gate insulator and a sacrificial layer ranging from the first region to the second region; removing the sacrificial layer from the first region; depositing a first gate electrode layer, on the gate insulator exposed in the first region, and on the sacrificial layer remaining in the second region; removing the first gate electrode layer and the sacrificial layer from the second region; depositing a second gate electrode layer on the gate insulator exposed in the second region; forming the transistor of the first conductivity type including the gate insulator and the first gate electrode layer; and forming the transistor of the second conductivity type including the gate insulator and the second gate electrode layer.09-11-2008
20130178054METHODS OF MAKING LOGIC TRANSISTORS AND NON-VOLATILE MEMORY CELLS - Methods of making a logic transistor in a logic region and an NVM cell in an NVM region of a substrate include forming a conductive layer on a gate dielectric, patterning the conductive layer over the NVM region, removing the conductive layer over the logic region, forming a dielectric layer over the NVM region, forming a protective layer over the dielectric layer, removing the dielectric layer and the protective layer from the logic region, forming a high-k dielectric layer over the logic region and a remaining portion of the protective layer, and forming a first metal layer over the high-k dielectric layer. The first metal layer, the high-k dielectric, and the remaining portion of the protective layer are removed over the NVM region. A conductive layer is deposited over the remaining portions of the dielectric layer and over the first metal layer, and the conductive layer is patterned.07-11-2013
20130102142STRESS MODULATION FOR METAL GATE SEMICONDUCTOR DEVICE - The present disclosure provides a method of semiconductor device fabrication including removing a sacrificial gate structure formed on a substrate to provide an opening. A metal gate structure is then formed in the opening. The forming of the metal gate structure includes forming a first layer (including metal) on a gate dielectric layer, wherein the first layer includes a metal and performing a stress modulation process on the first layer. The stress modulation process may include ion implantation of a neutral species such as silicon, argon, germanium, and xenon.04-25-2013
20130102143METHOD OF MAKING A NON-VOLATILE MEMORY CELL HAVING A FLOATING GATE - Forming an NVM structure includes forming a floating gate layer; forming a first dielectric layer over the floating gate layer; forming a plurality of nanocrystals over the first dielectric layer; etching the first dielectric layer using the plurality of nanocrystals as a mask to form dielectric structures, wherein the floating gate layer is exposed between adjacent dielectric structures; etching a first depth into the floating gate layer using the plurality of dielectric structures as a mask to form a plurality of patterned structures, wherein the first depth is less than a thickness of the floating gate layer; patterning the floating gate layer to form a floating gate; forming a second dielectric layer over the floating gate, wherein the second dielectric layer is formed over the patterned structures and on the floating gate layer between adjacent patterned structures; and forming a control gate layer over the second dielectric layer.04-25-2013
20130130487Integrated Circuit with Metal and Semi-Conducting Gate - A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.05-23-2013
20130130488Method of Patterning a Metal Gate of Semiconductor Device - Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.05-23-2013
20130157453METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming first auxiliary patterns, alternately forming first material layers and second material layers on the sidewalls of the first auxiliary patterns so that a gap region between the first auxiliary patterns adjacent to each other is filled, removing the second material layers, and forming charge storage layers in respective regions from which the second material layers have been removed.06-20-2013
20110223757WORK FUNCTION ADJUSTMENT WITH THE IMPLANT OF LANTHANIDES - Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.09-15-2011
20110250745METHODS OF FORMING PATTERNS, AND METHODS OF FORMING INTEGRATED CIRCUITS - Some embodiments include methods of forming patterns in substrates by utilizing block copolymer assemblies as patterning materials. A block copolymer assembly may be formed over a substrate, with the assembly having first and second subunits arranged in a pattern of two or more domains. Metal may be selectively coupled to the first subunits relative to the second subunits to form a pattern of metal-containing regions and non-metal-containing regions. At least some of the block copolymer may be removed to form a patterned mask corresponding to the metal-containing regions. A pattern defined by the patterned mask may be transferred into the substrate with one or more etches. In some embodiments, the patterning may be utilized to form integrated circuitry, such as, for example, gatelines.10-13-2011
20110275211Methods of Etching Nanodots, Methods of Removing Nanodots From Substrates, Methods of Fabricating Integrated Circuit Devices, Methods of Etching a Layer Comprising a Late Transition Metal, and Methods of Removing a Layer Comprising a Late Transition Metal From a Substrate - Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated circuit devices. In one embodiment, a method of etching nanodots that include a late transition metal includes exposing such nanodots to a gas comprising a phosphorus and halogen-containing compound and an oxidizing agent. After the exposing, the nanodots which are remaining and were exposed are etched (either partially or completely) with an aqueous solution comprising HF.11-10-2011
20120258585INCORPORATING IMPURITIES USING A DISCONTINUOUS MASK - Methods of incorporating impurities into materials can be useful in non-volatile memory devices as well as other integrated circuit devices. Various embodiments provide for incorporating impurities into a material using a discontinuous mask.10-11-2012
20100317183METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE - By removing an interlayer insulating film from a memory cell region in which a plurality of bit line diffusion layers and a plurality of word lines are formed, a trench which exposes the plurality of word lines and the sidewall insulating film is formed on the memory cell region. Thereafter, an ultraviolet light blocking film is formed on the exposed word lines and sidewall insulating film to fill the trench. Here, in the step of forming the trench, the trench is formed so that an end of the trench in a direction in which the bit line diffusion layers are extended is located on a word line located at an outermost portion of the memory cell region.12-16-2010
20110294287METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING DUAL FULLY-SILICIDED GATE - A method of manufacturing the semiconductor device having a dual fully-silicided gate includes the following steps. A substrate having a first transistor and a second transistor formed thereon is provided, wherein the first transistor includes a first gate and a first source/drain and the second transistor includes a second gate and a second source/drain. The gate height of the first gate is different from that of the second gate. A first silicidation process is performed to respectively transform the first gate and the second gate into a first silicided gate and a second silicided gate simultaneously, wherein the material of the first silicided gate is different from that of the second silicided gate.12-01-2011
20120015512METHOD OF MANUFACTURING NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.01-19-2012
20120021596METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The present invention relates to the field of semiconductor manufacturing. The present invention provides a method of manufacturing a semiconductor device, which comprises: providing a semiconductor substrate; forming an interface layer, a gate dielectric layer and a gate electrode on the substrate; forming a metal oxygen absorption layer on the gate electrode; performing a thermal annealing process on the semiconductor device so that the metal oxygen absorption layer absorbs oxygen in the interface layer and the thickness of the interface layer is reduced. By means of the present invention, the thickness of the interface layer can be reduced on one hand, and on the other hand the metal in the metal oxygen absorption layer is made to diffuse into the gate electrode and/or the gate dielectric layer through the annealing process, which further achieves the effects of adjusting the effective work function and controlling the threshold voltage.01-26-2012
20120028455Method of manufacturing a semiconductor device - A method of manufacturing a semiconductor device having a p-type field effect transistor and an n-type field effect transistor includes the steps of: forming an interface insulating layer and a high-permittivity layer on a substrate in the stated order; forming a pattern of a sacrifice layer on the high-permittivity layer; forming a metal-containing film containing metal elements therein on the high-permittivity layer in a first region where the sacrifice layer is formed and a second region where no sacrifice layer is formed; introducing the metal elements into an interface between the interface insulating layer and the high-permittivity layer in the second region by conducting a heat treatment; and removing the sacrifice layer by wet etching, wherein in the removing step, the sacrifice layer is etched easily more than the high-permittivity layer. With this configuration, the semiconductor device excellent in reliability is obtained.02-02-2012
20130196497METHOD FOR PRODUCING TRANSISTOR - According to the present invention, there is provided a process for producing a transistor having a high precision and a high quality with a high yield by selectively etching a natural silicon oxide film, and further by selectively etching a dummy gate made of silicon. The present invention relates to a process for producing a transistor using a structural body which includes a substrate, and a dummy gate laminate formed by laminating at least a high dielectric material film and a dummy gate made of silicon having a natural silicon oxide film on a surface thereof, a side wall disposed to cover a side surface of the laminate and an interlayer insulating film disposed to cover the side wall which are provided on the substrate, said process including an etching step using a specific etching solution and thereby replacing the dummy gate with an aluminum metal gate.08-01-2013
20120070975Methods of Forming Gate Structure and Methods of Manufacturing Semiconductor Device Including the Same - A method of forming agate structure having an improved electric characteristic is disclosed. A gate insulating layer is formed on a substrate and a metal layer is formed on the gate insulating layer. Then, an amorphous silicon layer is formed on the metal layer by a physical vapor deposition (PVD) process. An impurity doped polysilicon layer is formed on the amorphous silicon layer. Formation of an oxide layer at an interface between the amorphous silicon layer and the metal layer may be prevented.03-22-2012
20120302053NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE NONVOLATILE MEMORY DEVICE INCLUDING GIVING AN UPPER PORTION OF AN INSULATING LAYER AN ETCHING SELECTIVITY WITH RESPECT TO A LOWER PORTION - A nonvolatile memory device and a method of forming a nonvolatile memory device are provided. The nonvolatile memory device includes an active region of a semiconductor substrate defined by a device isolation layer, a tunnel insulating structure disposed on the active region, and a charge storage structure disposed on the tunnel insulating structure. The nonvolatile memory device also includes a gate interlayer dielectric layer disposed on the charge storage structure, and a control gate electrode disposed on the gate interlayer dielectric layer. The charge storage structure includes an upper charge storage structure and a lower charge storage structure, and the upper charge storage structure has a higher impurity concentration than the lower charge storage structure.11-29-2012
20120094477HAFNIUM TANTALUM OXYNITRIDE DIELECTRIC - Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film.04-19-2012
20120094476METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - According to an embodiment, there is provided a method of manufacturing a semiconductor device, including forming a nitride film by nitriding a surface of an underlying region having a semiconductor region containing silicon as a main component and an insulating region containing silicon and oxygen as a main component and adjacent to the semiconductor region, carrying out oxidation with respect to the nitride film to convert a portion of the nitride film which is formed on the insulating region into an oxide film and to leave a portion of the nitride film which is formed on the semiconductor region as at least part of a charge storage insulating film, forming a block insulating film on the charge storage insulating film, and forming a gate electrode film on the block insulating film.04-19-2012

Patent applications in class Gate insulator structure constructed of plural layers or nonsilicon containing compound