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Insulated gate formation

Subclass of:

438 - Semiconductor device manufacturing: process

438584000 - COATING WITH ELECTRICALLY OR THERMALLY CONDUCTIVE MATERIAL

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
438591000 Gate insulator structure constructed of plural layers or nonsilicon containing compound 246
438592000 Possessing plural conductive layers (e.g., polycide) 194
438586000 Combined with formation of ohmic contact to semiconductor region 117
438589000 Recessed into semiconductor substrate 72
438587000 Forming array of gate electrodes 60
438595000 Having sidewall structure 50
438590000 Compound semiconductor 4
20090221139Method of producing semiconductor device - A method of producing a semiconductor device includes the steps of: forming an oxide film on a silicon carbide substrate; forming a gate electrode layer on the oxide film; patterning the gate electrode layer to form a gate electrode; and processing thermally the gate electrode layer or the gate electrode under an oxidation environment. Further, the gate electrode layer or the gate electrode is thermally processed under the oxidation environment at a temperature between 750° C. and 900° C.09-03-2009
20110256704METHOD FOR MANUFACTURING A METAL GATE ELECTRODE/HIGH K DIELECTRIC GATE STACK - A method of manufacturing a metal gate/high K dielectric gate stack includes the steps of: forming an interfacial layer of SiON or SiO10-20-2011
20120108049CRYSTALLINE SEMICONDUCTOR THIN FILM, METHOD OF FABRICATING THE SAME, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING THE SAME - There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. A catalytic element for facilitating crystallization of an amorphous semiconductor thin film is added to the amorphous semiconductor thin film, and a heat treatment is carried out to obtain a crystalline semiconductor thin film. After the crystalline semiconductor thin film is irradiated with ultraviolet light or infrared light, a heat treatment at a temperature of 900 to 1200° C. is carried out in a reducing atmosphere. The surface of the crystalline semiconductor thin film is extremely flattened through this step, defects in crystal grains and crystal grain boundaries disappear, and the single crystal semiconductor thin film or substantially single crystal semiconductor thin film is obtained.05-03-2012
20130102141METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a MOSFET includes the steps of preparing a substrate (04-25-2013
Entries
DocumentTitleDate
20110207312SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE FOR APPLYING TENSILE STRESS TO SILICON SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME - A gate insulating film (08-25-2011
20100062590NOVEL SOLUTION FOR POLYMER AND CAPPING LAYER REMOVING WITH WET DIPPING IN HK METAL GATE ETCHING PROCESS - The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes applying a first etching process to the substrate to remove a polysilicon layer and a metal gate layer on the substrate; applying a diluted hydrofluoric acid (HF) to the substrate to remove polymeric residue; thereafter applying to the substrate with a cleaning solution including hydrochloride (HCl), hydrogen peroxide (H2O2) and water (H2O); applying a wet etching process diluted hydrochloride (HCl) to the substrate to remove a capping layer; and applying to the substrate with a second etching process to remove a high k dielectric material layer.03-11-2010
20100022078Aluminum Inks and Methods of Making the Same, Methods for Depositing Aluminum Inks, and Films Formed by Printing and/or Depositing an Aluminum Ink - Aluminum metal ink compositions, methods of forming such compositions, and methods of forming aluminum metal layers and/or patterns are disclosed. The ink composition includes an aluminum metal precursor and an organic solvent. Conductive structures may be made using such ink compositions by printing or coating the aluminum precursor ink on a substrate (decomposing the aluminum metal precursors in the ink) and curing the composition. The present aluminum precursor inks provide aluminum films having high conductivity, and reduce the number of inks and printing steps needed to fabricate printed, integrated circuits.01-28-2010
20120184093HIGH-K/METAL GATE STACK USING CAPPING LAYER METHODS, IC AND RELATED TRANSISTORS - Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.07-19-2012
20100159684Metal High-K (MHK) Dual Gate Stress Engineering Using Hybrid Orientation (HOT) CMOS - A hybrid orientation technology (HOT) CMOS structure is comprised of a tensile stressed NFET gate stack and a compressively stressed PFET gate stack, where each gate stack is comprised of a high dielectric constant oxide/metal, and where the source of the stress in the tensile stressed NFET gate stack and the compressively stressed PFET gate stack is the metal in the high-k metal gate stack.06-24-2010
20110195564Memory Cell Layout - A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once the spacers have been formed, the dummy layers may be removed and the spacers may be used as a mask. By using the spacers instead of a standard lithographic process, the inherent limitations of the lithographic process can be avoided and further scaling of FinFET devices can be achieved.08-11-2011
20130040448METHODS OF FORMING METAL OR METAL NITRIDE PATTERNS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - In a method of forming a metal or metal nitride pattern, a metal or metal nitride layer is formed on a substrate, and a photoresist pattern is formed on the metal or metal nitride layer. An over-coating composition is coated on the metal or metal nitride layer and on the photoresist pattern to form a capping layer on the photoresist pattern. The over-coating composition includes a polymer having amine groups as a side chain or a branch and a solvent. A remaining portion of the over-coating composition is removed by washing with a hydrophilic solution. The metal or metal nitride layer is partially removed using the capping layer and the photoresist pattern as an etching mask.02-14-2013
20090155991Methods of fabricating a semiconductor device - A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.06-18-2009
20100041221HIGH PERFORMANCE CMOS CIRCUITS, AND METHODS FOR FABRICATING SAME - The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.02-18-2010
20100136776SELECTIVE DEPOSITION OF NOBLE METAL THIN FILMS - Processes are provided for selectively depositing thin films comprising one or more noble metals on a substrate by vapor deposition processes. In some embodiments, atomic layer deposition (ALD) processes are used to deposit a noble metal containing thin film on a high-k material, metal, metal nitride or other conductive metal compound while avoiding deposition on a lower k insulator such as silicon oxide. The ability to deposit on a first surface, such as a high-k material, while avoiding deposition on a second surface, such as a silicon oxide or silicon nitride surface, may be utilized, for example, in the formation of a gate electrode.06-03-2010
20100330790TECHNIQUE FOR EXPOSING A PLACEHOLDER MATERIAL IN A REPLACEMENT GATE APPROACH BY MODIFYING A REMOVAL RATE OF STRESSED DIELECTRIC OVERLAYERS - In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.12-30-2010
20130089975METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device having a MOS transistor, includes forming a gate electrode material layer on a first insulating film formed on a semiconductor substrate, forming an etching mask on the gate electrode material layer, forming a gate electrode by patterning the gate electrode material layer such that a protective film that protects at least a lower portion of a side face of the gate electrode and a portion of the first insulating film, which is adjacent to the side face, is formed while the gate electrode material layer is patterned, forming a second insulating film on the semiconductor substrate on which the gate electrode is formed, and forming an interlayer insulation film on the second insulating film.04-11-2013
20090253255Semiconductor device having a pair of fins and method of manufacturing the same - Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.10-08-2009
20090233429SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SUBSTRATE PROCESSING APPARATUS - Nitrogen supplied into the high dielectric constant film is prevented from leaving from the film.09-17-2009
20100062591N2 BASED PLASMA TREATMENT AND ASH FOR HK METAL GATE PROTECTION - The present disclosure provides a method for making a semiconductor device. The method includes forming a first material layer on substrate; forming a patterned photoresist layer on the first material layer; applying an etching process to the first material layer using the patterned photoresist layer as a mask; and applying a nitrogen-containing plasma to the substrate to remove the patterned photoresist layer.03-11-2010
20090047776Method of Forming a Thin Film Transistor - A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.02-19-2009
20100087055METHOD FOR GATE HEIGHT CONTROL IN A GATE LAST PROCESS - Provided is a method that includes forming first and second gate structures in first and second regions, respectively, the first gate structure including a first hard mask layer having a first thickness and the second gate structure including a second hard mask layer having a second thickness less than the first thickness, removing the second hard mask layer from the second gate structure, forming an inter-layer dielectric (ILD) over the first and second gate structures, performing a first chemical mechanical polishing (CMP), remove the silicon layer from the second gate structure thereby forming a first trench, forming a first metal layer to fill the first trench, performing a second CMP, remove the remaining portion of the first hard mask layer and the silicon layer from the first gate structure thereby forming a second trench, forming a second metal layer to fill the second trench, and performing a third CMP.04-08-2010
20100087056METHOD FOR GATE HEIGHT CONTROL IN A GATE LAST PROCESS - A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate, forming a transistor in the substrate, the transistor having a gate structure that includes a dummy gate structure, forming an inter-layer dielectric (ILD), performing a first chemical mechanical polishing (CMP) to expose a top surface of the dummy gate structure, removing a portion of the ILD such that a top surface of the ILD is at a distance below the top surface of the dummy gate structure, forming a material layer over the ILD and dummy gate structure, performing a second CMP on the material layer to expose the top surface of the dummy gate structure, removing the dummy gate structure thereby forming a trench, forming a metal layer to fill in the trench, and performing a third CMP that substantially stops at the top surface of the ILD.04-08-2010
20100210096PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - It is intended to provide a method of producing a semiconductor device, comprising the steps of: providing a substrate on one side of which at least one semiconductor pillar stands; forming a first dielectric film to at least partially cover a surface of the at least one semiconductor pillar; forming a conductive film on the first dielectric film; removing by etching a portion of the conductive film located on a top surface and along an upper portion of a side surface of the semiconductor pillar; forming a protective film on at least a part of the top surface and the upper portion of the side surface of the semiconductor pillar; etching back the protective film to form a protective film-based sidewall on respective top surfaces of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar; forming a resist pattern for forming a gate line in such a manner that at least a portion of the resist pattern is formed on the top surface of the semiconductor pillar by applying a resist and using lithography; and partially removing by etching the conductive film using the resist pattern as a mask while protecting, by the protective film-based sidewall, the portions of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar, to form a gate electrode and a gate line extending from the gate electrode.08-19-2010
20110281425METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a photoresist pattern on an insulating film formed on a semiconductor substrate by applying a photoresist on the insulating film; processing the insulating film by removing an unnecessary portion of the insulating film by wet etching; and implanting ions into the insulating film before and/or after forming the photoresist pattern. In implanting the ions, the depth of a damaged region formed in the insulating film by implanting the ions is changed in accordance with the presence or absence of the photoresist pattern.11-17-2011
20110300698METHODS FOR FORMING A GATE AND A SHALLOW TRENCH ISOLATION REGION AND FOR PLANARIZING AN ETCHED SURFACE OF SILICON SUBSTRATE - A method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, includes the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. The present invention further provides a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region, and a method for planarizing an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.12-08-2011
20120108046Patterning Methodology for Uniformity Control - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.05-03-2012
20090117723Methods of forming a conductive pattern in semiconductor devices and methods of manufacturing semiconductor devices having a conductive pattern - In a method of forming a conductive pattern in a semiconductor device, a conductive layer including a metal is formed on a substrate. A mask including carbon is provided on the conductive layer, and the conductive pattern is formed on the substrate by etching the conductive layer using the mask as an etching mask. The mask is removed from the conductive pattern by an oxygen plasma ashing process. An oxidized portion of the conductive pattern is reduced. The conductive pattern may have a desired resistance by reducing the oxidized portion to improve electrical characteristics and reliability of the semiconductor device.05-07-2009
20110294285PHOTO KEY AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE PHOTO KEY - A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from one another. Each of the photo key regions includes a plurality of first conductive patterns spaced apart from one another; and a plurality of second conductive patterns interposed between the first conductive patterns.12-01-2011
20100136775METHOD OF MANUFACTURING THIN-FILM TRANSISTOR SUBSTRATE - Provided is a method for manufacturing a thin-film transistor substrate, in which the etching characteristics of an insulating film and a passivation layer are enhanced. The insulating film and the passivation layer are deposited by low temperature chemical vapor deposition. The method includes disposing a gate wiring on an insulating substrate; disposing a gate insulating film on the gate wiring; disposing a data wiring on the gate insulating film; disposing a passivation layer on the data wiring; and forming a contact hole by etching at least one of the gate insulating film and the passivation layer, wherein at least one of the gate insulating film and the passivation layer is disposed at a temperature of about 280° C. or below, and the forming of the contact hole is performed at a pressure of about 60 mT or below.06-03-2010
20100136777FLEXIBLE SUBSTRATE WITH ELECTRONIC DEVICES FORMED THEREON - A method of manufacturing an electronic device (06-03-2010
20100112796PATTERNING METHOD - Disclosed is a patterning method including: forming, on a thin film, a sacrificial film made of a material different from that of the thin film and made of SiBN; processing the sacrificial film into a pattern having a preset interval by using a photolithography technique; forming, on sidewalls of the processed sacrificial film, sidewall spacers made of a material different from those of the sacrificial film and the thin film; removing the processed sacrificial film; and processing the thin film by using the sidewall spacers as a mask.05-06-2010
20090149009SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material using an electrochemical etch to form a first cavity, a second cavity, wherein the first cavity is isolated from the second cavity, a first protrusion is between the first cavity and the second cavity, and the semiconductor material comprises silicon. The method further includes performing a thermal oxidation to convert a portion of the silicon of the semiconductor material to silicon dioxide and forming a first dielectric material over the first cavity, over the second cavity, over at least a portion of the semiconductor material, and over at least a portion of the first protrusion. Other embodiments are described and claimed.06-11-2009
20090087972FORMATION OF CARBON AND SEMICONDUCTOR NANOMATERIALS USING MOLECULAR ASSEMBLIES - The invention is directed to a method of forming carbon nanomaterials or semiconductor nanomaterials. The method comprises providing a substrate and attaching a molecular precursor to the substrate. The molecular precursor includes a surface binding group for attachment to the substrate and a binding group for attachment of metal-containing species. The metal-containing, species is selected from a metal cation, metal compound, or metal or metal-oxide nanoparticle to form a metallized molecular precursor. The metallized molecular precursor is then subjected to a heat treatment to provide a catalytic site from which the carbon nanomaterials or semiconductor nanomaterials form. The heating of the metallized molecular precursor is conducted under conditions suitable for chemical vapor deposition of the carbon nanomaterials or semiconductor nanomaterials.04-02-2009
20120142176Methods of Forming Semiconductor Devices - Methods of forming semiconductor devices are provided. The methods may include forming a gate pattern on an active region of a substrate. The methods may further include performing a deoxidization treatment on the substrate.06-07-2012
20090258482METHOD FOR FABRICATING A METAL GATE STRUCTURE - A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the first gate is located on the active region and the second gate at least partially overlaps with the isolation region; forming an inter-layer dielectric material covering the gates; planarizing the inter-layer dielectric material until exposing the gates and forming an inter layer-dielectric layer; performing an etching process to remove the gates to form a first recess and a second recess within the inter-layer dielectric layer; forming a gate dielectric material on a surface of each of the recesses; forming at least a metal material within the recesses; and performing a planarization process.10-15-2009
20120295432METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes forming an interlayer insulating layer over the semiconductor substrate of a cell region, and forming gate structures over the semiconductor substrate of a peripheral region. Reserved bit line regions are formed in the cell region by etching the interlayer insulating layer, and gates are formed by etching the gate structures in the peripheral region. A capping insulating layer and an isolation layer are formed over the reserved bit line regions and the gates, the isolation layer of the cell region is removed, and an etch-back process is performed on the capping insulating layer, and bit lines are formed in the respective reserved bit line regions. Semiconductor device yields can be enhanced because patterns having a fine critical dimension can be formed in peripheral regions with an increased degree of integration.11-22-2012
20120295431METHOD FOR ETCHING GATE STACK - A method for etching a metal gate stack is provided. The method includes forming a gate stack on a substrate, where the gate stack includes a metal gate. A wet etch process is performed on the gate stack. The wet etch process includes submersing the substrate with the gate stack in an aqueous solution composed of a wet etchant and an oxidizer, removing the substrate from the solution and rinsing the solution from the etched gate stack.11-22-2012
20100124815METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device according to an embodiment of the present invention forms at least one pair of gate electrodes having end portions opposed to each other across a gap. The method includes forming a gate insulator and a gate electrode layer on a substrate in order, forming a first anti-reflection coating and a first resist on the gate electrode layer in order, exposing and developing the first resist, etching the gate electrode layer, using the first resist or the first anti-reflection coating as a mask, to remove the gate electrode layer from a region for forming the gap, thereby forming a hole penetrating the gate electrode layer, forming a second anti-reflection coating and a second resist on the gate electrode layer where the hole has been formed, in order, exposing and developing the second resist, and etching the gate electrode layer, using the second resist or the second anti-reflection coating as a mask, to form, from the gate electrode layer, the at least one pair of gate electrodes having the end portions opposed to each other across the gap.05-20-2010
20090286385METHODS FOR REMOVING A PHOTORESIST FROM A METAL-COMPRISING MATERIAL - Methods for removing a photoresist from a metal-comprising material are provided. In accordance with an exemplary embodiment of the present invention, the method comprises applying to the photoresist a substantially non-aqueous-based solvent having a pH no less than about 9 or no pH and subsequently applying to the metal-comprising material an aqueous-based fluid having a pH no less than about 9.11-19-2009
20090291550POLY GATE ETCH METHOD AND DEVICE FOR SONOS-BASED FLASH MEMORY - A method for forming flash memory devices is provided. The method includes providing a semiconductor substrate, which comprises a silicon material and has a periphery region and a cell region. The method further includes forming an isolation structure between the cell region and the periphery region. Additionally, the method includes forming an ONO layer overlying the cell region and the periphery region. Furthermore, the method includes removing the ONO layer overlying the periphery region to expose silicon material in the periphery region. The method also includes forming a gate dielectric layer overlying the periphery region, while protecting the ONO layer in the cell region. In addition, the method includes forming a polysilicon layer overlying the cell region and the periphery region.11-26-2009
20120295433ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS - Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.11-22-2012
20090170300SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF - The object of the present invention is to provide a method of manufacturing high permittivity gate dielectrics for a device such as an MOSFET. A HfSiO film 07-02-2009
20080242069HYBRID SOI/BULK SEMICONDUCTOR TRANSISTORS - Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.10-02-2008
20080233725Methods for stressing semiconductor material structures to improve electron and/or hole mobility of transistor channels fabricated therefrom, and semiconductor devices including such structures - Semiconductor material strips are secured to substrates in such a way as to stress the semiconductor material. The strips of semiconductor material may be compressively stressed, subjected to tensile stress, or some strips may be compressively stressed while other strips are tensilely stressed. Stress may be induced by forming non-planarities on the surface of the substrate to which the strips are to be secured. The non-planarities may be configured to stress strips of semiconductor material as the strips are secured thereover and over an intervening surface of the substrate, or to stress strips as the non-planarities are removed from beneath the strips. The strain that ultimately results from stressing the strips improves carrier mobility (i.e., electron mobility, electron hole pair, or “hole,” mobility) relative to the carrier mobilities of unstrained semiconductor materials. The strained strips of semiconductor material may be used in the fabrication of semiconductor device structures such as transistors.09-25-2008
20080274605METHOD OF MANUFACTURING SILICON NITRIDE FILM, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method of manufacturing a silicon nitride film that forms a silicon nitride film on a surface of a substrate comprises sequentially repeating first through third steps. The first step includes feeding a first gas containing silicon and nitrogen to the surface of the substrate. The second step includes feeding a second gas containing nitrogen to the surface of the substrate. The third step includes feeding a third gas containing hydrogen to the surface of the substrate.11-06-2008
20080293227METHOD FOR FORMING GATE ELECTRODE OF SEMICONDUCTOR DEVICE - Provided is a method for forming a gate electrode of a semiconductor device which can form a gate electrode having a fine line width. Disclosed method steps include forming a gate oxide film, a polysilicon film for a gate electrode, and a first sacrificial layer on the entire surface of a semiconductor substrate and then forming an opening within the first sacrificial layer. The effective width of the hole is reduced, and an ion implantation layer is formed on the top surface of the polysilicon film in the region exposed through the hole. A gate electrode is formed under the ion implantation layer by using the ion implantation layer as a mask.11-27-2008
20080293226Semiconductor device and manufacturing method therefor - A method of manufacturing a semiconductor device comprises forming a gate insulation film on a semiconductor substrate; forming a first gate electrode and a second gate electrode on the gate insulation film; forming a mask material so as to expose an upper surface of the first gate electrode while keeping the second gate electrode covered; etching an upper part of the first gate electrode by using the mask material as a mask; removing the mask material; depositing a metal film on the first gate electrode and the second gate electrode; and siliciding the whole of the first gate electrode and an upper part of the second gate electrode.11-27-2008
20080305621CHANNEL STRAIN ENGINEERING IN FIELD-EFFECT-TRANSISTOR - There is disclosed a method of applying stress to a channel region underneath a gate of a field-effect-transistor, which includes the gate, a source region, and a drain region. The method includes steps of embedding stressors in the source and drain regions of the FET; forming a stress liner covering the gate and the source and drain regions; removing a portion of the stress liner, the portion of the stress liner being located on top of the gate of the FET; removing at least a substantial portion of the gate of a first gate material and thus creating an opening therein; and filling the opening with a second gate material.12-11-2008
20100279496MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To improve productivity and performance of a CMISFET including a high-dielectric-constant gate insulating film and a metal gate electrode. An Hf-containing insulating film for a gate insulating film is formed over the main surface of a semiconductor substrate. A metal nitride film is formed on the insulating film. The metal nitride film in an nMIS formation region where an n-channel MISFET is to be formed is selectively removed by wet etching using a photoresist pattern on the metal nitride films a mask. Then, a threshold adjustment film containing a rare-earth element is formed. The Hf-containing insulating film in the nMIS formation region reacts with the threshold adjustment film by heat treatment. The Hf-containing insulating film in a pMIS formation region where a p-channel MISFET is to be formed does not react with the threshold adjustment film because of the existence of the metal nitride film. Then, after removing the unreacted threshold adjustment film and the metal nitride film, metal gate electrodes are formed in the nMIS formation region and the pMIS formation region.11-04-2010
20110207311Method of Manufacturing Semiconductor Device - A method of manufacturing a semiconductor device may include sequentially forming a tunnel insulating layer, a first conductive layer, a dielectric layer, and a second conductive layer over a semiconductor substrate, forming hard mask patterns on the second conductive layer, forming a passivation layer on surfaces of the hard mask patterns, and etching the second conductive layer, the dielectric layer, and the first conductive layer using the hard mask patterns and the passivation layer as an etch mask.08-25-2011
20090191697METHOD FOR MANUFACTURING A NONVOLATILE MEMORY DEVICE - In a method for manufacturing a nonvolatile memory device, an etch mask layer formed on a dielectric layer to define contact holes in the dielectric layer is slope-etched to form an etch mask pattern having an opening wider at the upper end thereof than the lower end thereof. Thus, the contact holes are defined in the dielectric layer to have a finer size than the upper end of the opening of the etch mask pattern. The method for manufacturing a nonvolatile memory device includes forming an etch mask pattern on a dielectric layer such that a width of a lower end of each opening defined in the etch mask pattern is less than a width of an upper end thereof; and defining contact holes by removing portions of the dielectric layer using the etch mask pattern.07-30-2009
20120142178SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.06-07-2012
20090181528Method of Forming Gate Electrode - The present invention discloses to a method of forming a gate electrode, the method according to the present invention comprises the steps of forming a lower amorphous silicon layer using silane (SiH07-16-2009
20090163007METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device is manufactured suppressing generation of “vacancy-oxygen complex defects”. A general etching treatment is done using a general plasma gas including HBr, Cl06-25-2009
20090163006METHOD FOR FABRICATING VERTICAL CHANNEL TRANSISTOR - A method for fabricating a vertical channel transistor includes forming a structure including a plurality of trimmed pillar patterns, forming a conductive layer for a gate electrode including a seam over a resultant structure with the pillar patterns, performing an etch-back process until the seam is exposed, and forming a gate electrode by etching the etch-backed conductive layer.06-25-2009
20120070974MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device manufacture method includes: forming a first film above a semiconductor substrate; forming a first mask film above the first film; patterning the first mask film; executing a plasma process for a side wall of the patterned first mask film to transform the side wall into a transformed layer; after the plasma process, forming a second mask film covering the first mask film; etching the second mask film to remove the second mask film above the first mask film and leave the second mask film formed on the side wall; after the etching the second mask film, removing the transformed layer; and after the removing the transformed layer, etching the first film by using the first mask film and the second mask film as mask.03-22-2012
20110223754Integration Scheme for Dual Work Function Metal Gates - A transistor includes a semiconductor substrate includes having a gate hardmask over the gate electrode layer during the formation of transistor source/drain regions. An independent work function adjustment process implants Group Ma series dopants into a gate polysilicon layer of a PMOS transistor and implants lanthanide series dopants into a gate polysilicon layer of a NMOS transistor.09-15-2011
20090186472METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method including: forming a first region and a second region in a semiconductor substrate by forming an element isolation region; forming an insulating film on the semiconductor substrate in the first region and the second region; forming a first metal film on the insulating film in the first region and in the second region; removing the first metal film in the second region; forming a second metal film on the first metal film in the first region and on the insulating film in the second region; and flattening top surfaces in the first region and the second region by performing a flattening process.07-23-2009
20110223755METHOD FOR REMOVING OXIDES - A method for removing native oxides from a substrate surface is provided. In one embodiment, the method comprises positioning a substrate having an oxide layer into a processing chamber, generating a plasma of a reactive species from a gas mixture within the processing chamber, exposing the substrate to the reactive species while forming a volatile film on the substrate and maintaining the substrate at a temperature below 65° C., heating the substrate to a temperature of at least about 75° C. to vaporize the volatile film and remove the oxide layer, and depositing a first layer on the substrate after heating the substrate.09-15-2011
20110223752METHOD FOR FABRICATING A GATE STRUCTURE - The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode.09-15-2011
20090325370Field-effect transistor structure and fabrication method thereof - A field-effect transistor (FET) structure is provided. The FET structure includes a gate substrate, a dielectric layer, conductive electrodes, and a carbon nanotube (CNT). The gate substrate is made of a conductive material. The dielectric layer is disposed on the substrate. The conductive electrodes are disposed on the dielectric layer, and contain nickel and chromium. The CNT is disposed on the dielectric layer and electrically connects two conductive electrodes12-31-2009
20090325369Semiconductor device and method of fabricating the same - A method of fabricating a semiconductor device includes forming a gate dielectric on a substrate, forming a gate structure on the gate dielectric, the gate structure comprising a stacked layer of a silicon layer and a metal layer, selectively etching the gate structure to form a gate pattern, forming a capping layer surrounding the gate pattern, plasma-treating the capping layer, and performing a gate reoxidation process12-31-2009
20090209095Manufacturing Method for Semiconductor Devices and Substrate Processing Apparatus - The throughput in the overall gate stack forming process is improved. When using a cluster apparatus to perform a gate stack forming process including a high dielectric film forming step, a plasma nitriding step, an annealing step and a gate electrode forming step, the final ongoing gate electrode forming step is stopped in the middle, and the remainder of the gate electrode forming step is performed on multiple wafers as batch processing. This shortens the standby time for consecutive steps in the cluster apparatus to improve the throughput in the overall gate stack forming process.08-20-2009
20110223753Hard Mask Removal for Semiconductor Devices - A method of removing a hard mask during fabrication of semiconductor devices is provided. A protective layer, such as a bottom anti-reflective coating (BARC) layer or other dielectric layer, is formed over structures formed on a substrate, wherein spacers are formed alongside the structures. In an embodiment, the structures are gate electrodes having a hard mask formed thereon and the spacers are spacers formed alongside the gate electrodes. A photoresist layer is formed over the protective layer, and the photoresist layer may be patterned to remove a portion of the photoresist layer over portions of the protective layer. Thereafter, an etch-back process is performed, such that the protective layer adjacent to the spacers remains to substantially protect the spacers. The hard mask is then removed while the protective layer protects the spacers.09-15-2011
20100248463ENHANCING ADHESION OF INTERLAYER DIELECTRIC MATERIALS OF SEMICONDUCTOR DEVICES BY SUPPRESSING SILICIDE FORMATION AT THE SUBSTRATE EDGE - Adhesion of dielectric layer stacks to be formed after completing the basic configuration of transistor elements may be increased by avoiding the formation of a metal silicide in the edge region of the substrate. For this purpose, a dielectric protection layer may be selectively formed in the edge region prior to a corresponding pre-clean process or immediately prior to deposition of the refractory metal. Hence, non-reacted metal may be efficiently removed from the edge region without creating a non-desired metal silicide. Hence, the further processing may be continued on the basis of enhanced process conditions for forming interlayer dielectric materials.09-30-2010
20090075464Semiconductor device and manufacturing method thereof - A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.03-19-2009
20090017607GATE CD TRIMMING BEYOND PHOTOLITHOGRAPHY - A semiconductor device is fabricated with a selected critical dimension. A gate dielectric layer is formed over a semiconductor body. A gate layer comprised of a conductive material, such as polysilicon, is formed over the gate dielectric layer. The gate layer is patterned to form a gate electrode having a first horizontal dimension. One or more growth-stripping operations are performed to reduce a critical dimension of the gate electrode to a second horizontal dimension, where the second horizontal dimension is less than the first horizontal dimension.01-15-2009
20090203202Strained Gate Electrodes in Semiconductor Devices - Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an NMOS device and a PMOS device after having converted a portion of the intermediate NMOS gate electrode layer to an amorphous layer and then recrystallizing it before patterning to form the electrode. The average grain size in the NMOS recrystallized gate electrode is smaller than that in the PMOS recrystallized gate electrode. In another embodiment, the NMOS device comprises an amorphous gate electrode.08-13-2009
20090203201METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a dielectric film containing a porogen material above a substrate; removing a portion of the porogen material contained in the dielectric film so as to make a concentration of the porogen material higher in a part on a lower side of the dielectric film than in another part on a higher side of the dielectric film; forming an opening halfway in the dielectric film from which a portion of the porogen material has been removed to leave the dielectric film below a bottom of the opening; removing or polymerizing a remainder of the porogen material contained in the dielectric film; and etching the bottom of the opening after removing or polymerizing the remainder of the porogen material.08-13-2009
20090239364METHOD FOR FORMING INSULATING FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a method for forming a gate insulating film comprising an oxidation step wherein a silicon oxide film is formed by having an oxygen-containing plasma act on silicon in the surface of an object to be processed in a processing chamber of a plasma processing apparatus. The processing temperature in the oxidation step is more than 600° C. and not more than 1000° C., and the oxygen-containing plasma is formed by introducing an oxygen-containing processing gas containing at least a rare gas and an oxygen gas into the process chamber while introducing a high frequency wave or microwave into the process chamber through an antenna.09-24-2009
20090221137SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A silicon substrate having a first silicon oxide film formed via thermal oxidation and a second silicon oxide film formed via chemical vapor deposition and the like is subjected to preprocessing prior to selective epitaxial growth, wherein both the first and second silicon oxide films are etched with the same etching rate so as to completely remove the first silicon oxide film. Thus, it is possible to precisely control the sizes of contact holes formed in the silicon substrate, thus preventing contact plugs from short-circuiting with silicon epitaxial layers.09-03-2009
20090215254Design support system,computer readable medium, semiconductor device designing method and semiconductor device manufacturing method - A design support system which supports designing a semiconductor device is provided. The design support system includes a gate film information acquisition section and a maximum allowable antenna ratio setting section. The gate film information acquisition section acquires information on the thickness of the gate insulating film of a semiconductor device which has been designed. The gate insulating film thickness refers to a physical film thickness. The maximum allowable antenna ratio setting section sets maximum allowable antenna ratios for a gate electrode according to the film thickness information acquired by the gate film information acquisition section. Hence, a designer designing a semiconductor device can set concrete values when changing maximum allowable antenna ratios according to the thickness of the gate insulating film.08-27-2009
20090253254METHOD OF FABRICATING SEMICONDUCTOR DEVICE - In a method of fabricating a semiconductor device having vertical channels and a method of patterning a gate electrode of such semiconductor device, an initial conductive layer is removed by multiple etching processes.10-08-2009
20120142177METHODS OF MANUFACTURING A WIRING STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a wiring structure and a semiconductor device, the method of manufacturing a wiring structure including forming a first insulating interlayer on a substrate; forming a contact plug in an opening in the first insulating interlayer; forming a second insulating interlayer on the contact plug and the first insulating interlayer; removing a portion of the second insulating interlayer to form an opening therethrough such that the opening exposes the contact plug; filling a portion of the opening to form a wiring such that the wiring is electrically connected to the contact plug; and forming a diffusion barrier layer pattern on the wiring such that the diffusion barrier layer pattern fills a remaining portion of the opening.06-07-2012
20100159683Method for Fabricating Semiconductor Device Having Recess Channel - A method for fabricating a semiconductor device having a recess channel includes forming an isolation layer that delimits an active region over a semiconductor substrate; exposing a region to be formed with a bulb recess trench over the semiconductor substrate; forming an upper trench by etching the exposed portion of the semiconductor substrate; forming, on a side wall of the upper trench, a silicon nitride barrier layer that exposes a bottom face of the upper trench but blocks a side wall of the upper trench; forming a lower trench of a bulb type by etching the exposed bottom face of the upper trench using the etch barrier layer as an etch mask, to form the bulb recess trench including the upper trench and the lower trench; forming a fin-structured bottom protrusion part including an upper face and a side face by etching the isolation layer so that the isolation layer has a surface lower than the bottom face of the lower trench; and forming a gate stack overlapped with the bulb recess trench and the bottom protrusion part.06-24-2010
20080254606Method of Manufacturing Semiconductor Device - Provided is a method of manufacturing a semiconductor device in which properties of photoresist through a lithography process are changed to form a dummy structure, and the structure is applied to a process of forming a gate electrode. The method includes the steps of: forming a buffer layer on the top of a semiconductor substrate; applying an inorganic photoresist on the buffer layer, and forming a photoresist pattern using a lithography process; thermally treating the photoresist pattern using a predetermined gas; uniformly depositing an insulating layer on the thermally treated structure, and etching the deposited layer by the deposited thickness in order to expose the thermally treated photoresist pattern; depositing an insulating layer on the etched structure, and etching the deposited insulating layer to expose the thermally treated photoresist pattern; removing the exposed photoresist pattern using an etching process; forming a gate oxide layer in the portion in which the photoresist pattern is removed; and forming a gate electrode on the gate oxide layer. Accordingly, in forming a structure for manufacturing a nano-sized device, the properties of the layer formed by a lithography process are improved through thermal treatment, and thus the structure used to manufacture various devices can be easily formed.10-16-2008
20100240204METHODS FOR FORMING METAL GATE TRANSISTORS - A method for cleaning a diffusion barrier over a gate dielectric of a metal-gate transistor over a substrate is provided. The method includes cleaning the diffusion barrier with a first solution including at least one surfactant. The amount of the surfactant of the first solution is about a critical micelle concentration (CMC) or more. The diffusion barrier is cleaned with a second solution. The second solution has a physical force to remove particles over the diffusion barrier. The second solution is substantially free from interacting with the diffusion barrier.09-23-2010
20100227459METHOD FOR FORMING W-BASED FILM, METHOD FOR FORMING GATE ELECTRODE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a method for forming a W-based film including a step for placing a substrate in a processing chamber, a step for forming a WSi film by alternately repeating disposition of W through introduction of a W(CO)09-09-2010
20130217217PATTERN FORMING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND COATING APPARATUS - According to one embodiment, a pattern forming method is disclosed. A resist pattern having a top surface is formed pattern on a substrate. A coating film having a first thickness distribution is formed on the substrate. The coating film covers the resist pattern. The coating film is thinned to expose the top surface of the resist pattern. The first thickness distribution is changed into a second thickness distribution which is more uniform than the first thickness distribution. The resist pattern is removed without removing the coating film. A pattern is formed in the substrate by processing the substrate by using the coating film as a mask.08-22-2013
20090149010STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI MOS DEVICES BY GATE STRESS ENGINEERING WITH SiGe AND/OR Si:C - Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi (strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.06-11-2009
20090291552SUBSTRATE HAVING FILM PATTERN AND MANUFACTURING METHOD OF THE SAME, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, LIQUID CRYSTAL TELEVISION, AND EL TELEVISION - The invention provides a manufacturing method of a substrate having a film pattern including an insulating film, a semiconductor film, a conductive film and the like by simple steps, and also a manufacturing method of a semiconductor device which is low in cost with high throughput and yield. According to the invention, after forming a first protective film which has low wettability on a substrate, a material which has high wettability is applied or discharged on an outer edge of a first mask pattern, thereby a film pattern and a substrate having the film pattern are formed.11-26-2009
20090291551METHOD FOR FORMING VERTICAL CHANNEL TRANSISTOR OF SEMICONDUCTOR DEVICE - A method for forming a vertical channel transistor in a semiconductor device includes providing a substrate, forming pillar patterns extending perpendicular from the upper surface of the substrate, forming a spin on carbon (SOC) layer in a gap region between the pillar patterns, forming photoresist patterns above a resultant structure where the SOC layer is filled to expose a region for an isolation trench, etching the SOC layer between the photoresist pattern barriers to expose the region for the isolation trench, and etching the exposed structure to a certain depth forming the isolation trench.11-26-2009
20100099245Methods of Forming Semiconductor Devices - Provided are a semiconductor device and a method of forming the same. The method may include forming a metal oxide layer on a substrate and forming a sacrificial oxide layer on the metal oxide layer. An annealing process is performed on the substrate. A formation-free energy of the sacrificial oxide layer is greater than a formation-free energy of the metal oxide layer at a process temperature of the annealing process.04-22-2010
20120196431INSULATING FILM AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - It is made possible to provide an insulating film that can reduce the leakage current. An insulating film includes: an amorphous oxide dielectric film containing a metal, hydrogen, and nitrogen. The nitrogen amount [N] and the hydrogen amount [H] in the oxide dielectric film satisfy the following relationship: {[N]—[H]}/2≦1.0×1008-02-2012
20100035424Semiconductor Device and Fabrication Method Thereof - A hydrogenation method that utilizes plasma directly exposes a crystalline semiconductor film to the plasma, and therefore involves the problem that the crystalline semiconductor film is damaged by the ions generated simultaneously in the plasma. If a substrate is heated to 400° C. or above to recover this damage, hydrogen is re-emitted from the crystalline semiconductor film.02-11-2010
20100317180Method of Doping P-type Impurity Ions in Dual Poly Gate and Method of Forming Dual Poly Gate Using the Same - A method of doping p-type impurity ions in a dual poly gate, comprising: forming a polysilicon layer doped with n-type impurity ions on a substrate with a gate insulation layer being interposed between the polysilicon layer and the substrate; exposing a region of the polysilicon layer; implementing a first doping of p-type impurity ions into the exposed region of the polysilicon layer by ion implantation so with a projection range Rp to a predetermined depth of the polysilicon layer; and implementing a second doping of p-type impurity ions into the exposed region of the polysilicon layer doped with the p-type impurity ions by plasma doping with a sloped doping profile.12-16-2010
20090068826METHOD OF FABRICATING SEMICONDUCTOR DEVICE - The present invention includes the steps of: forming an device isolation region in a substrate to divide the device isolation region into a first and a second diffusion regions; forming a target film to be processed on the substrate; forming a hard mask layer and a first resist layer on the film to be processed; forming a first pattern on the first resist layer; etching the hard mask layer by using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer for isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer.03-12-2009
20110034015HEAT TREATMENT APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a heat treatment apparatus includes a light emitting unit to emit light to irradiate a wafer, a processing unit with a stage section and a control unit. The control unit implements a first irradiation to irradiate the light onto the wafer. After the first irradiation, the control unit changes at least one selected from a disposition of the wafer, a distribution of an intensity of the light on a major surface of the stage section along a circumferential edge direction of the wafer, and a distribution of a temperature of the wafer in a supplemental heating by the stage section along a circumferential edge direction of the wafer. After the changing, the control unit implements a second irradiation to irradiate the light onto the wafer. Durations of the first irradiation and the second irradiation are shorter than a time necessary for the changing.02-10-2011
20110053361FinFET Formation with a Thermal Oxide Spacer Hard Mask Formed from Crystalline Silicon Layer - A semiconductor process and apparatus provide a FinFET device by forming a second single crystal semiconductor layer (03-03-2011
20110244672METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including forming a mask layer on a polycrystalline silicon film formed on a semiconductor substrate via an insulating film; forming a dense pattern and a sparse pattern on the mask layer to form a mask; etching the polycrystalline silicon film with the mask by controlling a temperature of the semiconductor substrate placed in an etching chamber at 50 degrees Celsius or higher, supplying an etching gas composed of a hydrogen bromide containing gas and a fluoromethane based gas into the chamber, and generating plasma in the chamber.10-06-2011
20110244670Replacement Gate Approach for High-K Metal Gate Stacks by Avoiding a Polishing Process for Exposing the Placeholder Material - In a replacement gate approach, the exposure of the placeholder material of the gate electrode structures may be accomplished on the basis of an etch process, thereby avoiding the introduction of process-related non-uniformities, which are typically associated with a complex polishing process for exposing the top surface of the placeholder material. In some illustrative embodiments, the placeholder material may be exposed by an etch process based on a sacrificial mask material.10-06-2011
20120034770LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A liquid crystal display device includes a plurality of gate lines and data lines crossing each other to define a plurality of pixel regions, a plurality of thin film transistors, each disposed in one of the pixel regions, and a plurality of pixel electrodes, each disposed in one of the pixel regions, wherein the thin film transistor includes at least one Ti layer.02-09-2012
20110086502METHOD FOR FABRICATING A GATE STRUCTURE - An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.04-14-2011
20110129991Methods Of Patterning Materials, And Methods Of Forming Memory Cells - Some embodiments include methods of patterning materials. A mass may be formed over a material, and a first mask may be formed over the mass. First spacers may be formed along features of the first mask, and then the first mask may be removed to leave a second mask corresponding to the first spacers. A pattern of the second mask may be partially transferred into the mass to form an upper portion of the mass into a third mask. The first spacers may be removed from over the third mask, and then second spacers be formed along features of the third mask. The second spacers are a fourth mask. A pattern of the fourth mask may be transferred into a bottom portion of the mass, and then the bottom portion may be used as a mask during processing of the underlying material.06-02-2011
20110244671Method for Fabricating a III-Nitride Semiconductor Device - A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.10-06-2011
20090311854METHOD FOR FORMING GATE OF SEMICONDUCTOR DEVICE - A method for forming a triple gate of a semiconductor device is provided. The method includes: forming a buffer layer and a hard mask over a substrate; etching the hard mask and the buffer layer to form a hard mask pattern and a buffer pattern; forming first and second trenches spaced apart within the substrate by partially etching the substrate by a vapor etching process using the hard mask pattern as an etching barrier layer; forming a buried insulation layer to fill the first and second trenches; removing the hard mask pattern and the buffer pattern; forming a gate insulation layer over the substrate between the first trench and the second trench; forming a conductive layer to cover the gate insulation layer; and etching the conductive layer to form a gate electrode.12-17-2009
20090035927METHOD OF FORMING DIELECTRIC LAYERS ON A SUBSTRATE AND APPARATUS THEREFOR - Methods of forming dielectric layers on a substrate comprising silicon and oxygen are disclosed herein. In some embodiments, a method of forming a dielectric layer on a substrate includes provide a substrate having an exposed silicon oxide layer; treating an upper surface of the silicon oxide layer with a plasma; and depositing a silicon nitride layer on the treated silicon oxide layer via atomic layer deposition. The silicon nitride layer may be exposed to a plasma nitridation process. The silicon oxide and silicon nitride layers may be subsequently thermally annealed. The dielectric layers may be used as part of a gate structure.02-05-2009
20130157449METHOD FOR FORMING METAL GATE - A method for forming metal gates is provided. In the method, a substrate with a first region and a second region is provided. Dummy gate structures and an ILD layer is formed on the substrate. Dummy gates of the dummy gate structures are removed to form openings respectively within the two regions. Work function layers are respectively formed to overlay the openings. A metal layer is formed on the work function layers and then a CMP process is performed until the ILD layer is exposed, thereby forming the metal gates within the two regions at the same time. Only one CMP process is performed to the metal layer, so that over polishing of the ILD layer may be reduced and thickness of metal gates may be more accurately controlled.06-20-2013
20100055888Semiconductor device fabrication method - There is provided a semiconductor device fabrication method including: forming a gate electrode film on a substrate; forming an antireflection film on a surface at the opposite side of the gate electrode film to the substrate; forming a resist pattern on a surface at the opposite side of the antireflection film to the gate electrode film; irradiating plasma on the resist pattern by using an etching apparatus having an electrode for pulling-in ions within the plasma, by applying bias power to the electrode for pulling-in ions within the plasma such that an etching rate at the resist pattern becomes less than or equal to 100 Å/min to generate the plasma by using a gas that is non-reactive with the resist pattern; etching the antireflection film and the gate electrode by using, as a mask, the resist pattern; and removing the resist pattern and the antireflection film.03-04-2010
20090215253Method of Forming a Nitrogen-Enriched Region within Silicon-Oxide-Containing Masses - The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer. Source/drain regions are formed within the semiconductive substrate, and are gatedly connected to one another by the at least one conductive layer. The invention also encompasses transistor structures.08-27-2009
20110097883REDUCTION OF SHEET RESISTANCE OF PHOSPHORUS IMPLANTED POLY-SILICON - There is a process for reducing the sheet resistance of phosphorus-implanted poly-silicon. In an example embodiment, there is an MOS transistor structure. The structure has a gate region, drain region and a source region. A method for reducing the sheet resistance of the gate region comprises depositing intrinsic amorphous silicon at a predetermined temperature onto the gate region. An amorphizing species is implanted into the intrinsic amorphous silicon. Phosphorus species are then implanted into the gate region of the MOS transistor structure. A feature of this embodiment includes using Ar+ as the amorphizing species.04-28-2011
20100304555Semiconductor device and method of manufacturing semiconductor device - The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.12-02-2010
20110250743METHOD FOR PRODUCING A TRANSISTOR GATE WITH SUB-PHOTOLITHOGRAPHIC DIMENSIONS - Methods of fabricating compound semiconductor devices are described.10-13-2011
20110256700METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device capable of simplifying a fabrication process is provided. The method includes providing a substrate on which first and second regions are defined, forming an interlayer insulating film including first and second trenches on the substrate, the first and second trenches being formed in the first and second regions, respectively, forming a work function adjusting metal film on an upper surface of the interlayer insulating film, side and bottom surfaces of the first trench, and side and bottom surfaces of the second trench, forming a mask film on the interlayer insulating film to fill in the first and second trenches, the mask film including a developable material, forming a mask pattern by developing the mask film, the mask pattern exposing the work function adjusting metal film formed in the first region, removing the work function adjusting metal film formed in the first region by using the mask pattern, removing the mask pattern, and forming a first metal gate in the first trench and a second metal gate in the second trench.10-20-2011
20080305622METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming at least two gate insulating layers having different thickness on a substrate having low, medium and high voltage regions; and then depositing a gate layer material on the gate insulating layers; and then forming a first etch mask on the gate layer material; and then forming gate electrodes in the low, medium and high voltage regions by etching the gate layer material using the first etch mask; and then forming a second etch mask to expose a thickest one of the gate insulating layers, the gate electrode and the first etch mask each formed in the high voltage region while covering the remaining gate insulating layers, the gate electrodes and the first etch masks formed in the low and medium voltage regions; and then etching the thickest gate insulating layer using the second etch mask; and then removing the first and second etch masks. Thereby, the first etch mask used for forming the gates remains without being removed even after the gate is formed to perform a role of a barrier during etching the gate insulating layer.12-11-2008
20100297838INDEPENDENTLY ACCESSED DOUBLE-GATE AND TRI-GATE TRANSISTORS IN SAME PROCESS FLOW - A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device.11-25-2010
20110053364Method of manufacturing semiconductor device - A layer to be etched is first formed in a substrate. Then, a mask pattern is formed over the layer to be etched. Then, the layer to be etched is wet-etched using the mask pattern as a mask. In the procedure of performing wet etching, the substrate is dipped into an etching bath with the mask pattern downward.03-03-2011
20110053363SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a semiconductor substrate, and a memory cell and a peripheral circuit provided on the semiconductor substrate, the memory cell having a first insulating film, a first electrode layer, a second insulating film, and a second electrode layer provided on the semiconductor substrate in order, and the peripheral circuit having the first insulating film, the first electrode layer, the second insulating film having an opening for the peripheral circuit, and the second electrode layer electrically connected to the first electrode layer through the opening for the peripheral circuit, wherein a thickness of the first electrode layer under the second insulating film of the peripheral circuit is thicker than a thickness of the first electrode layer of the memory cell.03-03-2011
20110053362METHOD OF FORMING A MASK PATTERN, METHOD OF FORMING A MINUTE PATTERN, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - A method of forming a mask pattern, a method of forming a minute pattern, and a method of manufacturing a semiconductor device using the same, the method of forming the mask pattern including forming first mask patterns on a substrate; forming first preliminary capping layers on the first mask patterns; irradiating energy to the first preliminary capping patterns to form second preliminary capping layers ionically bonded with the first mask patterns; applying an acid to the second preliminary capping layers to form capping layers; forming a second mask layer between the capping layers, the second mask layer having a solubility lower than that of the capping layers; and removing the capping layers to form second mask patterns.03-03-2011
20110027978METHODS FOR FABRICATING NON-PLANAR SEMICONDUCTOR DEVICES HAVING STRESS MEMORY - Embodiments of a method are provided for fabricating a non-planar semiconductor device including a substrate having a plurality of raised crystalline structures formed thereon. In one embodiment, the method includes the steps of amorphorizing a portion of each raised crystalline structure included within the plurality of raised crystalline structures, forming a sacrificial strain layer over the plurality of raised crystalline structures to apply stress to the amorphized portion of each raised crystalline structure, annealing the non-planar semiconductor device to recrystallize the amorphized portion of each raised crystalline structure in a stress-memorized state, and removing the sacrificial strain layer.02-03-2011
20110076843LITHOGRAPHY PATTERNING METHOD - A method for fabricating an integrated circuit device is disclosed. The method is a lithography patterning method that can include providing a substrate; forming a protective layer over the substrate; forming a conductive layer over the protective layer; forming a resist layer over the conductive layer; and exposing and developing the resist layer.03-31-2011
20110003467METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes the following processes. A nitrogen-diffusion region is selectively formed in a semiconductor substrate having first and second regions. The nitrogen-diffusion region is at a shallow level of the first region. A first heat treatment is carried out to form a first oxide layer over the semiconductor substrate. The first oxide layer includes first and second portions. The first portion is in the first region. The second portion is in the second region. The first portion is thinner than the second portion.01-06-2011
20100330789Method of Forming Nonvolatile Memory Device - A method of forming the gate patterns of a nonvolatile memory device comprises stacking a gate insulating layer and a first conductive layer over a semiconductor substrate; forming isolation hard mask patterns over the first conductive layer; etching the first conductive layer using the isolation hard mask patterns as etch barriers, thus exposing the gate insulating layer; etching the gate insulating layer using the isolation hard mask patterns as etch barriers, thus exposing the semiconductor substrate; after exposing the semiconductor substrate, forming a passivation layer on the sidewalls of the first conductive layers and on the sidewalls of the gate insulating layers; and etching the semiconductor substrate using the passivation layer and the isolation hard mask patterns as etch barriers, thus forming trenches in the semiconductor substrate.12-30-2010
20090197403METHOD FOR FORMING INSULATING FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for forming an insulating film includes forming a silicon nitride film on a silicon surface by subjecting a target substrate wherein silicon is exposed in the surface to a treatment for nitriding the silicon, forming a silicon oxynitride film by heating the target substrate provided with the silicon nitride film in an N08-06-2009
20120309181PROCESS FOR DEPOSITING ELECTRODE WITH HIGH EFFECTIVE WORK FUNCTION - According to some embodiments, an electrode have a high effective work function is formed. The electrode may be the gate electrode of a transistor and may be formed on a high-k gate dielectric by depositing a first layer of conductive material, exposing that first layer to a hydrogen-containing gas, and depositing a second layer of conductive material over the first layer. The first layer may be deposited using a non-plasma process in which the substrate is not exposed to plasma or plasma-generated radicals. The hydrogen-containing gas to which the first layer is exposed may include an excited hydrogen species, which may be part of a hydrogen-containing plasma, and may be hydrogen-containing radicals. The first layer may also be exposed to oxygen before depositing the second layer. The work function of the gate electrode in the gate stack may be about 5 eV or higher in some embodiments.12-06-2012
20100190325SEMICONDUCTOR DEVICE HAVING MULTI-CHANNEL AND METHOD OF FABRICATING THE SAME - An embodiment of the present invention relates to a semiconductor device having a multi-channel and a method of fabricating the same. In an aspect, the semiconductor device includes a semiconductor substrate in which isolation layers are formed, a plurality of trenches formed within an active region of the semiconductor substrate, and a channel active region configured to connect opposite sidewalls within each trench region and having a surface used as a channel region.07-29-2010
20110263113METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device 10-27-2011
20080206973Process method to optimize fully silicided gate (FUSI) thru PAI implant - An improved method of forming a fully silicided (FUSI) gate in both NMOS and PMOS transistors of the same MOS device is disclosed. In one example, the method comprises forming oxide and nitride etch-stop layers over a top portion of the gates of the NMOS and PMOS transistors, forming a blocking layer over the etch-stop layer, planarizing the blocking layer down to the etch-stop layer over the gates, and removing a portion of the etch-stop layer overlying the gates. The method further includes implanting a preamorphizing species into the exposed gates to amorphize the gates, thereby permitting uniform silicide formation thereafter at substantially the same rates in the NMOS and PMOS transistors. The method may further comprise removing any remaining oxide or blocking layers, forming the gate silicide over the gates to form the FUSI gates, and forming source/drain silicide in moat areas of the NMOS and PMOS transistors.08-28-2008
20110111582METHOD FOR DEPOSITING ULTRA FINE GRAIN POLYSILICON THIN FILM - Disclosed is a method for depositing a polysilicon thin film with ultra-fine crystal grains. According to the present invention, the polysilicon thin film is deposited on a substrate by supplying source gases inside a chamber in which the substrate is loaded, wherein the source gases include a silicon-based gas and an oxygen-based gas. The mixing ratio of the oxygen-based gas to the silicon-based gas may be 0.15 or less (excluding 0). The oxygen within the thin film may be 20 atomic % (atomic percentage) or less (excluding 0).05-12-2011
20120040522METHOD FOR INTEGRATING MULTIPLE THRESHOLD VOLTAGE DEVICES FOR CMOS - A method to achieve multiple threshold voltage (Vt) devices on the same semiconductor chip is disclosed. The method provides different threshold voltage devices using threshold voltage adjusting materials and a subsequent drive in anneal instead of directly doping the channel. As such, the method of the present disclosure avoids short channel penalties. Additionally, no ground plane/back gates are utilized in the present application thereby the method of the present disclosure can be easily integrated into current complementary metal oxide semiconductor (CMOS) processing technology.02-16-2012
20110318913SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - There is provided a semiconductor device and a method for fabricating the same whose withstanding characteristic may be enhanced and whose ON resistance may be reduced. A MIS-type HEMT includes a carrier traveling layer made of a group-III nitride semiconductor and formed on a supporting substrate, a carrier supplying layer made of a group-III nitride semiconductor and formed on the carrier traveling layer, source and drain electrodes formed on the carrier supplying layer, insulating films formed on the carrier supplying layer and a gate electrode formed on the insulating films. The insulating film is formed in a region interposed between the source and drain electrodes and has a trench whose cross-section is inverted trapezoidal and whose upper opening is wider than a bottom thereof. The gate electrode is formed at least from the bottom of the trench onto the insulating films on the side of the drain electrode.12-29-2011
20120045888MULTILAYER LOW REFLECTIVITY HARD MASK AND PROCESS THEREFOR - A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).02-23-2012
20120208359Structure And Method For Fabrication Of Field Effect Transistor Gates With Or Without Field Plates - A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.08-16-2012
20110165766T-GATE FORMING METHOD FOR HIGH ELECTRON MOBILITY TRANSISTOR AND GATE STRUCTURE THEREOF - A T-gate forming method for a high electron mobility transistor includes the steps of: coating a first, a second and a third resist, each having an electron beam sensitivity different from each other, on a semiconductor substrate; performing a first exposure process by using an electron beam on the semiconductor substrate and then selectively developing the third resist; defining a gate head area by selectively developing the second resist to have a developed width wider than that of the third resist; performing a second exposure process by using an electron beam on the semiconductor substrate and then selectively developing the first resist in a bent shape at a temperature lower than in the development of the second and the third steps; and depositing metallic materials on the resists and then removing them to form a T-gate.07-07-2011
20120129329MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - The present invention is provided in order to remove contamination due to contaminant impurities of the interfaces of each film which forms a TFT, which is the major factor that reduces the reliability of TFTs. By connecting a washing chamber and a film formation chamber, film formation can be carried out without exposing TFTs to the air during the time from washing step to the film formation step and it becomes possible to maintain the cleanliness of the interfaces of each film which form the TFT.05-24-2012
20120208360METHOD FOR FORMING SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A microcrystalline semiconductor film is formed over a substrate using a plasma CVD apparatus which includes a reaction chamber in such a manner that a deposition gas and hydrogen are supplied to the reaction chamber in which the substrate is set between a first electrode and a second electrode; and plasma is generated in the reaction chamber by supplying high-frequency power to the first electrode. Note that the plasma density in a region overlapping with an end portion of the substrate in a region where the plasma is generated is set to be higher than that in a region which is positioned more on the inside than the region overlapping with the end portion of the substrate, so that the microcrystalline semiconductor film is formed over a region which is positioned more on the inside than the end portion of the substrate.08-16-2012
20120156866METHOD OF FORMING PATTERNS OF SEMICONDUCTOR DEVICE - A method of forming patterns of a semiconductor device includes forming a hard mask layer over stack layers including first to third regions, forming first patterns on the hard mask layer of the first region and second and third patterns, including first auxiliary layers and spacers formed on both sides of the first auxiliary layer, on the hard mask layer of the second and the third regions, forming hard mask patterns by etching the hard mask layer exposed through the first to third patterns, and forming word lines in the first region, a dummy word line in the second region, and select lines in the third region by etching the stack layers exposed through the hard mask patterns.06-21-2012
20120156865Enhanced Patterning Uniformity of Gate Electrodes of a Semiconductor Device by Late Gate Doping - When forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of the electrode material by using an appropriate mask or fill material for covering the active regions and using a lithography mask. In this manner, a high degree of flexibility is provided with respect to selecting an appropriate patterning regime, while at the same time a uniform and superior cross-sectional shape for any type of gate electrode structure is obtained.06-21-2012
20100291764Methods Of Removing Noble Metal-Containing Nanoparticles, Methods Of Forming NAND String Gates, And Methods Of Forming Integrated Circuitry - Some embodiments include methods of removing noble metal-containing particles from over a substrate. The substrate is exposed to a composition that reduces adhesion between the noble metal-containing particles and the substrate, and simultaneously the substrate is spun to sweep at least some of the noble metal-containing particles off from the substrate. Some embodiments include methods in which tunnel dielectric material is formed across a semiconductor wafer. Metallic nanoparticles are formed across the tunnel dielectric material. A stack of two or more different materials is formed over the metallic nanoparticles. A portion of the stack is covered with a protective mask while another portion of the stack is left unprotected. The unprotected portion of the stack is removed to expose some of the metallic nanoparticles. The semiconductor wafer to is subjected to etchant suitable to undercut at least some of the exposed metallic nanoparticles, and simultaneously the semiconductor wafer is spun.11-18-2010
20120252198METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - The present application discloses a method for manufacturing a semiconductor structure, comprising the steps of: a) providing an n-type field effect transistor comprising a source region, a drain region, and a first gate; b) forming a tensile stress layer on the n-type field effect transistor; c) removing the first gate so as to form a gate opening; d) performing an anneal so that the source region and the drain region memorize a stress induced by the tensile stress layer; e) forming a second gate; f) removing the tensile stress layer; and b) forming an interlayer dielectric layer on the n-type field effect transistor. The present method incorporates a replacement process and a stress memorization technique, which enhances the stress memorization effect and thus mobility of electrons, which in turn improves overall properties of the semiconductor structure.10-04-2012
20120315748METHOD FOR FABRICATING AN APERTURE - A method for fabricating an aperture is disclosed. The method includes the steps of: forming a hard mask containing carbon on a surface of a semiconductor substrate; and using a non-oxygen element containing gas to perform a first etching process for forming a first aperture in the hard mask.12-13-2012
20120164820SEMICONDUCTOR DEVICE FABRICATED USING A METAL MICROSTRUCTURE CONTROL PROCESS - The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal.06-28-2012
20100210097MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a manufacturing method of a semiconductor device including a gate insulating film which can be formed into a thin film and of which film composition is easy to be controlled. The manufacturing method includes: forming a manganese oxide film for serving as a gate insulating film on a semiconductor substrate, on which a transistor is formed; forming a conductive film for serving as a gate electrode on the manganese oxide film; and forming a gate electrode and a gate insulating film by processing the conductive film and the manganese oxide film.08-19-2010
20120135589CHEMICAL-MECHANICAL PLANARIZATION METHOD AND METHOD FOR FABRICATING METAL GATE IN GATE-LAST PROCESS - The present invention provides a chemical-mechanical planarization method and a method for fabricating a metal gate in gate last process. The chemical-mechanical planarization method includes: providing a substrate including a gate and source/drain regions on the sides of the gate, the gate and the source/drain regions being overlay by an insulating layer, and the insulating layer including a protruding part above the gate and a recessed part above a surface of the substrate between gates; selectively doping the insulating layer such that only the protruding part is doped; and performing CMP on the substrate after doping, to remove the protruding part and planarize the surface of the substrate. By selectively doping the insulating layer, the method makes only the protruding part of the insulating layer doped, enhancing the corrosive attacks on the material of the protruding part by the slurry in the CMP, and increasing the removal rate of the material of the protruding part by the CMP, thereby improving the within-die uniformity of the process, consequently, there will not be excess metal in the insulating layer between gates, thereby preventing device short circuit risk induced by POP CMP process.05-31-2012
20120135591SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING - Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. A method of forming a semiconductor structure includes forming sidewalls and spacers adjacent to a gate stack structure, and forming a recess in the gate stack structure. The method further includes epitaxially growing a straining material on a polysilicon layer of the gate stack structure, and in the recess in the gate stack structure. The straining material is Si:C and the gate stack structure is a PFET gate stack structure. The straining material is grown above and covering a top surface of the sidewalls and the spacers.05-31-2012
20120135590SILICON REMOVAL FROM SURFACES AND METHOD OF FORMING HIGH K METAL GATE STRUCTURES USING SAME - A method of fabricating a semiconductor device, comprising carrying out a gate last process including forming a dummy gate of polysilicon, and thereafter removing the dummy gate for replacement by a metal gate, wherein the dummy gate is removed by XeF05-31-2012
20120135588METHOD FOR PATTERNING A METAL LAYER AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES BY USING THE SAME - Disclosed herein is a method for patterning a metal layer, which includes the following steps. A substrate having a metal layer thereon is provided. A patterned conductive polymeric layer is formed on the metal layer, wherein a portion of the metal layer is exposed by the patterned conductive polymeric layer. The substrate having the patterned conductive polymer layer is disposed in an electrolytic cell, so that the exposed portion of the metal layer is immersed in the electrolytic solution of the electrolytic cell. The anode of the electrolytic cell is electrically coupled to the patterned conductive polymeric layer, while the cathode of the electrolytic cell is immersed in the electrolytic solution. Sequentially, an electrical potential is applied across the anode and the cathode to perform an electrolysis reaction so that the exposed portion of the metal layer is dissolved in the electrolytic solution.05-31-2012
20120214295METHOD FOR MANUFACTURING TRANSISTOR - A method for manufacturing a semiconductor device includes providing a substrate having an NMOS transistor and a PMOS transistor formed thereon, forming a stressed layer that covers the transistors, and selectively removing the stressed layer on the PMOS transistor. The method further includes annealing the substrate, removing the remaining stressed layer, forming a dielectric layer structure on the transistors; and performing a first planarization process on the dielectric layer structure. The method also includes forming a corrosion-resistant insulating structure on a rear surface of the substrate, and performing a second planarization process on the dielectric layer structure. The semiconductor device thus formed can withstand high voltages while maintaining gate oxide integrity.08-23-2012
20120252200PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - A plasma processing apparatus includes a processing chamber arranged in a vacuum vessel. A wafer placed on a sample stage in the processing chamber is processed using a plasma formed in the processing chamber. Before etching the film layers provided on the wafer composed of a metal substance and an underlying oxide film or a material having a high dielectric constant, another wafer, provided on surface thereof a film composed of a metal of the same kind as the metal substance, processed and particles of the metal are deposited on an inner wall of said processing chamber.10-04-2012
20120252199METHODS FOR FABRICATING A PHOTOLITHOGRAPHIC MASK AND FOR FABRICATING A SEMICONDUCTOR INTEGRATED CIRCUIT USING SUCH A MASK - Methods are provided for designing a photolithographic mask and for fabricating a semiconductor IC using such a mask. In accordance with one embodiment a method for fabricating a semiconductor IC includes determining a design target for a region within the IC. An initial mask geometry is determined for the region having a mask opening and a mask bias relative to the design target. A sub-resolution edge ring having a predetermined, fixed spacing to an edge of the mask opening is inserted into the mask geometry and a lithographic mask is generated. A material layer is applied overlying a semiconductor substrate upon which the IC is to be fabricated and a layer of photoresist is applied overlying the material layer. The layer of photoresist is exposed through the lithographic mask and is developed. A process step is then performed on the material layer using the layer of photoresist as a mask.10-04-2012
20120077336SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device of the present invention includes: a semiconductor layer; a gate insulation film provided on the semiconductor layer and including at least one of Hf and Zr; and a gate electrode provided on the gate insulation film and including a carbonitride which includes at least one of Hf and Zr.03-29-2012
20120214296Methods of Forming Semiconductor Devices - Provided are a semiconductor device and a method of forming the same. The method may include forming a metal oxide layer on a substrate and forming a sacrificial oxide layer on the metal oxide layer. An annealing process is performed on the substrate. A formation-free energy of the sacrificial oxide layer is greater than a formation-free energy of the metal oxide layer at a process temperature of the annealing process.08-23-2012
20120220113Method of Manufacturing Semiconductor Device Having Metal Gate - The present invention provides a method of manufacturing semiconductor device having metal gate. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench and then a first metal layer and a first material layer are formed in the first trench. Next, the first metal layer and the first material layer are flattened. The second sacrifice gate is removed to form a second trench and then a second metal layer and a second material layer are formed in the second trench. Lastly, the second metal layer and the second material layer are flattened.08-30-2012
20100048007HIGH PLANARIZING METHOD FOR USE IN A GATE LAST PROCESS - A method for performing a chemical-mechanical polishing (CMP) is provided. The method includes processing a semiconductor substrate to form a dummy gate structure on the substrate, to form a hard mask on the dummy gate structure, and to form a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer on the hard mask, performing a first CMP process with a first slurry to modify a non-planar topography of the ILD layer, performing a second CMP process with a second slurry to remove the hard mask, and performing a third CMP process with a third slurry to remove an interfacial layer that forms between the dummy gate and hard mask during semiconductor processing.02-25-2010
20110104880CORNER ROUNDING IN A REPLACEMENT GATE APPROACH BASED ON A SACRIFICIAL FILL MATERIAL APPLIED PRIOR TO WORK FUNCTION METAL DEPOSITION - In a replacement gate approach, a top area of a gate opening has a superior cross-sectional shape which is accomplished on the basis of a plasma assisted etch process or an ion sputter process. During the process, a sacrificial fill material protects sensitive materials, such as a high-k dielectric material and a corresponding cap material. Consequently, the subsequent deposition of a work function adjusting material layer may not result in a surface topography which may result in a non-reliable filling-in of the electrode metal. In some illustrative embodiments, the sacrificial fill material may also be used as a deposition mask for avoiding the deposition of the work function adjusting metal in certain gate openings in which a different type of work function adjusting species is required.05-05-2011
20120225545Method of Fabricating Semiconductor Device - The present invention provides a method of fabricating a semiconductor device. A substrate is provided. A first region and a second region are defined on the substrate. A first interfacial layer, a sacrifice layer and a sacrifice gate layer are disposed on the first region. The sacrifice layer and the sacrifice gate layer are disposed on the second region of the substrate. Next, a first etching step is performed to remove the sacrifice gate layer in the first region and the second region. Then, a second etching step is performed to remove the sacrifice layer in the first region and the second region to expose the substrate of the second region. Lastly, a second interfacial layer is formed on the substrate of the second region.09-06-2012
20090061607METHOD OF MANUFACTURING PHOTOMASK AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of an embodiment, a method of manufacturing a photomask has forming a laminate over a transparent substrate, the laminate having a light-shielding layer and a hard mask layer, forming a negative resist layer over the laminate, exposing and developing the negative resist layer over the laminate to form a first resist pattern having a main pattern in a main exposure area surrounded by an outer area, etching the hard mask layer using the first resist pattern as an etching mask to form a hard mask pattern, removing the first resist pattern from the laminate; forming a positive resist layer covering the hard mask pattern over the transparent substrate, exposing and developing the positive resist layer to form a second resist pattern, the second resist pattern and a light-shielding pattern disposed in the outer area and forming an opening disclosing the hard mask pattern.03-05-2009
20120083107FinFETs Having Dielectric Punch-Through Stoppers - A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.04-05-2012
20120083106METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - The present application discloses a method for manufacturing a semiconductor structure, comprising the steps of: a) providing a p-type field effect transistor; b) forming a tensile-stressed layer on the p-type field effect transistor; c) removing a portion of the tensile-stressed layer, so that the remaining portion of the tensile-stressed layer generates compressive stress in the channel of the p-type field effect transistor; and d) performing annealing, so as to achieve the object of memorizing compressive stress in a channel of a transistor and improving the performance of the transistor. The method according to the present invention memorizes the compressive stress in the channel of the transistor by a stress memorization technique, increases mobility of holes, and improves overall performance of the semiconductor structure.04-05-2012
20120264279METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, wherein the method comprises steps as follows: a semiconductor structure comprising a substrate, a dummy gate structure having a dielectric layer disposed over the substrate and a silicon layer disposed over the dielectric layer, and an etching stop layer (ESL) and an inter-layer dielectric (ILD) layer both of which are sequentially disposed over the substrate and the dummy gate structure is first provided. Then, a chemical mechanical polishing (CMP) is performed to planrizing the ILD layer and expose the ESL. Subsequently, an in-situ etching process is conducted to remove portions of the ESL and the silicon layer to form an opening in the dummy gate structure. Next, metal material is filled into the opening.10-18-2012
20080299752FABRICATION METHOD OF SEMICONDUCTOR DEVICE - Provided is a fabrication method of a semiconductor device having an improved production yield.12-04-2008
20080280429Method to control uniformity/composition of metal electrodes, silicides on topography and devices using this method - A method for depositing metals on surfaces is provided which comprises (a) providing a substrate (11-13-2008
20110045665REDUCING THE CREATION OF CHARGE TRAPS AT GATE DIELECTRICS IN MOS TRANSISTORS BY PERFORMING A HYDROGEN TREATMENT - By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in highly scaled P-channel transistors.02-24-2011
20120270385SWITCHING DEVICE HAVING A MOLYBDENUM OXYNITRIDE METAL GATE - A field effect transistor (FET) includes a body region and a source region disposed at least partially in the body region. The FET also includes a drain region disposed at least partially in the body region and a molybdenum oxynitride (MoNO) gate. The FET also includes a dielectric having a high dielectric constant (k) disposed between the body region and the MoNO gate.10-25-2012
20120322250N-Metal Film Deposition With Initiation Layer - Provided are methods of depositing N-Metals onto a substrate. Some methods comprise providing an initiation layer of TaM or TiM layer on a substrate, wherein M is selected from aluminum, carbon, noble metals, gallium, silicon, germanium and combinations thereof; and exposing the substrate having the TaM or TiM layer to a treatment process comprising soaking the surface of the substrate with a reducing agent to provided a treated initiation layer.12-20-2012
20110275206METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - In a method for fabricating a semiconductor device, a first insulating film which is to serve as a gate insulating film of a protected element is formed on a semiconductor substrate. At least a portion of the first insulating film is removed in a protective element portion. Thereafter, a surface of the first insulating film is nitrided in a protected element portion. A conductive film is selectively formed, extending over the protected element portion and the protective element portion, to form a gate electrode of the protected element and an electrode of a protective element, which are connected together.11-10-2011
20100216300SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method, the method including: forming a semiconductor element on a semiconductor substrate; and by using microwaves as a plasma source, forming an insulation film on the semiconductor element by performing a CVD process using microwave plasma having an electron temperature of plasma lower than 1.5 eV and an electron density of plasma higher than 1×1008-26-2010
20120100704SEMICONDUCTOR DEVICE WITH VERTICAL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device with a vertical transistor includes a plurality of active pillars; a plurality of vertical gates surrounding sidewalls of the active pillars; a plurality of word lines having exposed sidewalls whose surfaces are higher than the active pillars and connecting the adjacent vertical gates together; and a plurality of spacers surrounding the exposed sidewalls of the word lines over the vertical gates.04-26-2012
20130012009METHOD FOR SELF ALIGNED METAL GATE CMOS - A semiconductor device is formed by first providing a dual gate semiconductor device structure having FET pair precursors, which includes an nFET precursor and a pFET precursor, wherein each of the nFET precursor and the pFET precursor includes a dummy gate structure. At least one protective layer is deposited across the FET pair precursors, leaving the dummy gate structures exposed. The dummy gate structure is removed from one of the nFET precursor and the pFET precursor to create therein one of an nFET gate hole and a pFET gate hole, respectively. A fill is deposited into the formed one of the nFET gate hole and the pFET gate.01-10-2013
20130023114Method for making semiconductor device - One or more embodiments relate to a method for forming a memory device, the memory device including a control gate, a charge storage structure and a select gate, the method comprising: forming a gate tower, the gate tower including the control gate over the charge storage structure; forming a dummy tower laterally spaced apart from the gate tower; and forming a select gate between the gate tower and the dummy tower.01-24-2013
20080254605METHOD OF REDUCING THE INTERFACIAL OXIDE THICKNESS - One inventive aspect is related to a method of minimizing the final thickness of an interfacial oxide layer between a semiconductor material and a high dielectric constant material. The method comprises depositing a covering layer on the high dielectric constant material. The method further comprises removing adsorbed/absorbed water from the high dielectric constant material prior to depositing the covering layer. The removal of adsorbed/absorbed water is preferably done by a degas treatment. The covering layer may be a gate electrode or a spacer dielectric.10-16-2008
20090291549METAL FILM DECARBONIZING METHOD, FILM FORMING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - On a Si substrate 11-26-2009
20080248641Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device according to this invention includes; forming a first region in which a first insulating film is formed on a semiconductor substrate surface and a second region on which the semiconductor substrate surface is exposed; cleaning the semiconductor substrate surface exposed in the second region with a cleaning fluid; removing a chemical oxide film formed on the semiconductor substrate surface in the second region with the cleaning fluid; forming a second insulating film having a film thickness different from that of the first insulating film on the semiconductor substrate surface in the second region; and forming a gate electrode film on the first insulating film and the second insulating film to form a pattern in the gate electrode film (and the first insulating film and the second insulating film formed under the gate electrode film). In removing the oxide film, the oxide film is removed by processing the semiconductor substrate in the presence of a hydrogen gas at a temperature of not less than 940° and not more than 990° and a pressure of not less than 30 Torr and not more than 150 Torr.10-09-2008
20080248640Method for reducing polysilicon gate defects in semiconductor devices - Semiconductor devices and fabrication methods are provided, in which gate defects associated with photoresist stress after plasma trim/etch are substantially reduced. The method comprises forming a gate dielectric layer above a semiconductor body substrate; coating the gate dielectric layer with a photoresist coating; exposing and developing the photoresist coating; performing a resist annealing; and trimming and etching the photoresist coating.10-09-2008
20080233726Method for Manufacturing Semiconductor Device - A method for manufacturing a semiconductor device includes forming a gate conductive layer, a first mask layer, a second mask layer, and a third mask layer over a semiconductor substrate that includes a cell region and a peripheral region. The method also includes forming a second mask pattern and a third mask pattern using a gate mask. The method further includes trimming the second mask pattern in the peripheral region to form a fourth mask pattern having a size smaller than that of the second mask pattern. Still further, the method includes removing the third mask pattern, and patterning the first mask layer and the gate conductive layer using the fourth mask pattern as a mask.09-25-2008
20080227279METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to the present invention, it is provided a method of manufacturing a semiconductor device comprising a PMOS transistor and a NMOS transistor, wherein the method facilitates obtaining a FUSI phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps09-18-2008
20080227278METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including an NMOS transistor and a PMOS transistor is provided. The method includes: forming a silicon layer over a substrate through a gate insulating film; forming a first gate electrode and a second gate electrode by patterning the silicon layer, the first gate electrode being a gate electrode of the NMOS transistor, and the second gate electrode being a gate electrode of the PMOS transistor; selectively forming a silicon oxide film on the first gate electrode which is formed of silicon; after the selectively forming the silicon oxide film, forming a first metallic layer formed of a metal capable of forming a silicide over the first and second gate electrodes; and performing a first heat treatment such that a first silicide layer of a silicide of the first metallic layer is formed.09-18-2008
20080220602METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor manufacturing method comprises the step of forming a metal alloy film of an alloy of a metal of Ni or others and a noble metal over a semiconductor substrate containing a region where silicon is partially exposed; the step of selectively reacting the silicon in the region and the metal alloy film by thermal processing to form metal silicide film containing the metal of Ni or others and the noble metal on the region; and the step of removing the metal alloy film remaining unreacted by using a solution containing hydrogen peroxide with a transition metal, which has higher ionization tendency than the metal of Ni or others, dissolved in.09-11-2008
20080220601Methods for forming nonvolatile memory elements with resistive-switching metal oxides - Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.09-11-2008
20130137256SEMICONDUCTOR PROCESS - A semiconductor process is provided. The prior steps include: a first gate including a first cap layer and a second gate including a second cap layer are formed on a substrate. A hard mask layer is formed to cover the first gate and the second gate. The material of the hard mask layer is different from the material of the first cap layer and the second cap layer. The hard mask layer is removed entirely after a lithography process and an etching process are performed. The following steps include: a material is formed to entirely cover the first gate and the second gate. The material, the first gate and the second gate are etched back to make the first gate and the second gate have the same level and expose layers in both of them.05-30-2013
20130095645MEMORY ARRAY WITH SURROUNDING GATE ACCESS TRANSISTORS AND CAPACITORS WITH GLOBAL AND STAGGERED LOCAL BIT LINES - A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.04-18-2013
20130102138SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is disclosed. A dummy gate feature is formed between two active gate features in an inter-layer dielectric (ILD) over a substrate. An isolation structure is in the substrate and the dummy gate feature is over the isolation structure. Source/drain (S/D) features are formed at edges of the active gate features in the substrate for forming transistor devices. The disclosed method provides an improved method for reducing parasitic capacitance among the transistor devices. In an embodiment, the improved formation method is achieved by introducing species into the dummy gate feature to increase the resistance of the dummy gate feature.04-25-2013
20130102139METHOD FOR MANUFACTURING DOUBLE-GATE STRUCTURES - A method is provided for manufacturing a double-gate structure. The method includes providing a substrate and forming a first gate region on a surface of the substrate using a first gate layer. The method also includes forming a second gate layer on the surface of the substrate, wherein the second gate layer covers the first gate region, forming an etch-stop layer on the second gate layer, and forming a silicide layer on the etch-stop layer. The method also includes forming a second gate region, different from the first gate region, containing the second gate layer and the silicide layer without the etch-stop layer. Further, the etch-stop layer is arranged between the second gate layer and the silicide layer to facilitate even etching of the second gate layer around the first gate region.04-25-2013
20130122697Doping aluminum in tantalum silicide - Provided are methods of providing aluminum-doped TaSi05-16-2013
20130130486METHOD OF FORMING SILICIDE LAYERS - A method of forming silicide layers is disclosed, the method including: providing a silicon substrate which includes at least one first region and at least one second region; depositing a dielectric layer over the silicon substrate; forming at least one opening having a great width/depth ratio in the dielectric layer above the at least one first region, and forming at least one opening having a small width/depth ratio in the dielectric layer above the at least one second region; depositing a metal and performing a high-temperature annealing to form a thick silicide layer in each of the at least one opening above each of the at least one first region and to form a thin silicide layer in each of the at least one opening above each of the at least one second region; removing the remaining metal not formed into the silicide layers.05-23-2013
20110217831Nonvolatile semiconductor memory and method of manufacturing the same - A method of forming a nonvolatile semiconductor memory device includes forming a semiconductor substrate, forming upper and lower portions of a first gate electrode on a gate insulating film formed on the semiconductor substrate, the lower portion of the first gate electrode formed on the gate insulating film, the upper portion of the first gate electrode formed on the lower portion of the first gate electrode and having a gate length which is less than a gate length of the lower portion of the first gate electrode, forming a spacer insulating film to contact respective surfaces of the upper and lower portions of the first gate electrode, in which a length of the spacer insulating film combined with the gate length of the upper portion of the first gate electrode is equal to the gate length of the lower portion of the first gate electrode, forming an electric charge trapping film covering a portion of the semiconductor substrate, a surface of the lower portion of the first gate electrode, and a surface of the spacer insulating film, and forming a second gate electrode in a side direction of the first gate electrode and electrically insulated from the first gate electrode by the electric charge trapping film, the second gate electrode having a distance between the upper portion of the first gate electrode that is greater than a distance between the lower portion of the first gate electrode, in which the second gate electrode is separated by the upper portion of the first gate electrode by the electric charge trapping film and the spacer insulating film.09-08-2011
20130149851Methods of Protecting Elevated Polysilicon Structures During Etching Processes - Disclosed herein are various methods of protecting elevated polysilicon structures during etching processes. In one example, the method includes forming a layer stack above a semiconducting substrate for a memory device, forming a protective mask layer above the layer stack of the memory device and performing at least one etching process to define a gate electrode for a transistor while the protective mask is in position above the layer stack for the memory device.06-13-2013
20130149852METHOD FOR FORMING A SEMICONDUCTOR DEVICE - A method for forming a semiconductor device includes providing in a process chamber a metal-containing gate electrode film on a substrate, flowing a process gas consisting of hydrogen (H06-13-2013
20130122698METHOD FOR MANUFACTURING MULTI-GATE TRANSISTOR DEVICE - A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer and a patterned hard mask sequentially formed thereon, removing the patterned hard mask, performing a thermal treatment to rounding the patterned semiconductor layer with a process temperature lower than 800° C., and sequentially forming a gate dielectric layer and a gate layer covering a portion of the patterned semiconductor layer on the semiconductor substrate.05-16-2013
20110275207SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME - A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.11-10-2011
20100317182METHOD FOR MAKING SEMICONDUCTOR ELEMENT STRUCTURE - A method for forming a semiconductor element structure is provided. First, a substrate including a first MOS and a second MOS is provided. The gate electrode of the first MOS is connected to the gate electrode of the second MOS, wherein the first MOS includes a first high-K material and a first metal for use in a first gate, and a second MOS includes a second high-K material and a second metal for use in a second gate. Then the first gate and the second gate are partially removed to form a connecting recess. Afterwards, the connecting recess is filled with a conductive material to form a bridge channel for electrically connecting the first metal and the second metal.12-16-2010
20100317181Gate Stack Integration of Complementary MOS Devices - A method of forming an integrated circuit structure includes providing a substrate comprising a first device region and a second device region; forming an oxide cap over the substrate and in the first device region and the second device region; forming a first metal layer over the oxide cap, wherein the first metal layer has a first portion in the first device region and a second portion in the second device region; forming a mask to cover the second portion of the first metal layer, wherein the first portion of the first metal layer is exposed; removing the first portion of the first metal layer and the oxide cap from the first device region; removing the mask; and forming a second metal layer in the first device region and the second device region, wherein the second metal layer in the second device region is over the second portion of the first metal layer.12-16-2010
20100317179METHOD FOR MAKING INTEGRATED CIRCUIT DEVICE - A method for making an integrated circuit device by: forming a plurality of transistors on a semiconductor substrate; forming multilayer interconnects by depositing a layer of metal; patterning the metal layer; depositing a first dielectric material, depositing a second dielectric material, patterning the first and second dielectric materials; and depositing a via filling metal material into the patterned areas; or, alternatively, by forming transistors on a substrate; depositing one of an electrically insulating or electrically conducting material; patterning said one of an electrically insulating or electrically conducting material; and depositing the other of the electrically insulating or electrically conducting material, so as to form a layer over said transistors having both electrically insulating and electrically conducting portions; wherein the first dielectric material, which is an organosiloxane material, and the electrically insulating material each has a carbon to silicon ratio of 1.5 to 1 or more.12-16-2010
20120282764TECHNIQUE FOR EXPOSING A PLACEHOLDER MATERIAL IN A REPLACEMENT GATE APPROACH BY MODIFYING A REMOVAL RATE OF STRESSED DIELECTRIC OVERLAYERS - In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.11-08-2012
20130183818Methods of Fabricating Nonvolatile Memory Devices and Related Devices - Provided is a fabricating method of a nonvolatile memory. The fabricating method includes forming a plurality of gates extending in a first direction on a substrate to be adjacent to each other, forming a gap-fill layer filling at least a portion of a space between the plurality of gates, forming a supporter pattern supporting the plurality of gates on the plurality of gates and the gap-fill layer, and forming an air gap in the space between the plurality of gates by removing the gap-fill layer.07-18-2013
20130183819SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF - A silicon nitride film, which is a second hard mask, is dry etched to be removed completely. The silicon nitride film, which is formed on a sidewall of a silicon nitride film used as a first hard mask, has a relatively low etching rate. Therefore, if the silicon nitride film is continued etching until the corresponding portion thereof is removed, polysilicon is etched in a direction of depth in trench shape. Then, floating gates in adjacent cells are separated and a step portion of the polysilicon is formed. Consequently, a remaining portion of the silicon nitride film used as the first hard mask is removed, an ONO film is laminated on a whole surface of the poly silicon having the step portion on an edge that has been etched, and then, a polysilicon for a control gate is laminated on the ONO film.07-18-2013
20130122699NOVEL HARD MASK REMOVAL METHOD - A method of removing a hard mask used for patterning gate stacks including patterning gate stacks on a substrate, wherein the hard mask is deposited over the gate stacks. The method further includes depositing a dielectric layer on the substrate after the gate stacks are patterned and planarizing a first portion of the dielectric layer. The method further includes removing a second portion of the dielectric layer and the hard mask by using an etching gas and etching the remaining dielectric layer by using a wet etching chemistry.05-16-2013
20110312169ANTI-FUSE MEMORY CELL - An anti-fuse memory cell having a variable thickness gate dielectric. The variable thickness dielectric has a thick portion and a thin portion, where the thin portion has at least one dimension less than a minimum feature size of a process technology. The thin portion can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate dielectric substantially identical in thickness to the thick portion of the variable thickness gate dielectric of the anti-fuse transistor.12-22-2011
20100035423METHOD OF CONTROLLING INTERFACE LAYER THICKNESS IN HIGH DIELECTRIC CONSTANT FILM STRUCTURES - A method for controlling interface layer thickness in high dielectric constant (high-k) film structures found in semiconductor devices. According to one embodiment, the method includes providing a monocrystalline silicon substrate, growing a chemical oxide layer on the monocrystalline silicon substrate in an aqueous bath, vacuum annealing the chemical oxide layer, depositing a high-k film on the vacuum annealed chemical oxide layer, and optionally vacuum annealing the high-k film. According to another embodiment, the method includes depositing a high-k film on a chemical oxide layer, and vacuum annealing the high-k film.02-11-2010
20120021594Methods of Forming a Plurality of Transistor Gates, and Methods of Forming a Plurality of Transistor Gates Having at Least Two Different Work Functions - A method of forming a plurality of transistor gates having at least two different work functions includes forming first and second transistor gates over a substrate having different widths, with the first width being narrower than the second width. A material is deposited over the substrate including over the first and second gates. Within an etch chamber, the material is etched from over both the first and second gates to expose conductive material of the first gate and to reduce thickness of the material received over the second gate yet leave the second gate covered by the material. In situ within the etch chamber after the etching, the substrate is subjected to a plasma comprising a metal at a substrate temperature of at least 300° C. to diffuse said metal into the first gate to modify work function of the first gate as compared to work function of the second gate.01-26-2012
20130196495METHODS FOR FABRICATING MOS DEVICES WITH STRESS MEMORIZATION - A MOS device and methods for its fabrication are provided. In one embodiment the MOS device is fabricated on and within a semiconductor substrate. The method includes forming a gate structure having a top and sidewalls and having a gate insulator overlying the semiconductor substrate, a gate electrode overlying the gate insulator, and a cap overlying the gate electrode. An oxide liner is deposited over the top and sidewalls of the gate structure. In the method, the cap is etched from the gate structure and oxide needles extending upward from the gate structure are exposed. A stress-inducing layer is deposited over the oxide needles and gate structure and the semiconductor substrate is annealed. Then, the stress-inducing liner is removed.08-01-2013
20130095644PLANARIZATION PROCESS FOR SEMICONDUCTOR DEVICE FABRICATION - The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature.04-18-2013

Patent applications in class Insulated gate formation

Patent applications in all subclasses Insulated gate formation