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COATING WITH ELECTRICALLY OR THERMALLY CONDUCTIVE MATERIAL

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438 - Semiconductor device manufacturing: process

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Class / Patent application numberDescriptionNumber of patent applications / Date published
438597000 To form ohmic contact to semiconductive material 2083
438585000 Insulated gate formation 931
Entries
DocumentTitleDate
20110189844METHOD FOR ENCAPSULATING A MICROCOMPONENT USING A MECHANICALLY REINFORCED CAP - A method for encapsulating a micro component positioned on and/or in a substrate, including the following steps:08-04-2011
20080286955Fabrication of Recordable Electrical Memory - A memory cell of a memory device is fabricated by forming a first electrode on a substrate, positioning a photo mask at a first position relative to the substrate, and forming a first material layer on the first electrode based on a pattern on the photo mask. The photo mask is positioned at a second position relative to the substrate, and a second material layer is formed above the first material layer based on the pattern on the photo mask, the second material layer being offset from the first material layer so that a first sub-cell of the memory cell includes the first material layer and not the second material layer, and a second sub-cell of the memory cell includes both the first and second material layers. A second electrode is formed above the first and second material layers.11-20-2008
20130084695Methods of Forming Diodes - Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed.04-04-2013
20080268629Method of Forming Overlay Mark of Semiconductor Device - A method of fabricating a semiconductor device wherein, in forming an overlay mark in a scribe line region between dies in a mask process, a semiconductor substrate is provided in which a contact plug is formed in a contact hole of a dielectric layer in the scribe line region and a trench is formed on the contact plug. A first metal layer for a metal line is formed in the contact plug and the dielectric layer through an ALD (Atomic Layer Deposition) method so that a step generated by the trench remains intact. A second metal layer for a metal line is formed on the first metal layer using a sputtering method so that the step remains intact.10-30-2008
20090155990MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE AND METHOD FOR CREATING A LAYOUT THEREOF - A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.06-18-2009
20090093107SEMICONDUCTOR SUBSTRATE CLEANING METHODS, AND METHODS OF MANUFACTURE USING SAME - In a cleaning composition, a method of cleaning a semiconductor substrate and a method of manufacturing a semiconductor device, the cleaning composition includes about 0.5 to about 5% by weight of an organic ammonium hydroxide compound, about 0.1 to about 3% by weight of a fluoride compound, about 0.1 to about 3% by weight of a buffering agent, about 0.5 to about 5% by weight of an etching accelerant, and a remainder of water.04-09-2009
20110059600METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, CLEANING METHOD, AND SUBSTRATE PROCESSING APPARATUS - It is possible to efficiently remove deposited materials such as a conductive film or insulting film adhered to parts such as the inner wall of a processing chamber and a substrate supporting tool disposed in the processing chamber. There is provided a method of manufacturing a semiconductor device. The method comprises: loading a substrate into a processing chamber; forming a conductive film or an insulating film on the substrate by supplying a plurality of source gases into the processing chamber; unloading the substrate from the processing chamber; and modifying a conductive film or an insulating film adhered to the processing chamber by supplying a modifying gas into the processing chamber. After performing a cycle of the loading, the forming, the unloading, and the modifying processes a plurality of times, the modified conductive film or the modified insulating film adhered to the processing chamber is removed from the processing chamber by supplying a cleaning gas into the processing chamber.03-10-2011
20090269914PROCESS FOR FORMING A DIELECTRIC ON A COPPER-CONTAINING METALLIZATION AND CAPACITOR ARRANGEMENT - Process for forming a dielectric. The process may include forming the dielectric on a metallization and capacitor arrangement. The process allows the direct application of a dielectric layer to a copper-containing metallization. Accordingly, two process gases may be excited with different plasma powers per unit substrate area, or one process gas may be excited with a plasma and another process gas may not be excited.10-29-2009
20130065383Fabrication methods for T-gate and inverted L-gate structure for high frequency devices and circuits - In high frequency circuits, the switching speed of devices is often limited by the series resistance and capacitance across the input terminals. To reduce the resistance and capacitance, the cross-section of input electrodes is made into a T-shape or inverted L-shape through lithography. The prior art method for the formation of cavities for T-gate or inverted L-gate is achieved through several steps using multiple photomasks. Often, two or even three different photoresists with different sensitivity are required. In one embodiment of the present invention, an optical lithography method for the formation of T-gate or inverted L-gate structures using only one photomask is disclosed. In another embodiment, the structure for the T-gate or inverted L-gate is formed using the same type of photoresist material.03-14-2013
20100197127METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is disclosed, wherein a plating layer is formed on a first surface side of a semiconductor substrate stably and at a low cost, while preventing the plating liquid from being contaminated and avoiding deposition of uneven plating layer on a second surface side. An electrode is formed on the first surface of the semiconductor substrate, and another electrode is formed on the second surface. A curing resin is applied on the electrode on the second surface and a film is stuck on the curing resin, and the curing resin is then cured. After that, a plating process is conducted on the first surface. The film and the curing resin are then peeled off.08-05-2010
20090286384Dishing-free gap-filling with multiple CMPs - A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.11-19-2009
20080233724RECYCLING OF ELECTROCHEMICAL-MECHANICAL PLANARIZATION (ECMP) SLURRIES/ELECTROLYTES - A method, process and system for the recycling of electrochemical-mechanical planarization slurries/electrolytes as they are used in the back end of line of the semiconductor wafer manufacturing process is disclosed. The method, process and system includes with the removal of metal ions from slurries using ion exchange media and/or electrochemical deposition.09-25-2008
20090311853CONTROLLING WARPING IN INTEGRATED CIRCUIT DEVICES - Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.12-17-2009
20100144132METHODS FOR FORMING NANODOTS AND/OR A PATTERNED MATERIAL DURING THE FORMATION OF A SEMICONDUCTOR DEVICE - Methods for forming nanodots and/or a patterned material are provided. One such method involves forming a first patterning material over a base. Blades of a nanoimprint lithography template are placed within the first patterning material, wherein the blades extend along the base in a first direction. With the blades within the first patterning material, the first patterning material are cured. The blades are removed from the first patterning material to form a patterned first patterning material. The base is etched using the patterned first patterning material as a pattern to form openings in the base. The patterned first patterning material is removed from the base. A second patterning material is formed over the base and within the openings in the base. Blades of a nanoimprint lithography template are placed within the second patterning material, wherein the blades extend along the base in a second direction, which is generally perpendicular with respect to the first direction. With the blades within the second patterning material, the second patterning material is cured. The blades are removed from the second patterning material to form a patterned second patterning material. The base is etched using the patterned second patterning material as a pattern to form openings in the base. The patterned second patterning material is removed from the base.06-10-2010
20090029537Method for forming semiconductor package and mold cast used for the same - A method for fabricating a thermally enhanced semiconductor package including the steps of providing a substrate having a first surface and a second surface; providing a die on the first surface of the substrate and electrically connecting the die with the substrate; placing the die, the substrate, and a heat slug in a mold cavity defined by a mold cast, the mold cast having a protruding portion that touches the periphery on the surface of the heat slug, wherein the contact area is defined as a periphery region and the non-contact area enclosed by the periphery region is defined as a central region; and encapsulating the die and the heat slug by molding materials, wherein the periphery region and the central region of the heat slug are exposed to the ambient air.01-29-2009
20110230040INDUCTIVELY COUPLED DUAL ZONE PROCESSING CHAMBER WITH SINGLE PLANAR ANTENNA - A dual zone plasma processing chamber is provided. The plasma processing chamber includes a first substrate support having a first support surface adapted to support a first substrate within the processing chamber and a second substrate support having a second support surface adapted to support a second substrate within the processing chamber. One or more gas sources in fluid communication with one or more gas distribution members supply process gas to a first zone adjacent to the first substrate support and a second zone adjacent to the second substrate support. A radio-frequency (RF) antenna adapted to inductively couple RF energy into the interior of the processing chamber and energize the process gas into a plasma state in the first and second zones. The antenna is located between the first substrate support and the second substrate support.09-22-2011
20090258481SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing apparatus which uses a thermal CVD reaction to deposit a film onto a substrate has a ring with an electrode terminal that makes contact with either the substrate or the deposited film thereon, a power supply that applies a current or a potential to this electrode terminal of the ring, and a piston cylinder mechanism for moving the ring up and down, so as to cause its electrode terminal to make and break contact with the substrate or deposited film thereon.10-15-2009
20090215252Methods of Depositing Materials Over Substrates, and Methods of Forming Layers over Substrates - The invention includes methods of utilizing supercritical fluids to introduce precursors into reaction chambers. In some aspects, a supercritical fluid is utilized to introduce at least one precursor into a chamber during ALD, and in particular aspects the supercritical fluid is utilized to introduce multiple precursors into the reaction chamber during ALD. The invention can be utilized to form any of various materials, including metal-containing materials, such as, for example, metal oxides, metal nitrides, and materials consisting of metal. Metal oxides can be formed by utilizing a supercritical fluid can be utilized to introduce a metal-containing precursor into reaction chamber, with the precursor then forming a metal-containing layer over a surface of a substrate. Subsequently, the metal-containing layer can be reacted with oxygen to convert at least some of the metal within the layer to metal oxide.08-27-2009
20100068874METHOD FOR FORMING A SACRIFICIAL SANDWICH STRUCTURE - The present disclosure provides a method for making a semiconductor device. The method includes forming a first material layer on a substrate; forming a second material layer on the first material layer; forming a sacrificial layer on the second material layer; forming a patterned resist layer on the sacrificial layer; applying a first wet etching process using a first etch solution to the substrate to pattern the sacrificial layer using the patterned resist layer as a mask, resulting in a patterned sacrificial layer; applying an ammonia hydroxide-hydrogen peroxide-water mixture (APM) solution to the substrate to pattern the second material layer, resulting in a patterned second material layer; applying a second wet etching process using a second etch solution to the substrate to pattern the first material layer; and applying a third wet etching process using a third etch solution to remove the patterned sacrificial layer.03-18-2010
20110250742CONTROLLING WARPING IN INTEGRATED CIRCUIT DEVICES - Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.10-13-2011
20110021013SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - The semiconductor device includes: memory cells each having a first multilayer electrode including a first lower electrode made of a first conductive film and a first upper electrode made of a second conductive film formed one on the other with a first interface film therebetween; and a diode having a diode electrode made of the second conductive film and a second interface film as a silicon oxide film formed at the interface between the diode electrode and a substrate. The first interface film has a thickness with which electrical connection between the lower electrode and the upper electrode is maintained, and the second interface film has a thickness with which epitaxial growth between the substrate and the diode electrode is inhibited.01-27-2011
20110027977DEPOSITION OF RUTHENIUM OR RUTHENIUM DIOXIDE - Methods of forming ruthenium or ruthenium dioxide are provided. The methods may include using ruthenium tetraoxide (RuO02-03-2011
20090197402SUBSTRATE PROCESSING APPARATUS, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND PROCESS TUBE - In a substrate processing apparatus, a process vessel is configured to accommodate and process a substrate held at a horizontal position. A gas introduction port is installed at a periphery of a first side of the process vessel and configured to introduce gas into the process vessel from a lateral direction of the substrate. A gas exhaust port is installed at a second side of the process vessel which is opposite to the first side, and is configured to exhaust gas inside the process vessel from a lateral direction of the substrate. A slope part is installed between the gas introduction port and the gas exhaust port inside the process vessel, and is configured to guide a flow path of the gas introduced into the process vessel.08-06-2009
20120070973Methods of Forming Diodes - Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed.03-22-2012
20120070972NON-UNIFORMITY REDUCTION IN SEMICONDUCTOR PLANARIZATION - Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first layer over the substrate. The method includes forming a second layer over the first layer. The first and second layers have different material compositions. The method includes forming a third layer over the second layer. The method includes performing a polishing process on the third layer until the third layer is substantially removed. The method includes performing an etch back process to remove the second layer and a portion of the first layer. Wherein an etching selectivity of the etch back process with respect to the first and second layers is approximately 1:1.03-22-2012
20100291763METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - Oxidation of a metal film disposed under a high permittivity insulation film can be suppressed, and the productivity of a film-forming process can be improved. In a method of manufacturing a semiconductor device, a first high permittivity insulation film is formed on a substrate by alternately repeating a process of supplying a source into a processing chamber in which the substrate is accommodated and exhausting the source and a process of supplying a first oxidizing source into the processing chamber and exhausting the first oxidizing source; and a second high permittivity insulation film is formed on the first high permittivity insulation film by alternately repeating a process of supplying the source into the processing chamber and exhausting the source and a process of supplying a second oxidizing source different from the first oxidizing source into the processing chamber and exhausting the second oxidizing source.11-18-2010
20110212611METHODS OF FORMING DUAL GATE OF SEMICONDUCTOR DEVICE - Disclosed herein is a method for forming a dual gate of a semiconductor device. The method comprises the steps of forming a first polysilicon layer doped with p-type impurity ions and a second polysilicon layer doped with n-type impurity ions on a first region and a second region of a semiconductor substrate, respectively, and sequentially subjecting the surfaces of the first and second polysilicon layers to wet cleaning, drying, and dry cleaning. The wet cleaning is performed by using a sulfuric acid peroxide mixture (SPM), a buffered oxide etchant (BOE), and Standard Clean-1 (SC-1) as cleaning solutions.09-01-2011
20120322249MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE - In a manufacturing method of a semiconductor structure, a substrate having a front surface and a back surface is provided. The front surface has a device layer thereon and conductive plugs electrically connected to the device layer. A thinning process is performed on the back surface of the substrate, such that the back surface of the substrate and surfaces of the conductive plugs have a distance therebetween. Holes are formed in the substrate from the back surface to the conductive plugs, so as to form a porous film. An oxidization process is performed, such that the porous film correspondingly is reacted to form an oxide material layer. A polishing process is performed on the oxide material layer to expose the surfaces of the conductive plugs.12-20-2012
20100233872SEMICONDUCTOR CHIPS WITH CRACK STOP REGIONS FOR REDUCING CRACK PROPAGATION FROM CHIP EDGES/CORNERS - A chip fabrication method. A provided structure includes: a transistor on a semiconductor substrate, N interconnect layers on the semiconductor substrate and the transistor (N>0), and a first dielectric layer on the N interconnect layers. The transistor is electrically coupled to the N interconnect layers. P crack stop regions and Q crack stop regions are formed on the first dielectric layer (P, Q>0). The first dielectric layer is sandwiched between the N interconnect layers and a second dielectric layer that is formed on the first dielectric layer. Each P crack stop region is completely surrounded by the first and second dielectric layers. The second dielectric layer is sandwiched between the first dielectric layer and an underfill layer that is formed on the second dielectric layer. Each Q crack stop region is completely surrounded by the first dielectric layer and the underfill layer.09-16-2010
20120276727METHOD OF FORMING GATE PATTERN AND SEMICONDUCTOR DEVICE - This disclosure relates to a method of forming a gate pattern and a semiconductor device. The gate pattern comprises a plurality of parallel gate bars, and each gate bar is broken up by gaps. The method comprises: making an etching characteristic of a gate material layer at least at positions where the gaps are to be formed different from that at remaining positions; forming a plurality of parallel openings in a second resist layer; performing a first etching process on the gate material layer with the second resist layer as a mask, wherein portions of the gate material layer at least at the positions where the gaps are to be formed are selectively left; and performing a second etching process on the gate material layer so as to selectively remove the portions. This method can more accurately control the shape and size of the gate pattern.11-01-2012
20110159676FABRICATING LOW CONTACT RESISTANCE CONDUCTIVE LAYER IN SEMICONDUCTOR DEVICE - A conductive layer may be fabricated on a semiconductor substrate by loading a silicon substrate in to a chamber whose inside temperature is at a loading temperature in the range of approximately 250° C. to approximately 300° C., increasing the inside temperature of the chamber from the loading temperature to a process temperature, and sequentially stacking a single crystalline silicon layer and a polycrystalline silicon layer over the silicon substrate by supplying a silicon source gas and an impurity source gas in to the chamber, where the chamber may be, for example, a CVD chamber or a LPCVD chamber.06-30-2011
20080220600Semiconductor constructions, methods of forming multiple lines, and methods of forming high density structures and low density structures with a single photomask - Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.09-11-2008
20110212610METHODS OF FORMING DUAL GATE OF SEMICONDUCTOR DEVICE - Disclosed herein is a method for forming a dual gate of a semiconductor device. The method comprises the steps of forming a first polysilicon layer doped with p-type impurity ions and a second polysilicon layer doped with n-type impurity ions on a first region and a second region of a semiconductor substrate, respectively, and sequentially subjecting the surfaces of the first and second polysilicon layers to wet cleaning, drying, and dry cleaning. The wet cleaning is performed by using a sulfuric acid peroxide mixture (SPM), a buffered oxide etchant (BOE), and Standard Clean-1 (SC-1) as cleaning solutions.09-01-2011
20100317178REMOTE PLASMA PROCESSING OF INTERFACE SURFACES - Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus comprises a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal.12-16-2010
20120015511ON-CHIP EMBEDDED THERMAL ANTENNA FOR CHIP COOLING - An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures.01-19-2012

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