| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438570000 | FORMING SCHOTTKY JUNCTION (I.E., SEMICONDUCTOR-CONDUCTOR RECTIFYING JUNCTION CONTACT) | 25 |
| 20110263112 | METHOD FOR FORMING A SCHOTTKY DIODE HAVING A METAL-SEMICONDUCTOR SCHOTTKY CONTACT - A method for forming a metal-semiconductor Schottky contact in a well region is provided. The method includes forming a first insulating layer overlying a shallow trench isolation in the well region; and removing a portion of the first insulating layer such that only the well region and a portion of the shallow trench isolation is covered by a remaining portion of the first insulating layer. The method further includes forming a second insulating layer overlying the remaining portion of the first insulating layer and using a contact mask, forming a contact opening in the second insulating layer and the remaining portion of the first insulating layer to expose a portion of the well region. The method further includes forming the metal-semiconductor Schottky contact in the exposed portion of the well region by forming a metal layer in the contact opening and annealing the metal layer. | 10-27-2011 |
| 20120115319 | CONTACT PAD - The present disclosure relates to forming multi-layered contact pads for a semiconductor device, wherein the various layers of the contact pad are formed using one or more thin-film deposition processes, such as an evaporation process. Each contact pad includes an adhesion layer, which is formed over the device structure for the semiconductor device; a titanium nitride (TiN) barrier layer, which is formed over the adhesion layer; and an overlay layer, which is formed over the barrier layer. At least the titanium nitride (TiN) barrier layer is formed using an evaporation process. | 05-10-2012 |
| 20120122307 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device is disclosed. The method includes forming a first trench and a second trench in an n-type substrate surface, the first trenches being spaced apart from each other, the second trench surrounding the first trenches, the second trench being wider than the first trench. The method also includes forming a gate oxide film on the inner surfaces of the first and second trenches, and depositing an electrically conductive material to the thickness a half or more as large as the first trench width. The method further includes removing the electrically conductive material using the gate oxide film as a stopper layer, forming an insulator film thicker than the gate oxide film, and polishing the insulator film by CMP for exposing the n-type substrate and the electrically conductive material in the first trench. | 05-17-2012 |
| 20120149183 | SCHOTTKY DIODE SWITCH AND MEMORY UNITS CONTAINING THE SAME - A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts. | 06-14-2012 |
| 438571000 | Combined with formation of ohmic contact to semiconductor region | 6 |
| 20110177684 | METHOD OF MANUFACTURING A JUNCTION BARRIER SCHOTTKY DIODE WITH DUAL SILICIDES - An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well. | 07-21-2011 |
| 20110256699 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a silicon carbide semiconductor device which is capable of obtaining the silicon carbide semiconductor device having a high forward current and a low reverse leakage current by a simple method. The method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a film made of a first electrode material on one surface of a silicon carbide substrate, and forming an ohmic electrode by performing heat treatment at a temperature range of 930 to 950° C.; and forming a film made of a second electrode material on the other surface of the silicon carbide substrate, and forming a Schottky electrode by performing heat treatment. | 10-20-2011 |
| 20120302051 | MANUFACTURING METHOD OF SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer. | 11-29-2012 |
| 20120122308 | METHOD OF MANUFACTURING JUNCTION BARRIER SCHOTTKY DIODE WITH DUAL SILICIDES - An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well. | 05-17-2012 |
| 20080299751 | SCHOTTKY DIODE AND METHOD THEREFOR - In one embodiment, a Schottky diode is formed on a semiconductor substrate with other semiconductor devices and is also formed with a high breakdown voltage and a low forward resistance. | 12-04-2008 |
| 20130122696 | METHOD OF MANUFACTURING SCHOTTKY BARRIER DIODE - A silicon carbide substrate having a main face is prepared. By applying thermal oxidation to the main face of the silicon carbide substrate at a first temperature, an oxide film is formed on the main face. After the oxide film is formed, heat treatment is applied to the silicon carbide substrate at a second temperature higher than the first temperature. An opening exposing a portion of the main face is formed at the oxide film. A Schottky electrode is formed on the main face exposed by the opening. | 05-16-2013 |
| 438572000 | Compound semiconductor | 8 |
| 20110081772 | METHODS OF FABRICATING SILICON CARBIDE DEVICES INCORPORATING MULTIPLE FLOATING GUARD RING EDGE TERMINATIONS - Edge termination for silicon carbide devices has a plurality of concentric floating guard rings in a silicon carbide layer that are adjacent and spaced apart from a silicon carbide-based semiconductor junction. An insulating layer, such as an oxide, is provided on the floating guard rings and a silicon carbide surface charge compensation region is provided between the floating guard rings and is adjacent the insulating layer. Methods of fabricating such edge termination are also provided. | 04-07-2011 |
| 20090098719 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - An object of the invention is to provide a method for manufacturing a silicon carbide semiconductor device having constant characteristics with reduced variations in forward characteristics. The method for manufacturing the silicon carbide semiconductor device according to the invention includes the steps of: (a) preparing a silicon carbide substrate; (b) forming an epitaxial layer on a first main surface of the silicon carbide substrate; (c) forming a protective film on the epitaxial layer; (d) forming a first metal layer on a second main surface of the silicon carbide substrate; (e) applying heat treatment to the silicon carbide substrate at a predetermined temperature to form an ohmic junction between the first metal layer and the second main surface of the silicon carbide substrate; (f) removing the protective film; (g) forming a second metal layer on the epitaxial layer; and (h) applying heat treatment to the silicon carbide substrate at a temperature from 400° C. to 600° C. to form a Schottky junction of desired characteristics between the second metal layer and the epitaxial layer. | 04-16-2009 |
| 20090035926 | Methods of Fabricating Silicon Carbide Devices Incorporating Multiple Floating Guard Ring Edge Terminations - Edge termination for silicon carbide devices has a plurality of concentric floating guard rings in a silicon carbide layer that are adjacent and spaced apart from a silicon carbide-based semiconductor junction. An insulating layer, such as an oxide, is provided on the floating guard rings and a silicon carbide surface charge compensation region is provided between the floating guard rings and is adjacent the insulating layer. Methods of fabricating such edge termination are also provided. | 02-05-2009 |
| 20080220599 | Method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices - A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity. | 09-11-2008 |
| 438573000 | Multilayer electrode | 1 |
| 20110008953 | METHOD FOR MAKING SEMICONDUCTOR INSULATED-GATE FIELD-EFFECT TRANSISTOR HAVING MULTILAYER DEPOSITED METAL SOURCE(S) AND/OR DRAIN(S) - A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal. | 01-13-2011 |
| 438576000 | Into grooved or recessed semiconductor region | 3 |
| 20090111253 | METHOD FOR PRODUCING A TRANSISTOR GATE WITH SUB-PHOTOLITHOGRAPHIC DIMENSIONS - Methods of fabricating compound semiconductor devices are described. | 04-30-2009 |
| 438578000 | Forming electrode of specified shape (e.g., slanted, etc.) | 2 |
| 20090317965 | ELECTRICAL CONTACT FOR TERMINATING A COAXIAL CABLE - An electrical contact is provided for terminating an electrical conductor of a coaxial cable. The electrical contact includes a body having a first element extending between a cable receiving end portion and a contact portion. The first element includes a first surface configured to engage the electrical conductor. A second element extends from the cable receiving end portion of the first element. The second element includes a second surface configured to engage the electrical conductor. The first and second elements are configured to hold a portion of the electrical conductor therebetween such that the coaxial cable extends outwardly from the cable receiving end portion of the first element. | 12-24-2009 |
| 438579000 | T-shaped electrode | 1 |
| 20090075463 | METHOD OF FABRICATING T-GATE - A method of fabricating a T-gate is provided. The method includes the steps of: forming a photoresist layer on a substrate; patterning the photoresist layer formed on the substrate and forming a first opening; forming a first insulating layer on the photoresist layer and the substrate; removing the first insulating layer and forming a second opening to expose the substrate; forming a second insulating layer on the first insulating layer; removing the second insulating layer and forming a third opening to expose the substrate; forming a metal layer on the second insulating layer on which the photoresist layer and the third opening are formed; and removing the metal layer formed on the photoresist layer. Accordingly, a uniform and elaborate opening defining the length of a gate may be formed by deposition of the insulating layer and a blanket dry etching process, and thus a more elaborate micro T-gate electrode may be fabricated. | 03-19-2009 |
| 438580000 | Using platinum group metal (i.e., platinum (Pt), palladium (Pd), rhodium (Rh), ruthenium (Ru), iridium (Ir), osmium (Os), or alloy thereof) | 4 |
| 20130115765 | SEMICONDUCTOR DEVICE WITH BUFFER LAYER - A semiconductor device in one embodiment includes a depletion junction, a peripheral region adjacent the depletion junction, and a buffer layer. The buffer layer is adapted to reduce localization of avalanche breakdown proximate the interface between the depletion junction and the peripheral region. | 05-09-2013 |
| 438581000 | Silicide | 3 |
| 20120009771 | Implantless Dopant Segregation for Silicide Contacts - A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer. | 01-12-2012 |
| 20110159675 | PROCESS FOR FORMING SCHOTTKY RECTIFIER WITH PtNi SILICIDE SCHOTTKY BARRIER - A process for forming a Schottky barrier to silicon to a bather height selected at a value between 640 meV and 840 meV employs the deposition of a platinum or nickel film atop the silicon surface followed by the deposition of the other of a platinum or nickel film atop the first film. The two films are then exposed to anneal steps at suitable temperatures to cause their interdiffusion and a ultimate formation of Ni | 06-30-2011 |
| 20130130485 | METHOD FOR FABRICATING SCHOTTKY DEVICE - A method for fabricating a Schottky device includes the following sequences. First, a substrate with a first conductivity type is provided and an epitaxial layer with the first conductivity type is grown on the substrate. Then, a patterned dielectric layer is formed on the epitaxial layer, and a metal silicide layer is formed on a surface of the epitaxial layer. A dopant source layer with a second conductivity type is formed on the metal silicide layer, followed by applying a thermal drive-in process to diffuse the dopants inside the dopant source layer into the epitaxial layer. Finally, a conductive layer is formed on the metal silicide layer. | 05-23-2013 |
| 438582000 | Using refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof) | 3 |
| 20120129328 | MULTIPLE LAYER BARRIER METAL FOR DEVICE COMPONENT FORMED IN CONTACT TRENCH - A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer. | 05-24-2012 |
| 20130149850 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of preparing a substrate made of silicon carbide and having an n type region formed to include a main surface, forming a p type region in a region including the main surface, forming an oxide film on the main surface across the n type region and the p type region, by heating the substrate having the p type region formed therein at a temperature of 1250° C. or more, removing the oxide film to expose at least a part of the main surface, and forming a Schottky electrode in contact with the main surface that has been exposed by removing the oxide film. | 06-13-2013 |
| 438583000 | Silicide | 1 |
| 20090163005 | Schottky barrier source/drain N-MOSFET using ytterbium silicide - A method of fabricating an N-type Schottky barrier Source/Drain Transistor (N-SSDT) with ytterbium silicide (YbSi | 06-25-2009 |
