Class / Patent application number | Description | Number of patent applications / Date published |
438518000 | Of compound semiconductor | 38 |
20080286953 | Manufacturing method of semiconductor substrate, thin film transistor and semiconductor device - In manufacturing an SOI substrate, in a case where a step is present in a surface to be bonded, a substrate may warp and the contact area becomes small due to the step, an SOI layer having a desired shape cannot be obtained in some cases. However, the present invention provides an SOI substrate having a desired shape even when a step is produced on a surface to be bonded. Between steps on the surface to be bonded, dummy patterns | 11-20-2008 |
20110195563 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of manufacturing a silicon carbide semiconductor device according to the present invention includes the steps of (a) forming an implantation mask made up of a plurality of unit masks on a silicon carbide semiconductor layer, and (b) implanting predetermined ion in the silicon carbide semiconductor layer at a predetermined implantation energy by using the implantation mask. In the step (a), the implantation mask is formed such that a length from any point in the unit mask to an end of the unit mask can be equal to or less than a scattering length obtained when the predetermined ion is implanted in silicon carbide at the predetermined implantation energy and the implantation mask can have a plurality of regions different from each other in terms of a size and an arrangement interval of the unit masks. | 08-11-2011 |
20130045593 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide substrate having a surface is prepared. A coating film made of a first material is formed directly on the surface of the silicon carbide substrate. A mask layer made of a second material is formed on the coating film. The first material is higher in adhesiveness with silicon carbide than the second material. A first opening is formed in the mask layer. First impurity ions for providing a first conductivity type are implanted into the silicon carbide substrate by using ion beams passing through the first opening in the mask layer and through the coating film. | 02-21-2013 |
20130137254 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device has the following steps. A substrate having a silicon carbide layer of a first conductivity type is prepared. On the silicon carbide layer, a mask layer is formed. By ion implantation from above the mask layer, a well region of a second conductivity type is formed on the silicon carbide layer. At the step of forming the mask layer, the mask layer having an opening with a taper angle, which is an angle formed between a bottom surface and an inclined surface of mask layer, being larger than 60° and not larger than 80° is formed. Thus, a method of manufacturing a semiconductor device, capable of producing a semiconductor device having high degree of integration and high breakdown voltage, can be provided. | 05-30-2013 |
20130171811 | METHOD FOR MANUFACTURING COMPOUND SEMICONDUCTOR - In a method for manufacturing a compound semiconductor, a silicon oxide film is formed in an upper part of a substrate made of silicon. Subsequently, a base layer made of single crystal silicon to which ions are implanted is formed by performing ion implantation to a region of the substrate below the silicon oxide film and performing a thermal process. Then, the base layer is exposed by removing the silicon oxide film. Finally, a GaN layer is formed on the base layer. | 07-04-2013 |
20130237043 | SiC SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing an SiC semiconductor device according to the present invention includes the steps of (a) by using a single mask, etching regions of an SiC semiconductor layer which serve as an impurities implantation region and a mark region, to form recesses, (b) by using the same mask as in the step (a), performing ion-implantation in the recesses of the regions which serve as the impurities implantation region and the mark region, at least from an oblique direction relative to a surface of the SiC semiconductor layer and (c) positioning another mask based on the recess of the region which serves as the impurities implantation region or the mark region, and performing well implantation in a region containing the impurities implantation region. | 09-12-2013 |
20140363959 | SILICON CARBIDE SCHOTTKY-BARRIER DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a silicon carbide Schottky-barrier diode device and a method for manufacturing the same. The silicon carbide Schottky bather diode device includes a primary n− epitaxial layer, an n+ epitaxial region, and a Schottky metal layer. The primary n− epitaxial layer is deposited on an n+ substrate joined with an ohmic metal layer at an undersurface thereof. The n+ epitaxial region is formed by implanting n+ ions into a central region of the primary n− epitaxial layer. The Schottky metal layer is deposited on the n+ epitaxial layer. | 12-11-2014 |
438519000 | Including multiple implantation steps | 9 |
20090117722 | METHODS FOR FABRICATING SEMICONDUCTOR STRUCTURES - A method for fabricating a semiconductor structure includes forming a carbon masking layer on a semiconductor layer, forming a protective layer on the carbon masking layer. The method further includes forming an opening in the protective layer and the carbon masking layer and processing the semiconductor layer through the opening to form a first processed region in the semiconductor layer. The method further includes enlarging the opening in the carbon masking layer and performing an additional processing step on the semiconductor layer through the enlarged opening to form a second processed region in the semiconductor layer. | 05-07-2009 |
20090246948 | Method of Preparing P-Type Doped ZnO or ZnMgO - Method of preparing p-type doped ZnO or p-type doped ZnMgO, in which the following successive steps are carried out:
| 10-01-2009 |
20100048004 | SEMICONDUCTOR DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A production method for a semiconductor device includes the steps of: (a) providing a semiconductor substrate having a semiconductor layer | 02-25-2010 |
20100291762 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of manufacturing a silicon carbide semiconductor device is provided that includes a step of forming in a surface of a silicon carbide wafer of first conductivity type a first region of second conductivity type having a predetermined space thereinside by ion-implanting aluminum as a first impurity and boron as a second impurity; a step of forming a JTE region in the surface of the silicon carbide wafer from the first region by diffusing the boron ion-implanted in the first region toward its neighboring zones by an activation annealing treatment; a step of forming a first electrode on the surface of the silicon carbide wafer at the space inside the first region and at an inner part of the first region; and a step of forming a second electrode on the opposite surface of the silicon carbide wafer. Thereby, a JTE region can be formed that has a wide range of impurity concentration and a desired breakdown voltage without increasing the number of steps of the manufacturing process. | 11-18-2010 |
20110045663 | Field-effect transistor and method for fabricating the same - A field-effect transistor that increases the operation speeds of complementary field-effect transistors. Each of an nMOSFET and a pMODFET has a Ge channel and source and drain regions formed of an NiGe layer. The height of Schottky barriers formed at a junction between a channel region and the source region of the nMOSFET and at a junction between the channel region and the drain region of the nMOSFET is changed by very thin high-concentration segregation layers formed by making As atoms, Sb atoms, S atoms or the like segregate at the time of forming the NiGe layer. As a result, Schottky barrier height suitable for the nMOSFET and the pMODFET can be obtained, this being capable of realizing high-speed CMOSFETS. | 02-24-2011 |
20120184092 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide semiconductor device includes the step of forming a mask pattern of a silicon oxide film by removing a portion of the silicon oxide film by means of etching employing a gas containing oxygen gas and at least one fluorine compound gas selected from a group consisting of CF | 07-19-2012 |
20120315746 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - An impurity of a first conductivity type is implanted onto a silicon carbide substrate through an opening in a mask layer. First and second films made of first and second materials respectively are formed. It is sensed that etching of the first material is performed during anisotropic etching, and then anisotropic etching is stopped. An impurity of a second conductivity type is implanted onto the silicon carbide substrate through the opening narrowed by the first and second films. Thus, the impurity regions can be formed in an accurately self-aligned manner. | 12-13-2012 |
20140147997 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth, and a fifth semiconductor region, an insulating film, a control electrode, and a first and a second electrode. The first, the second, the third, the fourth and the fifth semiconductor region include silicon carbide. The first semiconductor region has a first impurity concentration, and has a first portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided between the first portion and the second semiconductor region. The fourth semiconductor region is provided between the first portion and the third semiconductor region. The fifth semiconductor region includes a first region provided between the first portion and the second semiconductor region, and has a second impurity concentration higher than the first impurity concentration. | 05-29-2014 |
438521000 | Using same conductivity-type dopant | 1 |
20160093495 | METHOD FOR PERFORMING ACTIVATION OF DOPANTS IN A GAN-BASE SEMICONDUCTOR LAYER BY SUCCESSIVE IMPLANTATIONS AND HEAT TREATMENTS - The method for performing activation of n-type or p-type dopants in a GaN-base semiconductor includes the following steps: providing a substrate including a GaN-base semiconductor material layer, performing the following successive steps at least twice: implanting electric dopant impurities in the semiconductor material layer, performing heat treatment so as to activate the electric dopant impurities in the semiconductor material layer, a cap layer covering the semiconductor material layer when the heat treatment is performed, two implantation steps of electric dopant impurities being separated by a heat treatment step. | 03-31-2016 |
438522000 | Including heat treatment | 21 |
20080254603 | Method of fabricating semiconductor device - There is provided a method of fabricating semiconductor devices that allows ion implantation to be performed at high temperature with ions accelerated with high energy to help to introduce dopant in a semiconductor substrate, in particular a SiC semiconductor substrate, at a selected region to sufficient depth. To achieve this the method includes the steps of: providing the semiconductor substrate at a surface thereof with a mask layer including a polyimide resin film, or a SiO | 10-16-2008 |
20080318400 | Method for manufacturing SIC semiconductor device - A method for manufacturing a SiC semiconductor device includes: forming an impurity layer in a SiC layer; and forming an oxide film on the SiC layer. The forming the impurity layer includes: implanting an impurity in the SiC layer; applying a cap layer on the SiC layer; annealing the cap layer to be transformed a carbon layer; annealing the SiC layer to activate the impurity; and removing the carbon layer. The annealing the SiC layer includes: increasing a temperature of the SiC layer from a second temperature to a first temperature within a first time duration; and decreasing the temperature of the SiC layer from the first temperature to the second temperature within a second time duration. The first temperature is equal to or higher than 1800° C., and the second temperature is lower than 1800° C. The first and second time durations are small. | 12-25-2008 |
20090042374 | METHOD OF GROWING A STRAINED LAYER - A method of forming a Si strained layer | 02-12-2009 |
20090042375 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of manufacturing a silicon carbide semiconductor device includes a step of ion-implanting an impurity in a surface of a silicon carbide wafer ( | 02-12-2009 |
20090170296 | METHOD AND APPARATUS FOR ACTIVATING COMPOUND SEMICONDUCTOR - A compound semiconductor is placed in a reaction vessel ( | 07-02-2009 |
20090186470 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR ELEMENT - A method of producing a silicon carbide semiconductor device, including: step (A) of forming an impurity-doped region by implanting impurity ions | 07-23-2009 |
20100093161 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - On one face of a semiconductor wafer | 04-15-2010 |
20110070723 | METHOD OF MANUFACTURING A SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of manufacturing a silicon carbide semiconductor device is disclosed in which a trench and a hole are controlled to have a predetermined configuration even if the silicon carbide semiconductor device is subjected to a heat treatment at a temperature of not lower than 1,500° C. A heat treatment step(s) of a method of the invention includes a step of heat treatment in an argon atmosphere at a temperature in a range of 1,600° C. to 1,800° C. under a pressure of at most 10 Torr for a time duration in a range of 0.1 min to 10 min to evaporate silicon atoms from a surface of the silicon carbide semiconductor substrate or the silicon carbide epitaxial layer and to obtain a silicon carbide surface with a carbon atom concentration of at least 95%. The method can further comprise a step of ion implantation of nitrogen ions or phosphorus ions in a dose amount of 8×10 | 03-24-2011 |
20110092057 | METHODS OF FABRICATING TRANSISTORS USING LASER ANNEALING OF SOURCE/DRAIN REGIONS - Fabrication of a Group III-nitride transistor device can include implanting dopant ions into a stacked Group III-nitride channel layer and Group III-nitride barrier layer to form source/drain regions therein with a channel region therebetween. The channel layer has a lower bandgap energy than the barrier layer along a heterojunction interface between the channel layer and the barrier layer. The source/drain regions have a lower defect centers energy than the channel region. The source/drain regions and the channel region are exposed to a laser beam with a wavelength having a photon energy that is less than the bandgap energy of the channel region and higher than the defect centers energy of the source/drain regions to locally heat the source/drain regions to a temperature that anneals the source/drain regions. | 04-21-2011 |
20120028452 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a silicon carbide semiconductor device, in order to obtain a smooth surface of silicon carbide while maintaining a high impurity activation rate, which includes a step of implanting an impurity into a surface layer of a silicon carbide substrate, a step of forming a carbon film on the surface of the silicon carbide substrate, a step of mounting the substrate on a sample stage of a susceptor disposed within the activation heat treatment furnace so that the carbon film and the susceptor are in contact with each other, and a step of performing an activation heat treatment on the silicon carbide substrate using the carbon film as a protective film. | 02-02-2012 |
20120028453 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - An object is to provide a method for manufacturing a silicon carbide semiconductor device in which a time required for removing a sacrificial oxide film can be shortened and damage to a surface of the silicon carbide layer can be reduced. The method for manufacturing a silicon carbide semiconductor device includes: (a) performing ion implantation to a silicon carbide layer; (b) performing activation annealing to the ion-implanted silicon carbide layer 2; (c) removing a surface layer of the silicon carbide layer 2, to which the activation annealing has been performed, by dry etching; (d) forming a sacrificial oxide film on a surface layer of the silicon carbide layer, to which the dry etching has been performed, by performing sacrificial oxidation thereto; and (e) removing the sacrificial oxide film by wet etching. | 02-02-2012 |
20120070968 | SUBSTRATE PROCESSING METHOD AND METHOD OF MANUFACTURING CRYSTALLINE SILICON CARBIDE (SIC) SUBSTRATE - The present invention provides a method of processing a substrate and a method of manufacturing a silicon carbide (SiC) substrate in which, when annealing processing is performed on a crystalline silicon carbide (SiC) substrate, the occurrence of surface roughness is suppressed. A substrate processing method according to an embodiment of the present invention includes a step of performing plasma irradiation on a single crystal silicon carbide (SiC) substrate ( | 03-22-2012 |
20120231618 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon nitride on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including a nitrogen atom. | 09-13-2012 |
20130040445 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A silicon carbide substrate having a surface is prepared. An impurity region is formed by implanting ions from the surface into the silicon carbide substrate. Annealing for activating the impurity region is performed. The annealing includes the step of applying first laser light having a first wavelength to the surface of the silicon carbide substrate, and the step of applying second laser light having a second wavelength to the surface of the silicon carbide substrate. The silicon carbide substrate has first and second extinction coefficients at the first and second wavelengths, respectively. A ratio of the first extinction coefficient to the first wavelength is higher than 5×10 | 02-14-2013 |
20130065382 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of manufacturing a silicon carbide semiconductor device of an embodiment includes: implanting ions in a silicon carbide substrate; performing first heating processing of the silicon carbide substrate in which the ions are implanted; and performing second heating processing of the silicon carbide substrate for which the first heating processing is performed, at a temperature lower than the first heating processing. | 03-14-2013 |
20140147998 | Ion Implantation at High Temperature Surface Equilibrium Conditions - There are disclosed herein various implementations of a method and system for ion implantation at high temperature surface equilibrium conditions. The method may include situating a III-Nitride semiconductor body in a surface equilibrium chamber, establishing a gas pressure greater than or approximately equal to a surface equilibrium pressure of the III-Nitride semiconductor body, and heating the III-Nitride semiconductor body to an elevated implantation temperature in the surface equilibrium chamber while substantially maintaining the gas pressure. The method also includes implanting the III-Nitride semiconductor body in the surface equilibrium at the elevated implantation temperature chamber while substantially maintaining the gas pressure, the implanting being performed using an ion implanter interfacing with the surface equilibrium chamber. | 05-29-2014 |
20140335684 | MANUFACTURING METHOD AND MANUFACTURING APPARATUS OF SEMICONDUCTOR DEVICE - A manufacturing method for a semiconductor device includes implanting dopants into a silicon carbide substrate, applying a carbon-containing material on at least one surface of the silicon carbide substrate, and heating the silicon carbide substrate having the carbon-containing material applied thereon to form a carbon layer on surfaces of the silicon carbide substrate. The heating is performed in a non-oxidizing atmosphere, and is followed by another heating step for activating the dopants. | 11-13-2014 |
20150017792 | METHOD AND SYSTEM FOR DIFFUSION AND IMPLANTATION IN GALLIUM NITRIDE BASED DEVICES - A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer. | 01-15-2015 |
20150099350 | ENABLING HIGH ACTIVATION OF DOPANTS IN INDIUM-ALUMINUM-GALIUM-NITRIDE MATERIAL SYSTEM USING HOT IMPLANTATION AND NANOSECOND ANNEALING - Embodiments of the present disclosure generally relate to doping and annealing substrates. The substrates may be doped during a hot implantation process, and subsequently annealed using a nanosecond annealing process. The combination of hot implantation and nanosecond annealing reduces lattice damage of the substrates and facilitates a higher dopant concentration near the surface of the substrate to facilitate increased electrical contact with the substrate. An optional capping layer may be placed over the substrate to reduce outgassing of dopants or to control dopant implant depth. | 04-09-2015 |
20150364325 | TECHNIQUES FOR INCREASED DOPANT ACTIVATION IN COMPOUND SEMICONDUCTORS - A method of doping a compound semiconductor substrate includes: setting a first substrate temperature for the compound semiconductor substrate in a first temperature range; implanting a dopant species into the compound semiconductor substrate at a first ion dose at the first substrate temperature; and annealing the compound semiconductor substrate after the implanting the ions. In conjunction with the annealing, the first ion dose is effective to generate a first dopant activation in the first temperature range higher than a second dopant activation resulting from implantation of the first ion dose at a second substrate temperature below the first temperature range, and is higher than a third dopant activation resulting from implantation of the first ion dose at a third substrate temperature above the first temperature range. | 12-17-2015 |
20160204000 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 07-14-2016 |
438523000 | And contact formation (i.e., metallization) | 1 |
20130288467 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (c) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer. | 10-31-2013 |