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Amorphous semiconductor

Subclass of:

438 - Semiconductor device manufacturing: process

438478000 - FORMATION OF SEMICONDUCTIVE ACTIVE REGION ON ANY SUBSTRATE (E.G., FLUID GROWTH, DEPOSITION)

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
438486000 And subsequent crystallization 87
438483000 Compound semiconductor 38
438485000 Deposition utilizing plasma (e.g., glow discharge, etc.) 5
20090233425PLASMA PROCESSING APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - By an evacuation unit including first and second turbo molecular pumps connected in series, the ultimate pressure in a reaction chamber is reduced to ultra-high vacuum. By a knife-edge-type metal-seal flange, the amount of leakage in the reaction chamber is reduced. A microcrystalline semiconductor film and an amorphous semiconductor film are stacked in the same reaction chamber where the pressure is reduced to ultra-high vacuum. By forming the amorphous semiconductor film covering the surface of the microcrystalline semiconductor film, oxidation of the microcrystalline semiconductor film is prevented.09-17-2009
20100068870High Speed Thin Film Deposition via Pre-Selected Intermediate - A method and apparatus for the unusually high rate deposition of thin film materials on a stationary or continuous substrate. The method includes delivery of a pre-selected precursor intermediate to a deposition chamber and formation of a thin film material from the intermediate. The intermediate is formed outside of the deposition chamber and includes a metastable species such as a free radical. The intermediate is pre-selected to include a metastable species conducive to the formation of a thin film material having a low defect concentration. By forming a low defect concentration material, deposition rate is decoupled from material quality and heretofore unprecedented deposition rates are achieved. In one embodiment, the pre-selected precursor intermediate is SiH03-18-2010
20100105195METHOD AND APPARATUS FOR FORMING A FILM BY DEPOSITION FROM A PLASMA - An apparatus is described for depositing a film on a substrate from a plasma. The apparatus comprises an enclosure, a plurality of plasma generator elements disposed within the enclosure, and means, also within the enclosure, for supporting the substrate. Each plasma generator element comprises a microwave antenna having an end from which microwaves are emitted, a magnet disposed in the region of the said antenna end and defining therewith an electron cyclotron resonance region in which a plasma can be generated, and a gas entry element having an outlet for a film precursor gas or a plasma gas. The outlet is arranged to direct gas towards a film deposition area situated beyond the magnet, as considered from the microwave antenna, the outlet being located in, or above, the hot electron confinement envelope.04-29-2010
20110189841FABRICATION OF LARGE GRAIN POLYCRYSTALLINE SILICON FILM BY NANO ALUMINUM-INDUCED CRYSTALLIZATION OF AMORPHOUS SILICON - One aspect of the present invention relates to a method for fabricating a polycrystalline silicon film. In one embodiment, the method includes the steps of providing a substrate having a thermally-grown silicon dioxide layer, forming an amorphous silicon film on the thermally-grown silicon dioxide layer of the substrate, forming an aluminum layer on the amorphous silicon film to form a structure having the substrate, the amorphous silicon film and the aluminum layer, and annealing the structure at an annealing temperature for a period of time in an N08-04-2011
20080299747METHOD FOR FORMING AMORPHOUSE SILICON FILM BY PLASMA CVD - A method includes introducing a silicon-containing source gas and a dilution gas to a reactor to deposit an amorphous silicon film on a substrate by plasma CVD; and adjusting a compressive film stress to 300 MPa or less and a uniformity of film thickness within the substrate surface to ±5% or less of the amorphous silicon film depositing on the substrate as a function of a flow rate of the source gas, a flow rate of the dilution gas, and a pressure of the reactor which are used as control parameters.12-04-2008
Entries
DocumentTitleDate
20100075485INTEGRATED EMITTER FORMATION AND PASSIVATION - Embodiments of the present invention provide a method for forming an emitter region in a crystalline silicon substrate and passivating the surface thereof by depositing a doped amorphous silicon layer onto the crystalline silicon substrate and thermally annealing the crystalline silicon substrate while oxidizing the surface thereof. In one embodiment, the deposited film is completely converted to oxide. In another embodiment, the doped amorphous silicon layer deposited onto the crystalline silicon substrate is converted into crystalline silicon having the same grain structure and crystal orientation as the underlying crystalline silicon substrate upon which the amorphous silicon was initially deposited during emitter formation. In one embodiment, at least a portion of the converted crystalline silicon is further converted into silicon dioxide during the emitter surface passivation.03-25-2010
20130084693THIN FILM FORMING METHOD AND FILM FORMING APPARATUS - A thin film forming method which forms a seed film and an impurity-containing silicon film on a surface of an object to be processed in a processing container configured to be vacuum exhaustible includes: performing a first step which forms the seed film by supplying a seed film raw material gas including at least any one of an aminosilane-based gas and a higher silane into the processing container; and performing a second step which forms the impurity-containing silicon film in an amorphous state by supplying a silane-based gas and an impurity-containing gas into the processing container.04-04-2013
20090142909METHOD FOR MANUFACTURING MICROCRYSTALLINE SEMICONDUCTOR FILM, THIN FILM TRANSISTOR HAVING MICROCRYSTALLINE SEMICONDUCTOR FILM, AND PHOTOELECTRIC CONVERSION DEVICE HAVING MICROCRYSTALLINE SEMICONDUCTOR FILM - A method for forming a microcrystalline semiconductor film over a base formed of a different material, which has high crystallinity in the entire film and at an interface with the base, is proposed. Further, a method for manufacturing a thin film transistor including a microcrystalline semiconductor film with high crystallinity is proposed. Furthermore, a method for manufacturing a photoelectric conversion device including a microcrystalline semiconductor film with high crystallinity is proposed. By forming crystal nuclei with high density and high crystallinity over a base film and then growing crystals in a semiconductor from the crystal nuclei, a microcrystalline semiconductor film which has high crystallinity at an interface with the base film, which has high crystallinity in crystal grains, and which has high adhesion between the adjacent crystal grains is formed.06-04-2009
20130029480FREE FORM PRINTING OF SILICON MICRO- AND NANOSTRUCTURES - A method of making a three-dimensional structure in semiconductor material includes providing a substrate (01-31-2013
20090111249Multilevel Phase Change Memory - A multilevel phase change memory may be formed of a chalcogenide material formed between a pair of spaced electrodes. The cross-sectional area of the chalcogenide material may decrease as the material extends from one electrode to another. As a result, the current density decreases from one electrode to the other. This means that a higher current is necessary to convert the material that has the largest cross-sectional area. As a result, different current levels may be utilized to convert different amounts of the chalcogenide material to the amorphous or reset state. A distinguishable resistance may be associated with each of those different amounts of amorphous material, providing the opportunity to engineer a number of different current selectable programmable states.04-30-2009
20090233424THIN FILM METAL OXYNITRIDE SEMICONDUCTORS - The present invention generally relates to a semiconductor film and a method of depositing the semiconductor film. The semiconductor film comprises oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, cadmium, gallium, indium, and tin. Additionally, the semiconductor film may be doped. The semiconductor film may be deposited by applying an electrical bias to a sputtering target comprising the one or more elements selected from the group consisting of zinc, cadmium, gallium, indium, and tin, and introducing a nitrogen containing gas and an oxygen containing gas. The sputtering target may optionally be doped. The semiconductor film has a mobility greater than amorphous silicon. After annealing, the semiconductor film has a mobility greater than polysilicon.09-17-2009
20090011576Ultra-Violet Protected Tamper Resistant Embedded EEPROM - A pre-metal dielectric structure of a single-poly EEPROM structure includes a UV light-absorbing film, which prevents the charge on a floating gate of the EEPROM structure from being changed in response to UV radiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer, an amorphous silicon layer located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the amorphous silicon layer.01-08-2009
20100035417METHOD OF FABRICATING POLYCRYSTALLINE SILICON THIN FILM - The present invention relates to a method of depositing a polycrystalline silicon thin film within a single chamber through a chemical vapor deposition (CVD) process employing a single wafer technique. Particularly, a fine crystalline structure of the polycrystalline silicon thin film is formed in a columnar shape by using SiH02-11-2010
20090098716METHOD FOR MAKING A SELF-CONVERGED MEMORY MATERIAL ELEMENT FOR MEMORY CELL - A self-converged memory material element is created during the manufacture of a memory cell comprising a base layer, with a bottom electrode, and an upper layer having a third, planarization stop layer over the base layer, a second layer over the third layer, and the first layer over the second layer. A keyhole opening is formed through the upper layer to expose the bottom electrode. The first layer has an overhanging portion extending into the opening. A dielectric material is deposited into the keyhole opening so to create a self-converged void within the keyhole opening. An anisotropic etch forms a sidewall of the dielectric material in the keyhole opening with an electrode hole aligned with the void and exposing the bottom electrode. A memory material is deposited into the electrode hole in contact with the bottom electrode and is planarized down to the third layer to create the memory material element.04-16-2009
20110263106Process for Eliminating Delamination between Amorphous Silicon Layers - One embodiment is a method of forming a circuit structure. The method comprises forming a first amorphous layer over a substrate; forming a first glue layer over and adjoining the first amorphous layer; forming a second amorphous layer over and adjoining the first glue layer; and forming a plurality of posts separated from each other by removing a first portion of the first amorphous layer and a first portion of the second amorphous layer. At least some of the plurality of posts each comprises a second portion of the first amorphous layer, a first portion of the first glue layer, and a second portion of the second amorphous layer.10-27-2011
20110263105AMORPHOUS SILICON FILM FORMATION METHOD AND AMORPHOUS SILICON FILM FORMATION APPARATUS - The amorphous silicon film formation method includes forming a seed layer on the surface of a base by heating the base and flowing aminosilane-based gas onto the heated base; and forming an amorphous silicon film on the seed layer by heating the base, supplying silane-based gas containing no amino group onto the seed layer on the surface of the heated base, and thermally decomposing the silane-based gas containing no amino group.10-27-2011
20090087964Manufacturing Method of Semiconductor Device and Substrate Processing Apparatus - To realize a high productivity while maintaining excellent film deposition characteristics on a substrate even if a plurality of processing gases of different gas species are used. There are provided the step of loading a plurality of substrates into a processing chamber; supplying a first processing gas to an upper stream side of a gas flow outside of a region where a plurality of substrates loaded into a processing chamber are arranged, supplying a second processing gas to the upper stream side of the gas flow outside of the region where the plurality of substrates loaded into the processing chamber are arranged, supplying the first processing gas to a middle part of the gas flow in the region where the plurality of substrates loaded into the processing chamber are arranged, and causing the first processing gas and the second processing gas to react with each other in the processing chamber, to form an amorphous material and form a thin film on main surfaces of the plurality of substrates; and the step of unloading the substrate after forming the thin film from the processing camber.04-02-2009
20110223747METHOD FOR PRODUCING POLYCRYSTALLINE LAYERS - In a method for producing polycrystalline layers a sequence of layers is deposited on a substrate (09-15-2011
20090061601METHOD AND APPARATUS FOR IMPROVED PUMPING MEDIUM FOR ELECTRO-OSMOTIC PUMPS - Various embodiments of the present invention comprise systems and methods of fabricating porous silicon. One application of such porous silicon is in the fabrication of electro-osmotic pumps and electro-osmotic pump substrates. The method can comprise operations performed on a silicon wafer. A liner material can be deposited on the silicon wafer, and a photoresist layer can be deposited on the liner material. The photoresist layer can be adapted to define a predetermined pattern on the silicon wafer. Then, porous silicon can be formed on the silicon wafer according to the predefined pattern. As a result, solid silicon can support porous silicon regions of the silicon wafer, providing a support structure for the pumping medium. Other embodiments, aspects, and features are also claimed and described.03-05-2009
20090104756METHOD TO FORM A REWRITEABLE MEMORY CELL COMPRISING A DIODE AND A RESISTIVITY-SWITCHING GROWN OXIDE - A method is described to form a rewriteable memory cell including a diode and an oxide layer, wherein the resistivity of the oxide layer can be reversibly switched. In preferred embodiments, the oxide layer is a grown oxide. The diode is preferably formed of polysilicon which has been crystallized in contact with a silicide which has a close lattice match to silicon. The silicide provides a crystallization template such that the polysilicon is large-grained with few defects, and thus relatively low-resistivity. In preferred embodiments, a monolithic three dimensional memory array can be formed, in which multiple memory levels of such rewriteable memory cells are monolithically formed vertically stacked above a substrate.04-23-2009
20090258477METHODS OF FORMING PHASE-CHANGE MEMORY UNITS, AND METHODS OF MANUFACTURING PHASE-CHANGE MEMORY DEVICES USING THE SAME - In a method of forming a phase-change memory unit, a conductive layer is formed on a substrate having a trench. The conductive layer is planarized until the substrate is exposed to form a first electrode. A spacer partially covering the first electrode is formed. A phase-change material layer is formed on the first electrode and the second spacer. A second electrode is formed on the phase-change material layer. Reset/set currents of the phase-change memory unit may be reduced and deterioration of the phase-change material layer may be reduced and/or prevented.10-15-2009
20100184275Semiconductor device and method for manufacturing the same - A semiconductor device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film comprising a plurality of insulating films provided on the charge storage layer and comprising a nitride film as an uppermost layer, and a single-layer control gate electrode provided on the second insulating film and comprising metal silicide.07-22-2010
20100159675METHOD FABRICATING NONVOLATILE MEMORY DEVICE - A method of fabricating a nonvolatile memory device includes; forming a first sacrificial layer pattern including a first open area that extends in a first direction on a lower dielectric layer, forming a pre-lower dielectric layer pattern including a recess that extends in the first direction using the first sacrificial layer pattern, forming a second sacrificial layer pattern including a second open area that extends in a second direction on the pre-lower dielectric layer pattern and the first sacrificial layer pattern, wherein the second open area intersects the first open area, forming a lower dielectric layer pattern including contact holes spaced apart in the recess using the first sacrificial layer pattern and second sacrificial layer pattern, wherein the contact holes extend to a bottom of the lower dielectric layer pattern, and forming a bottom electrode in the contact hole.06-24-2010
20100151665SMALL ELECTRODE FOR PHASE CHANGE MEMORIES - A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a memory cell, which in turn includes an electrode and a phase change material. The electrode may be disposed on a substrate and include a sublithographic lateral dimension parallel to the substrate. The phase change material may be coupled to the electrode and include a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the electrode. Various semiconductor devices and manufacturing methods are also provided.06-17-2010
20090291546Programmable Via Devices - A device comprises a heater, a dielectric layer, a phase-change element, and a capping layer. The dielectric layer is disposed at least partially on the heater and defines an opening having a lower portion and an upper portion. The phase-change element occupies the lower portion of the opening and is in thermal contact with the heater. The capping layer overlies the phase-change element and occupies the upper portion of the opening. At least a fraction of the phase-change element is operative to change between lower and higher electrical resistance states in response to an application of an electrical signal to the heater.11-26-2009
20100197120Forming Phase Change Memory Cell With Microtrenches - A semiconductor substrate is covered by a dielectric region. The dielectric region accommodates a memory element and a selection element forming a phase change memory cell. The memory element is formed by a resistive element and by a storage region of a phase change material extending on and in contact with the resistive element at a contact area. The selection element is formed by a switching region of chalcogenic material embedded in the dielectric region and belonging to a stack extending on the resistive element and including also the storage region. A mold region extends on top of the resistive element and delimits a trench having a substantially elongated shape. At least one portion of the storage region extends in the trench and defines a phase change memory portion over the contact area.08-05-2010
20130143395STABLE AMORPHOUS METAL OXIDE SEMICONDUCTOR - A thin film semiconductor device has a semiconductor layer including a mixture of an amorphous semiconductor ionic metal oxide and an amorphous insulating covalent metal oxide. A pair of terminals is positioned in communication with the semiconductor layer and define a conductive channel, and a gate terminal is positioned in communication with the conductive channel and further positioned to control conduction of the channel. The invention further includes a method of depositing the mixture including using nitrogen during the deposition process to control the carrier concentration in the resulting semiconductor layer.06-06-2013
20100009522Method for Forming Chalcogenide Switch with Crystallized Thin Film Diode Isolation - A three-dimensional memory array formed of one or more two-dimensional memory arrays of one-time programmable memory elements arranged in horizontal layers and stacked vertically upon one another; and a two-dimensional memory array of reprogrammable phase change memory elements stacked on the one or more two-dimensional memory arrays as the top layer of the three-dimensional memory array.01-14-2010
20110212605METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT AND DEPOSITION APPARATUS - An object of the present invention is to provide an apparatus for successive deposition used for manufacturing a semiconductor element including an oxide semiconductor in which impurities are not included. By using the deposition apparatus capable of successive deposition of the present invention that keeps its inside in high vacuum state, and thus allows films to be deposited without being exposed to the air, the entry of impurities such as hydrogen into the oxide semiconductor layer and the layer being in contact with the oxide semiconductor layer can be prevented; as a result, a semiconductor element including a high-purity oxide semiconductor layer in which hydrogen concentration is sufficiently reduced can be manufactured. In such a semiconductor element, off-state current is low, and a semiconductor device with low power consumption can be realized.09-01-2011
20120202339Semiconductor stacking layer and fabricating method thereof - A fabricating method of a semiconductor stacking layer includes following steps. First, an amorphous silicon (α-Si) layer is formed on a substrate. Surface treatment is then performed on a surface of the α-Si layer. After that, a doped microcrystalline silicon (μc-Si) layer is formed on the treated surface of the α-Si layer, wherein interface defects existing between the α-Si layer and the doped μc-Si layer occupy an area in a cross-sectional region having a width of 1.5 micrometers and a thickness of 40 nanometers, and a ratio of the occupied area in the cross-sectional region is equal to or less than 10%. The method of fabricating the semiconductor stacking layer can be applied to a fabrication process of a semiconductor device to effectively reduce the interface defects of the semiconductor stacking layer.08-09-2012
20120302047METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH PARTIALLY OPEN SIDEWALL - A method for fabricating a semiconductor device includes forming a structure having first surfaces at a height above a second surface, which is provided between the first surfaces, forming a first silicon layer on the structure, performing a tilt ion implantation process on the first silicon layer to form a crystalline region and an amorphous region, forming a second silicon layer on the amorphous region, removing the second silicon layer and the first silicon layer until a part of the second surface is exposed, thereby forming an etch barrier, and etching using the etch barrier to form an open part that exposes a part of a sidewall of the structure.11-29-2012
20110306188MANUFACTURING METHOD OF SILICON CARBIDE SEMICONDUCTOR DEVICE - In a manufacturing method of a silicon carbide semiconductor device, a semiconductor substrate made of single crystal silicon carbide is prepared, an amorphous layer is formed on a portion of the semiconductor substrate where an electrode is to be formed, a metal layer is formed on the amorphous layer, and the electrode including the metal layer and a silicide layer is formed by irradiating the metal layer with a laser light in such a manner that a part of the metal layer reacts with the amorphous layer and forms the silicide layer.12-15-2011
20090029533METHOD OF CONTROLLING FILM STRESS IN MEMS DEVICES - A structural film, typically of silicon, in MEMS or NEMS devices is fabricated by depositing the film in the presence of a gas other than nitrogen, and preferably argon as the carrier gas.01-29-2009
20120040518Plasma Deposition of Amorphous Semiconductors at Microwave Frequencies - Apparatus and method for plasma deposition of thin film photovoltaic materials at microwave frequencies. The apparatus inhibits deposition on windows or other microwave transmission elements that couple microwave energy to deposition species. The apparatus includes a microwave applicator with conduits passing therethrough that carry deposition species. The applicator transfers microwave energy to the deposition species to transform them to a reactive state conducive to formation of a thin film material. The conduits physically isolate deposition species that would react to form a thin film material at the point of microwave power transfer. The deposition species are separately energized and swept away from the point of power transfer to prevent thin film deposition. The invention allows for the ultrafast formation of silicon-containing amorphous semiconductors that exhibit high mobility, low porosity, little or no Staebler-Wronski degradation, and low defect concentration.02-16-2012
20120015506TWO TERMINAL RESISTIVE SWITCHING DEVICE STRUCTURE AND METHOD OF FABRICATING - A method of forming a two terminal device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a first side region, and a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms an opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element. A top wiring material including a conductive material is formed overlying at lease the opening region such that the conductive material is in direct contact with the switching element. A second etching process is performed to form at least a top wiring structure. In a specific embodiment, the side region of the first structure including a first side region of the switching element is free from a contaminant conductive material from the second etching process.01-19-2012
20120064703MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - An object is to provide a technique by which a semiconductor device including a high-performance and high-reliable transistor is manufactured. A protective conductive film which protects an oxide semiconductor layer when a wiring layer is formed from a conductive layer is formed between the oxide semiconductor layer and the conductive layer, and an etching process having two steps is performed. In a first etching step, an etching is performed under conditions that the protective conductive film is less etched than the conductive layer and the etching selectivity of the conductive layer to the protective conductive film is high. In a second etching step, etching is performed under conditions that the protective conductive film is more easily etched than the oxide semiconductor layer and the etching selectivity of the protective conductive film to the oxide semiconductor layer is high.03-15-2012
20100197119Resistor Random Access Memory Cell Device - A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode. Also, methods for making the memory cell device include steps of forming a bottom electrode island including an insulative element and a stop element over a bottom electrode, forming a separation layer surrounding the island, removing the stop element to form a hole over the insulative element in the separation layer, forming a conductive film in the hole and an insulative liner over conductive film, etching to form a cup-shaped conductive film having a rim and to form an opening through the insulative liner and the bottom of the cup-shaped conductive film to the surface of the bottom electrode, forming a plug of phase change memory material in the opening, and forming a top electrode in contact with the rim of the cup-shaped conductive film.08-05-2010
20110104879METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - Provided are a method of manufacturing a semiconductor device and a substrate processing apparatus, which can improve the surface roughness of an amorphous silicon film. The method of manufacturing a semiconductor device comprises: in a process of forming an amorphous silicon film on a substrate, setting, in an initial stage of the process, an in-furnace pressure to a first pressure to supply SiH05-05-2011
20120315744Reduction of Edge Effects from Aspect Ratio Trapping - A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduce edge effects in semiconductor devices. Embodiments of the invention can provide a planar surface over a buffer layer between a plurality of uncoalesced ART structures.12-13-2012
20110159669METHOD FOR DEPOSITING AMORPHOUS SILICON THIN FILM BY CHEMICAL VAPOR DEPOSITION - Provided is a method of depositing an amorphous silicon thin film by chemical vapor deposition (CVD) to prevent bubble defect occurring when an amorphous silicon thin film is deposited on a substrate contaminated by air exposure. The deposition method includes cleaning a surface of the contaminated substrate with a reaction gas activated by plasma and depositing an amorphous silicon thin film on the cleaned substrate. Here, a vacuum state is maintained from the substrate cleaning step to the thin film deposition step in order to prevent contamination of the surface of the cleaned substrate by re-exposure to air.06-30-2011
20130023110METHOD AND APPARATUS FOR FORMING AMORPHOUS SILICON FILM - A method of forming an amorphous silicon film includes: forming a seed layer on a surface of a base by heating the base and supplying an amino silane-based gas to the heated base, forming the amorphous silicon film with thickness for layer growth on the seed layer by heating the base and supplying a silane-based gas containing no amino group to the seed layer on the surface of the heated base, and decreasing a film thickness of the amorphous silicon film by etching the amorphous silicon film formed with thickness for layer growth.01-24-2013
20110212606Method of Fabricating Thin Film Transistor Structure - A method of fabricating a thin film transistor (TFT) is provided. The method comprises the steps of providing a substrate with a gate electrode formed thereon; forming an insulating layer on the substrate and covering the gate electrode; forming an intrinsic amorphous silicon layer (intrinsic a-Si layer) on the insulating layer; forming an etch-stop layer on the intrinsic amorphous silicon layer, and the etch-stop layer positioned correspondingly to the gate electrode; treating the etch-stop layer to form an oxide layer, and the oxide layer covering the etch-stop layer; forming a n+ a-Si layer above the intrinsic amorphous silicon layer, and the n+ a-Si layer covering partial surface of the etch-stop layer and the oxide layer separating a sidewall of the etch-stop layer and the n+ a-Si layer; and forming a conductive layer on the n+ a-Si layer.09-01-2011

Patent applications in class Amorphous semiconductor

Patent applications in all subclasses Amorphous semiconductor