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FORMATION OF SEMICONDUCTIVE ACTIVE REGION ON ANY SUBSTRATE (E.G., FLUID GROWTH, DEPOSITION)

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438 - Semiconductor device manufacturing: process

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Class / Patent application numberDescriptionNumber of patent applications / Date published
438479000 On insulating substrate or layer 181
438482000 Amorphous semiconductor 167
438507000 Fluid growth from gaseous state combined with subsequent diverse operation 63
438488000 Polycrystalline semiconductor 49
438503000 Fluid growth from gaseous state combined with preceding diverse operation 40
438493000 Plural fluid growth steps with intervening diverse operation 36
438492000 Fluid growth step with preceding and subsequent diverse operation 28
438500000 Fluid growth from liquid combined with subsequent diverse operation 17
438497000 Fluid growth from liquid combined with preceding diverse operation 3
20080242063Solder composition doped with a barrier component and method of making same - A solder composition and a method of making the composition. The solder composition comprises a Sn-containing base material and a barrier component having a reactivity with Sn which is higher than a reactivity of Ni or Cu with Sn, the barrier component being present in the composition in an amount sufficient to reduce a reactivity of Sn with both Ni and Cu.10-02-2008
20100009525METHOD INCLUDING PRODUCING A MONOCRYSTALLINE LAYER - A method including producing a monocrystalline layer is disclosed. A first lattice constant on a monocrystalline substrate has a second lattice constant at least in a near-surface region. The second lattice constant is different from the first lattice constant. Lattice matching atoms are implanted into the near-surface region. The near-surface region is momentarily melted. A layer is epitaxially deposited on the near-surface region that has solidified in monocrystalline fashion.01-14-2010
20100041216METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE - The present invention relates to a method of forming a nitride semiconductor substrate. This method includes steps of providing a substrate and then forming an epitaxy layer on the substrate. A patterned mask layer is formed on the epitaxy layer, wherein the patterned mask layer exposes a portion of the epitaxy layer. Next, an oxidation process is performed to oxidize the exposed epitaxy layer so as to form a plurality of dislocation blocking structures. The patterned mask layer is then removed. Further, a nitride semiconductor layer is formed on the epitaxy layer having the dislocation blocking structures.02-18-2010
Entries
DocumentTitleDate
20110177681Method of Producing High Quality Relaxed Silicon Germanium Layers - A method for minimizing particle generation during deposition of a graded Si07-21-2011
20110177677METHOD OF THIN FILM EPITAXIAL GROWTH USING ATOMIC LAYER DEPOSITION - A method of thin film epitaxial growth using atomic layer deposition is provided by introducing a first deposition precursor and a second deposition precursor into a chamber after a vent valve connected between the chamber and a vacuum pump is closed. The chamber is maintained in a thermal equilibrium state and a constant pressure as a result of keeping the first deposition precursor and the second deposition precursor inside the chamber thereby reducing deposition precursors consumption and achieving thin film epitaxial growth on the substrate.07-21-2011
20090203196Fabrication of metallic hollow nanoparticles - Metal and semiconductor nanoshells, particularly transition metal nanoshells, are fabricated using dendrimer molecules. Metallic colloids, metallic ions or semiconductors are attached to amine groups on the dendrimer surface in stabilized solution for the surface seeding method and the surface seedless method, respectively. Subsequently, the process is repeated with additional metallic ions or semiconductor, a stabilizer, and NaBH08-13-2009
20090047773METHOD OF FORMING STABLE FUNCTIONALIZED NANOPARTICLES - A novel top-down procedure for synthesis of stable passivated nanoparticles uses a one-step mechanochemical process to form and passivate the nanoparticles. High-energy ball milling (HEBM) can advantageously be used to mechanically reduce the size of material to nanoparticles. When the reduction of size occurs in a reactive medium, the passivation of the nanoparticles occurs as the nanoparticles are formed. This results in stable passivated silicon nanoparticles. This procedure can be used, for example in the synthesis of stable alkyl- or alkenyl-passivated silicon and germanium nanoparticles. The covalent bonds between the silicon or germanium and the carbon in the reactive medium create very stable nanoparticles.02-19-2009
20120184090METHOD OF FABRICATING SINGLE CRYSTAL GALLIUM NITRIDE SEMICONDUCTOR SUBSTRATE, NITRIDE GALLIUM SEMICONDUCTOR SUBSTRATE AND NITRIDE SEMICONDUCTOR EPITAXIAL SUBSTRATE - A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more single crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction of a predetermined axis. Each predetermined plane is inclined to the predetermined axis. Each substrate has a mirror polished primary surface. The primary surface has a first area and a second area. The first area is between an edge of the substrate and a line 3 millimeter away from the edge. The first area surrounds the second area. An axis perpendicular to the primary surface forms an off-angle with c-axis of the substrate. The off-angle takes a minimum value at a first position in the first area of the primary surface.07-19-2012
20120184089Organic Semiconductors - A semiconducting compound comprising the structure:07-19-2012
20120184088Method for Selective Deposition of a Semiconductor Material - A method for selective deposition of semiconductor materials in semiconductor processing is disclosed. In some embodiments, the method includes providing a patterned substrate comprising a first region and a second region, where the first region comprises an exposed first semiconductor material and the second region comprise an exposed insulator material. The method further includes selectively providing a film of the second semiconductor material on the first semiconductor material of the first region by providing a precursor of a second semiconductor material, a carrier gas that is not reactive with chlorine compounds, and tin-tetrachloride (SnCl07-19-2012
20120184087METHOD OF MANUFACTURING LACQUER USING INKJET PRINTING - A method of manufacturing a semiconductor device is provided. The method includes providing a transparent substrate having predefined active regions and non-active regions. Thereafter, the method includes spraying droplets of a lacquer on the predefined active regions to form corresponding lacquer layer regions, such that the non-active regions do not have presence of the lacquer. The lacquer layer regions are of a predefined thickness to enable their functional texturing. Texturing of lacquer layer enables light trapping or light extraction. Thereafter, one or more semiconductor layers are deposited o the lacquer layer regions and a cover substrate is provided. The cover substrate is joined to the transparent substrate at a portion of the non-active regions and encapsulates the lacquer layer regions and the one or more semiconductor layers between itself and the transparent substrate.07-19-2012
20100015786VAPOR GROWTH APPARATUS, VAPOR GROWTH METHOD, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A vapor growth apparatus forming a film on a substrate using a first source gas and a second source gas different form the first source gas, includes: a reaction chamber in which the substrate is disposed; a first source gas introduction path that communicates with the reaction chamber and introduces the first source gas; a second source gas introduction path that communicates with the reaction chamber and introduces the second source gas; and a separation gas introduction path that communicates with the reaction chamber between the first source gas introduction path and the second source gas introduction path and introduces a separation gas. The separation gas has a reaction rate with the first source gas and a reaction rate with the second source gas lower than the reaction rate between the first source gas and the second source gas.01-21-2010
20100151659Method of forming core-shell type structure and method of manufacturing transistor using the same - Example embodiments relate to a method of forming a core-shell structure. According to a method, a region in which the core-shell structure will be formed is defined on a substrate, and a core and a shell layer may be sequentially stacked in the defined region. A first shell layer may further be formed between the substrate and the core. When the core and the shell layer are sequentially stacked in the core-shell region, the method may further include forming a groove on the substrate, forming the first shell layer covering surfaces of the groove, forming the core in the groove of which surfaces are covered by the first shell layer, and forming a second shell layer covering the core.06-17-2010
20100035410Method for Manufacturing InGaN - To provide a method for manufacturing InGaN which causes less segregation of In and achieves high crystallinity of an InGaN layer with the proportion of In increased.02-11-2010
20090253247Method for manufacturing iron silicide nano-wires - A method for making iron silicide nano-wires comprises the following steps. Firstly, providing a growing substrate and a growing device, the growing device comprising a heating apparatus and a reacting room. Secondly, placing the growing substrate and a quantity of iron powder into the reacting room. Thirdly, introducing a silicon-containing gas into the reacting room. Finally, heating the reacting room to a temperature of 600-1200° C.10-08-2009
20100075483METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - A method for manufacturing a nitride semiconductor device, includes forming a p-type nitride semiconductor layer on a substrate, from an organic metal compound as a group III element source material, ammonia and a hydrazine derivative as group V element source materials, and a Mg source material gas as a p-type impurity source material. The flow velocity of the source material gases including the group III element source material, the group V element source materials, and the p-type impurity source material is more than 0.2 m/sec.03-25-2010
20120244684FILM-FORMING APPARATUS AND METHOD - A film-forming apparatus and method is provided that includes a reflector and insulator capable of suppressing the thermal degradation of components in close proximity to the heater in a film-forming apparatus. In a film-forming apparatus the reflector is used in combination with insulator. Specifically, in a film-forming apparatus a reflector is disposed below a heater with the insulator placed below the reflector. The insulator absorbs the radiant heat from the heater thus suppressing an excessive rise in temperature around the heater, it is therefore possible to prevent thermal degradation of components in close proximity of the heater. For example, when the temperature of a semiconductor substrate is 1650° C., the temperature of the quartz heater base maybe about 1000° C. This is lower than the softening point temperature of the quartz heater base, preventing deformation of the heater base.09-27-2012
20130078786HEAT TREATMENT METHOD FOR PROMOTING CRYSTALLIZATION OF HIGH DIELECTRIC CONSTANT FILM - A film of silicon dioxide is formed on the silicon-germanium layer, and a high dielectric constant film is further formed on the film of silicon dioxide. First irradiation from a flash lamp is performed on the semiconductor wafer to increase the temperature of a front surface of the semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 3 milliseconds to 1 second. Subsequently, second irradiation from the flash lamp is performed to maintain the temperature of the front surface of the semiconductor wafer within a ±25° C. range around the target temperature for a time period in the range of 3 milliseconds to 1 second. This promotes the crystallization of the high dielectric constant film while suppressing the alleviation of distortion in the silicon-germanium layer.03-28-2013
20100035412PRECISELY POSITIONED NANOWHISKERS AND NANOWHISKER ARRAYS AND METHOD FOR PREPARING THEM - A nanoengineered structure comprising an array of more than about 1000 nanowhiskers on a substrate in a predetermined spatial configuration, for use for example as a photonic band gap array, wherein each nanowhisker is sited within a distance from a predetermined site not greater than about 20% of its distance from its nearest neighbour. To produce the array, an array of masses of a catalytic material are positioned on the surface, heat is applied and materials in gaseous form are introduced such as to create a catalytic seed particle from each mass, and to grow, from the catalytic seed particle, epitaxially, a nanowhisker of a predetermined material, and wherein each mass upon melting, retains approximately the same interface with the substrate surface such that forces causing the mass to migrate across said surface are less than a holding force across a wetted interface on the substrate surface.02-11-2010
20130084689Trap Rich Layer Formation Techniques for Semiconductor Devices - A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.04-04-2013
20130084691BEAM HOMOGENIZER, LASER IRRADIATION APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention is to provide a beam homogenizer, a laser irradiation apparatus, and a method for manufacturing a semiconductor device, which can suppress the loss of a laser beam and form a beam spot having homogeneous energy distribution constantly on an irradiation surface without being affected by beam parameters of a laser beam. A deflector is provided at an entrance of an optical waveguide or a light pipe used for homogenizing a laser beam emitted from a laser oscillator. A pair of reflection planes of the deflector is provided so as to have a tilt angle to an optical axis of the laser beam, whereby the entrance of the optical waveguide or the light pipe is expanded. Accordingly, the loss of the laser beam can be suppressed. Moreover, by providing an angle adjusting mechanism to the deflector, a beam spot having homogeneous energy distribution can be formed at an exit of the optical waveguide.04-04-2013
20130084690MANUFACTURING APPARATUS AND METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device manufacturing apparatus includes a chamber in which a wafer is loaded; a first gas supply unit for supplying a process gas into the chamber; a gas exhaust unit for exhausting a gas from the chamber; a wafer support member on which the wafer is placed; a ring on which the wafer support member is placed; a rotation drive control unit connected to the ring to rotate the wafer; a heater disposed in the ring and comprising a heater element for heating the wafer to a predetermined temperature and including an SiC layer on at least a surface, and a heater electrode portion molded integrally with a heater element and including an SiC layer on at least a surface; and a second gas supply unit for supplying an SiC source gas into the ring.04-04-2013
20130084688MULTI-LAYER PATTERN FOR ALTERNATE ALD PROCESSES - A method of patterning a substrate. A sacrificial film is formed over a substrate and a pattern created therein. A first spacer layer is conformally deposited over the patterned sacrificial film and at least one horizontal portion of the first spacer layer is removed while vertical portions of the first spacer layer remain. A second spacer layer is conformally deposited over the patterned sacrificial film and the remaining portions of the first spacer layer. At least one horizontal portion of the second spacer layer is removed while vertical portions of the second spacer layer remain. Conformal deposition of the first and second spacer layers is optionally repeated one or more times. Conformal deposition of the first layer is optionally repeated. Then, one of the first or second spacer layers is removed while substantially leaving the vertical portions of the remaining one of the first or second spacer layers.04-04-2013
20130137247THERMALIZATION OF GASEOUS PRECURSORS IN CVD REACTORS - The present invention relates to the field of semiconductor processing and provides methods that improve chemical vapor deposition (CVD) of semiconductor materials by promoting more efficient thermalization of precursor gases prior to their reaction. In preferred embodiments, the method provides heat transfer structures and their arrangement within a CVD reactor so as to promote heat transfer to flowing process gases. In certain preferred embodiments applicable to CVD reactors transparent to radiation from heat lamps, the invention provides radiation-absorbent surfaces placed to intercept radiation from the heat lamps and to transfer it to flowing process gases.05-30-2013
20130137245METHOD FOR MAKING A STRUCTURE COMPRISING AT LEAST ONE MULTI-THICK ACTIVE PART - A method for making a structure comprising an active part comprising at least two layers from a first single crystal silicon substrate, said method comprising the steps of: 05-30-2013
20100055881HEAT TREATMENT METHOD FOR COMPOUND SEMICONDUCTOR AND APPARATUS THEREFOR - A heat treatment method for compound semiconductors includes a step for placing an object to be treated on a stage in a process chamber, and a step for irradiating the surface of the object with an electromagnetic wave having a specific frequency by introducing the electromagnetic wave into the process chamber. A compound semiconductor is heat-treated by the electromagnetic wave irradiated upon the surface of the object to be treated.03-04-2010
20130040440EPITAXIAL PROCESS WITH SURFACE CLEANING FIRST USING HCl/GeH4/H2SiCl2 - A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH02-14-2013
20130040442METHOD OF MANUFACTURING GaN-BASED FILM - The present method of manufacturing a GaN-based film includes the steps of preparing a composite substrate, the composite substrate including a support substrate in which a coefficient of thermal expansion in a main surface is more than 0.8 time and less than 1.2 times as high as a coefficient of thermal expansion of GaN crystal in a direction of a axis and a single crystal film arranged on a side of the main surface of the support substrate, the single crystal film having threefold symmetry with respect to an axis perpendicular to a main surface of the single crystal film, and forming a GaN-based film on the main surface of the single crystal film in the composite substrate. Thus, a method of manufacturing a GaN-based film capable of manufacturing a GaN-based film having a large main surface area and less warpage is provided.02-14-2013
20130040439METHOD OF MODIFYING ELECTRICAL PROPERTIES OF CARBON NANOTUBES USING NANOPARTICLES - Various embodiments relate to a method of modifying the electrical properties of carbon nanotubes. The method may include providing a substrate having carbon nanotubes deposited on a surface of the substrate, and depositing on the carbon nanotubes a coating layer comprising a mixture of nanoparticles, a matrix in which the nanoparticles are dissolved or stabilized, and an ionic liquid. A field-effect transistor including the modified carbon nanotubes is also provided.02-14-2013
20130040441VAPOR-PHASE GROWTH METHOD FOR SEMICONDUCTOR FILM - A process for supplying a mixed material gas that includes a chlorosilane gas and a carrier gas to a surface of a substrate heated at 1200 to 1400° C. from a direction perpendicular to the surface is provided. A supply rate of the chlorosilane gas is equal to or more than 200 μmol per minute per 1 cm02-14-2013
20130040443Method for Manufacturing a Semiconductor Device - A method for forming a semiconductor device is provided. The method includes providing a semiconductor body with a horizontal surface. An epitaxy hard mask is formed on the horizontal surface. An epitaxial region is formed by selective epitaxy on the horizontal surface relative to the epitaxy hard mask so that the epitaxial region is adjusted to the epitaxy hard mask. The epitaxial region is polished by a chemical-mechanical polishing process stopping on the epitaxy hard mask. A vertical trench is formed in the semiconductor body. An insulated field plate is formed in a lower portion of the vertical trench and an insulated gate electrode is formed above the insulated field plate. Further, a method for forming a field-effect semiconductor device is provided.02-14-2013
20130210217Precursors for GST Films in ALD/CVD Processes - The present invention is a process of making a germanium-antimony-tellurium alloy (GST) or germanium-bismuth-tellurium (GBT) film using a process selected from the group consisting of atomic layer deposition and chemical vapor deposition, wherein a silylantimony precursor is used as a source of antimony for the alloy film. The invention is also related to making antimony alloy with other elements using a process selected from the group consisting of atomic layer deposition and chemical vapor deposition, wherein a silylantimony or silylbismuth precursor is used as a source of antimony or bismuth.08-15-2013
20130210216EPITAXIAL CHANNEL FORMATION METHODS AND STRUCTURES - A method for forming field effect transistors (FETs) in a multiple wafers per batch epi-reactor includes, providing substrates having therein at least one semiconductor (SC) region with a substantially flat outer surface, modifying such substantially flat outer surface to form a convex-outward curved surface, forming an epitaxial semiconductor layer on the curved surface, and incorporating the epitaxial layer in a field effect transistor formed on the substrate. Where the SC region is of silicon, the epitaxial layer can include silicon-germanium. In a preferred embodiment, the epi-layer forms part of the FET channel. Because of the convex-outward curved surface, the epi-layer grown thereon has much more uniform thickness even when formed in a high volume reactor holding as many as 100 or more substrates per batch. FETs with much more uniform properties are obtained, thereby greatly increasing the manufacturing yield and reducing the cost.08-15-2013
20100022073Method of Fabricating CMOS Inverter and Integrated Circuits Utilizing Strained Silicon Surface Channel MOSFETS - A method of fabricating a circuit comprising an nMOSFET includes providing a substrate, depositing a strain-inducing material comprising germanium over the substrate, and integrating a pMOSFET on the substrate, the pMOSFET comprising a strained channel having a surface roughness of less than 1 nm. The strain-inducing material is proximate to and in contact with the pMOSFET channel, the strain in the pMOSFET channel is induced by the strain-inducing material, and a source and a drain of the pMOSFET are at least partially formed in the strain-inducing material.01-28-2010
20090311852BORON-DOPED DIAMOND SEMICONDUCTOR - First and second synthetic diamond regions are doped with boron. The second synthetic diamond region is doped with boron to a greater degree than the first synthetic diamond region, and in physical contact with the first synthetic diamond region. In a further example embodiment, the first and second synthetic diamond regions form a diamond semiconductor, such as a Schottky diode when attached to at least one metallic lead.12-17-2009
20090155987METHOD OF FABRICATING GALLIUM NITRIDE SUBSTRATE - A method of fabricating a gallium nitride (GaN) substrate provides a GaN thick film without causing bending and cracks which may occur in a growing process. To this end, a nitride embedding layer having a plurality of voids therein is embedded between a GaN layer and a base substrate. The method includes preparing a base substrate, growing, on the base substrate, the nitride embedding layer having a plurality of indium-rich parts at a first temperature, and growing a GaN layer on the nitride embedding layer at a second temperature higher than the first temperature so as to metallize the indium-rich part to form a plurality of voids in the nitride embedding layer.06-18-2009
20090155986METHOD FOR MANUFACTURING GALLIUM NITRIDE SINGLE CRYSTALLINE SUBSTRATE USING SELF-SPLIT - The present invention relates to a method for manufacturing a gallium nitride single crystalline substrate, including (a) growing a gallium nitride film on a flat base substrate made of a material having a smaller coefficient of thermal expansion than gallium nitride and cooling the gallium nitride film to bend convex upwards the base substrate and the gallium nitride film and create cracks in the gallium nitride film; (b) growing a gallium nitride single crystalline layer on the crack-created gallium nitride film located on the convex upward base substrate; and (c) cooling a resultant product having the grown gallium nitride single crystalline layer to make the convex upward resultant product flat or bend convex downwards the convex upward resultant product and at the same time to self-split the base substrate and the gallium nitride single crystalline layer from each other at the crack-created gallium nitride film interposed therebetween.06-18-2009
20100105193Storage nodes and methods of manufacturing and operating the same, phase change memory devices and methods of manufacturing and operating the same - In various embodiments, the present disclosure may provide a storage node. In various implementations, the storage node may include a bottom electrode having a non-planar bottom surface that conforms with and is connected to a non-planar top surface of a diode electrode of a memory device. The storage node may further include a phase change layer on top of a bottom diode and a top electrode on a top surface of a phase change layer.04-29-2010
20100041213Vapor Deposition Reactor For Forming Thin Film - A vapor deposition reactor includes a chamber filled with a first material, and at least one reaction module in the chamber. The reaction module may be configured to make a substrate pass the reaction module through a relative motion between the substrate and the reaction module. The reaction module may include an injection unit for injecting a second material to the substrate. A method for forming thin film includes positioning a substrate in a chamber, filling a first material in the chamber, moving the substrate relative to a reaction module in the chamber, and injecting a second material to the substrate while the substrate passes the reaction module.02-18-2010
20100041212FILM FORMING METHOD AND FILM FORMING APPARATUS - The present invention provides a film forming apparatus capable of removing a natural oxide film of a silicon substrate W at a very low temperature, as compared to the related art. The natural oxide film is removed at a low temperature by converting the natural oxide film on the silicon substrate W into a volatile material and evaporating the volatile material. The natural oxide film can be converted into volatile ammonium fluorosilicate by reaction with ammonium fluoride. A single crystal SiGe film can be grown on the silicon substrate W from which the natural oxide film is removed. The film forming apparatus includes an etching chamber, a SiGe growing chamber, and a substrate transport chamber that transports the silicon substrate in a controlled atmosphere.02-18-2010
20130029477APPARATUS INCLUDING 4-WAY VALVE FOR FABRICATING SEMICONDUCTOR DEVICE, METHOD OF CONTROLLING VALVE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE APPARATUS - An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.01-31-2013
20130045587LOW TEMPERATURE MIGRATION ENHANCED Si-Ge EPITAXY WITH PLASMA ASSISTED SURFACE ACTIVATION - Epitaxial films are grown by alternately exposed to precursor dosing regions, inert gas plasma regions, hydrogen-containing plasma regions, chlorine-containing plasma and metrology regions, or regions where an atomic hydrogen source is located. Alternately, laser irradiation techniques may be substituted for the plasma energy in some of the processing regions. The film growth process can be implemented at substrate temperatures between about 25 C and about 600 C, together with optional exposures to laser irradiation to cause the surface of the film to melt or to experience a near-melt condition.02-21-2013
20130045589SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.02-21-2013
20130045588METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is disclosed, comprising: providing a substrate, a gate region on the substrate and a semiconductor region at both sides of the gate region; forming sacrificial spacers, which cover a portion of the semiconductor region, on sidewalls of the gate region; forming a metal layer on a portion of the semiconductor region outside the sacrificial spacers and on the gate region; removing the sacrificial spacers; performing annealing so that the metal layer reacts with the semiconductor region to form a metal-semiconductor compound layer on the semiconductor region; and removing unreacted metal layer. By separating the metal layer from the channel and the gate region of the device with the thickness of the sacrificial spacers, the effect of metal layer diffusion on the channel and the gate region is reduced and performance of the device is improved.02-21-2013
20130052806DEPOSITION SYSTEMS HAVING ACCESS GATES AT DESIRABLE LOCATIONS, AND RELATED METHODS - Deposition systems include a reaction chamber, and a substrate support structure disposed at least partially within the reaction chamber. The systems further include at least one gas injection device and at least one vacuum device, which together are used to flow process gases through the reaction chamber. The systems also include at least one access gate through which a workpiece substrate may be loaded into the reaction chamber and unloaded out from the reaction chamber. The at least one access gate is located remote from the gas injection device. Methods of depositing semiconductor material may be performed using such deposition systems. Methods of fabricating such deposition systems may include coupling an access gate to a reaction chamber at a location remote from a gas injection device.02-28-2013
20130052805METHOD OF PRODUCING A THREE-DIMENSIONAL INTEGRATED CIRCUIT - Method of producing an integrated electronic circuit comprising at least the steps of: 02-28-2013
20130052804MULTI-GAS CENTRALLY COOLED SHOWERHEAD DESIGN - A method and apparatus for chemical vapor deposition and/or hydride vapor phase epitaxial deposition are provided. The apparatus generally include a lower bottom plate and an upper bottom plate defining a first plenum. The upper bottom plate and a mid-plate positioned above the upper bottom plate define a heat exchanging channel. The mid-plate and a top plate positioned above the mid-plate define a second plenum. A plurality of gas conduits extend from the second plenum through the heat exchanging channel and the first plenum. The method generally includes flowing a first gas through a first plenum into a processing region, and flowing a second gas through a second plenum into a processing region. A heat exchanging fluid is introduced to a heat exchanging channel disposed between the first plenum and the second plenum. The first gas and the second gas are then reacted to form a film on a substrate.02-28-2013
20130052803Method For Generating A Three-Dimensional NAND Memory With Mono-Crystalline Channels Using Sacrificial Material - A method for generating three-dimensional (3D) non-volatile memory (NVM) arrays includes forming multiple parallel horizontally-disposed mono-crystalline silicon beams that are spaced apart and arranged in a vertical stack (e.g., such that an elongated horizontal air gap is defined between each adjacent beam in the stack), forming separate charge storage layers on each of the mono-crystalline silicon beams such that each charge storage layer includes a high-quality thermal oxide layer that entirely covers (i.e., is formed on the upper, lower and opposing side surfaces of) each of the mono-crystalline silicon beams, and then forming multiple vertically-disposed poly-crystalline silicon wordline structures next to the stack such that each wordline structure is connected to each of the bitline structures in the stack by way of corresponding portions of the separate charge storage layers. The memory cells are accessed during read/write operations by way of the corresponding wordline and bitline structures.02-28-2013
20130089972METHOD FOR FORMING NANOCRYSTALLINE SILICON FILM - Provided is a method for forming a nanocrystalline silicon film that can be deposited on a substrate while maintaining a high degree of crystallinity at low temperatures. The method includes performing plasma treatment on a substrate, and forming a nanocrystalline silicon film by depositing the nanocrystalline silicon film on the substrate.04-11-2013
20090305486METHOD FOR PRODUCING A SEMICONDUCTOR LAYER - A method for producing a semiconductor layer is disclosed. One embodiment provides for a semiconductor layer on a semiconductor substrate containing oxygen. Crystal defects are produced at least in a near-surface region of the semiconductor substrate. A thermal process is carried out wherein the oxygen is taken up at the crystal defects. The semiconductor layer is deposited epitaxially over the near-surface region of the semiconductor substrate.12-10-2009
20090305485Method For Producing Semiconductor Substrate - The present invention is a method for producing a semiconductor substrate, including steps of forming a SiGe gradient composition layer and a SiGe constant composition layer on a Si single crystal substrate, flattening a surface of the SiGe constant composition layer, removing a natural oxide film on the flattened surface of the SiGe constant composition layer, and forming a strained Si layer on the surface of the SiGe constant composition layer from which the natural oxide film has been removed, wherein the formation of the SiGe gradient composition layer and the formation of the SiGe constant composition layer are performed at a temperature T12-10-2009
20090305484METHOD AND REACTOR FOR GROWING CRYSTALS - The reactor for growing crystals on substrates comprises a reaction chamber, support for at least one seed, inlet means for at least one reaction gas, inlet for combustion gasses and means for triggering combustion between said combustion gasses. The growth of a crystal on a seed located inside the reaction chamber comprises the steps of introducing at least one reaction gas into the reaction chamber, introducing combustion gasses into the reaction chamber, triggering combustion between the combustion gasses and depositing the material so generated on the seed.12-10-2009
20130072002Batch-Type Remote Plasma Processing Apparatus - A plasma processing apparatus comprises a processing chamber in which a plurality of substrates are stacked and accommodated; a pair of electrodes extending in the stacking direction of the plurality of substrates, which are disposed at one side of the plurality of substrates in said processing chamber, and to which high frequency electricity is applied; and a gas supply member which supplies processing gas into a space between the pair of electrodes.03-21-2013
20130072000Thin film processing equipment and the processing method thereof - This invention discloses a thin film processing equipment for depositing a film on a substrate and a process for depositing a film on a substrate using the same. The thin film processing equipment comprises a reaction chamber, a gas supplying mechanism, and a transferring mechanism. The thin film processing equipment is characterized in that a gas supplying mechanism is capable of moving up-and-down or left-and-right, and a tray is capable of moving up-and-down, thereby the distance between the gas supplying mechanism and the substrate can be adjusted. The film processing equipment is also provided with a heating mechanism with a pumped circulating heat source to improve the formation of thin films03-21-2013
20130072001Nitride Nanowires and Method of Producing Such - The present invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, LEDs and transistors. According to the method of the invention nitride semiconductor nanowires are grown utilizing a CVD based selective area growth technique. A nitrogen source and a metal-organic source are present during the nanowire growth step and at least the nitrogen source flow rate is continuous during the nanowire growth step. The V/III-ratio utilized in the inventive method is significantly lower than the V/III-ratios commonly associated with the growth of nitride based semiconductor.03-21-2013
20130071999HIGH THROUGHPUT EPITAXIAL LIFT OFF FOR FLEXIBLE ELECTRONICS - A method of removing a semiconductor device layer from an underlying base substrate is provided in which a sacrificial phosphide-containing layer is formed between a semiconductor device layer and a base substrate. In some embodiments, a semiconductor buffer layer can be formed on an upper surface of the base substrate prior to forming the sacrificial phosphide-buffer layer. The resultant structure is then etched utilizing a non-HF etchant to release the semiconductor device layer from the base semiconductor substrate. After releasing the semiconductor device layer from the base substrate, the base substrate can be re-used.03-21-2013
20120220109PLASMA CVD DEVICE AND METHOD OF MANUFACTURING SILICON THIN FILM - A plasma CVD device comprises a vacuum vessel that houses a discharge electrode plate and a ground electrode plate to which is attached a substrate for thin film formation. The plasma CVD device has an earth cover at an interval from and facing the aforementioned discharge electrode plate; the aforementioned discharge electrode plate has gas inlets and exhaust outlets (which expel gas introduced through said gas inlets) that are connected at one end to equipment supplying raw gas for thin film formation and that open at the other end at the bottom face of the aforementioned discharge electrode plate; the aforementioned earth cover has second gas inlets corresponding to the aforementioned gas inlets, and second exhaust outlets corresponding to the aforementioned exhaust outlets. The plasma CVD device has an electric potential control plate disposed at an interval from and facing the aforementioned ground cover.08-30-2012
20090093105Particle deposition apparatus, particle deposition method, and manufacturing method of light-emitting device - To provide a (homogeneous) particle deposit without any impurity contamination, on which only particles with a desired size are deposited. A solution, with particles dispersed in a solvent, is jetted as a flow of fine liquid droplets from a tip part of a capillary, and the jetted fine liquid droplets are electrically charged. This flow of the droplets is introduced into a vacuum chamber through a jet nozzle, as a free jet flow. The free jet flow that travels in the vacuum chamber is introduced into an inside of a deposition chamber, inside of which is set at lower pressure, through a skimmer nozzle provided in the deposition chamber, as an ion beam. Subsequently, by an energy separation device, only particles having particular energy are selected from the electrically charged particles in the flow, and are deposited on a deposited body disposed in an inside of the deposition chamber.04-09-2009
20130183815METHODS FOR DEPOSITING GROUP III-V LAYERS ON SUBSTRATES - Methods for depositing a group III-V layer on a substrate are disclosed herein. In some embodiments a method includes depositing a first layer comprising at least one of a first Group III element or a first Group V element on a silicon-containing surface oriented in a <111> direction at a first temperature ranging from about 300 to about 400 degrees Celsius; and depositing a second layer comprising second Group III element and a second Group V element atop the first layer at a second temperature ranging from about 300 to about 600 degrees Celsius.07-18-2013
20130059430High Throughput Multi-Wafer Epitaxial Reactor - An epitaxial reactor enabling simultaneous deposition of thin films on a multiplicity of wafers is disclosed. During deposition, a number of wafers are contained within a wafer sleeve comprising a number of wafer carrier plates spaced closely apart to minimize the process volume. Process gases flow preferentially into the interior volume of the wafer sleeve, which is heated by one or more lamp modules. Purge gases flow outside the wafer sleeve within a reactor chamber to minimize wall deposition. In addition, sequencing of the illumination of the individual lamps in the lamp module may further improve the linearity of variation in deposition rates within the wafer sleeve. To improve uniformity, the direction of process gas flow may be varied in a cross-flow configuration. Combining lamp sequencing with cross-flow processing in a multiple reactor system enables high throughput deposition with good film uniformities and efficient use of process gases.03-07-2013
20130059429METHOD OF PRODUCTION OF SIC SEMICONDUCTOR DEVICE - A method of production of an SiC semiconductor device, which can form an ohmic electrode while preventing electrode metal from diffusing in the SiC single crystal substrate, includes a step of forming an ohmic electrode on an SiC substrate, characterized by forming a gettering layer with a defect density higher than the SiC substrate on that substrate to be parallel with the substrate surface, then forming the ohmic electrode the gettering layer outward from the substrate.03-07-2013
20110014779Method of making damascene diodes using sacrificial material - A method of making a semiconductor device includes forming a first layer comprising a seed material over an underlying layer, forming a second layer comprising a sacrificial material over the first layer, the sacrificial material being different from the seed material, patterning the first layer and the second layer into a plurality of separate features, forming an insulating filling material between the plurality of the separate features, removing the sacrificial material from the separate features to form a plurality of openings in the insulating filling material such that the seed material is exposed in the plurality of openings, and growing a semiconductor material on the exposed seed material in the plurality of openings.01-20-2011
20090280624Precursors for Formation of Copper Selenide, Indium Selenide, Copper Indium Diselenide, and/or Copper Indium Gallium Diselenide Films - Liquid-based precursors for formation of Copper Selenide, Indium Selenide, Copper Indium Diselenide, and/or copper Indium Galium Diselenide include copper-organoselenides, particulate copper selenide suspensions, copper selenide ethylene diamine in liquid solvent, nanoparticulate indium selenide suspensions, and indium selenide ethylene diamine coordination compounds in solvent. These liquid-based precursors can be deposited in liquid form onto substrates and treated by rapid thermal processing to form crystalline copper selenide and indium selenide films.11-12-2009
20090269909NITRIDE BASED SEMICONDUCTOR DEVICE USING NANORODS AND PROCESS FOR PREPARING THE SAME - Disclosed are a nitride based semiconductor device, including a high-quality GaN layer formed on a silicone substrate, and a process for preparing the same. A nitride based semiconductor device in accordance with the present invention comprises a plurality of nanorods aligned and formed on the silicone substrate in the vertical direction; an amorphous matrix layer filling spaces between nanorods so as to protrude some upper portion of the nanorods; and a GaN layer formed on the matrix layer.10-29-2009
20120225542METHOD FOR PREPARING MULTILAYER OF NANOCRYSTALS, AND ORGANIC-INORGANIC HYBRID ELECTROLUMINESCENCE DEVICE COMPRISING MULTILAYER OF NANOCRYSTALS PREPARED BY THE METHOD - A method for preparing a multilayer of nanocrystals. The method includes the steps of (i) coating nanocrystals surface-coordinated by a photosensitive compound, or a mixed solution of a photosensitive compound and nanocrystals surface-coordinated by a material miscible with the photosensitive compound, on a substrate, drying the coated substrate, and exposing the dried substrate to UV light to form a first monolayer of nanocrystals, and (ii) repeating the procedure of step (i) to form one or more monolayers of nanocrystals on the first monolayer of nanocrystals. Further, an organic-inorganic hybrid electroluminescence device using a multilayer of nanocrystals prepared by the method as a luminescent layer.09-06-2012
20120225540Method for fabricating a porous semiconductor body region - A method for fabricating a porous semiconductor body region, comprising:09-06-2012
20120225539DEPOSITION METHODS FOR THE FORMATION OF III/V SEMICONDUCTOR MATERIALS, AND RELATED STRUCTURES - Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, the layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.09-06-2012
20130065380METHODS FOR MANUFACTURING INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE - A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall surface does not carry the sidewall surface variations introduced by photolithographic processes, or other patterning processes, involved in forming the mask element and etching the line.03-14-2013
20130065379METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a porous area of a semiconductor body. The semiconductor body includes a porous structure in the porous area. A semiconductor layer is formed on the porous area. Semiconductor regions are formed in the semiconductor layer. Then, the semiconductor layer is separated from the semiconductor body along the porous area, including introducing hydrogen into the porous area by a thermal treatment.03-14-2013
20130164919METHODS OF FABRICATING SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING GATE INSULATING LAYERS - A method of fabricating a semiconductor device may include forming active and field regions in a substrate; forming a gate trench in which the active and field regions are exposed; forming a gate insulating layer on a surface of the exposed active region, wherein forming the gate insulating layer includes forming a first gate oxide layer by primarily oxidizing the surface of the active region, and forming a second gate oxide layer between the surface of the active region and the first gate oxide layer by secondarily oxidizing the surface of the active region; conformally forming a gate barrier layer on the gate insulating layer and the exposed field region; forming a gate electrode layer on the gate barrier layer; and forming a gate capping layer in contact with the gate insulating layer, the gate barrier layer, and the gate electrode layer in the gate trench.06-27-2013
20130164916ABSORBERS FOR HIGH EFFICIENCY THIN-FILM PV - Methods are described for forming CIGS absorber layers in TFPV devices with graded compositions and graded band gaps. Methods are described for utilizing Ag to increase the band gap at the front surface of the absorber layer. Methods are described for utilizing Al to increase the band gap at the front surface of the absorber layer. Methods are described for utilizing at least one of Na, Mg, K, or Ca to increase the band gap at the front surface of the absorber layer.06-27-2013
20090263956Spray method for producing semiconductor nano-particles - A method is provided for producing semiconductor nanoparticles comprising: (i) dissolving a semiconductor compound or mixture of semiconductor compounds in a solution; (ii) generating spray droplets of the resulting solution of semiconductor compound(s); (iii) vaporizing the solvent of said spray droplets, consequently producing a stream of unsupported semiconductor nanoparticles; and (iv) collecting said unsupported semiconductor nanoparticles on a support.10-22-2009
20100124813Self-Aligned Three-Dimensional Non-Volatile Memory Fabrication - A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.05-20-2010
20090233421Methods of Fabricating Semiconductor Device Including Phase Change Layer - Provided are methods of fabricating a semiconductor device including a phase change layer. Methods may include forming a dielectric layer on a substrate, forming an opening in the dielectric layer and depositing, on the substrate having the opening, a phase change layer that contains an element that lowers a process temperature of a thermal treatment process to a temperature that is lower than a melting point of the phase change layer. Methods may include migrating a portion of the phase change layer from outside the opening, into the opening by the thermal treatment process that includes the process temperature that is lower than the melting point of the phase change layer.09-17-2009
20090233422SWITCHABLE MEMORY DIODE - A NEW MEMORY DEVICE - Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of a passive array. Moreover, the system provides for an efficient placement of memory cells on a wafer surface, and increases an amount of die space available for circuit design.09-17-2009
20120115313SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS AND METHOD - A sealing member is lifted to cause its edge to be in contact with a contact surface of a support member. In the state where a precision ejection nozzle is isolated, a gas exhaust unit is operated to exhaust the inside of a chamber to reduce the pressure in the chamber to a predetermined level. Then, a purge gas is introduced into the chamber from a purge gas supply source through a gas introduction section to replace the atmosphere in the chamber with the purge gas, and the pressure in the chamber is returned to the atmospheric pressure. After that, the sealing member is lowered to release the isolation of the precision ejection nozzle. Then, liquid droplets of a liquid device material are ejected toward the surface of a substrate while a carriage is reciprocated in the X direction.05-10-2012
20120115312THIN FILMS FOR PHOTOVOLTAIC CELLS - In one aspect, a method for forming CIGSSe-based thin films includes depositing at least two layers of particles on a substrate. At least one layer includes a CIGSSe particle having a chemical composition denoted by Cu(InI-xGax)(S1-ySey)2 where 0≦x ≦1 and 0≦y≦1. The particle layers are annealed individually or in combination to form a CIGSSe thin film having a composition profile along the depth of the film In addition, one or more of the particle layers may be also deposited on a pre-existing absorber and annealed to form a film having a composition profile along the depth of the film After depositing thin film precursor layers containing CIGSSe nanoparticles (and/or any other particles) on a suitable substrate in accordance with a desired concentration profile, a subsequent treatment under an Se and/or S containing atmosphere at elevated temperature may be used to convert the precursor layers into a CIGSSe absorber film In a further aspect, a method for forming multinary metal chalcogenide semiconductor layers directly on a substrate from a solution of precursors, includes depositing a plurality of metal chalcogenide particles onto a substrate to form a precursor film A species containing a metal, chalcogen, or combination thereof is dissolved in a solution containing one or more solvents to form a liquid chalcogen medium. The precursor film is contacted with the liquid chalcogen medium at a temperature of at least 50 C to form a multinary metal chalcogenide thin film05-10-2012
20120115311METHOD FOR FORMING A MULTILAYER STRUCTURE - The method for forming a multilayer structure on a substrate comprises providing a stack successively comprising an electron hole blocking layer, a first layer made from N-doped semiconductor material having a dopant concentration greater than or equal to 1005-10-2012
20120115310METHOD OF SIGE EPITAXY WITH HIGH GERMANIUM CONCENTRATION - The present invention discloses a method of SiGe epitaxy with high germanium concentration, a germanium concentration can be increased by reducing the percentage of silane and germane during introduction silane and germane. With the same flow of germanium source, the germanium concentration is significantly increased as the germane flow is reduced, therefore a defect-free SiGe epitaxial film with a germanium atomic percentage of 25˜35% can be obtained. The present invention can balance epitaxial growth rate and germanium doping concentration by using existing equipments to obtain a high germanium concentration, and the epitaxial growth rate is only reduced a little, which can keep the SiGe epitaxial layer having no defect to meet the requirements of devices and can maintain sufficient throughput.05-10-2012
20120115309Methods of Manufacturing a Vertical Type Semiconductor Device - Methods of manufacturing a semiconductor device include forming a stopping layer pattern in a first region of a substrate. A first mold structure is formed in a second region of the substrate that is adjacent the first region. The first mold structure includes first sacrificial patterns and first interlayer patterns stacked alternately. A second mold structure is formed on the first mold structure and the stopping layer pattern. The second mold structure includes second sacrificial patterns and second interlayer patterns stacked alternately. The second mold structure partially covers the stopping layer pattern. A channel pattern is formed and passes through the first mold structure and the second mold structure.05-10-2012
20090011573Carrier used for deposition of materials on a non-planar surface - A carrier for effectuating semiconductor processing on a non-planar substrate is disclosed. The carrier is configured for holding at least one non-planar substrate throughout a semiconductor processing step and concurrently rotating non-planar substrates as they travel down a translational path of a processing chamber. As the non-planar substrates simultaneously rotate and translate down a processing chamber, the rotation exposes the whole or any desired portion of the surface area of the non-planar substrates to the deposition process, allowing for uniform deposition as desired. Alternatively, any predetermined pattern is able to be exposed on the surface of the non-planar substrates. Such a carrier effectuates manufacture of non-planar semiconductor devices, including, but not limited to, non-planar light emitting diodes, non-planar photovoltaic cells, and the like.01-08-2009
20100087049RELAXATION OF A STRAINED MATERIAL LAYER WITH APPLICATION OF A STIFFENER - The invention relates to methods of fabricating a layer of at least partially relaxed material, such as for electronics, optoelectronics or photovoltaics. An exemplary method includes supplying a structure that includes a layer of strained material situated between a reflow layer and a stiffener layer. The method further includes applying a heat treatment that brings the reflow layer to a temperature equal to or greater than the glass transition temperature of the reflow layer, and the thickness of the stiffener layer is progressively reduced during heat treatment. The invention also relates to an exemplary method of fabricating semiconductor devices on a layer of at least partially relaxed material. Specifically, at least one active layer may be formed on the at least partially relaxed material layer. The active layer may include laser components, photovoltaic components and/or electroluminescent diodes.04-08-2010
20120238080Method of Forming Epitaxial Film - A method of growing an epitaxial film and transferring it to an assembly substrate is disclosed. The film growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications.09-20-2012
20120238079Method of Transferring Epitaxial Film - A method of growing an epitaxial film and transferring it to an assembly substrate is disclosed. The film growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications.09-20-2012
20120238078Method of Integrating Epitaxial Film Onto Assembly Substrate - A method of growing an epitaxial film and transferring it to an assembly substrate is disclosed. The film growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications.09-20-2012
20120238077Methods of Forming High Density Structures and Low Density Structures with a Single Photomask - Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.09-20-2012
20120238076Method and Apparatus for Forming a III-V Family Layer - Provided is an apparatus. The apparatus includes: a first deposition component that is operable to form a compound over a semiconductor wafer, the compound including at least one of: a III-family element and a V-family element; a second deposition component that is operable to form a passivation layer over the compound; and a transfer component that is operable to move the semiconductor wafer between the first and second deposition components, the transfer component enclosing a space that contains substantially no oxygen and substantially no silicon; wherein the loading component, the first and second deposition components, and the transfer component are all integrated into a single fabrication tool.09-20-2012
20120238075COATING APPARATUS AND COATING METHOD - A coating apparatus including a coating part which applies a liquid material containing an oxidizable metal and a solvent to a substrate; a chamber having a coating space in which the coating part applies the liquid material to the substrate and a transport space into which the substrate is transported; and a removal part which removes the liquid material from the atmosphere inside the chamber when a concentration of the solvent in the atmosphere inside the chamber exceeds a threshold value.09-20-2012
20130164917Absorbers For High-Efficiency Thin-Film PV - Methods are described for forming CIGS absorber layers in TFPV devices with graded compositions and graded band gaps. Methods are described for utilizing Ag to increase the band gap at the front surface of the absorber layer. Methods are described for utilizing Al to increase the band gap at the front surface of the absorber layer. Methods are described for utilizing metal chalcogenide layers to impact the band gap and the morphology of the absorber layer.06-27-2013
20130164918Absorbers For High-Efficiency Thin-Film PV - Methods are described for forming CZTS absorber layers in TFPV devices with graded compositions and graded bandgaps. Methods are described for utilizing at least one of Zn, Ge, or Ag to alter the bandgap within the absorber layer. Methods are described for utilizing Te, S, Se, O, Cd, Hg, or Sn to alter the bandgap within the absorber layer. Methods are described for utilizing either a 2-step process or a 4-step process to alter the bandgap within the absorber layer.06-27-2013
20110177679METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes preparing a substrate having a low-dislocation region and a high-dislocation region having a higher dislocation density than dislocation density of the low-dislocation region; forming an insulating film on the low-dislocation region surrounding the high-dislocation region but not covering the high-dislocation region; and forming a nitride-based semiconductor layer on the substrate, after forming the insulating film.07-21-2011
20100167502Nanoimprint enhanced resist spacer patterning method - A method of making a device is disclosed including: forming a first hard mask layer over an underlying layer; forming a first imprint resist layer over the underlying layer; forming first features over the first hard mask layer by bringing a first imprint template in contact with the first imprint resist layer; forming a first spacer layer over the first features; etching the first spacer layer to form a first spacer pattern and to expose top of the first features; removing the first features; patterning the first hard mask, using the first spacer pattern as a mask, to form first hard mask features; and etching at least part of the underlying layer using the first hard mask features as a mask.07-01-2010
20110281423METHOD OF PRODUCING SEMICONDUCTOR WAFER AND SEMICONDUCTOR WAFER - A method of producing a semiconductor wafer includes placing a base wafer within a reaction chamber, and epitaxially growing a p-type Group 3-5 compound semiconductor on the base wafer by supplying, into the reaction chamber, a Group 3 source gas consisting of an organometallic compound of a Group 3 element, a Group 5 source gas consisting of a compound of a Group 5 element, and an impurity gas including an impurity that is to be incorporated as a dopant into a semiconductor to serve as a donor. Here, during the epitaxial growth of the p-type Group 3-5 compound semiconductor, the flow rate of the impurity gas and the flow rate ratio of the Group 5 source gas to the Group 3 source gas are set so that the product N×d (cm11-17-2011
20110281422METHOD FOR OBTAINING HIGH-QUALITY BOUNDARY FOR SEMICONDUCTOR DEVICES FABRICATED ON A PARTITIONED SUBSTRATE - One embodiment of the present invention provides a process for obtaining high-quality boundaries for individual multilayer structures which are fabricated on a trench-partitioned substrate. During operation, the process receives a trench-partitioned substrate wherein the substrate surface is partitioned into arrays of isolated deposition platforms which are separated by arrays of trenches. The process then forms a multilayer structure, which comprises a first doped layer, an active layer, and a second doped layer, on one of the deposition platforms. Next, the process removes sidewalls of the multilayer structure.11-17-2011
20110281421PROCESS FOR PRODUCING POWDERS OF GERMANIUM - A method of producing a powder of crystalline germanium.11-17-2011
20090286383TREATMENT OF WHISKERS - A photo-curing or photosintering process is utilized to modify, reduce or eliminate whiskers or nanowires growing on a material surface.11-19-2009
20110136325Method for fabricating a monolithic integrated composite group III-V and group IV semiconductor device - According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group III-V semiconductor device may be a III-nitride high electron mobility transistor (HEMT).06-09-2011
20110165762MONOSILANE OR DISILANE DERIVATIVES AND METHOD FOR LOW TEMPERATURE DEPOSITION OF SILICON-CONTAINING FILMS USING THE SAME - This invention relates to silicon precursor compositions for forming silicon-containing films by low temperature (e.g., <550° C.) chemical vapor deposition processes for fabrication of ULSI devices and device structures. Such silicon precursor compositions comprise at least a silane or disilane derivative that is substituted with at least one alkylhydrazine functional groups and is free of halogen substitutes.07-07-2011
20110201180FABRICATION OF GAN AND III-NITRIDE ALLOYS FREESTANDING EPILAYERS MEMBRANES USING A NONBONDING LASER - Using a laser lift-off (LLO) nonbonding technique, freestanding 4-layer GaN/AlGaN heterostructure membranes have been formed. A 4×4 mm mask was attached to the area at the center of the most-upper AlGaN layer was attached using a nonbonding material such as vacuum grease. A microscopic slide attached by an adhesive provided support for the structure during the laser lift-off without bonding to the layers. The vacuum grease and the mask isolated the adhesive from the structure at the center. The microscopic slide served as a temporarily nonbonding handle substrate. Laser lift-off of the sapphire substrate from the heterostructures was performed. The remaining adhesive served as a supporting frame for the structure making a free-standing 4-layer GaN/AGaN heterostructure membrane. Other frameless freestanding membranes can be fabricated for a variety of applications including further III-nitride growth, heterogeneous integration, packaging of micro systems, and thin film patterns.08-18-2011
20110287613MANUFACTURING METHOD OF SUPERJUNCTION STRUCTURE - A manufacturing method of superjunction structure is disclosed. After the growth of an epitaxial layer on a substrate, deep trenches are etched in the epitaxial layer. A mixture of silicon source gas, hydrogen gas, halide gas and doping gas is used for trench tilling by means of epitaxial growth. The epitaxial growth rate on trench sidewalls near the bottom of the trench is set to be higher than that near the top of the trench by adjusting the flow rates of the silicon source gas and the halide gas and other parameters. By changing the flow rate of the doping gas at different stages of the epitaxial filling process, the trenches can be filled with epitaxial layers of different doping concentrations, with higher doping concentration near the bottom and lower doping concentration near the top.11-24-2011
20110287612Nonvolatile Memory Device, Method of Manufacturing the Nonvolatile Memory Device, and Memory Module and System Including the Nonvolatile Memory Device - A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer.11-24-2011
20110287611Reducing Variation by Using Combination Epitaxy Growth - A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first growth-to-etching (E/G) ratio of process gases used in the first growth stage; and performing a second growth stage with a second E/G ratio of process gases used in the second growth stage different from the first E/G ratio.11-24-2011
20110294280METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - Provided are a method of manufacturing a semiconductor device and a substrate processing apparatus capable of improving defects of conventional CVD and ALD methods, satisfying requirements of film-thinning, and realizing high film-forming rate. The method includes forming a first layer including a first element being able to become solid state by itself on a substrate by supplying a gas containing the first element into a process vessel in which the substrate is accommodated under a condition that a CVD reaction occurs, and forming a second layer including the first element and a second element being unable to become solid state by itself by supplying a gas containing the second element into the process vessel to modify the first layer, wherein a cycle including the forming of the first layer and the forming of the second layer is performed at least once to form a thin film including the first and second elements and having a predetermined thickness.12-01-2011
20110294282Semiconductor device and method for manufacturing the same - A method for manufacturing a semiconductor device including a vertical double-diffused metal-oxide-semiconductor (VDMOS) transistor includes preparing a semiconductor substrate and injecting a first impurity of a second conductivity type to a first region, injecting a second impurity to a second region that is located inside and is narrower than the first region, and forming an epitaxial layer on the semiconductor substrate and forming the semiconductor layer constituted by the semiconductor substrate and the epitaxial layer, and at a same time, diffusing the first and the second impurities injected in a first impurity injection and a second impurity injection to form a buried layer of the second conductivity type.12-01-2011
20110294281METHOD OF AT LEAST PARTIALLY RELEASING AN EPITAXIAL LAYER - A method of at least partially releasing an epitaxial layer of a material from a substrate. The method comprises the steps of: forming a patterned sacrificial layer on the substrate such that the substrate is partially exposed and partially covered by the sacrificial layer; growing the epitaxial layer on the patterned sacrificial layer by nano-epitaxial lateral overgrowth such that the epitaxial layer is formed above an intermediate layer comprising the patterned sacrificial layer and said material; and selectively etching the patterned sacrificial layer such that the epitaxial layer is at least partially released from the substrate.12-01-2011
20110027973METHOD OF FORMING LED STRUCTURES - One embodiment of fabricating a p-down light emitting diode (LED) structure comprises depositing a high crystal quality p type contact layer, depositing an active region on top of the p type contact layer, and depositing an n type contact layer on top of the active region using a hydride vapor phase epitaxy (HVPE) process. The high crystal quality p type contact layer is deposited at high temperature to ensure the high crystal quality of the p type film. The n type contact layer is formed on top of the active region in a HVPE chamber at a low temperature to prevent thermal damage to the quantum wells in the active region below the n type contact layer. The processing chamber used to form the p type contact layer is a separate processing chamber than the processing chamber used to form the n type contact layer.02-03-2011
20100055880SELECTIVE GROWTH OF POLYCRYSTALLINE SILICON-CONTAINING SEMICONDUCTOR MATERIAL ON A SILICON-CONTAINING SEMICONDUCTOR SURFACE - A method of depositing polycrystalline silicon exclusively on monocrystalline first silicon surface portions of a substrate surface which besides the first surface portions additionally has insulator surface portions, comprising the steps of depositing boron on the first silicon surface portions in an amount which in relation to the first silicon surface portions respectively corresponds to more than a monolayer of boron, and depositing silicon on the first silicon surface portions treated in that way.03-04-2010
20090298267SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - It is an apparatus for semiconductor device production in which a feed gas is fed into a chamber having a semiconductor wafer placed therein to deposit a thin film on the surface of the semiconductor wafer based on a catalyzed chemical reaction. It comprises the chamber for placing a semiconductor wafer therein, a feed gas supply means with which a feed gas which is a raw material for the thin film is sent into the chamber, and a gas-blowing means which has a gas-blowing opening through which the feed gas sent from the feed gas supply means is blown against the surface of the semiconductor wafer placed in the chamber. The gas-blowing means changes in the state of the gas-blowing opening according to the feed gas blowing position to thereby regulate the amount of the feed gas to be blown.12-03-2009
20090298266DOPANT CONFINEMENT IN THE DELTA DOPED LAYER USING A DOPANT SEGREGRATION BARRIER IN QUANTUM WELL STRUCTURES - A device grade III-V quantum well structure and method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×1012-03-2009
20090298265Method of Manufacturing III Nitride Crystal, III Nitride Crystal Substrate, and Semiconductor Device - Affords III-nitride crystals having a major surface whose variance in crystallographic plane orientation with respect to an {hkil} plane chosen exclusive of the {0001} form is minimal. A method of manufacturing the III-nitride crystal is one of: conditioning a plurality of crystal plates (12-03-2009
20100136769GERMANIUM-BASED POLYMERS AND PRODUCTS FORMED FROM GERMANIUM-BASED POLYMERS - Germanium-based polymers are described. In one embodiment, a germanium-based polymer includes a structure given by the formula:06-03-2010
20100035413Active layer for solar cell and the manufacturing method making the same - A method for manufacturing an active layer of a solar cell is disclosed, the active layer manufactured including multiple micro cavities in sub-micrometer scale, which can increase the photoelectric conversion rate of a solar cell. The method comprises following steps: providing a substrate having multiple layers of nanospheres which are formed by the aggregated nanospheres; forming at least one silicon active layer to fill the inter-gap between the nanospheres and part of the surface of the substrate; and removing the nanospheres to form an active layer having plural micro cavities on the surface of the substrate. The present invention also provides a solar cell comprising: a substrate, an active layer, a transparent top-passivation, at least one front contact pad, and at least one back contact pad. The active layer locates on a surface of the substrate and has plural micro cavities whose diameter is less than one micrometer.02-11-2010
20100035411METHOD OF MANUFACTURING SILCON CARBIDE SEMICONDUCTOR DEVICE - A method of manufacturing an SiC semiconductor device includes the steps of ion implanting a dopant at least in a part of a surface of an SiC single crystal, forming an Si film on the surface of the ion-implanted SiC single crystal, and heating the SiC single crystal on which the Si film is formed to a temperature not less than a melting temperature of the Si film.02-11-2010
20090239356DEVICE MANUFACTURING METHOD - A device manufacturing method includes a buffer layer forming step of forming a buffer layer on an underlying substrate, a mask pattern forming step of forming, on the buffer layer, a mask pattern which partially covers the buffer layer, a growth step of growing a group III nitride crystal from regions exposed by the mask pattern on the surface of the buffer layer, thereby forming a structure in which a plurality of crystal members are arranged with gaps therebetween so as to partially cover the buffer layer and the mask pattern, a channel forming step of forming a channel, to supply a second etchant for the buffer layer to the buffer layer, by selectively etching the mask pattern using a first etchant for the mask pattern, and a separation step of separating the plurality of crystal members from the underlying substrate and separating the plurality of crystal members from each other by supplying the second etchant to the buffer layer through the gaps and the channel and selectively etching the buffer layer.09-24-2009
20090203194TRANSPARENT CONDUCTIVE FILM DEPOSITION APPARATUS, FILM DEPOSITION APPARATUS FOR CONTINUOUS FORMATION OF MULTILAYERED TRANSPARENT CONDUCTIVE FILM, AND METHOD OF FORMING THE FILM - Raw materials are economized and a film deposition rate is improved while maintaining film evenness and high film quality.08-13-2009
20090186467Substrate Processing Apparatus and Producing Method of Semiconductor Device - A substrate treatment apparatus includes a reaction tube and a heater heating a silicon wafer. Trimethyl aluminum (TMA) and ozone (O07-23-2009
20090098714Method for forming III-nitrides semiconductor epilayer on the semiconductor substrate - GaN layer on semiconductor substrate is grown by using GaN nanorod buffer layer. Firstly, semiconductor substrate is cleaned and thermally degassed to remove the contaminant in the growth chamber. After the above step, the GaN nanorods layer is grown under the N-rich condition. Then, GaN epilayer is overgrown on the GaN nanorods layer under the Ga-rich condition for forming Group of III-Nitrides semiconductor layer on the semiconductor substrate.04-16-2009
20090181523Method of manufacturing semiconductor device and apparatus for processing substrate - A process for producing a semiconductor device, in which in the formation of a boron doped silicon film from, for example, monosilane and boron trichloride by vacuum CVD technique, there can be produced a film excelling in inter-batch homogeneity with respect to the growth rate and concentration of a dopant element, such as boron. The process includes the step of performing the first purge through conducting at least once of while a substrate after treatment is housed in a reaction furnace, vacuuming of the reaction furnace and inert gas supply thereto and the steps of performing the second purge through conducting at least once of after carrying of the substrate after treatment out of the reaction furnace, prior to carrying of a substrate to be next treated into the reaction furnace and while at least no product substrate is housed in the reaction furnace, vacuuming of the reaction furnace and inert gas supply thereto.07-16-2009
20100112789Method for Producing Semiconductor Chips using Thin Film Technology - For semiconductor chips using thin film technology, an active layer sequence is applied to a growth substrate, on which a reflective electrically conductive contact material layer is then formed. The active layer sequence is patterned to form active layer stacks, and reflective electrically conductive contact material layer is patterned to be located on each active layer stack. Then, a flexible, electrically conductive foil is applied to the contact material layers as an auxiliary carrier layer, and the growth substrate is removed.05-06-2010
20110263102Methods of Fabricating Normally-Off Semiconductor Devices - Normally-off semiconductor devices are provided. A Group III-nitride buffer layer is provided. A Group III-nitride barrier layer is provided on the Group III-nitride buffer layer. A non-conducting spacer layer is provided on the Group III-nitride barrier layer. The Group III-nitride barrier layer and the spacer layer are etched to form a trench. The trench extends through the barrier layer and exposes a portion of the buffer layer. A dielectric layer is formed on the spacer layer and in the trench and a gate electrode is formed on the dielectric layer. Related methods of forming semiconductor devices are also provided herein.10-27-2011
20100129991NITRIDE SEMICONDUCTOR DEVICE HAVING A SILICON-CONTAINING LAYER AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided which enable reduction and enhanced stability of contact resistance between the back surface of a nitride substrate and an electrode formed thereover. A nitride semiconductor device includes an n-type Ga—N substrate (05-27-2010
20100267221GROUP III NITRIDE SEMICONDUCTOR DEVICE AND LIGHT-EMITTING DEVICE USING THE SAME - A Group III nitride semiconductor device and method for producing the same. The device includes a substrate, and a plurality of Group III nitride semiconductor layers provided on the substrate. A first layer which is in contact with the substrate is composed of Al10-21-2010
20080268620METHOD AND DEVICE FOR PROTECTING INTERFEROMETRIC MODULATORS FROM ELECTROSTATIC DISCHARGE - A MEMS device such as an interferometric modulator includes an integrated ESD protection element capable of shunting to ground an excess current carried by an electrical conductor in the MEMS device. The protection element may be a diode and may be formed by depositing a plurality of doped semiconductor layers over the substrate on which the MEMS device is formed.10-30-2008
20120190177N-type carrier enhancement in semiconductors - A method includes epitaxially growing a germanium (Ge) layer onto a Ge substrate and incorporating a compensating species with a compensating atomic radius into the Ge layer. The method includes implanting an n-type dopant species with a dopant atomic radius into the Ge layer. The method includes selecting the n-type dopant species and the compensating species in such manner that the size of the Ge atomic radius is inbetween the n-type dopant atomic radius and the compensating atomic radius.07-26-2012
20120190176CATALYTIC CVD EQUIPMENT, METHOD FOR FORMATION OF FILM, AND PROCESS FOR PRODUCTION OF SOLAR CELL - In a catalytic CVD equipment, the control unit controls a temperature of the catalytic wires to a standby temperature at predetermined time intervals before and after the film is formed. The standby time is a predetermined temperature which is lower than the temperature of the catalytic wires when the film is formed, and is higher than room temperature.07-26-2012
20100144124METHOD OF GROWING PURE Ge THIN FILM WITH LOW THREADING DISLOCATION DENSITY - Provided is a method of growing a pure germanium (Ge) thin film with low threading dislocation density using reduced pressure chemical vapor deposition (RPCVD), which includes growing a Ge thin film on a silicon (Si) substrate at a low temperature, performing real-time annealing for a short period of time, and growing the annealed Ge thin film at a high temperature. The grown Ge single crystal thin film can overcome conventional problems of generation of a Si—Ge layer due to Si diffusion, and propagation of misfit dislocation to a high-temperature Ge thin film.06-10-2010
20100129992METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes: a III-V nitride semiconductor layer including a channel region in which carriers travel; a concave portion provided in an upper portion of the channel region in the III-V nitride semiconductor layer; and a Schottky electrode consisting of a conductive material forming a Schottky junction with the semiconductor layer, and formed on a semiconductor layer, which spreads over the concave portion and peripheral portions of the concave portion, on the III-V nitride semiconductor layer. A dimension of the concave portion in a depth direction is set so that a portion of the Schottky electrode provided in the concave portion can adjust a quantity of the carriers traveling in the channel region.05-27-2010
20100120233Continuous Feed Chemical Vapor Deposition - Embodiments of the invention generally relate to a method for forming a multi-layered material during a continuous chemical vapor deposition (CVD) process. In one embodiment, a method for forming a multi-layered material during a continuous CVD process is provided which includes continuously advancing a plurality of wafers through a deposition system having at least four deposition zones. Multiple layers of materials are deposited on each wafer, such that one layer is deposited at each deposition zone. The methods provide advancing each wafer through each deposition zone while depositing a first layer from the first deposition zone, a second layer from the second deposition zone, a third layer from the third deposition zone, and a fourth layer from the fourth deposition zone. Embodiments described herein may be utilized to form an assortment of materials on wafers or substrates, especially for forming Group III/V materials on GaAs wafers.05-13-2010
20100087050Chemical vapor deposition with energy input - Methods of depositing compound semiconductors onto substrates are disclosed, including directing gaseous reactants into a reaction chamber containing the substrates, selectively supplying energy to one of the gaseous reactants in order to impart sufficient energy to activate that reactant but insufficient to decompose the reactant, and then decomposing the reactant at the surface of the substrate in order to react with the other reactants. The preferred energy source is microwave or infrared radiation, and reactors for carrying out these methods are also disclosed.04-08-2010
20100081260Method for forming a semiconductor film - An apparatus for high-rate chemical vapor (CVD) deposition of semiconductor films comprises a reaction chamber for receiving therein a substrate and a film forming gas, a gas inlet for introducing the film forming gas into the reaction chamber, an incidence window in the reaction chamber for transmission of a laser sheet into the reaction chamber, a laser disposed outside the reaction chamber for generating the laser sheet and an antenna disposed outside the reaction chamber for generating a plasma therein. The film forming gas in the chamber is excited and decomposed by the laser sheet, which passes in parallel with the substrate along a plane spaced apart therefrom, and concurrent ionization effected by the antenna, thereby forming a dense semiconductor film on the substrate at high rate.04-01-2010
20100081261Method of fabricating silicon carbide (SiC) layer - A method of fabricating a silicon carbide (SiC) layer is disclosed, which comprises steps: (S04-01-2010
20090263957METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device according to one embodiment includes: exposing a surface of a semiconductor substrate to a halogen-containing gas that contains at least one of Si and Ge, the semiconductor substrate being provided with a member comprising an oxide and consisting mainly of Si; and exposing the surface of the semiconductor substrate to an atmosphere containing at least one of a Si-containing gas not containing halogen and a Ge-containing gas not containing halogen after starting exposure of the surface of the semiconductor substrate to the halogen-containing gas, thereby epitaxially growing a crystal film containing at least one of Si and Ge on the surface.10-22-2009
20090162998Methods of Manufacturing Memory Units, and Methods of Manufacturing Semiconductor Devices - Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided.06-25-2009
20100099241METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device according to one embodiment includes: removing a native oxide film and adhering silicon nitrides on an area of a Si based substrate in hydrogen gas atmosphere under a condition in which a pressure is a first pressure and a temperature is a first temperature, a silicon nitride-containing member being formed on the Si based substrate, the area being a area not covered by the member; lowering the temperature to a second temperature from the first temperature while maintaining the pressure at the first pressure in hydrogen gas atmosphere; lowering the pressure to a second pressure from the first pressure while maintaining the temperature at the second temperature in hydrogen gas atmosphere; and epitaxially growing a crystal on the area of the Si based substrate in a precursor gas atmosphere after the pressure is lowered to the second pressure, the crystal including at least one of Si and Ge, the precursor gas atmosphere including at least one of hydrogen, Si and Ge.04-22-2010
20100279493DOPING OF SEMICONDUCTOR LAYER FOR IMPROVED EFFICIENCY OF SEMICONDUCTOR STRUCTURES - A system and method for intentional doping, including variable doping, within a semiconductor structure for improved efficiency is described. One embodiment includes a method for forming a semiconductor structure, the method comprising forming a first semiconductor layer, wherein the first semiconductor layer comprises a first semiconductor material, and forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer comprises a second semiconductor material, wherein the second semiconductor material is an oppositely-typed semiconductor material from the first semiconductor material, and wherein the second semiconductor layer comprises a first region adjacent to the first semiconductor layer, wherein the first region comprises second semiconductor material, and a second region adjacent to the first region, wherein the second region comprises intentionally doped second semiconductor material to increase a built-in potential of the semiconductor structure.11-04-2010
20110201181APPARATUS AND METHOD FOR GROWING NITRIDE SEMICONDUCTOR CRYSTAL FILM - An apparatus for growing a nitride semiconductor crystal film, comprises a chamber that can control inside temperature and air pressure, a susceptor supported by a rotating shaft inside the chamber and on which a growth substrate is placed, a reactant gas supplier that emits reactant gas to the growth substrate in parallel to a surface of the growth substrate, a first subflow gas supplier that emits first subflow gas for pressing the reactant gas down to the surface of the growth substrate at an inclination angle of 45 to 90 degrees in a same in-plane direction as the reactant gas, a second subflow gas supplier that emits second subflow gas for removing the reactant gas from an periphery of the growth substrate to the surface at an inclination angle of 45 to 90 degrees, and an exhaust device that exhausts gas from the chamber.08-18-2011
20120295421LOW TEMPERATURE SELECTIVE EPITAXY OF SILICON GERMANIUM ALLOYS EMPLOYING CYCLIC DEPOSIT AND ETCH - Cyclic deposit and etch (CDE) selective epitaxial growth employs an etch chemistry employing a combination of hydrogen chloride and a germanium-containing gas to provide selective deposition of a silicon germanium alloy at temperatures lower than 625° C. High strain epitaxial silicon germanium alloys having a germanium concentration greater than 35 atomic percent in a temperature range between 400° C. and 550° C. A high order silane having a formula of SinH2n+2, in which n is an integer greater than 3, in combination with a germanium-containing precursor gas is employed to deposit the silicon germanium alloy with thickness uniformity and at a high deposition rate during each deposition step in this temperature range. Presence of the germanium-containing gas in the etch chemistry enhances the etch rate of the deposited silicon germanium alloy material during the etch step.11-22-2012
20110171815PATTERNING METHOD FOR HIGH DENSITY PILLAR STRUCTURES - A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.07-14-2011
20100279494Method For Releasing a Thin-Film Substrate - The present disclosure relates to methods for selectively etching a porous semiconductor layer to separate a thin-film semiconductor substrate (TFSS) having planar or three-dimensional features from a corresponding semiconductor template. The method involves forming a conformal sacrificial porous semiconductor layer on a template. Next, a conformal thin film silicon substrate is formed on top of the porous silicon layer. The middle porous silicon layer is then selectively etched to separate the TFSS and semiconductor template. The disclosed advanced etching chemistries and etching methods achieve selective etching with minimal damage to the TFSS and template.11-04-2010
20080206965STRAINED SILICON MADE BY PRECIPITATING CARBON FROM Si(1-x-y)GexCy ALLOY - Disclosed herein is a method of preparing strained silicon comprising annealing a carbon-doped silicon-germanium (SiGe:C) alloy containing region disposed adjacent to a silicon region, wherein the lattice constant of the SiGe:C alloy after annealing is greater than that of the SiGe:C alloy prior to annealing. The method can be used to prepare articles including metal oxide semiconductor field effect transistor (MOSFET) devices.08-28-2008
20090280625METHOD FOR SEPARATING SEMICONDUCTOR LAYER FROM SUBSTRATE - A method for separating a semiconductor from a substrate is disclosed. The method comprises the following steps: forming a plurality of columns on a substrate; epitaxially growing a semiconductor on the plurality of columns; and injecting etching liquid into the void among the plurality of columns so as to separate the semiconductor from the substrate. The method of this invention can enhance the etching efficiency of separating the semiconductor from the substrate and reduce the fabrication cost because the etching area is increased due to the void among the plurality of columns. In addition, the method will not confine the material of the above-mentioned substrate.11-12-2009
20120289034Methods of Forming NAND Memory Constructions - Some embodiments include NAND memory constructions. The constructions may contain semiconductor material pillars extending upwardly between dielectric regions, with individual pillars having a pair of opposing vertically-extending sides along a cross-section. First conductivity type regions may be along first sides of the pillars, and second conductivity type regions may be along second sides of the individual pillars; with the second conductivity type regions contacting interconnect lines. Vertical NAND strings may be over the pillars, and select devices may selectively couple the NAND strings with the interconnect lines. The select devices may have vertical channels directly against the semiconductor material pillars and directly against upper regions of the first and second conductivity type regions. Some embodiments include methods of forming NAND memory constructions.11-15-2012
20120289033METHOD AND DEVICE FOR PRODUCING A COMPOUND SEMICONDUCTOR LAYER - In a method for producing a I-III-VI compound semiconductor layer, a substrate is provided with a coating which has a metallic precursor layer. The coating is kept, for the duration of a process time, at temperatures of at least 350 degrees C. and the metallic precursor layer, in the presence of a chalcogen at an ambient pressure of between 500 mbar and 1500 mbar, is converted into a compound semiconductor layer. The coating is kept at temperatures for the duration of an activation time which attain at least an activation barrier temperature, whereby as the activation barrier temperature a value of at least 600° C. is selected.11-15-2012
20120289029METHOD OF CONTROLLING AMOUNT OF ADSORBED CARBON NANOTUBES AND METHOD OF FABRICATING CARBON NANOTUBE DEVICE - Provided are a method of controlling an amount of adsorbed carbon nanotubes (CNTs) and a method of fabricating a CNT device. The method of controlling an amount of adsorbed CNTs includes adsorbing CNT particles onto a semiconductor structure, and removing some of the adsorbed CNTs by performing an oxygen plasma treatment on the adsorbed CNT particles.11-15-2012
20120289032SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed. Over the main surface, insulating films 11-15-2012
20120289030ION-ASSISTED DIRECT GROWTH OF POROUS MATERIALS - Methods of creating porous materials, such as silicon, are described. In some embodiments, plasma sheath modification is used to create ion beams of various incidence angles. These ion beams may, in some cases, form a focused ion beam. The wide range of incidence angles allows the material to be deposited amorphously. The porosity and pore size can be varied by changing various process parameters. In other embodiments, porous oxides can be created by adding oxygen to previously created layers of porous material.11-15-2012
20100144122Hybrid chemical vapor deposition process combining hot-wire cvd and plasma-enhanced cvd - Hybrid chemical vapor deposition systems for depositing a semiconductor-containing thin film over a substrate comprise a reaction space, a substrate support member configured to permit movement of a substrate in a longitudinal direction and a plasma-generating apparatus disposed in the reaction space and configured to form plasma-excited species of a vapor phase chemical. The systems further comprise a hot wire unit disposed in the reaction space and configured to heat and decompose a vapor phase chemical. The hot wire unit can be a filament. The systems can further comprise an additional reaction space proximate the reaction space. The additional reaction space can comprise a plasma-generating apparatus configured to form plasma-excited species of a vapor phase chemical and a hot wire unit configured to heat and decompose a vapor phase chemical.06-10-2010
20100144126METHODS FOR SITE-SELECTIVE GROWTH OF HORIZONTAL NANOWIRES, NANOWIRES GROWN BY THE METHODS AND NANODEVICES COMPRISING THE NANOWIRES - Methods for the site-selective growth of horizontal nanowires are provided. According to the methods, horizontal nanowires having a predetermined length and diameter can be grown site-selectively at desired sites in a direction parallel to a substrate to fabricate a device with high degree of integration. Further provided are nanowires grown by the methods and nanodevices comprising the nanowires.06-10-2010
20090170291Method of fabricating an organic thin film transistor - An organic thin film transistor that prevents the surface of an organic semiconductor layer from being damaged and reduces turn-off current, a method of fabricating the same, and an organic light-emitting device incorporating the organic thin film transistor. The organic thin film transistor includes a substrate, source and drain electrodes arranged on the substrate, a semiconductor layer contacting the source and drain electrodes and comprising a channel region, a protective film arranged on the semiconductor layer and having a same pattern as the semiconductor layer, the protective film comprising a laser-absorbing material, a gate insulating film arranged between the gate and the source and drain electrodes, a gate electrode arranged on the gate insulating film and a separation pattern arranged within the semiconductor layer and within the protective film, the separation pattern adapted to define the channel region of the semiconductor layer.07-02-2009
20080293223Method for Manufacturing Strained Silicon - In accordance with a particular embodiment of the present invention, a method for manufacturing strained silicon is provided. In one embodiment, the method for manufacturing strained silicon includes inducing a curvature in a silicon wafer, depositing an epitaxial layer of silicon upon an upper surface of the silicon water while the silicon wafer is under the induced curvature, and releasing the silicon wafer from the induced curvature, after depositing the epitaxial layer, such that a strain is induced in the epitaxial layer.11-27-2008
20090311851NONVOLATILE MEMORY DEVICE USING SEMICONDUCTOR NANOCRYSTALS AND METHOD FORMING SAME - A method of making a nanoparticle array that includes replicating a dimension of a self-assembled film into a dielectric film, to form a porous dielectric film, conformally depositing a material over said porous dielectric film, and anisotropically and selectively etching said deposited material.12-17-2009
20100267220Methods Of Depositing Antimony-Comprising Phase Change Material Onto A Substrate And Methods Of Forming Phase Change Memory Circuitry - A method of depositing an antimony-comprising phase change material onto a substrate includes providing a reducing agent and vaporized Sb(OR)10-21-2010
20080242060METHOD FOR FORMING AlGaN CRYSTAL LAYER - A method for preparing an AlGaN crystal layer with good surface flatness is provided. A surface layer of AlN is epitaxially formed on a c-plane sapphire single crystal base material by MOCVD method, and the resulting laminated body is then heated at a temperature of 1300° C. or higher so that a template substrate applying in-plane compressive stress and having a surface layer flat at a substantially atomic level is obtained. An AlGaN layer is formed on the template substrate at a deposition temperature higher than 1000° C. by an MOCVD method that includes depositing alternating layers of a first unit layer including a Group III nitride represented by the composition formula Al10-02-2008
20110269298Irradiation assisted nucleation of quantum confinements by atomic layer deposition - A method of fabricating quantum confinements is provided. The method includes depositing, using a deposition apparatus, a material layer on a substrate, where the depositing includes irradiating the layer, before a cycle, during a cycle, and/or after a cycle of the deposition to alter nucleation of quantum confinements in the material layer to control a size and/or a shape of the quantum confinements. The quantum confinements can include quantum wells, nanowires, or quantum dots. The irradiation can be in-situ or ex-situ with respect to the deposition apparatus. The irradiation can include irradiation by photons, electrons, or ions. The deposition is can include atomic layer deposition, chemical vapor deposition, MOCVD, molecular beam epitaxy, evaporation, sputtering, or pulsed-laser deposition.11-03-2011
20090181524Method of manufacturing semiconductor device and apparatus for processing substrate - A process for producing a semiconductor device, in which in the formation of a boron doped silicon film from, for example, monosilane and boron trichloride by vacuum CVD technique, there can be produced a film excelling in inter-batch homogeneity with respect to the growth rate and concentration of a dopant element, such as boron. The process includes the step of performing the first purge through conducting at least once of while a substrate after treatment is housed in a reaction furnace, vacuuming of the reaction furnace and inert gas supply thereto and the steps of performing the second purge through conducting at least once of after carrying of the substrate after treatment out of the reaction furnace, prior to carrying of a substrate to be next treated into the reaction furnace and while at least no product substrate is housed in the reaction furnace, vacuuming of the reaction furnace and inert gas supply thereto.07-16-2009
20110269299DIRECT CHEMICAL VAPOR DEPOSITION OF GRAPHENE ON DIELECTRIC SURFACES - A substrate is provided that has a metallic layer on a substrate surface of a substrate. A film made of a two dimensional (2-D) material, such as graphene, is deposited on a metallic surface of the metallic layer. The metallic layer is dewet and/or removed to provide the film on the substrate surface.11-03-2011
20100273314NON-CIRCULAR SUBSTRATE HOLDERS - A substrate holder comprises a generally circular planar body, the body having greater than or equal to two pairs of diametrically opposed, parallel flat edges, and wherein the substrate holder is configured to fit on a generally circular susceptor within a processing chamber. In some embodiments the substrate holder has four pairs of diametrically opposed, parallel flat edges, whereby the substrate holder is substantially octagonal. Furthermore, in some embodiments the substrate holder covers less than eighty percent of the susceptor area. A method of processing a substrate using the substrate holder includes: loading the substrate into a recess in the substrate holder; transferring the substrate holder through a loadlock into the processing chamber, the substrate holder being presented with a smallest cross-section aligned for passage through the loadlock; placing the substrate holder on the susceptor; and processing the substrate. The substrate holder may carry a plurality of substrates. Alternatively, the substrate holder may carry a single large substrate, the substrate being trimmed to fit the substrate holder.10-28-2010
20120064699METHODS AND SYSTEMS FOR SPRAY PYROLYSIS WITH ADDITION OF VOLATILE NON-POLAR MATERIALS - Method and system for forming a cadmium-sulfide layer on a substrate. The method includes preparing a solution and loading the solution into a pyrolysis-deposition system. The solution uses at least one cadmium-containing solute, at least one sulfur-containing solute, water, and at least one selected material. The pyrolysis-deposition system includes one or more nozzles and one or more heating devices. The method further includes placing a substrate into the pyrolysis-deposition system, adjusting a distance between the substrate and the one or more nozzles, heating the substrate with the one or more heating devices, and spraying the solution including the selected material towards the substrate. The selected material satisfies at least one property selected from a group consisting of the selected material being non-polar, the selected material having at least higher volatility than water, and the selected material having at least lower heat capacity than water.03-15-2012
20120142167METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes steps of forming a semiconductor device layer on an upper surface of a substrate including the upper surface, a lower surface and a dislocation concentrated region arranged so as to part a first side closer to the upper surface and a second side closer to the lower surface, exposing a portion where the dislocation concentrated region does not exist above on the lower surface by removing the substrate on the second side along with at least a part of the dislocation concentrated region, and forming an electrode on the portion.06-07-2012
20090029530Method of manufacturing thin film semiconductor device - Disclosed herein is a method of manufacturing a thin film semiconductor device includes the step of forming a silicon thin film including a crystalline structure on a substrate by a plasma CVD process in which a high order silane gas represented by the formula Si01-29-2009
20090181522Method for producing semiconductor optical device - To grasp a removable particle contamination and appropriately removing a particle contamination exposing from a surface of a semiconductor layer, this production method of the semiconductor optical device includes a surface treatment step in which particle contaminations removed from a surface of a cap layer 07-16-2009
20110207299COMPOUND SEMICONDUCTOR MANUFACTURING DEVICE, COMPOUND SEMICONDUCTOR MANUFACTURING METHOD, AND JIG FOR MANUFACTURING COMPOUND SEMICONDUCTOR - When compound semiconductor layers are formed on a compound semiconductor substrate (08-25-2011
20110207298DENSE PITCH BULK FINFET PROCESS BY SELECTIVE EPI AND ETCH - Disclosed is a method of forming a pair of transistors by epitaxially growing a pair of silicon fins on a silicon germanium fin on a bulk wafer. In one embodiment a gate conductor between the fins is isolated from a conductor layer on the bulk wafer so a front gate may be formed. In another embodiment a gate conductor between the fins contacts a conductor layer on the bulk wafer so a back gate may be formed. In yet another embodiment both of the previous structures are simultaneously formed on the same bulk wafer. The method allow the pairs of transistors to be formed with a variety of features.08-25-2011
20110207297Method for Manufacturing Chalcopyrite Film - A highly safe method of obtaining chalcopyrite film wherein a Ib group metal and IIIb group metal are sufficiently combined with a VIb group element by only heat treatment without using an atmosphere containing a VIb group element (Se, S, Te).08-25-2011
20110207296FABRICATION METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor-device fabrication method includes forming a second semiconductor region of a second conductivity on a surface layer of a first semiconductor region of a first conductivity, the second semiconductor region having an impurity concentration higher than the first semiconductor region; forming a trench penetrating the second semiconductor region, to the first semiconductor region; embedding a first electrode inside the trench via an insulating film, at a height lower than a surface of the second semiconductor region; forming an interlayer insulating film inside the trench, covering the first electrode; leaving the interlayer insulating film on only a surface of the first electrode; removing the second semiconductor region such that the surface thereof is positioned lower than an interface between the first electrode and the interlayer insulating film; and forming a second electrode contacting the second semiconductor region and adjacent to the first electrode via the insulating film in the trench.08-25-2011
20100151660METHOD FOR FORMING SEMICONDUCTOR DEVICES WITH ACTIVE SILICON HEIGHT VARIATION - A method for forming different active thicknesses on the same silicon layer includes masking the silicon layer and exposing selected regions of the silicon layer. The thickness of the silicon layer at the exposed regions is changed, either by adding silicon or subtracting silicon from the layer at the exposed regions. Once the mask is removed, the silicon layer has regions of different active thicknesses, respectively suitable for use in different types of devices, such as diodes and transistors.06-17-2010
20090137099MBE DEVICE AND METHOD FOR THE OPERATION THEREOF - A molecular beam epitaxy (MBE) device (05-28-2009
20100151662FIELD EFFECT TRANSISTOR AND ITS MANUFACTURING METHOD - The present invention is an object to provide a high-performance vertical field effect transistor having a microminiaturized structure in which the distance between the gate and the channel is made short not through a microfabrication process, having a large gate capacitance, and so elaborated that the gate can control the channel current with a low voltage, and a method for simply and efficiently manufacturing such a field effect transistor not through a complex process such as a microfabrication process. The field effect transistor of the present invention comprises a first electrode, a second electrode so arranged as to be electrically insulated from the first electrode, a semiconductive rod-shaped body extending through at least one of the first and second electrodes, provided along the inner wall of a hole in which the first and second electrodes are exposed, and interconnecting the first and second electrodes, and a third electrode at least partially inserted in the hole and opposed to the semiconductive rod-shaped body with an insulating layer interposed between the third electrode and the semiconductive rod-shaped body. The aspect preferably include an aspect in which the thickness of the insulating layer is 50 nm or less and an aspect in which the semiconductive rod-shaped body is a single-wall carbon nanotube.06-17-2010
20100151661NANOSTRUCTURES FORMED OF BRANCHED NANOWHISKERS AND METHODS OF PRODUCING THE SAME - A method of forming a nanostructure having the form of a tree, comprises a first stage and a second stage. The first stage includes providing one or more catalytic particles on a substrate surface, and growing a first nanowhisker via each catalytic particle. The second stage includes providing, on the periphery of each first nanowhisker, one or more second catalytic particles, and growing, from each second catalytic particle, a second nanowhisker extending transversely from the periphery of the respective first nanowhisker. Further stages may be included to grow one or more further nanowhiskers extending from the nanowhisker(s) of the preceding stage. Heterostructures may be created within the nanowhiskers. Such nanostructures may form the components of a solar cell array or a light emitting flat panel, where the nanowhiskers are formed of a photosensitive material. A neural network may be formed by positioning the first nanowhiskers close together so that adjacent trees contact one another through nanowhiskers grown in a subsequent stage, and heterojunctions within the nanowhiskers create tunnel barriers to current flow.06-17-2010
20090325365METHOD OF MANUFACTURING SILICON NANOWIRES USING SILICON NANODOT THIN FILM - Provided is a method of manufacturing silicon nanowires including: forming a silicon nanodot thin film having a plurality of silicon nanodots exposed on a substrate; and growing the silicon nanowires on the silicon nanodot thin film using the silicon nanodots as a nucleation site. The silicon nanowires can be manufactured using the silicon nanodot thin film disposed in a silicon nitride matrix, as a nucleation site instead of using catalytic metal islands, wherein the silicon nanodot thin film includes the silicon nanodots.12-31-2009
20090325366SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - There are provided a substrate processing method and apparatus adapted to prevent deterioration of film thickness uniformity while maintaining the film forming rate. The substrate processing method comprises: (a) accommodating a plurality of substrates in a process chamber by carrying and stacking the substrates in the process chamber, (b) forming first amorphous silicon films to a predetermined thickness by heating at least the substrates and supplying first gas, and (c) forming second amorphous silicon films to a predetermined thickness by heating at least the substrates and supplying second gas different from the first gas. The first gas is higher order gas than the second gas.12-31-2009
20130217212FABRICATION METHOD OF NITRIDE FORMING ON SILICON SUBSTRATE - The invention is directed to a method for forming a nitride on a silicon substrate. In the method of the present invention, a silicon substrate is provided and a buffer layer is formed on the silicon substrate. The formation of the buffer layer includes a multi-level temperature modulation process having a plurality temperature levels and a plurality of temperature modulations. For each of the temperature modulations, the temperature is gradually decreased. A nitride is formed on the buffer layer.08-22-2013
20130217213PRODUCTION PROCESS OF EPITAXIAL SILICON CARBIDE SINGLE CRYSTAL SUBSTRATE - An object of the present invention is to provide a production process of an epitaxial silicon carbide single crystal substrate having a high-quality silicon carbide single crystal thin film reduced in the surface defect and the like on a silicon carbide single crystal substrate with a small off-angle.08-22-2013
20090081854Method of forming nanowire and method of manufacturing semiconductor device comprising the nanowire - A method of forming a nanowire and a semiconductor device comprising the nanowire are provided. The method of forming a nanowire includes forming a patterned Si03-26-2009
20100248459METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device including: cleaning an apparatus used to grow a layer including Ga; performing a first step of forming a first layer on a substrate made of silicon by using the apparatus, the first layer including a nitride semiconductor that does not include Ga as a composition element and has a Ga impurity concentration of 2×1009-30-2010
20100248458COATING APPARATUS AND COATING METHOD - The present invention provides a coating apparatus capable of efficiently performing a deposition process and also provides an efficient coating method.09-30-2010
20100248457METHOD OF FORMING NONVOLATILE MEMORY DEVICE - Provided is a method of forming a nonvolatile memory device. The method may include alternatingly stacking n number of dielectric layers and n number of conductive layers on a substrate, forming a non-photosensitive pattern on the alternatingly stacked dielectric layers and conductive layers, etching the i-th conductive layer and i-th dielectric (2≦i≦n, i is a natural number indicating a stacking order of the conductive layers and the dielectric layers) by using the non-photosensitive pattern as an etch mask, laterally etching a sidewall of the non-photosensitive pattern and etching the i-th conductive layer, (i−1)-th conductive layer, i-th dielectric layer and (i−1)-th dielectric layer by using the etched non-photosensitive pattern as an etch mask.09-30-2010
20100248456Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first etching process is performed to etch a layer using a resist mask and a hard mask. The resist mask covers the hard mask. The hard mask covers the layer. Then, a second etching process is performed to etch the layer using the hard mask, substantially in the absence of the resist mask.09-30-2010
20100248455Manufacturing method of group III nitride semiconductor - A manufacturing method of a group III nitride semiconductor comprising: preparing a substrate including a buffer layer; forming a first layer on the buffer layer from a group III nitride semiconductor by MOCVD while doping an anti-surfactant, wherein a thickness of the first layer is equal to or thinner than 2 μm; forming a second layer on the first layer from a group III nitride semiconductor by MOCVD while doping at least one of surfactant and an anti-surfactant; and controlling a crystalline quality and a surface flatness of the second layer by adjusting an amount of the anti-surfactant and the surfactant doped during the formation of the second layer.09-30-2010
20100248454METHOD OF FORMING FIN STRUCTURES USING A SACRIFICIAL ETCH STOP LAYER ON BULK SEMICONDUCTOR MATERIAL - A method of manufacturing semiconductor fins for a semiconductor device may begin by providing a bulk semiconductor substrate. The method continues by growing a layer of first epitaxial semiconductor material on the bulk semiconductor substrate, and by growing a layer of second epitaxial semiconductor material on the layer of first epitaxial semiconductor material. The method then creates a fin pattern mask on the layer of second epitaxial semiconductor material. The fin pattern mask has features corresponding to a plurality of fins. Next, the method anisotropically etches the layer of second epitaxial semiconductor material, using the fin pattern mask as an etch mask, and using the layer of first epitaxial semiconductor material as an etch stop layer. This etching step results in a plurality of fins formed from the layer of second epitaxial semiconductor material.09-30-2010
20110143523Semiconductor integrated device and manufacturing method for the same - A manufacturing method for a semiconductor integrated device including forming a second impurity layer of a second conductivity type that is higher in impurity concentration than a second well of the second conductivity type on a first impurity layer of a first conductivity type that is higher in impurity concentration than a first well of the first conductivity type, forming the first well of the first conductivity type on the second impurity layer of the second conductivity type on the first impurity layer of the first conductivity type, the first well being supplied with potential from the first impurity layer of the first conductivity type, and forming the second well of the second conductivity type on the second impurity layer of the second conductivity type on the first impurity layer of the first conductivity type, the second well being supplied with potential from the second impurity layer of the second conductivity type.06-16-2011
20090081853PROCESS FOR DEPOSITING LAYERS CONTAINING SILICON AND GERMANIUM - The invention relates to a method for depositing at least one semiconductor layer on at least one substrate in a processing chamber (03-26-2009
20090087963METHOD FOR REDUCING PILLAR STRUCTURE DIMENSIONS OF A SEMICONDUCTOR DEVICE - A method creates pillar structures on a semiconductor wafer and includes the steps of providing a layer of semiconductor. A layer of photoresist is applied over the layer of semiconductor. The layer of photoresist is exposed with an initial pattern of light to effect the layer of photoresist. The photoresist layer is then etched away to provide a photoresist pattern to create the pillar structures. The photoresist pattern is processed in the layer of photoresist after the step of exposing the layer of photoresist and prior to the step of etching to reduce the dimensions of the photoresist pattern in the layer of photoresist.04-02-2009
20090004830Device and method for depositing especially doped layers by means of OVPD or the like - The invention relates to a method for producing especially doped layers for electronic, luminescent or photovoltaic components, especially OLEDs, where one or more liquid or solid starting materials evaporate in a source (01-01-2009
20090305487NON-VOLATILE RESISTANCE SWITCHING MEMORY - A microelectronic device or non-volatile resistance switching memory comprising the switching material for storing digital information. A process includes a step of depositing the switching material by a CMOS deposition technique at a temperature lower than 400° C.12-10-2009
20090017601CRYSTALLINE FILM DEVICES, APPARATUSES FOR AND METHODS OF FABRICATION - Methods of depositing thin film materials having crystalline content are provided. The methods use plasma enhanced chemical vapor deposition. According to one embodiment of the present invention, microcrystalline silicon films are obtained. According to a second embodiment of the present invention, crystalline films of zinc oxide are obtained. According to a third embodiment of the present invention, crystalline films of iron oxide are obtained.01-15-2009
20090203195Hybrid nanocomposite semiconductor material, and method of producing inorganic semiconductor therefor - Hybrid semiconductor materials have an inorganic semiconductor incorporated into a hole-conductive fluorene copolymer film. Nanometer-sized particles of the inorganic semiconductor may be prepared by mixing inorganic semiconductor precursors with a steric-hindering coordinating solvent and heating the mixture with microwaves to a temperature below the boiling point of the solvent.08-13-2009
20120142171METHOD OF FORMING A HIGH CAPACITANCE DIODE - In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.06-07-2012
20120142169PROGRAMMABLE METALLIZATION MEMORY CELL WITH PLANARIZED SILVER ELECTRODE - Programmable metallization memory cells having a planarized silver electrode and methods of forming the same are disclosed. The programmable metallization memory cells include a first metal contact and a second metal contact, an ion conductor solid electrolyte material is between the first metal contact and the second metal contact, and either a silver alloy doping electrode separates the ion conductor solid electrolyte material from the first metal contact or the second metal contact, or a silver doping electrode separates the ion conductor solid electrolyte material from the first metal contact. The silver electrode includes a silver layer and a metal seed layer separating the silver layer from the first metal contact.06-07-2012
20090221132METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING ELECTRO-OPTICAL APPARATUS - A method for manufacturing a semiconductor apparatus includes forming a step layer in a first region on a substrate; forming a first semiconductor thin film on the top surface and sidewalls of the step layer; removing part of the first semiconductor thin film from the top surface while leaving part of the first semiconductor thin film on the sidewalls; removing the step layer; and forming a fin-type transistor that includes the first semiconductor thin film disposed on the sidewalls as a channel.09-03-2009
20090246943APPARATUS FOR MASS-PRODUCING SILICON-BASED THIN FILM AND METHOD FOR MASS-PRODUCING SILICON-BASED THIN FILM - A silicon-based thin film mass-producing apparatus, including transparent electrodes placed to face in parallel to corresponding counter electrodes with a space therebetween, and silicon-based thin films are deposited on the transparent electrodes by feeding a raw material gas for depositing the silicon-based thin films into the chamber and by applying a DC pulse voltage to the counter electrodes to generate plasma. Unlike methods in which a radio frequency voltage is intermittently applied to perform discharge, a high plasma density distribution does not occur, and in-plane film thickness distribution does not occur. Furthermore, since the DC pulse voltage rises sharply, the ON period can be shortened. As a result, generation of a sheath ceases in the transient state before reaching the steady state, and the thickness of the sheath is small, which allows the space between the counter and transparent electrodes to decrease.10-01-2009
20090209091Method of Manufacturing Group III Nitride Crystal - Made available is a Group III nitride crystal manufacturing method whereby incidence of cracking in the III-nitride crystal when the III-nitride substrate is removed is kept to a minimum. III nitride crystal manufacturing method provided with: a step of growing, onto one principal face (08-20-2009
20120171847THIN-FILM DEVICES FORMED FROM SOLID PARTICLES - Methods and devices are provided for forming thin-films from solid group IIIA-based particles. In one embodiment of the present invention, a method is described comprising of providing a first material comprising an alloy of a) a group IIIA-based material and b) at least one other material. The material may be included in an amount sufficient so that no liquid phase of the alloy is present within the first material in a temperature range between room temperature and a deposition or pre-deposition temperature higher than room temperature, wherein the group IIIA-based material is otherwise liquid in that temperature range. The other material may be a group IA material. A precursor material may be formulated comprising a) particles of the first material and b) particles containing at least one element from the group consisting of: group IB, IIIA, VIA element, alloys containing any of the foregoing elements, or combinations thereof.07-05-2012
20090221131Method for preparing substrate having monocrystalline film - Provided is a method for easily preparing a substrate comprising a monocrystalline film thereon or thereabove with almost no crystal defects without using a special substrate. More specifically, provided is a method for preparing a substrate comprising a monocrystalline film formed on or above a handle substrate, the method comprising: a step A of providing a donor substrate and the handle substrate; a step B of growing a monocrystalline layer on the donor substrate; a step C of implanting ions into the monocrystalline layer on the donor substrate so as to form an ion-implanted layer; a step D of bonding a surface of the monocrystalline layer of the ion-implanted donor substrate to a surface of the handle substrate; and a step E of peeling the bonded donor substrate at the ion-implanted layer existing in the monocrystalline layer so as to form the monocrystalline film on or above the handle substrate; wherein at least the steps A to E are repeated by using the handle substrate having the monocrystalline film formed thereon or thereabove as a donor substrate.09-03-2009
20120171848Method and System for Manufacturing Silicon and Silicon Carbide - The present invention provides a method of manufacturing silicon and a manufacturing system for manufacturing and extracting silicon by grinding silicon carbide and silica, mixing each at predetermined ratio after cleaning them, housing them in a crucible, heating this by a heating unit to make them react, oxidizing the silicon carbide with the silica and further, reducing the silica with the silicon carbide. The present invention further provides a method of simultaneously manufacturing silicon and silicon carbide and a manufacturing system for producing silicon carbide by forming a silicon carbide film by vapor phase epitaxy using active gas generated in heating for reaction for material and recovering the silicon carbide film.07-05-2012
20090239358Memory Device Manufacturing Method - A method for making a memory device includes providing a dielectric material, having first and second upwardly and inwardly tapering surfaces and a surface segment connecting the first and second surfaces. First and second electrodes are formed over the first and second surfaces. A memory element is formed over the surface segment to electrically connect the first and second electrodes.09-24-2009
20090246945METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE - A method for manufacturing a nitride semiconductor substrate includes the steps of growing a first nitride semiconductor on a substrate, patterning the first nitride semiconductor to obtain a pattern surrounded by a plane equivalent to the (11-20) plane and having at least two concave portions that are similar in their planar shape, and growing a second nitride semiconductor layer, using a plane equivalent to the (11-20) plane in the first nitride semiconductor pattern as a growth nucleus.10-01-2009
20090246940System and method for depositing a material on a substrate - A method and apparatus for depositing a film on a substrate includes a plasma source positioned proximate to a distributor configured to provide a semiconductor coating on a substrate.10-01-2009
20090246941DEPOSITION APPARATUS, DEPOSITION SYSTEM AND DEPOSITION METHOD - A deposition system is provided to avoid cross contamination in each layer formed in a manufacturing process of organic electroluminescent device, etc., and also provided to reduce footprint. Provided is an apparatus 10-01-2009
20090239357AlGaN SUBSTRATE AND PRODUCTION METHOD THEREOF - A substrate is formed of Al09-24-2009
20090253249Method of manufacturing semiconductor device - There is provided a method of manufacturing a semiconductor device which, in the case where an InP-based device is formed with a sacrificial layer in between, is capable of obtaining better device characteristics than those in the case where an AlAs single layer is used as the sacrificial layer, and which does not have the possibility that the device layer is etched together with the sacrificial layer during etching of the sacrificial layer. A method of manufacturing a semiconductor device includes: a formation step of forming a sacrificial layer which is pseudomorphic to InP on an InP substrate, and then forming an InP-based device layer on the sacrificial layer; and a separation step of separating the InP substrate and the device layer from each other by etching the sacrificial layer.10-08-2009
20090253246PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - There is provided a plasma processing device capable of forming a film in a favorable manner irrespective of deflection generated in an anode electrode and a cathode electrode in the case where an area of the electrodes is increased.10-08-2009
20090253248Method of manufacturing silicon nano-structure - A method for making silicon nano-structure, the method includes the following steps. Firstly, providing a growing substrate and a growing device, the growing device comprising a heating apparatus and a reacting room. Secondly, placing the growing substrate and a quantity of catalyst separately into the reacting room. Thirdly, introducing a silicon-containing gas and hydrogen gas into the reacting room. Lastly, heating the reacting room to a temperature of 500˜1100° C.10-08-2009
20090253250FORMATION OF NANOWHISKERS ON A SUBSTRATE OF DISSIMILAR MATERIAL - A method for forming a nanowhisker of, e.g., a III-V semiconductor material on a silicon substrate, comprises: preparing a surface of the silicon substrate with measures including passivating the substrate surface by HF etching, so that the substrate surface is essentially atomically flat. Catalytic particles on the substrate surface are deposited from an aerosol; the substrate is annealed; and gases for a MOVPE process are introduced into the atmosphere surrounding the substrate, so that nanowhiskers are grown by the VLS mechanism. In the grown nanowhisker, the crystal directions of the substrate are transferred to the epitaxial crystal planes at the base of the nanowhisker and adjacent the substrate surface. A segment of an optically active material may be formed within the nanowhisker and bounded by heterojunctions so as to create a quantum well wherein the height of the quantum well is much greater than the thermal energy at room temperature, whereby the luminescence properties of the segment remain constant without quenching from cryogenic temperatures up to room temperature.10-08-2009
20120142166STACKING FAULT AND TWIN BLOCKING BARRIER FOR INTEGRATING III-V ON SI - A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×1006-07-2012
20100151658METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - A method for manufacturing a nitride semiconductor device, comprises epitaxially growing a semiconductor layer of a GaN-based material on the Ga surface of a GaN substrate while the GaN substrate is mounted on a substrate holder the substrate warping during the epitaxial growth so that a epitaxial deposit is deposited on the N surface of the substrate; and subjecting the N surface of the GaN substrate to vacuum suction after the epitaxial growth of the semiconductor layer; removing the epitaxial deposit from the N side of the GaN substrate after the semiconductor layer has been epitaxially grown, and before the N surface of the n-type GaN substrate is subjected to vacuum suction.06-17-2010
20100261338Nanostructures, methods of depositing nanostructures and devices incorporating the same - A method for depositing nanowires is disclosed. The method includes depositing multiple nanowires onto a surface of a liquid. The method also includes partially compressing the nanowires. The method also includes dipping a substrate into the liquid. The method further includes pulling the substrate out of the liquid at a controlled speed. The method also includes transferring the nanowires onto the substrate parallel to a direction of the pulling.10-14-2010
20130122692Semiconductor Device Manufacturing Method and Substrate Manufacturing Method - Provided is a substrate processing apparatus, a semiconductor device manufacturing method, and a substrate manufacturing method. The substrate processing apparatus comprises: a reaction chamber configured to process substrates; a first gas supply system configured to supply at least a silicon-containing gas and a chlorine-containing gas or at least a gas containing silicon and chlorine; a first gas supply unit connected to the first gas supply system; a second gas supply system configured to supply at least a reducing gas; a second gas supply unit connected to the second gas supply system; a third gas supply system configured to supply at least a carbon-containing gas and connected to at least one of the first gas supply unit and the second gas supply unit; and a control unit configured to control the first to third gas supply systems.05-16-2013
20100261340CLUSTER TOOL FOR LEDS - The present invention generally provides apparatus and methods for forming LED structures. One embodiment of the present invention provides a method for fabricating a compound nitride structure comprising forming a first layer comprising a first group-III element and nitrogen on substrates in a first processing chamber by a hydride vapor phase epitaxial (HVPE) process or a metal organic chemical vapor deposition (MOCVD) process, forming a second layer comprising a second group-III element and nitrogen over the first layer in a second processing chamber by a MOCVD process, and forming a third layer comprising a third group-III element and nitrogen over the second layer by a MOCVD process.10-14-2010
20100261339SINGLE CRYSTAL GROWTH ON A MIS-MATCHED SUBSTRATE - A process for forming a single crystal layer of one material type such as III-V semiconductor) onto a substrate of a different material type such as silicon. A substrate of a first material type is provided. At least one discrete region of catalyst material is deposited onto the substrate, the discrete region defining a seed area of the substrate. A second material type such as III-V semiconductor is grown as a single crystal nanowire onto the substrate between the substrate and catalyst material, the nanowire of second material type extending upward from the substrate with lateral dimensions not substantially exceeding the seed area. After growth of the nanowire, growth conditions are changed so as to epitaxially grow the second material type laterally from the single crystal nanowire in a direction parallel to the substrate surface.10-14-2010
20100197118MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES - A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.08-05-2010
20100227456METHOD OF GROWING SEMICONDUCTOR MICRO-CRYSTALLINE ISLANDS ON AN AMORPHOUS SUBSTARATE - A method for growing islands of semiconductor monocrystals from a solution on an amorphous substrate includes the procedures of depositing a semiconductor-metal mixture layer, applying lithography and etching for forming at least one platform, heating the at least one platform, and saturating the semiconductor-metal solution until a monocrystal of the semiconductor component is formed. The procedure of depositing a semiconductor-metal mixture layer, includes a semiconductor component and at least one other metal component, is performed on top of the amorphous substrate. The procedure of applying lithography and etching to the semiconductor-metal mixture layer and a portion of the amorphous substrate is performed for forming at least one platform, the at least one platform having a top view shape corresponding to crystal growth direction and habit respective of the semiconductor component. The procedure of heating the at least one platform is performed until the semiconductor-metal mixture layer of the at least one platform is melted and becomes a semiconductor-metal solution. The procedure of saturating the semiconductor-metal solution is performed until a monocrystal of the semiconductor component is formed from the solution on each of the at least one platform.09-09-2010
20110059597METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device capable of realizing a high yield of a large-scale semiconductor device even when a silicon carbide semiconductor including a defect is used is provided. The method of manufacturing a semiconductor device includes: a step of epitaxially growing a silicon carbide semiconductor layer on a silicon carbide semiconductor substrate; a step of polishing a surface of the silicon carbide semiconductor layer; a step of ion-implanting impurities into the silicon carbide semiconductor layer after the step of polishing; a step of performing heat treatment to activate the impurities; a step of forming a first thermal oxide film on the surface of the silicon carbide semiconductor layer after the step of performing heat treatment; a step of chemically removing the first thermal oxide film; and a step of forming an electrode layer on the silicon carbide semiconductor film.03-10-2011
20100216296Processing Method and Recording Medium - [Object] To provide a processing method capable of removing an oxide film adhering on a Si layer from the Si layer without adversely affecting parts other than the oxide film and capable of surely forming a SiGe layer with good film quality without roughening the crystal structure of a surface of the Si layer from which the oxide film has been removed, and to provide a recording medium.08-26-2010
20120129321APPARATUS FOR MANUFACTURING SEMICONDUCTOR - A semiconductor device manufacturing apparatus includes a chamber including a reaction space, a substrate disposing unit configured to dispose a substrate within the chamber, a first heating unit configured to optically heat the reaction space and disposed under the chamber, a second heating unit configured to heat the reaction space through resistive heating and disposed over the chamber, and a plasma generating unit configured to generate plasma in the reaction space. Since the apparatus generates the plasma using the plasma generating unit disposed over the chamber, the deposition process based on heating and the etch process based on the plasma can be simultaneously performed in one single chamber.05-24-2012
20100216297METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES - Methods for fabricating semiconductor device structures are disclosed. In some embodiments, methods for fabricating semiconductor device structures may comprising forming at least one raised element on a surface of a substrate, the at least one raised element of the plurality including sloped sides and a peak, aligning a strip comprising conductive material at least partially over the at least one raised element, and at least partially securing the strip to a surface of the at least one raised element and the surface of the substrate.08-26-2010
20100227455EPITAXIAL FILM GROWING METHOD, WAFER SUPPORTING STRUCTURE AND SUSCEPTOR - An annular step portion provided to a periphery of a wafer housing portion is provided to an area with which an area of 1 to 6 mm from a boundary line with a chamfered surface of a wafer rear surface toward a wafer center comes in contact. As a result, it is possible to produce an epitaxial wafer having no scratch in a boundary area between the rear surface and the chamfered surface, and to eliminate particles generated due to a scratch in a device process.09-09-2010
20100159674METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided is a method of fabricating a semiconductor device. The method includes forming a first layer, a second layer, an ion implantation layer between the first and second layers, and an anti-oxidation layer on the second layer, and performing a heat treating process to form an insulating layer between the first and second layers while preventing loss of the second layer using the anti-oxidation layer.06-24-2010
20100240197SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND RELATED FABRICATION METHOD - Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.09-23-2010
20130217211Controlled-Pressure Process for Production of CZTS Thin-Films - In one embodiment, a method includes depositing a CZT(S, Se) precursor layer onto a substrate and then annealing the precursor layer in the presence of a gaseous phase comprising Sn(S, Se), where the partial pressure of each component of the gaseous phase is kept approximately constant over substantially all of the surface of the precursor layer.08-22-2013
20100120234METHOD FOR GROWTH OF GaN SINGLE CRYSTAL, METHOD FOR PREPARATION OF GaN SUBSTRATE, PROCESS FOR PRODUCING GaN-BASED ELEMENT, AND GaN-BASED ELEMENT - A GaN-based thin film (thick film) is grown using a metal buffer layer grown on a substrate. (a) A metal buffer layer (05-13-2010
20100144125Rapid Patterning of Nanostructures - A process for forming nanostructures comprises generating charged nanoparticles with an electrospray system and introduction of the charged nanoparticles to a substrate, so that the particles adhere to the substrate in order to form the desired structure. The charged nanoparticles may be directed to a target position by at least one deflector in the electrospray apparatus, which may also include a column optic system. The adhered nanoparticles may be sintered to form the structure. The electrospray apparatus may be single source, multi-source injection, or multi-source selection. An array of electrospray apparatuses with deflectors may be used concurrently to form the structure.06-10-2010
20100144123METHODS OF FORMING A COMPOUND SEMICONDUCTOR DEVICE INCLUDING A DIFFUSION REGION - Provided is a method of forming a compound semiconductor device. In the method, a dopant element layer is formed on an undoped compound semiconductor layer. An annealing process is performed to diffuse dopants in the dopant element layer into the undoped compound semiconductor layer, thereby forming a dopant diffusion region. A rapid cooling process is performed using liquid nitrogen with respect to the substrate having the dopant diffusion region.06-10-2010
20100144121Germanium FinFETs Having Dielectric Punch-Through Stoppers - A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.06-10-2010
20120034763Method of Manufacturing Nitride Semiconductor Substrate - The present invention provides a method of manufacturing a nitride semiconductor substrate capable of efficiently manufacturing a nitride semiconductor substrate having a nonpolar plane as a major surface in which polycrystalline growth is minimized. A method of manufacturing a GaN substrate, which is a nitride semiconductor substrate, includes steps (S02-09-2012
20100120232METHOD OF FABRICATING THIN FILM DEVICE - Provided is a method of fabricating a thin film device. A sacrifice layer is formed on a first substrate. A thin film laminated body is formed on the sacrifice layer. A separation groove exposing the sacrifice layer is formed to divide the thin film laminated body into at least one thin film device. The sacrifice layer is partially removed using a dry etching process. After the partial removal of the sacrifice layer, a remaining sacrifice layer region maintains the thin film device on the first substrate. A supporting structure is temporarily joined to the thin film device. The thin film device joined to the supporting structure is separated from the first substrate. Then, the remaining sacrifice layer is removed. The thin film device joined to the supporting structure is joined to a second substrate. Finally, the supporting structure is separated from the thin film device.05-13-2010
20120142170METHOD OF FORMING PHOTONIC CRYSTALS - According to an embodiment of the present invention, a method of forming photonic crystals is provided. The method includes: forming a layer arrangement on a support substrate. The layer arrangement includes a first partial layer arrangement and a second partial layer arrangement, wherein the second partial layer arrangement is disposed over the first partial layer arrangement, wherein each partial layer arrangement comprises a first layer and a second layer, wherein the second layer is disposed over the first layer, and wherein the material of the second layer has a different etching characteristic than the material of the first layer. The method further includes removing at least one portion of the second layer and removing the first layer, wherein forming the layer arrangement occurs prior to removing the at least one portion of the second layer and the first layer.06-07-2012
20120142168III-V Compound Crystal and Semiconductor Electronic Circuit Element - Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates, and can be used to manufacture semiconductor devices with good quality and at high yields. The III-V crystals are characterized by the following properties: the carrier concentration, resistivity, and dislocation density of the III-V compound crystal are uniform to within ±30% variation along the surface; the III-V compound crystal is misoriented from the c-plane such that the crystal surface does not include any region where its off-axis angle with the c-plane is 0°; and the full width at half-maximum in XRD at the crystal center of the III-V compound is not greater than 150 arcsec.06-07-2012
20100221896Electrical Device with Improved Electrode Surface - An electronic device having a reduced-roughness electrode surface. The device includes an active material that forms an interface with a treated electrode surface. Treatment of the electrode surface reduces the roughness of the surface to promote adhesion, conformality, and/or electrical contact of the active material to the electrode. The reduced-roughness electrode surface facilitates the formation of a regular, uniform interface with the active material and minimizes the formation of interfacial voids and/or localized contact points that compromise device performance or endurance. Active materials include variable resistance materials and electrical switching materials.09-02-2010
20100221895SURFACE TREATMENT APPARATUS AND SURFACE TREATMENT METHOD - HF-originated radicals generated in a plasma-forming chamber are fed to a treatment chamber via feed holes, while HF gas molecules as the treatment gas are supplied to the treatment chamber from near the radical feed holes to suppress the excitation energy, thereby increasing the selectivity to Si to remove a native oxide film. Even with the dry-treatment, the surface treatment provides good surface flatness equivalent to that obtained by the wet-cleaning which requires high-temperature treatment, and further attains growth of Si single crystal film on the substrate after the surface treatment. The surface of formed Si single crystal film has small quantity of impurities of oxygen, carbon, and the like. After sputtering Hf and the like onto the surface of the grown Si single crystal film, oxidation and nitrification are applied thereto to form a dielectric insulation film such as HfO thereon, thus forming a metal electrode film. All through the above steps, the substrate is not exposed to atmospheric air, thereby suppressing the adsorption of impurities onto the interface, and thus obtaining a C-V curve with small hysteresis. As a result, good device characteristics are obtained in MOS-FET.09-02-2010
20100221894METHOD FOR MANUFACTURING NANOWIRES BY USING A STRESS-INDUCED GROWTH - Provided is a method for manufacturing a nanowire using stress-induced growth. The method includes: providing a substrate with an intermediate layer formed thereon; forming thin film on the intermediate layer, wherein the thin film made of material having more than 2×1009-02-2010
20090162997Thin diamond like coating for semiconductor processing equipment - Accordingly, systems and methods of thin diamond like coatings for semiconductor processing equipment. A semiconductor substrate processing system includes an enclosure for containing a semiconductor processing gas. The enclosure has an interior surface that is at least partially coated with a diamond-like Carbon coating to a desired thickness that is less than about 0.5 μm. The enclosure may be inlet piping for conveying the semiconductor processing gas to a processing chamber for processing the semiconductor substrate, a processing chamber and/or an exhaust flume for conveying used semiconductor processing gas away from a processing chamber06-25-2009
20090111246INHIBITORS FOR SELECTIVE DEPOSITION OF SILICON CONTAINING FILMS - A method for depositing a single crystalline silicon film comprises: providing a substrate disposed within a chamber; introducing to the chamber under chemical vapor deposition conditions a silicon precursor, a chlorine-containing etchant and an inhibitor source for decelerating reactions between the silicon precursor and the chlorine-containing etchant; and selectively depositing a doped crystalline Si-containing film onto the substrate.04-30-2009
20110117729FLUID BED REACTOR - Fluidized bed reactor systems for producing high purity silicon-coated particles are disclosed. A vessel has an outer wall, an insulation layer inwardly of the outer wall, at least one heater positioned inwardly of the insulation layer, a removable concentric liner inwardly of the heater, a central inlet nozzle, a plurality of fluidization nozzles, at least one cooling gas nozzle, and at least one product outlet. The system may include a removable concentric sleeve inwardly of the liner. In particular systems the central inlet nozzle is configured to produce a primary gas vertical plume centrally in the reactor chamber to minimize silicon deposition on reactor surfaces.05-19-2011
20110117728METHOD OF DECONTAMINATION OF PROCESS CHAMBER AFTER IN-SITU CHAMBER CLEAN - A method and apparatus for removing deposition products from internal surfaces of a processing chamber, and for preventing or slowing growth of such deposition products. A halogen containing gas is provided to the chamber to etch away deposition products. A halogen scavenging gas is provided to the chamber to remove any residual halogen. The halogen scavenging gas is generally activated by exposure to electromagnetic energy, either inside the processing chamber by thermal energy, or in a remote chamber by electric field, UV, or microwave. A deposition precursor may be added to the halogen scavenging gas to form a deposition resistant film on the internal surfaces of the chamber. Additionally, or alternately, a deposition resistant film may be formed by sputtering a deposition resistant metal onto internal components of the processing chamber in a PVD process.05-19-2011
20130137246METHOD OF PRODUCING GROUP III NITRIDE SEMICONDUCTOR GROWTH SUBSTRATE - An object of the present invention is to provide a method for producing a Group III nitride semiconductor epitaxial substrate, a Group III nitride semiconductor element, and a Group III nitride semiconductor free-standing substrate, which have good crystallinity, with not only AlGaN, GaN, and GaInN the growth temperature of which is 1050° C. or less, but also with Al05-30-2013
20100311228METHOD FOR FORMING TRANSPARENT CONDUCTIVE OXIDE - Embodiments disclosed herein generally relate to a process of depositing a transparent conductive oxide layer over a substrate. The transparent oxide layer is sometimes deposited onto a substrate for later use in a solar cell device. The transparent conductive oxide layer may be deposited by a “cold” sputtering process. In other words, during the sputtering process, a plasma is ignited in the processing chamber which naturally heats the substrate. No additional heat is provided to the substrate during deposition such as from the susceptor. After the transparent conductive oxide layer is deposited, the substrate may be annealed and etched, in either order, to texture the transparent conductive oxide layer. In order to tailor the shape of the texturing, different wet etch chemistries may be utilized. The different etch chemistries may be used to shape the surface of the transparent conductive oxide and the etch rate.12-09-2010
20100317174Manufacturing method of semiconductor device and substrate processing apparatus - A manufacturing method of a semiconductor device is provided, comprising: loading a substrate into a processing chamber; forming a first film on the substrate by supplying silicon atom-containing gas, boron atom-containing gas, and germanium atom-containing gas into the processing chamber; forming a second film on the first film by supplying the silicon atom-containing gas and the boron atom-containing gas into the processing chamber; and unloading the substrate from the processing chamber.12-16-2010
20130164915METHOD FOR FABRICATING POWER SEMICONDUCTOR DEVICE WITH SUPER JUNCTION STRUCTURE - A method for fabricating a power semiconductor device is provided. A substrate with a first conductivity type is prepared. A semiconductor layer with a second conductivity type is formed on the substrate. A hard mask pattern having at least an opening is formed on the semiconductor layer. A first trench etching is performed to form a first recess in the semiconductor layer via the opening. A first ion implantation is performed to vertically implant dopants into the bottom of the first recess via the opening, thereby forming a first doping region. A second trench etching is performed to etch through the first doping region, thereby forming a second recess.06-27-2013
20130143391REACTED LAYER FOR IMPROVING THICKNESS UNIFORMITY OF STRAINED STRUCTURES - Methods are disclosed of forming and removing a reacted layer on a surface of a recess to provide mechanisms for improving thickness uniformity of a semiconductor material formed in the recess. The improved thickness uniformity in turn improves the uniformity of device performance.06-06-2013
20130143392IN-SITU SIN GROWTH TO ENABLE SCHOTTKY CONTACT FOR GAN DEVICES - A method of fabricating a diode in gallium nitride (GaN) materials includes providing a n-type GaN substrate having a first surface and a second surface and forming a n-type GaN drift layer coupled to the first surface of the n-type GaN substrate. The method also includes forming an in-situ Si06-06-2013
20110111577SEMICONDUCTOR CARBON NANOTUBES AND METHOD OF SELECTIVELY GROWING SEMICONDUCTOR CARBON NANOTUBES USING LIGHT IRRADIATION - A method of selectively growing a plurality of semiconductor carbon nanotubes using light irradiation. The method includes disposing a plurality of nanodots, which include a catalyst material, on a substrate; growing a plurality of carbon nanotubes from the plurality of nanodots, and irradiating light onto the nanodot to selectively grow the plurality of semiconductor carbon nanotubes.05-12-2011
20100323500System and Process for Producing Nanowire Composites and Electronic Substrates Therefrom - The present invention relates to a system and process for producing a nanowire-material composite. A substrate having nanowires attached to a portion of at least one surface is provided. A material is deposited over the portion to form the nanowire-material composite. The process further optionally includes separating the nanowire-material composite from the substrate to form a freestanding nanowire-material composite. The freestanding nanowire material composite is optionally further processed into a electronic substrate. A variety of electronic substrates can be produced using the methods described herein. For example, a multi-color light-emitting diode can be produced from multiple, stacked layers of nanowire-material composites, each composite layer emitting light at a different wavelength.12-23-2010
20090068820Microspheres including nanoparticles - A microparticle can include a central region and a peripheral region. The peripheral region can include a nanoparticle, such as a metal nanoparticle, a metal oxide nanoparticle, or a semiconductor nanocrystal. The microparticle can be a member of a monodisperse population of particles.03-12-2009
20100184273GROUP III NITRIDE COMPOUND SEMICONDUCTOR DEVICE - Disclosed is a group III nitride compound semiconductor device having a substrate, buffer layers on the substrate, and a group III nitride compound semiconductor layer on the top layer of the buffer layers. The buffer layers comprises a first buffer layer formed on the substrate and a second buffer layer formed on the first buffer layer. The first buffer layer is made of transition metal nitride, and the second buffer layer is made of nitride of gallium and a transition metal.07-22-2010
20110027974INDIUM SURFACTANT ASSISTED HVPE OF HIGH QUALITY GALLIUM NITRIDE AND GALLIUM NITRIDE ALLOY FILMS - One embodiment of depositing a gallium nitride (GaN) film on a substrate comprises providing a source of indium (In) and gallium (Ga) and depositing a monolayer of indium (In) on the surface of the gallium nitride (GaN) film. The monolayer of indium (In) acts as a surfactant to modify the surface energy and facilitate the epitaxial growth of the film by suppressing three dimensional growth and enhancing or facilitating two dimensional growth. The deposition temperature is kept sufficiently high to enable the indium (In) to undergo absorption and desorption on the gallium nitride (GaN) film without being incorporated into the solid phase gallium nitride (GaN) film. The gallium (Ga) and indium (In) can be provided by a single source or separate sources.02-03-2011
20120244686METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - An exemplary method for fabricating a semiconductor device includes the steps (a) growing a p-type gallium nitride-based compound semiconductor layer in a heated atmosphere; (b) cooling the p-type gallium nitride-based compound semiconductor layer; (c) forming three or more well layers before the step (a); and (d) forming an n-type semiconductor layer on a substrate before the step (c), wherein the step (c) includes growing each of the well layers to a thickness of 5 nm or more with the supply of the hydrogen gas to the reaction chamber cut off, and wherein the step (a) includes supplying hydrogen gas to the reaction chamber, and wherein the step (b) includes cooling the p-type gallium nitride-based compound semiconductor layer with the supply of the hydrogen gas to the reaction chamber cut off.09-27-2012
20120244685Manufacturing Apparatus and Method for Semiconductor Device - A semiconductor manufacturing apparatus includes: a plurality of reaction chambers into which wafers are introduced and deposition process is performed; a material gas supply mechanism that includes a plurality of material gas supply lines that respectively supply a material gas to the plurality of reaction chambers and a flow rate control mechanism that controls a flow rate of the marital gas in the material gas supply lines; a carrier gas supply mechanism that includes a plurality of carrier gas supply lines that respectively supplies a carrier gas into the plurality of reaction chambers; and a material gas switching mechanism that intermittently opens and closes the plurality of material gas supply lines respectively so that at least one of the plurality of material gas supply lines comes to be in an opened state at a same time, and sequentially switches the reaction chamber to which the material gas is supplied.09-27-2012
20110034008METHOD FOR FORMING A TEXTURED SURFACE ON A SEMICONDUCTOR SUBSTRATE USING A NANOFABRIC LAYER - A method of forming a textured surface on a substrate or material layer within a semiconductor fabrication process. In one aspect of the disclosure, a sacrificial nanofabric layer is deposited over a material layer and an etch process is used to transfer the surface texture of the nanofabric layer downward to the material layer. In another aspect of the disclosure, a thin material layer is deposited over a nanofabric layer such that the surface texture of the nanofabric layer is transferred upward to the material layer. Within both aspects, varying the porosity of nanofabric layer provides a measure of control over the degree of texturization of the material layer.02-10-2011
20110111578METHOD OF FORMING p-TYPE GALLIUM NITRIDE BASED SEMICONDUCTOR, METHOD OF FORMING NITRIDE SEMICONDUCTOR DEVICE, AND METHOD OF FORMING EPITAXIAL WAFER - A method of forming a p-type gallium nitride based semiconductor without activation annealing is provided, and the method can provide a gallium nitride based semiconductor doped with a p-type dopant. A GaN semiconductor region 05-12-2011
20110124182SYSTEM FOR THE DELIVERY OF GERMANIUM-BASED PRECURSOR - A supply of a germanium precursor such as germanium n-butylamidinate is provided in close proximity to a microelectronic device substrate to be contacted therewith for deposition of germanium-containing material on the substrate. Specific arrangements are described, including tray and reservoir structures from which solid, liquid, suspended or dissolved germanium precursor can be volatilized for transport to the substrate surface together with other precursors, carrier gases, co-reactants or the like. In such manner, the germanium precursor can be activated independently of the activation of other precursors, within the deposition chamber, to achieve highly efficient formation of germanium-containing material on the substrate, e.g., a GST film of a phase change memory device.05-26-2011
20110244665MANUFACTURING METHOD OF GaN BASED SEMICONDUCTOR EPITAXIAL SUBSTRATE - A low-temperature protective layer having AlN is grown on a rare earth perovskite substrate and a first GaN based semiconductor layer having Al10-06-2011
20110244663FORMING A COMPOUND-NITRIDE STRUCTURE THAT INCLUDES A NUCLEATION LAYER - The present invention generally provides apparatus and methods for forming LED structures. In one embodiment, a method for fabricating a compound nitride-based semiconductor structure is provided. The method comprises forming a Group III-nitride buffer layer over one or more substrates in a first processing chamber, transferring the one or more substrates having the Group III-nitride buffer layer deposited thereon into a second processing chamber without exposing the one or more substrates to an ambient atmospheric environment, and forming a bulk Group III-V layers over the Group III-nitride buffer layer in the second processing chamber. In one example, the first processing chamber may be a MOCVD, PVD based chamber, CVD based chamber, ALD based chamber, sputtering chamber, or any other vapor deposition chamber. The second processing chamber may be a MOCVD or HVPE chamber.10-06-2011
20110244661Large Scale High Quality Graphene Nanoribbons From Unzipped Carbon Nanotubes - A new method is disclosed for large-scale production of pristine few-layer graphene nanoribbons (GNRs) through unzipping of mildly gas-phase oxidized, and, optionally, metal-assisted oxidized, multiwalled and few-walled carbon nanotubes. The method further comprises sonication in an organic solvent. High-resolution transmission electron microscopy revealed nearly atomically smooth edges for narrow GNRs (2-30 nm). The GNRs exhibit ultra-high quality with low ratios of disorder (D) to graphitic (G) Raman bands (I10-06-2011
20120034762Method for Selective Deposition of a Semiconductor Material - A method is disclosed comprising providing a substrate comprising an insulating material and a second semiconductor material and pre-treating the substrate with a plasma produced from a gas selected from the group consisting of a carbon-containing gas, a halogen-containing gas, and a carbon-and-halogen containing gas. The method further comprises depositing a first semiconductor material on the pre-treated substrate by chemical vapor deposition, where the first semiconductor material is selectively deposited on the second semiconductor material. The method may be used to manufacture a semiconducting device, such as a microelectromechanical system device, or to manufacture a semiconducting device feature, such as an interconnect.02-09-2012
20090029529METHOD FOR CLEANING SEMICONDUCTOR DEVICE - Disclosed is a method for cleaning a semiconductor device to remove native oxides or by-products created in the process of forming silicon germanium layers. The use of the method enables removal of native oxides or by-products created in the process of forming silicon germanium layers using hydrogen bromide and prevents reoxidation which may occur in subsequent processes after forming silicon germanium layers.01-29-2009
20110212602SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a trench MOS barrier Schottky diode having an integrated PN diode and a method is for manufacturing same.09-01-2011
20110212600METHOD FOR FORMING CHANNEL LAYER WITH HIGH GE CONTENT ON SUBSTRATE - A method for forming a channel layer with high Ge content on a substrate is provided. The method may comprise steps of: preparing the substrate (09-01-2011
20090098715Process for manufacturing silicon wafers for solar cell - A process for manufacturing silicon wafers for solar cell is disclosed wherein one first breaks the refined metallurgical silicon, then remove visible impurities, then performs chemical cleaning and then places the silicon into a crystal growing furnace. Gallium or gallium phosphide is added to the silicon, where the concentration of gallium atoms should be in the range from 5 ppma to 14 ppma. Crystal growth is initiated, followed by subdivision and inspection after the crystal rods or crystal bars have grown, yielding the desired silicon wafers. With this solution, the refined metallurgical silicon can be used for manufacturing of solar cells, so as to reduce the cost of materials, and it is conducive to the universal application of silicon solar cells.04-16-2009
20110086497METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A method of producing a device includes embedding trenches with an epitaxial layer having high crystallinity while a mask oxide film remains unremoved. An n-type semiconductor is formed on the surface of a silicon substrate, and a mask oxide film and a mask nitride film are formed on the surface of the n-type semiconductor. The mask laminated film is opened by photolithography and etching, and trenches are formed in the silicon substrate. The width of the remaining mask laminated film is narrowed and portions of the n-type semiconductor close to the opening ends of the trenches are exposed. The trenches are embedded with a p-type semiconductor and the surface of the mask laminated film is prevented from being covered with the p-type semiconductor. The p-type semiconductor is grown from the second exposed portions of the n-type semiconductor. V-shaped grooves are prevented from forming on the surface of the p-type semiconductor.04-14-2011
20110244666Methods Of Manufacturing Stair-Type Structures And Methods Of Manufacturing Nonvolatile Memory Devices Using The Same - Methods of manufacturing stair-type structures and methods of manufacturing nonvolatile memory devices using the same. Methods of manufacturing stair-type structures may include forming a plurality of thin layers stacked in plate shapes, forming a mask on an utmost thin layer, patterning the utmost layer using the mask as an etch mask, escalating a width of the mask and etching each of the thin layers at a different width of the mask to form a stair-type structure of the thin layers. Control gates may be formed into the stair-type structures using the methods of manufacturing stair-type structures.10-06-2011
20110244664METHOD OF MANUFACTURING SUPERJUNCTION STRUCTURE - The present invention discloses a method of manufacturing superjunction structure, which comprises: step 1, grow an N type epitaxial layer on a substrate having a (100) or (110) oriented surface; step 2, etch the N type epitaxial layer to form trenches therein; step 3, fill the trenches by P type epitaxial growth in the trenches by using a mixture of silicon source gas, halide gas, hydrogen gas, and doping gas. By using the manufacturing method according to the present invention, no void or only small voids are formed in the trenches after trench filling.10-06-2011
20110244662METHOD OF MANUFACTURING GRAPHENE BY USING GERMANIUM LAYER - A method of manufacturing graphene includes forming a germanium layer on a surface of a substrate, and forming the graphene directly on the germanium layer by supplying carbon-containing gas into a chamber in which the substrate is disposed.10-06-2011
20130157443PRODUCTION OF ELECTRONIC SWITCHING DEVICES - A technique of producing one or more electronic switching devices, each switching device comprising a semiconductor channel between two electrodes, and a dielectric element separating said semiconductor channel from a switching electrode, the method comprising: depositing onto a substrate a layer of material for at least partly forming said semiconductor channel or said dielectric element of said one or more switching devices by transferring said material onto said substrate from a rotating first roller.06-20-2013
20110097877METHOD FOR MANUFACTURING MICROCRYSTALLINE SEMICONDUCTOR AND THIN FILM TRANSISTOR - A technique for manufacturing a microcrystalline semiconductor layer with high mass productivity is provided. In a reaction chamber of a plasma CVD apparatus, an upper electrode and a lower electrode are provided in almost parallel to each other. A hollow portion is formed in the upper electrode, and the upper electrode includes a shower plate having a plurality of holes formed on a surface of the upper electrode which faces the lower electrode. A substrate is provided over the lower electrode. A gas containing a deposition gas and hydrogen is supplied to the reaction chamber from the shower plate through the hollow portion of the upper electrode, and a rare gas is supplied to the reaction chamber from a portion different from the upper electrode. Accordingly, high-frequency power is supplied to the upper electrode to generate plasma, so that a microcrystalline semiconductor layer is formed over the substrate.04-28-2011
20110177676METHOD OF TRANSFERRING A LAYER ONTO A LIQUID MATERIAL - A method for transferring a layer onto a support includes transferring the layer, assembled on an initial substrate, onto a liquid layer that has been previously deposited on the support. The layer is subsequently released from the initial substrate by chemical etching, and the liquid layer is evacuated to allow molecular adhesion of the layer to the support.07-21-2011
20090029531HYBRID ORIENTATION SUBSTRATE AND METHOD FOR FABRICATION THEREOF - A method for fabricating a hybrid orientation substrate provides for: (1) a horizontal epitaxial augmentation of a masked surface semiconductor layer that leaves exposed a portion of a base semiconductor substrate; and (2) a vertical epitaxial augmentation of the exposed portion of the base semiconductor substrate. The resulting surface semiconductor layer and epitaxial surface semiconductor layer adjoin with an interface that is not perpendicular to the base semiconductor substrate. The method also includes implanting through the surface semiconductor layer and the epitaxial surface semiconductor layer a dielectric forming ion to provide a buried dielectric layer that separates the surface semiconductor layer and the epitaxial surface semiconductor layer from the base semiconductor substrate.01-29-2009
20110097879METHOD OF PREPARING LUMINESCENT NANOCRYSTALS, THE RESULTING NANOCRYSTALS AND USES THEREOF - The present invention comprises a method for preparing a nanocrystal having (i) a core comprising a semiconductor comprising A representing a metal or metalloid in the +III oxidation state and B representing an element in the −III oxidation state, coated with (ii) a shell in which the outer portion comprises a semiconductor having the formula ZnS04-28-2011
20110097878CHAMBER FOR PECVD - A method and apparatus for plasma processing of substrates in a substantially vertical orientation is described. Substrates are positioned on a carrier comprising at least two frames oriented substantially vertically. The carrier is disposed in a plasma chamber with an antenna structure positioned between the substrates. Multiple plasma chambers may be coupled to a transfer chamber with a turntable for directing the carrier to a target chamber. A loader moves substrates between the carrier and a load-lock chamber in which substrates are staged in a substantially horizontal position.04-28-2011
20110097880FILM DEPOSITION METHOD - Provided is a film deposition method capable of improving the crystal characteristic near an interface according to the lattice constant of a material that will constitute a thin film to be deposited. Specifically, a substrate is curved relative to the direction along one main surface on which the thin film is to be deposited, according to the lattice constant the material that will constitute the thin film to be deposited and the lattice constant of a material constituting the one main surface. The thin film is deposited on the one main surface of the substrate with the substrate curved.04-28-2011
20110250737TRANSISTOR WITH A-FACE CONDUCTIVE CHANNEL AND TRENCH PROTECTING WELL REGION - A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.10-13-2011
20110250736SCHOTTKY BARRIER DIODE AND METHOD FOR MAKING THE SAME - A schottky diode includes a SiC substrate which has a first surface and a second surface facing away from the first surface, a semiconductor layer which is formed on the first surface of the SiC substrate, a schottky electrode which is in contact with the semiconductor layer, and an ohmic electrode which is in contact with the second surface of the SiC substrate. The first surface of the SiC substrate is a (000-1) C surface, upon which the semiconductor layer is formed.10-13-2011
20110097876CHEMICAL VAPOR DEPOSITION REACTOR HAVING MULTIPLE INLETS - A chemical vapor deposition reactor has a wafer carrier which cooperates with a chamber of the reactor to facilitate laminar flow of reaction gas within the chamber and a plurality of injectors configured in flow controllable zones so as to mitigate depletion.04-28-2011
20110086496METAL ORGANIC CHEMICAL VAPOR DEPOSITION APPARATUS AND METHOD - A metal organic chemical vapor deposition apparatus includes reaction chambers in which nitride layers is deposited on a substrate using a group III-V material, a buffer chamber connected to the reaction chambers and in which a transfer robot is disposed to transfer the substrate into the reaction chambers, a gas supply device configured to selectively supply one or more of hydrogen, nitrogen, and ammonia gases into the buffer chamber so that when the buffer chamber communicates with one of the reaction chambers, the buffer chamber has the same atmosphere as an atmosphere of the reaction chamber, and a heater disposed in the buffer chamber. Nitride layers are deposited on a substrate in the reaction chambers, and the temperature and gas atmosphere of the buffer chamber are adjusted such that when the substrate is transferred, epitaxial layers formed on the substrate can be stably maintained.04-14-2011
20110076839MAKING FILMS COMPOSED OF SEMICONDUCTOR NANOCRYSTALS - A method of making a film of large II-VI nanocrystals, including: providing a mixture of column II, column VI chemical precursors, and coordinating solvents selected from amines, phosphines, phosphine oxides, esters, ethers, or combinations thereof by: injecting under heat a higher molar quantity of column II chemical precursor than column VI chemical precursor; and ii) increasing the ratio of column VI to column II chemical precursors during the course of the reaction while still heating the mixture until the molar ratio of column VI chemical precursor to column II chemical precursor is in a range of 1 to 10; heating the mixture to grow large nanocrystals functionalized with coordinating ligands; washing the grown nanocrystals to remove the unreacted precursors and excess coordinating solvents; and d) depositing the large II-VI nanocrystals on a substrate in order to form the film.03-31-2011
20110151648Apparatus and method for transformation of substrate - A method is disclosed for forming a layer of a wide bandgap material in a non-wide bandgap material. The method comprises providing a substrate of a non-wide bandgap material and converting a layer of the non-wide bandgap material into a layer of a wide bandgap material. An improved component such as wide bandgap semiconductor device may be formed within the wide bandgap material through a further conversion process.06-23-2011
20100297834METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STOP AT A PLANAR SURFACE - A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.11-25-2010
20130157445POLYCRYSTALLINE ALUMINUM NITRIDE BASE MATERIAL FOR CRYSTAL GROWTH OF GaN-BASE SEMICONDUCTOR AND METHOD FOR MANUFACTURING GaN-BASE SEMICONDUCTOR USING THE SAME - There is provided a polycrystalline aluminum nitride base material having a linear expansion coefficient similar to GaN. The polycrystalline aluminum nitride base material as a substrate material for crystal growth of GaN-base semiconductors has a mean linear expansion coefficient of 4.9×1006-20-2013
20110212604METHOD OF FABRICATING TRANSISTOR - A method of fabricating a transistor is provided. The transistor includes a SiGe epitaxial layer formed in a recess region of a substrate at both side of a gate electrode and a SiGe capping layer formed on the SiGe epitaxial layer. The transistor further includes a SiGe seed layer formed under the SiGe epitaxial layer and a silicon capping layer formed on the SiGe capping layer.09-01-2011
20100304553METHOD FOR MANUFACTURING QUANTUM DOT - A silicon oxide film (12-02-2010
20090023274Hybrid Chemical Vapor Deposition Process Combining Hot-Wire CVD and Plasma-Enhanced CVD - Hybrid chemical vapor deposition systems for depositing a semiconductor-containing thin film over a substrate comprise a reaction space, a substrate support member configured to permit movement of a substrate in a longitudinal direction and a plasma-generating apparatus disposed in the reaction space and configured to form plasma-excited species of a vapor phase chemical. The systems further comprise a hot wire unit disposed in the reaction space and configured to heat and decompose a vapor phase chemical. The hot wire unit can be a filament. The systems can further comprise an additional reaction space proximate the reaction space. The additional reaction space can comprise a plasma-generating apparatus configured to form plasma-excited species of a vapor phase chemical and a hot wire unit configured to heat and decompose a vapor phase chemical.01-22-2009
20090023275METHOD FOR FORMING SILICON WELLS OF DIFFERENT CRYSTALLOGRAPHIC ORIENTATIONS - A method for manufacturing silicon wells of various crystallographic orientations in a silicon support, including the steps of: forming a silicon layer having a first orientation on a silicon substrate having a second orientation; forming insulating walls, defining wells extend at least down to the border between the silicon substrate and the silicon layer; performing, in first wells, a chemical vapor etch (CVE) of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C.; and performing, in the first wells, a vapor-phase epitaxy on the silicon substrate in the presence of a precursor of silicon and hydrochloric acid, at a temperature ranging between 700° C. and 900° C. and up to the upper surface of the silicon layer.01-22-2009
20110151649METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a first semiconductor layer on a front side of the semiconductor substrate. Additional semiconductor layers may be formed on a font side of the first semiconductor layer. The substrate is subsequently removed. In some embodiments, one or more additional semiconductor layers may be formed on the back side of the first semiconductor layer after the semiconductor substrate has been removed. Additionally, in some embodiments, a portion of the first semiconductor layer is removed along with the semiconductor substrate. In such embodiments, the first semiconductor layer is subsequently etched to a known thickness. Source regions and device electrodes may be then be formed.06-23-2011
20100003810METHOD OF FORMING P-TYPE COMPOUND SEMICONDUCTOR LAYER - A method of forming a p-type compound semiconductor layer includes increasing a temperature of a substrate loaded into a reaction chamber to a first temperature. A source gas of a Group III element, a source gas of a p-type impurity, and a source gas of nitrogen containing hydrogen are supplied into the reaction chamber to grow the p-type compound semiconductor layer. Then, the supply of the source gas of the Group III element and the source gas of the p-type impurity is stopped and the temperature of the substrate is lowered to a second temperature. The supply of the source gas of nitrogen containing hydrogen is stopped and drawn out at the second temperature, and the temperature of the substrate is lowered to room temperature using a cooling gas. Accordingly, hydrogen is prevented from bonding to the p-type impurity in the p-type compound semiconductor layer.01-07-2010
20110151646MICROWAVE ANNEALING METHOD FOR DEVICE PROCESSING WITH PLASTIC SUBSTRATE - The present invention provides a microwave annealing method for a plastic substrate. The method comprises pulsed microwave annealing to an organic photo-voltaic device to avoid warpage and degradation of the plastic substrate. Utilizing pulsed microwave annealing method can improve the wettability of the organic layer on the plastic substrate verified by contact angle measurement, and achieving the organic solar cell fabricated with higher power conversion efficiency.06-23-2011
20090275188Slurry for polishing phase change material and method for patterning polishing phase change material using the same - Disclosed is a slurry for polishing a phase change material. The slurry includes an abrasive, an alkaline polishing promoter and deionized water. Due to the use of the abrasive and the alkaline polishing promoter, the pH of the slurry is adjusted, the polishing rate of the phase change material is improved, and the polishing selectivity of the phase change material to an underlying insulating layer is increased. Further disclosed is a method for patterning a phase change material using the slurry.11-05-2009
20090246942APPARATUS FOR DEPOSITING SILICON-BASED THIN FILM AND METHOD FOR DEPOSITING SILICON-BASED THIN FILM - A silicon-based thin film depositing apparatus, including a plurality of transparent electrodes disposed to face corresponding counter electrodes with a space therebetween. Subsequently, while injecting a raw material gas from raw material gas injection orifices toward the supporting electrodes and also injecting a barrier gas from barrier gas injection orifices in the same direction as the direction in which the raw material gas is injected, the gases are discharged from a gas outlet, and thereby, the pressure in a chamber is controlled to a pressure of more than 1 kPa. Then, a DC pulse voltage is applied to each counter electrode to deposit a silicon-based thin film. A DC pulse voltage is applied to perform discharge. Therefore, even in a state where the distance between the electrodes is increased, plasma can be generated efficiently, and the in-plane distribution of film thickness can be improved.10-01-2009
20110151647Semiconductor substrate, semiconductor device, and manufacturing methods thereof - Exemplary embodiments of the present invention provide a method of fabricating a semiconductor substrate, the method including forming a first semiconductor layer on a substrate, forming a metallic material layer on the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer and the metallic material layer, etching the substrate using a solution to remove the metallic material layer and a portion of the first semiconductor layer, and forming a cavity in the first semiconductor layer under where the metallic material layer was removed.06-23-2011
20120202338EPITAXY OF HIGH TENSILE SILICON ALLOY FOR TENSILE STRAIN APPLICATIONS - Embodiments of the present invention generally relate to methods for forming silicon epitaxial layers on semiconductor devices. The methods include forming a silicon epitaxial layer on a substrate at increased pressure and reduced temperature. The silicon epitaxial layer has a phosphorus concentration of about 1×1008-09-2012
20110177680ETCHANT COMPOSITION FOR METAL WIRING AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL USING THE SAME - The present invention relates to an etchant for wet etching a wiring that includes copper, where the etchant includes approximately 5 to approximately 25 wt % of a peroxide, approximately 0.5 to approximately 5 wt % of an oxidant, approximately 0.1 to approximately 1 wt % of a fluoride-based compound and approximately 1 to approximately 10 wt % of a glycol. The etchant can provide an etching rate that is suitable to many processes, and produces an appropriate etching amount as well as an appropriate taper angle.07-21-2011
20110177678METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - A method for manufacturing a nitride semiconductor device includes forming an n-type nitride-based semiconductor layer on a substrate; forming an active layer of a nitride-based semiconductors including In on the n-type nitride-based semiconductor layer using ammonia and a hydrazine derivative as group-V element source materials and a carrier gas including hydrogen; and forming a p-type nitride-based semiconductor layer on the active layer using ammonia and a hydrazine derivative as group-V element source materials.07-21-2011
20110212603METHODS FOR IMPROVING THE QUALITY OF STRUCTURES COMPRISING SEMICONDUCTOR MATERIALS - Methods which can be applied during the epitaxial growth of semiconductor structures and layers of III-nitride materials so that the qualities of successive layers are successively improved. An intermediate epitaxial layer is grown on an initial surface so that growth pits form at surface dislocations present in the initial surface. A following layer is then grown on the intermediate layer according to the known phenomena of epitaxial lateral overgrowth so it extends laterally and encloses at least the agglomerations of intersecting growth pits. Preferably, prior to growing the following layer, a discontinuous film of a dielectric material is deposited so that the dielectric material deposits discontinuously so as to reduce the number of dislocations in the laterally growing material. The methods of the invention can be performed multiple times to the same structure. Also, semiconductor structures fabricated by these methods.09-01-2011
20120276718METHOD OF FABRICATING GRAPHENE-BASED FIELD EFFECT TRANSISTOR - The present invention provides a method of fabricating a graphene-based field effect transistor, which includes steps of: providing a semiconductor substrate on which a non-functionized graphene layer is formed; forming a metal oxide film as a nucleation layer through a reaction between a metal source and water which acts as oxidizer and is physically absorbed to a surface of the graphene layer; and generating a HfO11-01-2012
20110256695BEAM HOMOGENIZER, LASER IRRADIATION APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The energy distribution of the beam spot on the irradiated surface changes due to the change in the oscillation condition of the laser or before and after the maintenance. The present invention provides an optical system for forming a rectangular beam spot on an irradiated surface including a beam homogenizer for homogenizing the energy distribution of the rectangular beam spot on the irradiated surface in a direction of its long or short side. The beam homogenizer includes an optical element having a pair of reflection planes provided oppositely for reflecting the laser beam in the direction where the energy distribution is homogenized and having a curved shape in its entrance surface. The entrance surface of the optical element means a surface of the optical element where the laser beam is incident first.10-20-2011
20080293222METHOD FOR FORMING SILICON-GERMANIUM EPITAXIAL LAYER - A method for forming a SiGe epitaxial layer is described. A first SEG process is performed under a first condition, consuming about 1% to 20% of the total process time for forming the SiGe epitaxial layer. Then, a second SEG process is performed under a second condition, consuming about 99% to 80% of the total process time. The first condition and the second condition include different temperatures or pressures. The first and the second SEG processes each uses a reactant gas that includes at least a Si-containing gas and a Ge-containing gas.11-27-2008
20110053352Method of forming a passivated densified nanoparticle thin film on a substrate - A method for forming a passivated densified nanoparticle thin film on a substrate in a chamber is disclosed. The method includes depositing a nanoparticle ink on a first region on the substrate, the nanoparticle ink including a set of Group IV semiconductor particles and a solvent. The method also includes heating the nanoparticle ink to a first temperature between about 30° C. and about 400° C., and for a first time period between about 1 minute and about 60 minutes, wherein the solvent is substantially removed, and a porous compact is formed. The method further includes flowing an oxidizer gas into the chamber; and heating the porous compact to a second temperature between about 600° C. and about 1000° C., and for a second time period of between about 5 seconds and about 1 hour; wherein the passivated densified nanoparticle thin film is formed.03-03-2011
20110027975SUBSTRATE FOR GROWING A III-V LIGHT EMITTING DEVICE - A substrate including a host and a seed layer bonded to the host is provided, then a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region is grown on the seed layer. In some embodiments, a bonding layer bonds the host to the seed layer. The seed layer may be thinner than a critical thickness for relaxation of strain in the semiconductor structure, such that strain in the semiconductor structure is relieved by dislocations formed in the seed layer, or by gliding between the seed layer and the bonding layer an interface between the two layers. In some embodiments, the host may be separated from the semiconductor structure and seed layer by etching away the bonding layer.02-03-2011
20100285656FORMATION OF METAL-CONTAINING NANO-PARTICLES FOR USE AS CATALYSTS FOR CARBON NANOTUBE SYNTHESIS - The present invention relates to a method for forming metal-silicide catalyst nanoparticles with controllable diameter. The method according to embodiments of the invention leads to the formation of ‘active’ metal-suicide catalyst nanoparticles, with which is meant that they are suitable to be used as a catalyst in carbon nanotube growth. The nano-particles are formed on the surface of a substrate or in case the substrate is a porous substrate within the surface of the inner pores of a substrate. The metal-silicide nanoparticles can be Co-silicide, Ni-silicide or Fe-silicide particles. The present invention relates also to a method to form carbon nanotubes (CNT) on metal-silicide nanoparticles, the metal-silicide containing particles hereby acting as catalyst during the growth process, e.g. during the chemical vapour deposition (CVD) process. Starting from very defined metal-containing nanoparticles as catalysts, the diameter of grown CNT can be well controlled and a homogeneous set of CNT will be obtained.11-11-2010
20110256696SEMICONDUCTOR DEVICE FOR PREVENTING THE LEANING OF STORAGE NODES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device for preventing the leaning of storage nodes and a method of manufacturing the same is described. The semiconductor device includes support patterns that are formed to support a plurality of cylinder type storage nodes. The support patterns are formed of a BN layer and have a hexagonal structure. The BN layer forming the support patterns has compressive stress as opposed to tensile stress and can therefore withstand cracking in the support patterns.10-20-2011
20110256693Method for Synthesis of High Quality Large Area Bulk Gallium Based Crystals - A large area nitride crystal, comprising gallium and nitrogen, with a non-polar or semi-polar large-area face, is disclosed, along with a method of manufacture. The crystal is useful as a substrate for a light emitting diode, a laser diode, a transistor, a photodetector, a solar cell, or for photoelectrochemical water splitting for hydrogen generation.10-20-2011
20110263100ANTIMONY AND GERMANIUM COMPLEXES USEFUL FOR CVD/ALD OF METAL THIN FILMS - Antimony, germanium and tellurium precursors useful for CVD/ALD of corresponding metal-containing thin films are described, along with compositions including such precursors, methods of making such precursors, and films and microelectronic device products manufactured using such precursors, as well as corresponding manufacturing methods. The precursors of the invention are useful for forming germanium-antimony-tellurium (GST) films and microelectronic device products, such as phase change memory devices, including such films.10-27-2011
20110263101CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT - Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.10-27-2011
20110263103METHOD AND APPARATUS FOR CLEANING A SUBSTRATE SURFACE - Embodiments described herein provide methods for processing a substrate. One embodiment comprises positioning a substrate in a processing region of a processing chamber, exposing a surface of the substrate disposed in the processing chamber to an oxygen containing gas to form a first oxygen containing layer on the surface, removing at least a portion of the first oxygen containing layer to expose at least a portion of the surface of the substrate, and exposing the surface of the substrate to an oxygen containing gas to form a second oxygen containing layer on the surface.10-27-2011
20110086495METHODS FOR PROTECTING FILM LAYERS WHILE REMOVING HARDMASKS DURING FABRICATION OF SEMICONDUCTOR DEVICES - Methods for fabricating semiconductor devices are provided. The methods include providing a semiconductor substrate having pFET and nFET regions, each having active areas and shallow trench isolation. A hardmask layer is formed overlying the semiconductor substrate. A photoresist layer is provided over the hardmask layer. The phoresist layer is patterned. An exposed portion of the hardmask layer is removed from one of the pFET region and nFET region with the patterned photoresist acting as an etch mask to define a masked region and an unmasked region. An epitaxial silicon layer is formed on the active area in the unmasked region. A protective oxide layer is formed overlying the epitaxial silicon layer. The hardmask layer is removed from the masked region with the protective oxide layer protecting the epitaxial silicon layer during such removal step. The protective oxide layer is removed from the epitaxial silicon layer.04-14-2011
20100323499METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is disclosed in which, after semiconductor function regions and patterns of interlayer insulating films including required contact holes are formed on one main surface side of a semiconductor substrate, an aluminum film or an aluminum alloy film which is thick is formed all over the main surface side of the semiconductor substrate and brought into conductive contact with the surface of the semiconductor substrate including bottom surfaces of the contact holes so as to form a required electrode film. Formation of the aluminum film or the aluminum alloy film is divided into a plurality of steps so that the thickness of the aluminum film or the aluminum alloy film is formed gradually, and between every two of the plurality of steps of forming the aluminum film or the aluminum alloy film, there is provided a step of performing isotropic etching to flatten irregularities in a surface of the aluminum film or the aluminum alloy film formed in the previous step. The method for manufacturing a semiconductor device prevents the formation of voids in the surface of an Al electrode film on the surface side of a semiconductor substrate.12-23-2010
20090197398III Nitride Single Crystal and Method of Manufacturing Semiconductor Device Incorporating the III Nitride Single Crystal - A III nitride single-crystal manufacturing method in which a liquid layer (08-06-2009
20090197397Method of Manufacturing Semiconductor Device - The present invention discloses a method of manufacturing a semiconductor device including a plurality of semiconductor layers grown on a substrate and removing the substrate from the plurality of semiconductor layers. The method of manufacturing the semiconductor device comprises a first step for growing a III-nitride compound semiconductor layer between the substrate and the plurality of semiconductor layers, and a second step for removing the substrate by etching the III-nitride compound semiconductor layer.08-06-2009
20120309176SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate, a gate insulating film formed over the semiconductor substrate, a gate electrode formed on the gate insulating film, a first semiconductor layer which is embedded into a portion on both sides of the gate electrode in the semiconductor substrate, and which includes Si and a 4B group element other than Si, and a second semiconductor layer which is embedded into the portion on both sides of the gate electrode in the semiconductor substrate, so as to be superposed on the first semiconductor layer, and which includes Si and a 4B group element other than Si, wherein the gate electrode is more separated from an end of the first semiconductor layer than from an end of the second semiconductor layer.12-06-2012
20120309177TRENCHED POWER SEMICONDUCTOR STRUCTURE WITH REDUCED GATE IMPEDANCE AND FABRICATION METHOD THEREOF - A trenched power semiconductor structure with reduced gate impedance and a fabrication method thereof is provided. The trenched power semiconductor structure has a silicon base, a gate trench, a gate oxide layer, and a gate polysilicon structure. The gate trench is formed in the silicon base and extended to an upper surface of the silicon base. The gate oxide layer is formed at least on the inner surface of the gate trench. The gate polysilicon structure is formed in the gate trench with a protruding portion extended form the upper surface of the semiconductor substrate upward. A concave is formed on a sidewall of the protruding portion to expose the upper surface of the silicon base adjacent to the gate trench.12-06-2012
20120309175VAPOR-PHASE GROWTH SEMICONDUCTOR SUBSTRATE SUPPORT SUSCEPTOR, EPITAXIAL WAFER MANUFACTURING APPARATUS, AND EPITAXIAL WAFER MANUFACTURING METHOD - According to the present invention, there is provided a vapor-phase growth semiconductor substrate support susceptor for supporting a semiconductor substrate at the time of vapor-phase growth, wherein the susceptor comprises a pocket portion in which the semiconductor substrate is arranged and has a taper portion having a taper formed such that an upper surface of the susceptor is inclined upwards or downwards from an edge of the pocket portion to an outer side. As a result, there can be provided the susceptor for supporting the semiconductor substrate at the time of vapor-phase growth that can improve flatness of an epitaxial wafer by controlling a layer thickness of an epitaxial layer at a peripheral portion on a main front surface side of the epitaxial wafer, and the epitaxial wafer manufacturing apparatus using this susceptor.12-06-2012
20120309174METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a MOSFET includes the steps of preparing a silicon carbide substrate, forming an active layer on the silicon carbide substrate, forming a gate oxide film on the active layer, forming a gate electrode on the gate oxide film, forming a source contact electrode on the active layer, and forming a source interconnection on the source contact electrode. The step of forming the source interconnection includes the steps of forming a conductor film on the source contact electrode and processing the conductor film by etching the conductor film with reactive ion etching. Then, the method of manufacturing a MOSFET further includes the step of performing annealing of heating the silicon carbide substrate to a temperature not lower than 50° C. after the step of processing the conductor film.12-06-2012
20120309173ISOLATION FOR NANOWIRE DEVICES - The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.12-06-2012
20120309172Epitaxial Lift-Off and Wafer Reuse - A method of reusing a III-nitride growth substrate according to embodiments of the invention includes epitaxially growing a III-nitride semiconductor structure on a III-nitride substrate. The III-nitride semiconductor structure includes a sacrificial layer and an additional layer grown over the sacrificial layer. The sacrificial layer is implanted with at least one implant species. The III-nitride substrate is separated from the additional layer at the implanted sacrificial layer. In some embodiments the III-nitride substrate is GaN and the sacrificial layer is GaN, an aluminum-containing III-nitride layer, or an indium-containing III-nitride layer. In some embodiments, the III-nitride substrate is separated from the additional layer by etching the implanted sacrificial layer.12-06-2012
20120309171METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming a film stack on the substrate and covering the gate structure, wherein the film stack comprises at least an oxide layer and a nitride layer; removing a portion of the film stack for forming recesses adjacent to two sides of the gate structure and a disposable spacer on the sidewall of the gate structure; and filling the recesses with a material comprising silicon atoms for forming a faceted material layer.12-06-2012
20100190321METHOD OF FABRICATING PHASE-CHANGE MEMORY DEVICE HAVING TiC LAYER - Provided is a method of fabricating a phase-change memory device. The phase-change memory device includes a memory cell having a switching device and a phase change pattern. The method includes; forming a TiC layer on a contact electrically connecting the switching device using a plasma enhanced cyclic chemical vapor deposition (PE-cyclic CVD) process, patterning the TiC layer to form a lower electrode on the contact, and forming the phase-change pattern on the lower electrode.07-29-2010
20110263099Manufacturing method of semiconductor device having vertical transistor - A method of manufacturing a semiconductor device includes forming a gate electrode material that covers a gate insulating film formed on each of side surfaces of first and second silicon pillars, wherein a film formation amount of the gate electrode material is controlled so that a first part with which the side surface of the first silicon pillar is covered via the gate insulating film does not contact with a second part with which the side surface of the second silicon pillar is covered via the gate insulating film. The method further includes: forming a mask insulating film that covers the first and second parts and fills a region between the first and second parts; and etching the gate electrode material using the mask insulating film as a mask, thereby forming gate electrodes with which the side surfaces of the first and second silicon pillars are covered via the gate insulating film, respectively and a conductive film electrically connecting the gate electrodes to each other.10-27-2011
20110189840METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES - In a first aspect, a method is provided that includes: forming a plurality of conductive or semiconductive features above a first dielectric material; depositing a second dielectric material above the conductive or semiconductive features; etching a void in the second dielectric material, wherein the etch is selective between the first and the second dielectric material and the etch stops on the first dielectric material; and exposing a portion of the conductive or semiconductive features. Numerous other aspects are provided.08-04-2011
20110189839Method for producing a semiconductor device with a semiconductor body - A semiconductor device with a semiconductor body and method for its production is disclosed. The semiconductor body includes drift zones of epitaxially grown semiconductor material of a first conduction type. The semiconductor body further includes charge compensation zones of a second conduction type complementing the first conduction type, which are arranged laterally adjacent to the drift zones. The charge compensation zones are provided with a laterally limited charge compensation zone doping, which is introduced into the epitaxially grown semiconductor material. The epitaxially grown semiconductor material includes 20 to 80 atomic % of the doping material of the drift zones and a doping material balance of 80 to 20 atomic % introduced by ion implantation and diffusion.08-04-2011
20110189838Zirconium and Hafnium Boride Alloy Templates on Silicon for Nitride Integration Applications - Semiconductor structures are provided comprising a substrate and a epitaxial layer formed over the substrate, wherein the epitaxial layer comprises B; and one or more element selected from the group consisting of Zr, Hf and Al and has a thickness greater than 50 nm. Further, methods for integrating Group III nitrides onto a substrate comprising, forming an epitaxial buffer layer of a diboride of Zr, Hf, Al, or mixtures thereof, over a substrate; and forming a Group III nitride layer over the buffer layer, are provided which serve to thermally decouple the buffer layer from the underlying substrate, thereby greatly reducing the strain induced in the semiconductor structures upon fabrication and/or operation.08-04-2011
20110189837Realizing N-Face III-Nitride Semiconductors by Nitridation Treatment - A method of forming a semiconductor structure includes providing a substrate; forming a buffer/nucleation layer over the substrate; forming a group-III nitride (III-nitride) layer over the buffer/nucleation layer; and subjecting the III-nitride layer to a nitridation. The step of forming the III-nitride layer comprises metal organic chemical vapor deposition.08-04-2011
20120149176METHOD AND APPARATUS FOR FORMING A III-V FAMILY LAYER - Provided is an apparatus. The apparatus includes: a first deposition component that is operable to form a compound over a semiconductor wafer, the compound including at least one of: a III-family element and a V-family element; a second deposition component that is operable to form a passivation layer over the compound; and a transfer component that is operable to move the semiconductor wafer between the first and second deposition components, the transfer component enclosing a space that contains substantially no oxygen and substantially no silicon; wherein the loading component, the first and second deposition components, and the transfer component are all integrated into a single fabrication tool.06-14-2012
20100029064GROUP III-NITRIDES ON SI SUBSTRATES USING A NANOSTRUCTURED INTERLAYER - A layered group III-nitride article includes a single crystal silicon substrate, and a highly textured group III-nitride layer, such as GaN, disposed on the silicon substrate. The highly textured group III-nitride layer is crack free and has a thickness of at least 10 μm. A method for forming highly textured group III-nitride layers includes the steps of providing a single crystal silicon comprising substrate, depositing a nanostructured In02-04-2010
20100029063CARBON NANOTUBE FABRICATION FROM CRYSTALLOGRAPHY ORIENTED CATALYST - A device and method associated with carbon nanowires, such as single walled carbon nanowires having a high degree of alignment are set forth herein. A catalyst layer is deposited having a predetermined crystallographic configuration so as to control a growth parameter, such as an alignment direction, a diameter, a crystallinity and the like of the carbon nanowire. The catalyst layer is etched to expose a sidewall portion. The carbon nanowire is nucleated from the exposed sidewall portion. An electrical circuit device can include a single crystal substrate, such as Silicon, and a crystallographically oriented catalyst layer on the substrate having an exposed sidewall portion. In the device, carbon nanowires are disposed on the single crystal substrate aligned in a direction associated with the crystallographic properties of the catalyst layer.02-04-2010
20100029065METHOD AND APPARATUS FOR PRODUCING GROUP III NITRIDE - A method of producing a group III nitride such as aluminum nitride, comprising the step of reacting a group III halide gas such as aluminum trichloride gas with a nitrogen source gas such as ammonia gas in a growth chamber to grow a group III nitride on a substrate held in the growth chamber, wherein the method further comprises premixing together the group III halide gas and the nitrogen source gas to obtain a mixed gas and then introducing the mixed gas into the growth chamber without forming a deposit in the mixed gas substantially to be reacted each other.02-04-2010
20090137100Tellurium Precursors for GST Films in an ALD or CVD Process - The present invention is a process of making a germanium-antimony-tellurium alloy film using a process selected from the group consisting of atomic layer deposition and chemical vapor deposition, wherein a silyltellurium precursor is used as a source of tellurium for the alloy film and is reacted with an alcohol during the deposition process.05-28-2009
20100297832SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SUBSTRATE PROCESSING APPARATUS, SUBSTRATE MANUFACTURING METHOD - Provided is a substrate processing apparatus, a semiconductor device manufacturing method, and a substrate manufacturing method. The substrate processing apparatus comprises: a reaction chamber configured to process substrates; a first gas supply system configured to supply at least a silicon-containing gas and a chlorine-containing gas or at least a gas containing silicon and chlorine; a first gas supply unit connected to the first gas supply system; a second gas supply system configured to supply at least a reducing gas; a second gas supply unit connected to the second gas supply system; a third gas supply system configured to supply at least a carbon-containing gas and connected to at least one of the first gas supply unit and the second gas supply unit; and a control unit configured to control the first to third gas supply systems.11-25-2010
20100029067ROLL-TO-ROLL CONTINUOUS THIN FILM PV MANUFACTURING PROCESS AND EQUIPMENT WITH REAL TIME ONLINE IV MEASUREMENT - Apparatuses and methods are provided for the continuous, roll-to-roll formation of photovoltaic (PV) cells. Apparatuses include reel-to-reel transport chambers, one or more deposition chambers, a differential process isolation unit and a chamber for obtaining real time quality data, including IV data, yield data and uniformity data.02-04-2010
20110076840Method of Manufacturing a Fast Recovery Rectifier - A fast recovery rectifier structure with the combination of Schottky structure to relieve the minority carriers during the forward bias condition for the further reduction of the reverse recovery time during switching in addition to the lifetime killer such as Pt, Au, and/or irradiation. This fast recovery rectifier uses unpolished substrates and thick impurity diffusion for low cost production. A reduced p-n junction structure with a heavily doped film is provided to terminate and shorten the p-n junction space charge region. This reduced p-n junction with less total charge in the p-n junction to further improve the reverse recovery time. This reduced p-n junction can be used alone, with the traditional lifetime killer method, with the Schottky structure and/or with the epitaxial substrate.03-31-2011
20090263958CLATHRATE COMPOUNDS AND METHODS OF MANUFACTURING - The present invention comprises new materials, material structures, and processes of fabrication of such that may be used in technologies involving the conversion of light to electricity and/or heat to electricity, and in optoelectronics technologies. The present invention provide for the fabrication of a clathrate compound comprising a type II clathrate lattice with atoms of silicon and germanium as a main framework forming lattice spacings within the framework, wherein the clathrate lattice follows the general formula Si10-22-2009
20120302045METHOD FOR PRODUCING MOSAIC DIAMOND - The present invention discloses a method for producing a mosaic diamond comprising implanting ions in the vicinity of the surfaces of a plurality of single-crystal diamond substrates arranged in the form of a mosaic, or in the vicinity of the surfaces of mosaic single-crystal diamond substrates whose back surfaces are bonded by a single-crystal diamond layer, so as to form non-diamond layers; growing a single-crystal diamond layer by a vapor-phase synthesis method; and separating the single-crystal diamond layer above the non-diamond layers by etching the non-diamond layers. The method of the present invention prevents the destruction of single-crystal diamond substrates by using a process that is simpler than conventional methods, thus allowing a large quantity of mosaic diamond to be produced in a stable and efficient manner.11-29-2012
20120302044METHOD FOR DEPOSITION OF NANOPARTICLES ONTO SUBSTRATES - A method for electrodepositing nanoparticles onto a substrate, including heating a nonaqueous polar suspension of a plurality of semiconducting nanoparticles to a temperature between about 30 degrees Celsius and about 100 degrees Celsius, placing a substrate into the suspension, imparting opposite surface charges onto the plurality of semiconducting particles and onto the substrate, establishing an electric field in the suspension, depositing a film of semiconducting particles onto the substrate to define a coated substrate, removing the coated substrate from the suspension into air, and coating the film of semiconducting particles with an electrically conducting metal layer.11-29-2012
20110306186METHODS FOR LOW TEMPERATURE CONDITIONING OF PROCESS CHAMBERS - Methods for removing residue from interior surfaces of process chambers are provided herein. In some embodiments, a method of conditioning interior surfaces of a process chamber may include maintaining a process chamber at a first pressure and at a first temperature of less than about 800 degrees Celsius; providing a process gas to the process chamber at the first pressure and the first temperature, wherein the process gas comprises chlorine and nitrogen to remove residue disposed on interior surfaces of the process chamber; and increasing the pressure in the process chamber from the first pressure to a second pressure while continuing to provide the process gas to the process chamber.12-15-2011
20110306187METHOD AND APPARATUS FOR SILICON REFINEMENT - A method and respect material for the production of chlorosilanes (primarily: trichlorosilane) and the deposition of high purity poly-silicon from these chlorosilanes. The source for the chlorosilane production consists of eutectic or hypo-eutectic copper-silicon, the concentration range of said copper-silicon is between 10 and 16 wt % silicon. The eutectic or hypo-eutectic copper-silicon is cast in a shape suitable for a chlorination reactor, where it is exposed to a process gas, which consists, at least partially, of HCl. The gas reacts at the surface of the eutectic or hypo-eutectic copper-silicon and extracts silicon in the form of volatile chlorosilane. The depleted eutectic or hypo-eutectic material might be afterwards recycled in such a way that the amount of extracted silicon is replenished and the material is re-cast into the material shape desired.12-15-2011
20110306185METHOD FOR FORMING LAMINATED RESIN FILM AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes the steps of forming a semiconductor layer; forming a non-silicon-containing resin layer on the semiconductor layer; forming a pattern in the non-silicon-containing resin layer; forming a silicon-containing resin layer on the non-silicon-containing resin layer; etching the silicon-containing resin layer; selectively etching the non-silicon-containing resin layer; and etching the semiconductor layer. The step of forming the silicon-containing resin layer includes the steps of applying a silicon-containing resin solution with a first viscosity on a surface of the non-silicon-containing resin layer, the silicon-containing resin solution containing a silicon-containing resin and a volatile solvent; heating the silicon-containing resin layer to a first temperature, the silicon-containing resin layer having a second viscosity by heating to the first temperature, the second viscosity being larger than the first viscosity; and applying a rinse solution containing a volatile component to an edge portion of the silicon-containing resin layer.12-15-2011
20090035921FORMATION OF LATTICE-TUNING SEMICONDUCTOR SUBSTRATES - A method of forming a lattice-tuning semiconductor substrate comprises defining a selected area (02-05-2009
20120040512METHOD TO FORM NANOPORE ARRAY - A method of forming nanopore is provided that includes forming a first structure on a substrate, and forming a second structure overlying the first structure. An intersecting portion of the first and the second structures is etched to provide an opening of nanopore dimensions. The substrate may be etched with a backside substrate etch to expose the nanopore opening.02-16-2012
20120040513Plasma Deposition of Amorphous Semiconductors at Microwave Frequencies - Apparatus and method for plasma deposition of thin film photovoltaic materials at microwave frequencies. The apparatus avoids unintended deposition on windows or other microwave transmission elements that couple microwave energy to deposition species. The apparatus includes a microwave applicator with one or more conduits passing therethrough that carry deposition species. The applicator transfers microwave energy to the deposition species to activate or energize them to a reactive state. The conduits physically isolate deposition species that would react or otherwise combine to form a thin film material at the point of microwave power transfer and deliver the microwave-excited species to a deposition chamber. One or more supplemental material streams may be delivered directly to the deposition chamber without passing through the microwave applicator and may combine with deposition species exiting the one or more conduits to form a thin film material. Precursors for the microwave-excited deposition species include fluorinated forms of silicon. Precursors delivered as supplemental material streams include hydrogenated forms of silicon. The invention allows for the ultrafast formation of silicon-containing amorphous semiconductors that exhibit high mobility, low porosity, little or no Staebler-Wronski degradation, and low defect concentration.02-16-2012
20120040517METHODS FOR FORMING ISOLATED FIN STRUCTURES ON BULK SEMICONDUCTOR MATERIAL - Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.02-16-2012
20120040516METHOD AND DEVICE FOR DEPOSITING SEMICONDUCTOR FILM ON SUBSTRATE USING CLOSE-SPACED SUBLIMATION PROCESS - A method and device for depositing a semiconductor film. The method includes: a) carrying a semiconductor material by a carrier gas to a crucible installed in a vacuum deposition chamber via a passage; and b) heating the crucible to sublimate the semiconductor material to be vapor and depositing the vapor on a substrate. The device includes a semiconductor material feeding device, a passage, a vacuum deposition chamber, a crucible installed in the vacuum deposition chamber, and a substrate located above the crucible. The semiconductor material feeding device and the crucible are connected via the passage. The semiconductor material feeding device supplies semiconductor material and carrier gas. The semiconductor material is carried by the carrier gas and enters the crucible via the passage. The method and device can supply semiconductor materials continuously or periodically without opening a vacuum deposition chamber thereof and the uniformity of thin film can be controlled effectively.02-16-2012
20120040514CHEMICAL VAPOR DEPOSITION WITH ELEVATED TEMPERATURE GAS INJECTION - A chemical vapor deposition reactor and method. Reactive gases, such as gases including a Group III metal source and a Group V metal source, are introduced into the chamber (02-16-2012
20120178243METHOD FOR MAKING SEMICONDUCTOR EPITAXIAL STRUCTURE - A method for making a semiconductor epitaxial structure is provided. The method includes growing a substrate having an epitaxial growth surface, placing a carbon nanotube layer on the epitaxial growth surface, epitaxially growing a doped semiconductor epitaxial layer on the epitaxial growth surface. The carbon nanotube layer can be suspended above the epitaxial growth surface.07-12-2012
20100105192Method of Manufacturing Semiconductor Device and Substrate Processing Apparatus - A method of manufacturing a semiconductor device includes: forming an oxide film having a predetermined film thickness on a substrate by repeating a process of forming a predetermined element-containing layer on the substrate by supplying source gas containing a predetermined element into a process vessel accommodating the substrate, and a process of changing the predetermined element-containing layer to an oxide layer by supplying oxygen-containing gas and hydrogen-containing gas into the process vessel that is set below atmospheric pressure, wherein the oxygen-containing gas is oxygen gas or ozone gas, the hydrogen-containing gas is hydrogen gas or deuterium gas, and the temperature of the substrate is in a range from 400° C. or more to 700° C. or less in the process of forming the oxide film.04-29-2010
20110318906Separation Apparatus, Separation Method, and Method for Manufacturing Semiconductor Element - Objects are to reduce the number of steps in a process for separating a substrate and a semiconductor element, to provide a separation apparatus capable of reducing the number of steps, to suppress manufacturing cost by reducing the number of steps in a separation process, and to improve productivity in manufacturing semiconductor elements. A separation apparatus including a frame body, a porous body having a chamfered, rounded corner portion, a suction unit configured to create suction in the porous body and the frame body, and a jig which includes a unit adopted to press down part of an object to be separated and a unit adopted to lift another part of the object to be separated, and also a separation method and a method for manufacturing a semiconductor element by using the separation apparatus, are provided.12-29-2011
20120208355GALLIUM NITRIDE SUBSTRATE - A gallium nitride substrate comprising a primary surface, the primary surface being tilted at an angle in a range of 20 to 160 degrees with respect to a C-plane of the substrate, and the substrate having a fracture toughness of more than or equal to 1.36 MN/m08-16-2012
20120045885METHOD FOR MAKING NANOWIRE ELEMENT - A method for making a nanowire element includes: providing an imprint mold including a first substrate and a conductive pattern-transferring layer, the pattern-transferring layer includes first conductive strips; electrifying the pattern-transferring layer with an alternating current; applying a nanowire-containing suspension on the pattern-transferring layer; reorienting the nanowires in the nanowire-containing suspension using a dielectrophoresis method, thereby the nanowires connected between two adjacent first conductive strips; providing a pattern-receiving body, the pattern-receiving body including a second substrate and a pattern-receiving layer; pressing the imprint mold onto the pattern-receiving body with the conductive pattern-transferring layer facing the pattern-receiving layer, thereby defining a patterned recess in the pattern-receiving layer and transferring the nanowires to the second substrate; forming a first conductive layer on the second substrate to obtain a conductive pattern layer, the conductive pattern layer including second conductive strips, the nanowires connecting two adjacent second conductive strips; and removing the pattern-receiving layer.02-23-2012
20120003821METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes performing thermal cleaning for a surface of a silicon substrate in an atmosphere including hydrogen under a condition that a thermal cleaning temperature is higher than or equal to 700° C. and is lower than or equal to 1060° C., and a thermal cleaning time is longer than or equal to 5 minutes and is shorter than or equal to 15 minutes; forming a first AlN layer on the substrate with a first V/III source ratio, the forming of the first AlN layer including supplying an Al source to the surface of the substrate without supplying a N source, and supplying both the Al source and the N source; forming a second AlN layer on the first AlN layer with a second V/III source ratio that is greater than the first ratio; and forming a GaN-based semiconductor layer on the second AlN layer.01-05-2012
20120003820METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming an AlN layer on a substrate made of silicon by supplying an Al source without supplying a N source and then supplying both the Al source and the N source, and forming a GaN-based semiconductor layer on the AlN layer after the forming of the AlN layer. The forming of the AlN layer grows the AlN layer so as to satisfy the following:01-05-2012
20090291545PROCESS FOR ENHANCING SOLUBILITY AND REACTION RATES IN SUPERCRITICAL FLUIDS - Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, providing a supercritical fluid containing at least one reactant, the supercritical fluid being maintained at above its critical point, exposing at least a portion of the surface of the semiconductor substrate to the supercritical fluid, applying acoustic energy, and reacting the at least one reactant to cause a change in at least a portion of the surface of the semiconductor substrate.11-26-2009
20120003823METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A combined substrate is prepared which has a supporting portion and first and second silicon carbide substrates. The first silicon carbide substrate has a first front-side surface and a first side surface. The second silicon carbide substrate has a second front-side surface and a second side surface. The second side surface is disposed such that a gap having an opening between the first and second front-side surfaces is formed between the first side surface and the second side surface. By introducing melted silicon from the opening into the gap, a silicon connecting portion is formed to connect the first and second side surfaces so as to close the opening. By carbonizing the silicon connecting portion, a silicon carbide connecting portion is formed.01-05-2012
20120003819Methods and apparatus for selective epitaxy of si-containing materials and substitutionally doped crystalline si-containing material - The present invention discloses that under modified chemical vapor deposition (mCVD) conditions an epitaxial silicon film may be formed by exposing a substrate contained within a chamber to a relatively high carrier gas flow rate in combination with a relatively low silicon precursor flow rate at a temperature of less than about 550° C. and a pressure in the range of about 10 mTorr-200 Torr. Furthermore, the crystalline Si may be in situ doped to contain relatively high levels of substitutional carbon by carrying out the deposition at a relatively high flow rate using tetrasilane as a silicon source and a carbon-containing gas such as dodecalmethylcyclohexasilane or tetramethyldisilane under modified CVD conditions.01-05-2012
20120003822Wafer Guide, MOCVD Equipment, and Nitride Semiconductor Growth Method - Wafer guide for MOCVD equipment that reduces influence from III-nitride deposits. A wafer support (01-05-2012
20120064698MULTIPLE SECTION SHOWERHEAD ASSEMBLY - Embodiments of the present invention generally provide a method and apparatus that may be utilized for deposition of Group III-nitride films using MOCVD and/or HVPE hardware. In one embodiment, the apparatus is a showerhead assembly made of multiple sections that are isolated from one another and attached to a top plate. Each showerhead section has separate inlets and passages for delivering separate processing gases into a processing volume of a processing chamber without mixing the gases prior to entering the processing volume. In one embodiment, each showerhead section includes a temperature control manifold for flowing a cooling fluid through the respective showerhead section. By providing multiple, isolated showerhead sections, manufacturing complexity and costs are significantly reduced as compared to conventionally manufacturing the entire showerhead from a single block or stack of plates.03-15-2012
20110008951Method of manufacturing strained-silicon semiconductor device - A method for fabricating a strained-silicon semiconductor device to ameliorate undesirable variation in selectively grown epitaxial film thickness. The layout or component configuration for the proposed semiconductor device is evaluated to determine areas of relatively light or dense population in order to determine whether local-loading-effect defects are likely to occur. If a possibility of such defects occurring exists, a dummy pattern of epitaxial structures may be indicated. If so, the dummy pattern appropriate to the proposed layout is created, incorporated into the mask design, and then implemented on the substrate along with the originally-proposed component configuration.01-13-2011
20120045886Methods for Infusing One or More Materials into Nano-Voids of Nanoporous or Nanostructured Materials - A method of forming composite nanostructures using one or more nanomaterials. The method provides a nanostructure material having a surface region and one or more nano void regions within a first thickness in the surface region. The method subjects the surface region of the nanostructure material with a fluid. An external energy is applied to the fluid and/or the nanostructure material to drive in a portion of the fluid into one or more of the void regions and cause the one or more nano void regions to be substantially filled with the fluid and free from air gaps.02-23-2012
20130196486Semiconductor Substrates Using Bandgap Material Between III-V Channel Material and Insulator Layer - Improved semiconductor substrates are provided that employ a wide bandgap material between the channel and the insulator. A semiconductor substrate comprises a channel layer comprised of a III-V material; an insulator layer; and a wide bandgap material between the channel layer and the insulator layer, wherein a conduction band offset (ΔE) between the channel layer and the wide bandgap material is between 0.05 eV and 0.8 eV. The channel layer can be comprised of, for example, In08-01-2013
20120009765COMPARTMENTALIZED CHAMBER - Embodiments of the present invention generally relate to apparatus for improving processing uniformity and reducing needs of chamber cleaning. Particularly, embodiments of the present invention relate to a processing chamber having a loading compartment and a processing compartment in substantial fluid isolation and methods of depositing films in the processing chamber.01-12-2012
20120009764METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - A method of manufacturing a semiconductor device includes conveying a first substrate provided with an opposing surface having insulator regions and a semiconductor region exposed between the insulator regions and a second substrate provided with an insulator surface exposed toward the opposing surface of the first substrate, into a process chamber in a state that the second substrate is arranged in to face the opposing surface of the first substrate, and selectively forming a silicon-containing film with a flat surface at least on the semiconductor region of the opposing surface of the first substrate by heating an inside of the process chamber and supplying at least a silicon-containing gas and a chlorine-containing gas into the process chamber.01-12-2012
20120015504SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor device includes: a first semiconductor region formed on a substrate and having an upper surface and a side surface; a first impurity region of a first conductivity type formed in an upper portion of the first semiconductor region; a second impurity region of a first conductivity type formed in a side portion of the first semiconductor region; and a gate insulating film formed so as to cover at least a side surface and an upper corner of a predetermined portion of the first semiconductor region. A radius of curvature r′ of an upper corner of a portion of the first semiconductor region located outside the gate insulating film is greater than a radius of curvature r of an upper corner of a portion of the first semiconductor region located under the gate insulating film and is less than or equal to 2r.01-19-2012
20120015503METHOD OF FORMING SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor device includes chemically cleaning a surface of a substrate to form a chemical oxide material on the surface. At least a portion of the chemical oxide material is removed at a removing rate of about 2 nanometer/minute (nm/min) or less. Thereafter, a gate dielectric layer is formed over the surface of the substrate.01-19-2012
20120015502p-GaN Fabrication Process Utilizing a Dedicated Chamber and Method of Minimizing Magnesium Redistribution for Sharper Decay Profile - Methods and systems for the fabrication of p-GaN, and related, films utilizing a dedicated chamber in a multi-chamber tool are described. Also described are methods of fabricating a magnesium doped group III-V material layer, such as a GaN layer, with a sharp magnesium decay profile.01-19-2012
20120015501Silicon Surface Modification for the Electrochemical Synthesis of Silicon Particles in Suspension - A process of silicon (Si) surface modification is provided for the electrochemical synthesis of Si particles in suspension. The process begins with a Si first substrate with a surface, and forms Si particles attached to the surface. Hydrogen-terminated Si particles are created and the first substrate is immersed in a hexane/1-octene (1/1 volume ratio) solution with a catalytic amount of chloroplatinic acid (H01-19-2012
20110165764METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A first silicon carbide substrate having a first back-side surface and a second silicon carbide substrate having a second back-side surface are prepared. The first and second silicon carbide substrates are placed so as to expose each of the first and second back-side surfaces in one direction. A connecting portion is formed to connect the first and second back-side surfaces to each other. The step of forming the connecting portion includes a step of forming a growth layer made of silicon carbide on each of the first and second back-side surfaces, using a sublimation method of supplying a sublimate thereto in the one direction.07-07-2011
20110165763SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor body with a semiconductor device structure including at least a first electrode and a second electrode. Between the two electrodes, a drift region is arranged, the drift region including charge compensation zones and drift zones arranged substantially parallel to one another. At least one charge carrier storage region which is at least partially free of charge compensation zones is arranged in the semiconductor body.07-07-2011
20110165761METHODS OF FABRICATING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED BY THE SAME - Example methods and example embodiments include methods of fabricating semiconductor devices and semiconductor devices fabricated by the same. Example fabricating methods include forming a first nanowire, oxidizing the first nanowire to form a first nanostructure including a first insulator and a second nanowire, and oxidizing the second nanowire to form a second nanostructure including a second insulator and nanodots. Example semiconductor devices include nanostructures including nanodots and nanostructures providing storage nodes in memory devices.07-07-2011
20110165760METHOD OF PRODUCING BIPOLAR TRANSISTOR STRUCTURES IN A SEMICONDUCTOR PROCESS - In the method of producing bipolar transistor structures in a semiconductor process, an advanced epitaxial trisilane process can be used without the risk of poly stringers being formed. A base window is structured in a polycrystalline silicon layer covered with an oxide layer, and a further step is epitaxial growing of a silicon layer in the base window from trisilane. The window structuring is performed in a sequence of anisotropic etch and isotropic ash steps, thereby creating stepped and inwardly sloping window edges. Due to the inwardly sloping side walls of the window, the epitaxially grown silicon layer is formed without inwardly overhanging structures, and the cause of poly stringers forming is thus eliminated.07-07-2011
20120058628Multiple-Gate Transistors with Reverse T-Shaped Fins - A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric.03-08-2012
20120058627COMPOUND SEMICONDUCTOR DEPOSITION METHOD AND APPARATUS - Provided is a compound semiconductor deposition method of adjusting the luminous wavelength of a compound semiconductor of a ternary or higher system in a nanometer order in depositing the compound semiconductor on a substrate. In the compound semiconductor deposition method of depositing a compound semiconductor of a ternary or higher system on a substrate, propagation light of a smaller energy than a desired ideal excitation energy for the compound semiconductor is irradiated onto the substrate 03-08-2012
20120058626METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR CRYSTAL LAYER - According to one embodiment, a method is disclosed for manufacturing a nitride semiconductor crystal layer. The method can include forming the nitride semiconductor crystal layer having a first thickness on a silicon crystal layer. The silicon crystal layer is provided on a base body. The silicon crystal layer has a second thickness before the forming the nitride semiconductor crystal layer. The second thickness is thinner than the first thickness. The forming the nitride semiconductor crystal layer includes making at least a portion of the silicon crystal layer incorporated into the nitride semiconductor crystal layer to reduce a thickness of the silicon crystal layer from the second thickness.03-08-2012
20120208352METHODS AND SYSTEMS FOR FORMING THIN FILMS - A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.08-16-2012
20120208356Device component forming method with a trim step prior to sidewall image transfer (SIT) processing - Disclosed is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed.08-16-2012
20120208354SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME - In a MOS-type semiconductor device in which, on a Si substrate, a SiGe layer having a valence band edge energy value smaller than a valence band edge energy value of the first semiconductor layer and a mobility larger than a mobility of the first semiconductor layer, a Si cap layer, and an insulating layer are sequentially laminated, the problem of the shift of the absolute value of the threshold voltage toward a smaller value caused by negative fixed charges formed in or near the interface between the Si cap layer and the insulting film by diffusion of Ge is overcome by neutralizing the negative fixed charges by positive charges induced in and near the interface between the Si cap layer and the insulating film along with addition of nitrogen atoms to the semiconductor device surface by NO gas annealing and thereby shifting the threshold voltage toward a larger value.08-16-2012
20120208353Method for Manufacturing a Semiconductor Component - A semiconductor component having a low resistance conduction path and a method for manufacturing the semiconductor component. When the semiconductor component is a Schottky diode, one or more trenches are formed in an epitaxial layer of a first conductivity type that is formed over a semiconductor substrate of the first conductivity type. The trenches may extend into the semiconductor material. Epitaxial semiconductor material of a second conductivity type is selectively grown along the sidewalls of the trenches. An anode contact is formed in contact with the epitaxial layer and the selectively grown epitaxial material and a cathode contact is formed in contact with the semiconductor substrate.08-16-2012
20120208351CLEANING APPARATUS FOR SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A cleaning apparatus for a semiconductor manufacturing apparatus includes: a oxide removal unit that removes an oxide over a surface of a deposit adhered to components of the semiconductor manufacturing apparatus, and a deposit removal unit that removes the deposit after the oxide over the surface is removed by the oxide removal unit.08-16-2012
20120108036Active Region Patterning in Double Patterning Processes - A method includes forming an SRAM cell including a first and a second pull-up transistor and a first and a second pull-down transistor. The step of forming the SRAM cell includes forming a first and a second active region of the first and the second pull-up transistors using a first lithography mask, and forming a third and a fourth active region of the first and the second pull-down transistors using a second lithography mask.05-03-2012
20090246944METHOD FOR HETEROEPITAXIAL GROWTH OF HIGH-QUALITY N-FACE GaN, InN, AND AlN AND THEIR ALLOYS BY METAL ORGANIC CHEMICAL VAPOR DEPOSITION - Methods for the heteroepitaxial growth of smooth, high quality films of N-face GaN film grown by MOCVD are disclosed. Use of a misoriented substrate and possibly nitridizing the substrate allow for the growth of smooth N-face GaN and other Group III nitride films as disclosed herein. The present invention also avoids the typical large (μm sized) hexagonal features which make N-face GaN material unacceptable for device applications. The present invention allows for the growth of smooth, high quality films which makes the development of N-face devices possible.10-01-2009
20120070965SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device includes a first conductive type first semiconductor region, a second semiconductor region, and a second conductive type lateral RESURF region. The first semiconductor region is arranged on a first electrode side. The second semiconductor region includes first conductive type first pillar regions and a terminal part. The second pillar regions are alternately arranged on an element part. The terminal part is formed around the element part along a surface of the first semiconductor region on a second electrode side opposite to the first electrode side of the first semiconductor region. Furthermore, the second conductive type lateral RESURF region is formed in the second semiconductor region on the terminal part.03-22-2012
20120070964METHOD FOR ELIMINATING THE METAL CATALYST RESIDUES ON THE SURFACE OF WIRES PRODUCED BY CATALYTIC GROWTH - This method for eliminating the catalyst residues present on the surface of solid structures made from a first material and obtained by catalytic growth, includes the following steps: 03-22-2012
20120070962Freestanding III-Nitride Single-Crystal Substrate and Method of Manufacturing Semiconductor Device Utilizing the Substrate - Freestanding III-nitride single-crystal substrates whose average dislocation density is not greater than 5×1003-22-2012
20120070963PLASMA DEPOSITION - An apparatus for depositing a group III metal nitride film on a substrate, the apparatus comprising a plasma generator to generate a nitrogen plasma from a nitrogen source, a reaction chamber in which to react a reagent comprising a group III metal with a reactive nitrogen species derived from the nitrogen plasma so as to deposit a group III metal nitride on the substrate, a plasma inlet to facilitate the passage of nitrogen plasma from the plasma generator into the reaction chamber and a baffle having one or more flow channels for passage of the nitrogen plasma. The baffle is located between the plasma inlet and the substrate and prevents a direct line of passage for nitrogen plasma between the plasma inlet and the substrate.03-22-2012
20090221130N-TYPE SEMICONDUCTOR CARBON NANOMATERIAL, METHOD FOR PRODUCING N-TYPE SEMICONDUCTOR CARBON NANOMATERIAL, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An n-Type semiconductor carbon nanomaterial is produced by mixing a substance having a functional group such as an amino or alkyl group with an inert gas and reacting a semiconductor carbon nanomaterial with the mixture under irradiation with VUV to covalently bond the amino or alkyl group to the carbon nanomaterial. The amino or alkyl group covalently bonded to the semiconductor carbon nanomaterial serves as electron-donating groups to convert the carbon nanomaterial into an n-type one. According to the invention, since the electron-donating group is covalently bonded, a stable n-type semiconductor carbon nanomaterial is obtained which little changes into a p-type one. Further, since the n-type semiconductor carbon nanomaterial is produced by a dry process, bundling or inclusion of impurities can be suppressed. Therefore, the uniform n-type semiconductor carbon nanomaterial having high reliability and stability can be produced.09-03-2009
20120156863SUBSTRATE PRETREATMENT FOR SUBSEQUENT HIGH TEMPERATURE GROUP III DEPOSITIONS - Embodiments of the present invention relate to apparatus and method for pretreatment of substrates for manufacturing devices such as light emitting diodes (LEDs) or laser diodes (LDs). One embodiment of the present invention comprises pretreating the aluminum oxide containing substrate by exposing a surface of the aluminum oxide containing substrate to a pretreatment gas mixture, wherein the pretreatment gas mixture comprises ammonia (NH06-21-2012
20120156862HIGH EFFICIENCY RECTIFIER - A method for forming a rectifier device is provided. The method forms a first layer on a substrate, a second layer is formed on the first layer and a photoresist layer is deposited on the second layer in which a plurality of trench patterns are formed. A plurality of trenches are formed in the first layer and the second layer by etching based on the trench patterns in the photoresist. The method then laterally etches the second layer to expose a corner portion of the first layer at mesas formed in between the two trenches. A portion of the second layer is preserved at an edge of the rectifier device.06-21-2012
20100003809METHOD FOR DESTRUCTION OF METALLIC CARBON NANOTUBES, METHOD FOR PRODUCTION OF AGGREGATE OF SEMICONDUCTING CARBON NANOTUBES, METHOD FOR PRODUCTION OF THIN FILM OF SEMICONDUCTING CARBON NANOTUBES, METHOD FOR DESTRUCTION OF SEMICONDUCTING CARBON NANOTUBES, METHOD FOR - A method for destruction of metallic carbon nanotubes is provided. The method includes irradiating a mixture of semiconducting carbon nanotubes and metallic carbon nanotubes with energy beams (such as laser light), thereby selectively destroying metallic carbon nanotubes or semiconducting carbon nanotubes. The energy beams have energy components for resonance absorption by the metallic carbon nanotubes or semiconducting carbon nanotubes.01-07-2010
20110092055COMPOUND SEMICONDUCTOR SUBSTRATE GROWN ON METAL LAYER, METHOD OF MANUFACTURING THE SAME, AND COMPOUND SEMICONDUCTOR DEVICE USING THE SAME - The present invention relates to a compound semiconductor substrate and a method for manufacturing the same. The present invention provides the manufacturing method which coats spherical balls on a substrate, forms a metal layer between the spherical balls, removes the spherical balls to form openings, and grows a compound semiconductor layer from the openings. According to the present invention, the manufacturing method can be simplified and grow a high quality compound semiconductor layer rapidly, simply and inexpensively, as compared with a conventional ELO (Epitaxial Lateral Overgrowth) method or a method for forming a compound semiconductor layer on a metal layer. And, the metal layer serves as one electrode of a light emitting device and a light reflecting film to provide a light emitting device having reduced power consumption and high light emitting efficiency.04-21-2011
20120252192METHOD OF GROWING HETEROEPITAXIAL SINGLE CRYSTAL OR LARGE GRAINED SEMICONDUCTOR FILMS ON GLASS SUBSTRATES AND DEVICES THEREON - Inexpensive semiconductors are produced by depositing a single crystal or large grained silicon on an inexpensive substrate. These semiconductors are produced at low enough temperatures such as temperatures below the melting point of glass. Semiconductors produced are suitable for semiconductor devices such as photovoltaics or displays10-04-2012
20110104877Compositions and Methods for Forming a Semiconducting and/or Silicon-Containing Film, and Structures Formed Therefrom - Compositions, inks and methods for forming a patterned silicon-containing film and patterned structures including such a film. The composition generally includes (a) passivated semiconductor nanoparticles and (b) first and second cyclic Group IVA compounds in which the cyclic species predominantly contains Si and/or Ge atoms. The ink generally includes the composition and a solvent in which the composition is soluble. The method generally includes the steps of (1) printing the composition or ink on a substrate to form a pattern, and (2) curing the patterned composition or ink. In an alternative embodiment, the method includes the steps of (i) curing either a semiconductor nanoparticle composition or at least one cyclic Group IVA compound to form a thin film, (ii) coating the thin film with the other, and (iii) curing the coated thin film to form a semiconducting thin film. The semiconducting thin film includes a sintered mixture of semiconductor nanoparticles in hydrogenated, at least partially amorphous silicon and/or germanium. The thin film exhibits improved conductivity, density, adhesion and/or carrier mobility relative to an otherwise identical structure made by an identical process, but without either the semiconductor nanoparticles or the hydrogenated Group IVA element polymer. The present invention advantageously provides semiconducting thin film structures having qualities suitable for use in electronics applications, such as display devices or RF ID tags, while enabling high-throughput printing processes that form such thin films in seconds or minutes, rather than hours or days as with conventional photolithographic processes.05-05-2011
20110104878SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN - By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.05-05-2011
20110104876ATMOSPHERIC PRESSURE CHEMICAL VAPOR DEPOSITION METHOD FOR PRODUCING A N-SEMICONDUCTIVE METAL SULFIDE THIN LAYER - An atmospheric pressure chemical vapor deposition method for producing an N-type semiconductive metal sulfide thin film on a heated substrate includes converting an indium-containing precursor to at least one of a liquid phase and a gaseous phase. The indium-containing precursor is mixed with an inert carrier gas stream and hydrogen sulfide in a mixing zone so as to form a mixed precursor. A substrate is heated to a temperature in a range of 100° C. to 275° C. and the mixed precursor is directed onto the substrate. The hydrogen sulfide is supplied at a rate so as to obtain an absolute concentration of hydrogen sulfide in the mixing zone of no more than 1% by volume. The In-concentration of the indium containing precursor is selected so as to produce a compact indium sulfide film.05-05-2011
20110104875SELECTIVE SILICON ETCH PROCESS - A process for etching a silicon layer disposed on a substrate, including anisotropically etching a first trench in the silicon layer; selectively anisotropic wet etching silicon surfaces in the first trench, the wet etching comprising exposing the silicon surfaces to an aqueous composition including an aromatic tri(lower)alkyl quaternary onium hydroxide, and an unsymmetrical tetraalkyl quaternary phosphonium salt; in which the wet etching etches (110) and (100) planes of the silicon layer at about equal rates and preferentially to the (111) plane to form an enlarged trench having a sidewall in the (111) plane. A silicon alloy may be epitaxially deposited in the thus-produced trench as part of a process of introducing stress into at least a portion of the silicon layer.05-05-2011
20120122301METHOD OF MANUFACTURING GaN-BASED FILM - A method of manufacturing a GaN-based film includes the steps of preparing a composite substrate, the composite substrate including a support substrate in which a coefficient of thermal expansion in its main surface is more than 0.8 time and less than 1.0 time as high as a coefficient of thermal expansion of GaN crystal in a direction of a axis and a single crystal film arranged on a main surface side of the support substrate, the single crystal film having threefold symmetry with respect to an axis perpendicular to a main surface of the single crystal film, and forming a GaN-based film on the main surface of the single crystal film in the composite substrate, the single crystal film in the composite substrate being an SiC film. Thus, a method of manufacturing a GaN-based film capable of manufacturing a GaN-based film having a large main surface area and less warpage without crack being produced in a substrate is provided.05-17-2012
20120315741ENHANCED MAGNESIUM INCORPORATION INTO GALLIUM NITRIDE FILMS THROUGH HIGH PRESSURE OR ALD-TYPE PROCESSING - Enhanced magnesium incorporation into gallium nitride films through high pressure or ALD-type processing is described. In an example, a method of fabricating a group III-nitride film includes flowing a group III precursor, a nitrogen precursor, and a p-type dopant precursor into a reaction chamber having a substrate therein. A p-type doped group III-nitride layer is formed in the reaction chamber, above the substrate, while a total pressure in the reaction chamber is approximately in the range of 300-760 Torr.12-13-2012
20120122302Apparatus And Methods For Deposition Of Silicon Carbide And Silicon Carbonitride Films - Methods for deposition of silicon carbide films on a substrate surface are provided. The methods include the use of vapor phase carbosilane precursors and may employ plasma enhanced atomic layer deposition processes. The methods may be carried out at temperatures less than 600° C., for example between about 23° C. and about 200° C. or at about 100° C. This silicon carbide layer may then be densified to remove hydrogen content. Additionally, the silicon carbide layer may be exposed to a nitrogen source to provide reactive N—H groups, which can then be used to continue film deposition using other methods. Plasma processing conditions can be used to adjust the carbon, hydrogen and/or nitrogen content of the films.05-17-2012
20090130826Method of Forming a Semiconductor Device Having a Strained Silicon Layer on a Silicon-Germanium Layer - A method of forming a semiconductor device having a strained silicon (Si) layer on a silicon germanium (SiGe) layer is provided. The method includes preparing a silicon substrate. A SiGe layer is formed on the silicon substrate. At least a part of the SiGe layer has a first dislocation density. A strained Si layer having a second dislocation density lower than the first dislocation density is formed on the SiGe layer.05-21-2009
20090130825Joined Assembly, Wafer Holding Assembly, Attaching Structure Thereof and Method for Processing Wafer - The object of the present invention is to provide an assembly, wafer holding assembly and attaching structure thereof, wherein sufficient air-tightness is assured during prolonged cycles of temperature rises and uninstallations and replacements of the assemblies are possible.05-21-2009
20120214292Gallium ink and methods of making and using same - A gallium ink is provided, comprising, as initial components: a gallium component comprising gallium; a stabilizing component, wherein the stabilizing component is selected from 1,3-propanedithiol, beta-mercaptoethanol, analogs thereof and mixtures thereof; an additive, wherein the additive is selected from the group consisting of pyrazine; 2-methylpyrazine; 3-methylpyrazole; methyl 2-pyrazinecarboxylate; pyrazole; praxadine; pyrazine carboxamide; pyrazine carbonitrile; 2,5-dimethylpyrazine; 2,3,5,6-tetramethylpyrazine; 2-aminopyrazine; 2-ethylpyrazine; quinoxaline; quinoxaline substituted with a C08-23-2012
20110183499Nano-tube MOSFET technology and devices - This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.07-28-2011
20110183501THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - The present invention provides a step in which a channel-length of a TFT can be controlled with higher reproducibility. In addition, the present invention provides a step in which a short channel-length of the TFT can be manufactured. Further, the present invention provides a structure of the TFT in which a current-voltage characteristic can be improved. The present invention refers to a thin film transistor comprising a lamination layer wherein a first conductive film, a first insulating film and a second conductive film are sequentially laminated, a semiconductor film formed so as to be in contact with the side surface of the lamination layer, and a third conductive film covering the semiconductor film through a second insulating film. The first conductive film and the second conductive film are a source electrode and a drain electrode, and a region which is in contact with the first insulating film and the third conductive film is a channel forming region in semiconductor film, and the third conductive film is a gate electrode.07-28-2011
20110183500MANUFACTURING METHOD OF MEMORY ELEMENT, LASER IRRADIATION APPARATUS, AND LASER IRRADIATION METHOD - A method for rapidly performing laser irradiation in a desired position as laser irradiation patterns are switched is proposed. A laser beam emitted from a laser oscillator is entered into a deflector, and a laser beam which has passed through the deflector is entered into a diffractive optical element to be diverged into a plurality of laser beams. Then, a photoresist formed over an insulating film is irradiated with the laser beam which is made to diverge into the plurality of laser beams, and the photoresist irradiated with the laser beam is developed so as to selectively etch the insulating film.07-28-2011
20110183498 High Pressure Apparatus and Method for Nitride Crystal Growth - An improved high pressure apparatus and methods for processing supercritical fluids is described. The apparatus includes a capsule, a heater, and at least one ceramic ring contained by a metal sleeve. The apparatus is capable of accessing pressures and temperatures of 0.2-2 GPa and 400-1200° C.07-28-2011
20110183497METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include multiply stacking an insulating layer and a conductive layer alternately above a base member. The insulating layer includes silicon oxide. The conductive layer includes silicon. In addition, the method can form a SiOC film on a stacked body of the insulating layers and the conductive layers, pattern the SiOC film, and make a hole in the stacked body by etching the insulating layers and the conductive layers using the patterned SiOC film as a mask.07-28-2011
20120129320METHOD OF NISIGE EPITAXIAL GROWTH BY INTRODUCING AL INTERLAYER - The present invention discloses a method of NiSiGe epitaxial growth by introducing Al interlayer, comprising the deposition of an Al thin film on the surface of SiGe layer, subsequent deposition of a Ni layer on Al thin film and then the annealing process for the reaction between Ni layer and SiGe material of SiGe layer to form NiSiGe material. Due to the barrier effect of Al interlayer, NiSiGe layer features a single crystal structure, a flat interface with SiGe substrate and a thickness of up to 0.3 nm, significantly enhancing interface performance.05-24-2012
20100210092METHOD AND APPARATUS FOR MANUFACTURING SILICON THIN FILM LAYER AND MANUFACTURING APPARATUS OF SOLAR CELL - A method and apparatus for manufacturing a silicon thin film layer and a manufacturing apparatus of a solar cell are disclosed. The manufacturing apparatus of solar cell comprises an outer chamber; an inner chamber disposed within the outer chamber; a container disposed at the inner chamber and which receives a fluid; and a heat exchanger disposed at the outside of the outer chamber and which exchanges heat of the fluid.08-19-2010
20120220108SUBSTRATE PROCESSING APPARATUS, AND METHOD OF MANUFACTURING SUBSTRATE - When processing such as SiC epitaxial growth is performed at an ultrahigh temperature of 1500° C. to 1700° C., a film-forming gas can be decreased to heat-resistant temperature of a manifold and film quality uniformity can be improved. A substrate processing apparatus includes a reaction chamber for processing a plurality of substrates, a boat for holding the plurality of substrates, a gas supply nozzle for supplying a film-forming gas to the plurality of substrates, an exhaust port for exhausting the film-forming gas supplied into the reaction chamber, a heat exchange part which defines a second flow path narrower than a first flow path defined by an inner wall of the reaction chamber and the boat, and a gas discharge part installed under the lowermost substrate of the plurality of substrates.08-30-2012
20120220107SUBSTRATE PROCESSING APPARATUS, WAFER HOLDER, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a substrate processing apparatus having a stack structure of wafers that can endure a high temperature without bad influence on film-forming precision. The stack structure includes a holder base (08-30-2012
20120315743COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device is provided with a substrate, an AlN layer formed over the substrate, an AlGaN layer formed over the AlN layer and larger in electron affinity than the AlN layer, another AlGaN layer formed over the AlGaN layer and smaller in electron affinity than the AlGaN layer. Furthermore, there are provided an i-GaN layer formed over the latter AlGaN layer, and an i-AlGaN layer and an n-AlGaN layer formed over the i-GaN layer.12-13-2012
20120315742METHOD FOR FORMING NITRIDE SEMICONDUCTOR DEVICE - A method for producing a nitride semiconductor device is disclosed. The method includes steps of: forming a channel layer, an InAlN doped layer sequentially on the substrate, raising a temperature of the substrate as supplying a gas source containing In, and/or another gas source containing Al, and growing GaN layer on the InAlN doped. Or, the method grows the channel layer, the InAlN layer, and another GaN layer sequentially on the substrate, raising the temperature of the substrate, and growing the GaN layer. These methods suppress the sublimation of InN from the InAlN layer.12-13-2012
20120220106CARBON NANOTUBE FORMING METHOD AND PRE-TREATMENT METHOD THEREFOR - A carbon nanotube forming method including providing a target substrate to be processed, a catalytic metal layer being formed on a surface of the target substrate; producing catalytic fine metal particles whose surfaces are oxidized by action of an oxygen plasma on the catalytic metal layer at a temperature T08-30-2012
20100173479VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF FORMING VARIABLE RESISTANCE MEMORY DEVICES - Provided are variable resistance memory devices and methods of forming the variable resistance memory devices. The methods can include forming an etch stop layer on an electrode, forming a molding layer on the etch stop layer, forming a recess region including a lower part having a first width and an upper part having a second width by recessing the etch stop layer and the molding layer, and forming a layer of variable resistance material in the recess region.07-08-2010
20100173478CONCENTRIC GATE NANOTUBE TRANSISTOR DEVICES - Single-walled carbon nanotube transistor devices, and associated methods of making such devices include a porous structure for the single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another material. Electrodes for source and drain of a transistor are provided at opposite ends of the single-walled carbon nanotube devices. A concentric gate surrounds at least a portion of a nanotube in a pore. A transistor of the invention may be especially suited for power transistor or power amplifier applications.07-08-2010
20120171851Patterned Substrate for Hetero-epitaxial Growth of Group-III Nitride Film - A circuit structure includes a substrate and a film over the substrate and including a plurality of portions allocated as a plurality of rows. Each of the plurality of rows of the plurality of portions includes a plurality of convex portions and a plurality of concave portions. In each of the plurality of rows, the plurality of convex portions and the plurality of concave portions are allocated in an alternating pattern.07-05-2012
20120171850SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes the steps of forming a semiconductor layer made of SiC on an SiC substrate, forming a film on the semiconductor layer, and forming a groove in the film. The semiconductor device including a chip having an interlayer insulating film includes a groove formed in the interlayer insulating film to cross the chip.07-05-2012
20120171849APPARATUS FOR FORMING DEPOSITED FILM AND METHOD FOR FORMING DEPOSITED FILM - In order to form a high quality film without causing in-plane nonuniformity in film quality, an apparatus for forming deposited film according to an aspect of the present invention includes: a chamber; a first electrode located in the chamber; a second electrode that is located in the chamber with a predetermined spacing from the first electrode and includes a plurality of supply parts configured to supply material gases; an introduction path connected to the supply parts, through which the material gases are introduced; a heater located in the introduction path; and a cooling mechanism configured to cool the second electrode.07-05-2012
20120171846METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED BIT LINES - A method for fabricating a semiconductor device includes etching a substrate to form trenches that separate active regions, forming an insulation layer having an opening to open a portion of a sidewall of each active region, forming a silicon layer pattern to gap-fill a portion of each trench and cover the opening in the insulation layer, forming a metal layer over the silicon layer pattern, and forming a metal silicide layer as buried bit lines, where the metal silicide layer is formed when the metal layer reacts with the silicon layer pattern.07-05-2012
20120171845CHUCK FOR CHEMICAL VAPOR DEPOSITION SYSTEMS AND RELATED METHODS THEREFOR - The present invention provides chucks having a well that supports rods produced during chemical vapor deposition. The chucks can utilize slats and windows around the well up to which the rod can grow and become supported.07-05-2012
20120220105METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF CLEANING SEMICONDUCTOR SUBSTRATE - A method of manufacturing a semiconductor device includes: holding a semiconductor substrate with a surface inclined with respect to the vertical direction and the horizontal direction; and immersing the semiconductor substrate in a cleaning solution including an acid.08-30-2012
20120214294METHOD FOR MANUFACTURING COMPOUND SEMICONDUCTOR DEVICE AND DETERGENT - A method for manufacturing a compound semiconductor device, the method includes: forming a compound semiconductor laminated structure; removing a part of the compound semiconductor laminated structure, so as to form a concave portion; and cleaning the inside of the concave portion by using a detergent, wherein the detergent contains a base resin compatible with residues present in the concave portion and a solvent.08-23-2012
20120252191GALLIUM NITRIDE SEMICONDUCTOR DEVICE ON SOI AND PROCESS FOR MAKING SAME - Methods and apparatus for producing a gallium nitride semiconductor on insulator structure include: bonding a single crystal silicon layer to a transparent substrate; and growing a single crystal gallium nitride layer on the single crystal silicon layer.10-04-2012
20120252190Plasma Spraying with Mixed Feedstock - The instant invention discloses compositions for source material for a plasma spray gun comprising a Group IV based powder, optionally, a Group IV based liquid, optionally, a gas containing Group IV based gases, optionally a dopant, and a carrier gas, optionally, inert.10-04-2012
20120214293ELECTRODEPOSITING DOPED CIGS THIN FILMS FOR PHOTOVOLTAIC DEVICES - Aspects of the present inventions include an electrodeposition solution for deposition of a thin film that includes a Group VA material, a method of electroplating to deposit a thin film that includes a Group VA material, among others.08-23-2012
20120178244METHOD FOR MAKING EPITAXIAL STRUCTURE - A method for making an epitaxial structure is provided. The method includes the following steps. A substrate is provided. The substrate has an epitaxial growth surface for growing epitaxial layer. A carbon nanotube layer is placed on the epitaxial growth surface. A plurality of epitaxial crystal grains spaced from each other is epitaxially grown on the epitaxial growth surface. Also, the carbon nanotube layer can be further removed.07-12-2012
20120178245METHOD FOR MAKING EPITAXIAL STRUCTURE - A method for making an epitaxial structure is provided. The method includes the following steps. A substrate is provided. The substrate has an epitaxial growth surface for growing epitaxial layer. A first carbon nanotube layer is placed on the epitaxial growth surface. A first epitaxial layer is epitaxially grown on the epitaxial growth surface. A second carbon nanotube layer is placed on the first epitaxial layer. A second epitaxial layer is epitaxially grown on the first epitaxial layer.07-12-2012
20120178241CONDUCTIVE METAL AND DIFFUSION BARRIER SEED COMPOSITIONS, AND METHODS OF USE IN SEMICONDUCTOR AND INTERLEVEL DIELECTRIC SUBSTRATES - A metal seed composition useful in seeding a metal diffusion barrier or conductive metal layer on a semiconductor or dielectric substrate, the composition comprising: a nanoscopic metal component that includes a metal useful as a metal diffusion barrier or conductive metal; an adhesive component for attaching said nanoscopic metal component on said semiconductor or dielectric substrate; and a linker component that links said nanoscopic metal component with said adhesive component. Semiconductor and dielectric substrates coated with the seed compositions, as well as methods for depositing the seed compositions, are also described.07-12-2012
20120178242METHOD FOR MAKING EPITAXIAL STRUCTURE - A method for making epitaxial structure is provided. The method includes providing a substrate having an epitaxial growth surface, placing a carbon nanotube layer on the epitaxial growth surface, and epitaxially growing an epitaxial layer on the epitaxial growth surface. The carbon nanotube layer can be a carbon nanotube film drawn from a carbon nanotube array and including a plurality of successive and oriented carbon nanotubes joined end-to-end by van der Waals attractive force therebetween.07-12-2012
20100273316METHOD FOR FABRICATING SILICON AND/OR GERMANIUM NANOWIRES - The invention relates to a method for fabricating silicon and/or germanium nanowires on a substrate, comprising a step of bringing a precursor comprising silicon and/or a precursor comprising germanium into contact with a compound comprising copper oxide present on the said substrate, by means of which growth of nanowires takes place.10-28-2010
20100273315Thin Film Deposition via Charged Particle-Depleted Plasma Achieved by Magnetic Confinement - A method and apparatus for forming thin film materials via a plasma deposition process in the presence of a magnetic field. A precursor is delivered to a deposition chamber and activated to form a plasma. The plasma may be initiated in the presence of a magnetic field or subjected to a magnetic field after initiation. The plasma includes ionized and neutral species derived from the precursor and the magnetic field manipulates the plasma to effect a reduction in the population of ionized species and an enhancement of the population of neutral species. A thin film material is subsequently formed from the resulting neutral-enriched deposition medium. The method permits formation of thin film materials having a low density of defects. In one embodiment, the thin film material is a photovoltaic material and the suppression of defects leads to an enhancement in photovoltaic efficiency.10-28-2010
20090061600METHOD FOR REUSE OF WAFERS FOR GROWTH OF VERTICALLY-ALIGNED WIRE ARRAYS - Reusing a Si wafer for the formation of wire arrays by transferring the wire arrays to a polymer matrix, reusing a patterned oxide for several array growths, and finally polishing and reoxidizing the wafer surface and reapplying the patterned oxide.03-05-2009
20100291758Thin-Film Devices Formed From Solid Particles - Methods and devices are provided for forming thin-films from solid group IIIA-based particles. In one embodiment of the present invention, a method is described comprising of providing a first material comprising an alloy of a) a group IIIA-based material and b) at least one other material. The material may be included in an amount sufficient so that no liquid phase of the alloy is present within the first material in a temperature range between room temperature and a deposition or pre-deposition temperature higher than room temperature, wherein the group IIIA-based material is otherwise liquid in that temperature range. The other material may be a group IA material. A precursor material may be formulated comprising a) particles of the first material and b) particles containing at least one element from the group consisting of: group IB, IIIA, VIA element, alloys containing any of the foregoing elements, or combinations thereof. The temperature range described above may be between about 20° C. and about 200° C. It should be understood that the alloy may have a higher melting temperature than a melting temperature of the IIIA-based material in elemental form.11-18-2010
20100291759COMPLEXES OF CARBON NANOTUBES AND FULLERENES WITH MOLECULAR-CLIPS AND USE THEREOF - Separation of carbon nanotubes or fullerenes according to diameter through non-covalent pi-pi interaction with molecular clips is provided. Molecular clips are prepared by Diels-Alder reaction of polyacenes with a variety of dienophiles. The pi-pi complexes of carbon nanotubes with molecular clips are also used for selective placement of carbon nanotubes and fullerenes on substrates.11-18-2010
20120225541Nitride Semiconductor Structure - A structure method for producing same provides suppressed lattice defects when epitaxially forming nitride layers over non-c-plane oriented layers, such as a semi-polar oriented template layer or substrate. A patterned mask with “window” openings, or trenches formed in the substrate with appropriate vertical dimensions, such as the product of the window width times the cotangent of the angle between the surface normal and the c-axis direction, provides significant blocking of all diagonally running defects during growth. In addition, inclined posts of appropriate height and spacing provide a blocking barrier to vertically running defects is created. When used in conjunction with the aforementioned aspects of mask windows or trenches, the post structure provides significant blocking of both vertically and diagonally running defects during growth.09-06-2012
20120083101SYSTEMS AND METHODS FOR FORMING SEMICONDUCTOR MATERIALS BY ATOMIC LAYER DEPOSITION - Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.04-05-2012
20120258581MOCVD FABRICATION OF GROUP III-NITRIDE MATERIALS USING IN-SITU GENERATED HYDRAZINE OR FRAGMENTS THERE FROM - The metal-organic chemical vapor deposition (MOCVD) fabrication of group III-nitride materials using in-situ generated hydrazine or fragments there from is described. For example, a method of fabricating a group III-nitride material includes forming hydrazine in an in-situ process. The hydrazine, or fragments there from, is reacted with a group III precursor in a metal-organic chemical vapor deposition (MOCVD) chamber. From the reacting, a group III-nitride layer is formed above a substrate.10-11-2012
20120258580PLASMA-ASSISTED MOCVD FABRICATION OF P-TYPE GROUP III-NITRIDE MATERIALS - The plasma-assisted metal-organic chemical vapor deposition (MOCVD) fabrication of a p-type group III-nitride material is described. For example, a method of fabricating a p-type group III-nitride material includes generating a nitrogen-based plasma. A nitrogen-containing species from the nitrogen-based plasma is reacted with a group III precursor and a p-type dopant precursor in a metal-organic chemical vapor deposition (MOCVD) chamber. A group III-nitride layer including p-type dopants is then formed above a substrate.10-11-2012
20100203711Trench Formation Method For Releasing A Thin-Film Substrate From A Reusable Semiconductor Template - A method is provided for fabricating a thin-film semiconductor substrate by forming a porous semiconductor layer conformally on a reusable semiconductor template and then forming a thin-film semiconductor substrate conformally on the porous semiconductor layer. An inner trench having a depth less than the thickness of the thin-film semiconductor substrate is formed on the thin-film semiconductor substrate. An outer trench providing access to the porous semiconductor layer is formed on the thin-film semiconductor substrate and is positioned between the inner trench and the edge of the thin-film semiconductor substrate. The thin-film semiconductor substrate is then released from the reusable semiconductor template.08-12-2010
20120231611DIHALIDE GERMANIUM(II) PRECURSORS FOR GERMANIUM-CONTAINING FILM DEPOSITIONS - Disclosed are GeX09-13-2012
20120231612METHOD FOR MANUFACTURING SILICON EPITAXIAL WAFER - A method for manufacturing a silicon epitaxial wafer, including vapor-phase growing a silicon single crystal thin film on a silicon single crystal substrate in a hydrogen atmosphere while supplying a source gas; and cooling a silicon epitaxial wafer having the formed silicon single crystal thin film by calculating a temperature at which a standard value or a process average value of concentration of an evaluation target impurity present in the silicon single crystal thin film coincides with solubility limit concentration of the evaluation target impurity and setting a cooling rate of the silicon epitaxial wafer after the film formation to be less than 20° C./sec in a temperature range of at least plus or minus 50° C. from the calculated temperature.09-13-2012
20120231610VAPOR-PHASE GROWING APPARATUS AND VAPOR-PHASE GROWING METHOD - According to one embodiment, a vapor-phase growing apparatus, includes: a reactor containing a plurality of gas introduction portions and a gas reaction portion located below the gas introduction portions; a susceptor, of which a surface is exposed in an interior space of the gas reaction portion of the reactor, for disposing and fixing a substrate on the surface thereof; a gas distributor provided between the gas introduction portions and the gas reaction portion of the reactor; a plurality of gas inlet conduits which are connected with the gas introduction portions, respectively; and a switching device, which is provided in an outside of the reactor, for switching gases to be supplied to the gas inlet conduits, respectively.09-13-2012
20120231609VAPOR-PHASE GROWING APPARATUS AND VAPOR-PHASE GROWING METHOD - According to one embodiment, a vapor-phase growing apparatus, includes: a reactor containing a gas introduction portion and a gas reaction portion continued from the gas introduction portion; a susceptor, of which a surface is exposed in an interior space of the gas reaction portion of the reactor, for disposing and fixing a substrate on the surface thereof; a plurality of gas inlet conduits which are arranged subsequently along a direction of height of the reactor in the gas introduction portion of the reactor; and a switching device, which is provided in an outside of the reactor, for switching gases to be supplied to the gas inlet conduits, respectively.09-13-2012
20100330781SUBSTRATE PROCESSING APPARATUS , METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SUBSTRATE - There are provided a substrate processing apparatus, a method of manufacturing a semiconductor device, and a method of manufacturing a substrate, for growing a SiC epitaxial film at a high-temperature condition. The substrate processing apparatus comprises: a reaction chamber; a first gas supply system configured to supply at least a gas containing silicon atoms and a gas containing chlorine atoms, or a gas containing silicon and chlorine atoms; a second gas supply system configured to supply at least a reducing gas; a third gas supply system configured to supply at least a gas containing carbon atoms; a first gas supply nozzle connected to the first gas supply system or the first and third gas supply systems; a second gas supply nozzle connected to the second gas supply system or the second and third gas supply systems; and a controller configured to control the first to third gas supply systems.12-30-2010
20100203710Method of manufacturing a semiconductor device - A method of manufacturing a semiconductor device by thinning a substrate by grinding, and performing ion implantation. In a diode in which a P anode layer and an anode electrode are formed at a side of a right face of an N08-12-2010
20100203709DEPOSITION OF CHALCOGENIDE MATERIALS VIA VAPORIZATION PROCESS - A method of depositing a chalcogenide material. The method includes forming a condensed phase chalcogenide source material on a deposition surface, capping the deposition surface, vaporizing the chalcogenide source material, and subsequently forming a product chalcogenide material on the deposition surface by condensing the vapor. Vaporization may occur via sublimation or evaporation and the condensed phase chalcogenide source material may be a solid-phase source material or a liquid-phase source material. The sublimation-condensation process achieves a spatial redistribution of chalcogenide material on the deposition surface. The deposition surface may include a patterned feature such as a hole, trench or other opening, where the spatial redistribution afforded by the method provides more conformal coverage or more uniform filling of the feature. The composition of the redistributed product chalcogenide material closely corresponds to the composition of the chalcogenide source material.08-12-2010
20110003463DOPING METHOD - Methods of doping a III-V compound semiconductor film are disclosed.01-06-2011
20110039400METHOD FOR FABRICATING GaNAsSb SEMICONDUCTOR - Disclosed is a method for fabrication of a semiconductor of gallium nitride arsenide antimonide (GaNAsSb) on a substrate wherein the fabrication is performed at a fabrication temperature followed by annealing at an annealing temperature for an annealing time; wherein at least one of:02-17-2011
20110039399MANUFACTURING APPARATUS AND METHOD FOR SEMICONDUCTOR DEVICE - A manufacturing apparatus for a semiconductor device includes: a chamber configured to load a wafer into the chamber; a gas supplying mechanism configured to supply processed gas into the chamber; a gas discharging mechanism configured to discharge the gas from the chamber; a wafer supporting member configured to mount the wafer; a heater including a heater element configured to heat the wafer up to a predetermined temperature and a heater electrode molded integrally with the heater element; an electrode part connected to the heater electrode and configured to applied a voltage to the heater element via the heater electrode; a base configured to fix the electrode part; and a rotational drive control mechanism configured to rotate the wafer; wherein at least a part of a connection portion of the heater electrode and the electrode part is positioned under the upper surface of the base.02-17-2011
20110045660Large-Area Nanoenabled Macroelectronic Substrates and Uses Therefor - A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.02-24-2011
20110045659SEMICONDUCTOR BUFFER ARCHITECTURE FOR III-V DEVICES ON SILICON SUBSTRATES - A composite buffer architecture for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×1002-24-2011
20110045658METHOD FOR FABRICATING A SEMI-POLAR NITRIDE SEMICONDUCTOR - A method for fabricating a semi-polar nitride semiconductor is disclosed, comprising following steps: firstly, a (001) substrate tilted at 7 degrees and having a plurality of V-like grooves is provided, and tilted surfaces of the V-like groove are a (111) surface at 61.7 degrees and a ( 02-24-2011
20120270382METHOD OF FABRICATING AN EPITAXIAL LAYER - A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C.10-25-2012
20110212601Stress-Enhanced Performance Of A Finfet Using Surface/Channel Orientations And Strained Capping Layers - Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs.09-01-2011
20110237054PLANAR NONPOLAR GROUP III-NITRIDE FILMS GROWN ON MISCUT SUBSTRATES - A nonpolar III-nitride film grown on a miscut angle of a substrate. The miscut angle towards the <000-1> direction is 0.75° or greater miscut and less than 27° miscut towards the <000-1> direction. Surface undulations are suppressed and may comprise faceted pyramids. A device fabricated using the film is also disclosed. A nonpolar III-nitride film having a smooth surface morphology fabricated using a method comprising selecting a miscut angle of a substrate upon which the nonpolar III-nitride films are grown in order to suppress surface undulations of the nonpolar III-nitride films. A nonpolar III-nitride-based device grown on a film having a smooth surface morphology grown on a miscut angle of a substrate which the nonpolar III-nitride films are grown. The miscut angle may also be selected to achieve long wavelength light emission from the nonpolar film.09-29-2011
20110237052METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to an embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming an epitaxial crystal from a seed crystal exposed between first and second structures; heating the epitaxial crystal at a temperature equal to or less than a melting point of the epitaxial crystal to migrate the epitaxial crystal; and migrating the epitaxial crystal to form plural aggregates between the first and second structures.09-29-2011
20110237051PROCESS AND APPARATUS FOR DEPOSITION OF MULTICOMPONENT SEMICONDUCTOR LAYERS - A deposition process involves the formation of multicomponent semiconductor layers, in particular III-V epitaxial layers, on a substrate. Due to pyrolytic decomposition inside the reaction chamber, one of the process gases forms a first decomposition product. Together with a second decomposition product of a second process gas, the decomposition products form a layer on the surface of a heated substrate and also adhere to surfaces of the process chamber. To remove these adherences, during an etching step a purge gas containing a reactive substance formed by free radicals is introduced into the process chamber. The etching step may be performed before or after the deposition process.09-29-2011
20120129322COMPOSITE MATERIAL COMPRISING NANOPARTICLES AND PRODUCTION OF PHOTOACTIVE LAYERS CONTAINING QUATERNARY, PENTANARY AND HIGHER-ORDER COMPOSITE SEMICONDUCTOR NANOPARTICLES - A composite material includes at least two components, wherein at least one component is present in the form of nanoparticles, which consist of at least three metals and at least one non-metal and the diameter of which is less than one micrometre, preferably less than 200 nm. The novel composite material is particularly well suited for the production of photoactive layers.05-24-2012
20120276719METHODS OF FORMING SEMICONDUCTOR MEMORY DEVICES HAVING VERTICALLY STACKED MEMORY CELLS THEREIN - Methods of forming vertical nonvolatile memory devices utilize carbon-blocking sacrificial capping layers to increase device yield by reducing the likelihood that one or more vertically-stacked layers of materials will lift-off during fabrication. These capping layers may be provided to cover carbon-containing sacrificial layers that are highly polymerized.11-01-2012
20120276720CONTROL OF THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACK AND STRUCTURES FOR CMOS DEVICES - A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the diffusion barrier layer, and a conductive electrode layer formed above the high-k dielectric layer.11-01-2012
20100233870Method of fabricating group III nitride semiconductor single crystal, and method of fabricating group III nitride semiconductor single crystal substrate - A method of fabricating a group III nitride semiconductor single crystal includes preparing a seed substrate which includes group III nitride semiconductor and has a crystal growth face of single index plane, and epitaxially growing the group III nitride semiconductor single crystal on the crystal growth face, wherein the group III nitride semiconductor single crystal is epitaxially grown while being surrounded by a plurality of crystal surfaces including low-index planes spontaneously formed, and the low-index planes have a structure that each of plane indices showing a crystal plane is not more than 3.09-16-2010
20120322244METHOD FOR CONTROLLED REMOVAL OF A SEMICONDUCTOR DEVICE LAYER FROM A BASE SUBSTRATE - A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.12-20-2012
20120322245METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - A method of manufacturing a nitride semiconductor device includes: forming a high-resistance buffer layer made of a nitride semiconductor having a carbon concentration of at least 1012-20-2012
20110263098HYBRID DEPOSITION CHAMBER FOR IN-SITU FORMATION OF GROUP IV SEMICONDUCTORS & COMPOUNDS WITH GROUP III-NITRIDES - Hybrid MOCVD or HVPE epitaxial system for in-situ epitaxially growth of group III-nitride layers and group IV semiconductor layers and/or group IV compounds. A hybrid deposition chamber is coupled to each of a first and second precursor delivery system to grow both a transition film comprising either group IV semiconductor or group IV compound and a film comprising a group III-nitride on the transition film. In one embodiment, the first precursor delivery system is coupled to both a silicon precursor and a second group IV precursor while the second precursor delivery system is coupled to a metalorganic precursor. In embodiments, a layer comprising a silicon semiconductor is deposited over a substrate and a group III-nitride epitaxial film is then deposited in-situ over the substrate.10-27-2011
20120329254Method for Forming Antimony-Based FETs Monolithically - An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.12-27-2012
20120329253METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention relates to a method of manufacturing a semiconductor device by which the length of nanowires perpendicularly formed can be fabricated with high reproducibility. The method of manufacturing a semiconductor device includes the steps of forming a first layer; forming a stop layer on the first layer, the stop layer having a higher Young's modulus than the first layer; forming a recess by partially removing the first layer and the stop layer; growing nanowires in the recess; forming a planarizing layer; removing the planarizing layer to the level of the stop layer to expose the nanowires from the surface of the planarizing layer; and forming an electrode so as to be in contact with the upper ends of the nanowires.12-27-2012
20120329251DOPED ELONGATED SEMICONDUCTORS, GROWING SUCH SEMICONDUCTORS, DEVICES INCLUDING SUCH SEMICONDUCTORS AND FABRICATING SUCH DEVICES - A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and may have, at any point along a longitudinal section of such a semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be a single crystal and may be free-standing. Such a semiconductor may be either lightly n-doped, heavily n-doped, lightly p-doped or heavily p-doped. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and a variety of assembling techniques may be used to fabricate devices from such a semiconductor. Two or more of such a semiconductors, including an array of such semiconductors, may be combined to form devices, for example, to form a crossed p-n junction of a device. Such devices at certain sizes may exhibit quantum confinement and other quantum phenomena, and the wavelength of light emitted from one or more of such semiconductors may be controlled by selecting a width of such semiconductors. Such semiconductors and device made therefrom may be used for a variety of applications.12-27-2012
20120329252SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include a semiconductor substrate with an active region, a gate line disposed on the active region, an epitaxial pattern disposed on the semiconductor substrate beside the gate line, the epitaxial pattern including a semiconductor material different from the semiconductor substrate, and a capping pattern disposed on the epitaxial pattern. The capping pattern may improve contact with contact plug and may reduce variation in mean ion depths of an associated field effect transistor.12-27-2012
20120100701METHOD FOR CLEANING SILICON WAFER, AND METHOD FOR PRODUCING EPITAXIAL WAFER USING THE CLEANING METHOD - A silicon wafer after being subjected to mirror polishing but before being subjected to form an epitaxial layer thereon is subjected to an ozone gas treatment that oxidizes a surface of the silicon wafer by use of ozone gas, a hydrofluoric acid gas treatment that dissolves and removes the oxidized surface of the silicon wafer by use of hydrofluoric acid gas, and a washing treatment that removes foreign substances remaining on the surface of the silicon wafer, whereby PIDs (Polishing Induced Defects) generated by the mirror polishing are forcedly oxidized, dissolved and removed. By performing epitaxial treatment thereafter, PID-induced convex defects can be prevented from generating on the surface of the epitaxial wafer.04-26-2012
20120100700METHOD FOR FABRICATING NON-VOLATILE MEMORY DEVICE - A method for fabricating a non-volatile memory device includes repeatedly stacking interlayer dielectric layers and gate conductive layers on a substrate; etching the interlayer dielectric layers and the gate conductive layers to form cell channel holes that expose the substrate, forming a protective layer along a resultant structure, forming a capping layer on the protective layer to fill the cell channel holes, planarizing the protective layer and the capping layer until an uppermost one of the interlayer dielectric layers is exposed, forming a gate conductive layer for select transistors and an interlayer dielectric layer for select transistors on a resultant structure, etching the interlayer dielectric layer and the gate conductive layer, to form select transistor channel holes that expose the capping layer while removing the capping layer buried in the cell channel holes, and removing the protective layer.04-26-2012
20120100699METHODS OF MAKING QUANTUM DOT FILMS - In an example embodiment, an optical device includes an integrated circuit, an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region. In another example embodiment, a method of forming a nanocrystalline film includes fabricating nanocrystals having a plurality of first ligands attached to their outer surfaces, exchanging the first ligands for second ligands of a different chemical composition, forming a film of the ligand-exchanged nanocrystals, removing the second ligands, and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals. In another example embodiment, a film includes a network of fused nanocrystals with at least portions of the fused nanocrystals being in direct physical contact with adjacent nanocrystals, the film having substantially no defect states in regions where cores of the nanocrystals are fused.04-26-2012
20120100698METHOD FOR FORMING AN ALUMINUM NITRIDE THIN FILM - The method is adapted for forming an aluminum nitride thin film having a high density and a high resistance to thermal shock by a chemical vapor deposition process and includes steps of mixing a gas containing aluminum atoms (Al) and a gas containing nitrogen atoms (N) with a gas containing oxygen atoms (O) and feeding the mixture to a member to be covered by an aluminum nitride thin film.04-26-2012
20100178754METHOD OF MANUFACTURING CMOS TRANSISTOR - A method of manufacturing a complementary metal-oxide semiconductor (CMOS) transistor includes: forming a semiconductor layer in which an n-MOS transistor region and a p-MOS transistor region are defined; forming an insulation layer on the semiconductor layer; forming a conductive layer on the insulation layer; forming a mask pattern exposing the n-MOS transistor region, on the conductive layer; generating a damage region in an upper portion of the conductive layer by implanting impurities in the conductive layer of the n-MOS transistor region using the mask pattern as a mask; removing the mask pattern; removing the damage region; and patterning the conductive layer to form an n-MOS transistor gate and a p-MOS transistor gate. Accordingly, gate thinning and formation of a step between the n-MOS transistor region gate and the p-MOS transistor region gate can be prevented.07-15-2010
20100167504Methods of Fabricating Nanostructures - A method is shown for fabricating nanostructures, and more particularly, to methods of fabricating silicon nanowires. The method of manufacturing a nanowire includes forming a sandwich structure of SiX material and material Si over a substrate and etching the sandwich structure to expose sidewalls of the Si material and the SiX material. The method further includes etching the SiX material to expose portions of the Si material and etching the exposed portions of the Si material. The method also includes breaking away the Si material to form silicon nanowires.07-01-2010
20100167503Methods and systems of transferring, docking and processing substrates - In accordance with some embodiments described herein, a method for transferring a substrate to two or more process modules is provided, comprising loading at least one substrate into one or more mobile transverse chambers, the mobile transverse chambers being carried on a rail positioned adjacent to the two or more process modules, and wherein each mobile transverse chamber is configured to maintain a specified gas condition during conveyance of the substrate. One or more drive systems are actuated to propel at least one of the one or more mobile transverse chambers along the rail. The at least one mobile transfer chamber docks to at least one of the process modules, and the substrate is conveyed from the mobile transverse chamber to the at least one process modules.07-01-2010
20130012003METHODS FOR DEPOSITING THIN FILMS COMPRISING GALLIUM NITRIDE BY ATOMIC LAYER DEPOSITION - Atomic layer deposition (ALD) processes for forming thin films comprising GaN are provided. In some embodiments, ALD processes for forming doped GaN thin films are provided. The thin films may find use, for example, in light-emitting diodes.01-10-2013
20130012002METHOD FOR PRODUCING SEMICONDUCTOR OPTICAL INTEGRATED DEVICE - A method for producing a semiconductor optical integrated device includes the steps of forming a substrate product including first and second stacked semiconductor layer portions; forming a first mask on the first and second stacked semiconductor layer portions, the first mask including a stripe-shaped first pattern region and a second pattern region, the second pattern region including a first end edge; forming a stripe-shaped mesa structure; removing the second pattern region of the first mask; forming a second mask on the second stacked semiconductor layer portion; and selectively growing a buried semiconductor layer with the first and second masks. The second mask includes a second end edge separated from the first end edge of the first mask, the second end edge being located on the side of the second stacked semiconductor layer portion in the predetermined direction with respect to the first end edge of the first mask.01-10-2013
20130012004MANUFACTURING METHOD OF SEMICONDUCTOR SUBSTRATE - A manufacturing method of a semiconductor substrate includes: forming a trench in a semiconductor board by a dry etching method; etching a surface portion of an inner wall of the trench by a chemical etching method so that a first damage layer is removed, wherein the surface portion has a thickness equal to or larger than 50 nanometers; and performing a heat treatment at temperature equal to or higher than 1050° C. in non-oxidizing and non-azotizing gas so that crystallinity of a second damage layer is recovered, wherein the second damage layer is disposed under the first damage layer. The crystallinity around the trench is sufficiently recovered01-10-2013
20130012001METHOD FOR PRODUCING SEMICONDUCTOR OPTICAL DEVICE - A method for producing a semiconductor optical device includes the steps of growing a semiconductor stacked layer including an etch stop layer and a plurality of semiconductor layers on a major surface of a substrate; forming a mask layer on a top surface of the semiconductor stacked layer so that a tip portion of each of protrusions that protrude from the top surface among protrusions generated in the step of growing the semiconductor stacked layer is exposed; etching the protrusion by wet etching using the mask layer; after etching the protrusion by wet etching, removing the protrusion by dry etching; and removing the mask layer from the top surface, after removing the protrusion by dry etching.01-10-2013
20130012005SILICON ON GERMANIUM - A monolayer or partial monolayer sequencing processing, such as atomic layer deposition (ALD), can be used to form a semiconductor structure of a silicon film on a germanium substrate. Such structures may be useful in high performance electronic devices. A structure may be formed by deposition of a thin silicon layer on a germanium substrate surface, forming a hafnium oxide dielectric layer, and forming a tantalum nitride electrode. The properties of the dielectric may be varied by replacing the hafnium oxide with another dielectric such as zirconium oxide or titanium oxide.01-10-2013
20100129990SUSCEPTOR AND METHOD FOR MANUFACTURING SILICON EPITAXIAL WAFER - Provided is a susceptor 05-27-2010
20120149179METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a method of manufacturing a semiconductor device which, in the case where an InP-based device is formed with a sacrificial layer in between, is capable of obtaining better device characteristics than those in the case where an AlAs single layer is used as the sacrificial layer, and which does not have the possibility that the device layer is etched together with the sacrificial layer during etching of the sacrificial layer. A method of manufacturing a semiconductor device includes: a formation step of forming a sacrificial layer which is pseudomorphic to InP on an InP substrate, and then forming an InP-based device layer on the sacrificial layer; and a separation step of separating the InP substrate and the device layer from each other by etching the sacrificial layer.06-14-2012
20120149178Process for Making a Slot-Type Optical Waveguide on Silicon - In a process for fabrication of an optical slot waveguide on silicon, a thin single-crystal silicon film is deposited on a substrate covered with an insulating buried layer; a local thermal oxidation is carried out over the entire depth of the thin single-crystal silicon film in order to form an insulating oxidized strip extending along the desired path of the waveguide; an insulating or semi-insulating layer is deposited on the silicon film; two openings having vertical sidewalls are excavated over the entire thickness of this insulating or semi-insulating layer, said openings being separated by a narrow gap constituting an insulating or semi-insulating vertical wall that will be the material of the slot; single-crystal silicon is grown in the openings and right to the edges of the insulating or semi-insulating wall; and then the upper part of the silicon is etched in order to complete the geometry of the waveguide.06-14-2012
20120149177METHOD OF PRODUCING EPITAXIAL SILICON WAFER - An object of the invention is to provide an epitaxial silicon wafer in higher quality with good flatness and thickness uniformity. The object is achieved by a method characterized in that after an epitaxial film 06-14-2012
20110159667SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method for fabricating a semiconductor device according to the present invention includes the steps of: growing a p-type gallium nitride-based compound semiconductor layer by performing a metalorganic chemical vapor deposition process in a heated atmosphere so that the crystal-growing plane of the semiconductor layer is an m plane (Step S06-30-2011
20110159666DEPOSITION SYSTEMS AND METHODS - Systems, methods, and products made by a deposition process are shown and described. A work piece is supported in a main deposition chamber so that the work piece is positioned above each container of deposition material as the container is moved into and out of the deposition chamber. One or more containers are sequentially moved from each of a plurality of auxiliary chambers into and out of the deposition chamber so as to deposit material from each of the containers onto the work piece in a sequential manner.06-30-2011
20130178048METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING BURIED WIRING AND RELATED DEVICE - According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes forming a sacrificial pattern having SiGe on a crystalline silicon substrate. A body having crystalline silicon is formed on the sacrificial pattern. At least one active element is formed on the body. An insulating layer is formed to cover the sacrificial pattern, the body, and the active element. A contact hole is formed to expose the sacrificial pattern through the insulating layer. A void space is formed by removing the sacrificial pattern. An amorphous silicon layer is formed in the contact hole and the void space. The amorphous silicon layer is transformed into a metal silicide layer.07-11-2013
20130171805GaN Epitaxy With Migration Enhancement and Surface Energy Modification - Methods and apparatus for depositing thin films incorporating the use of a surfactant are described. Methods and apparatuses include a deposition process and system comprising multiple isolated processing regions which enables rapid repetition of sub-monolayer deposition of thin films. The use of surfactants allows the deposition of high quality epitaxial films at lower temperatures having low values of surface roughness. The deposition of Group III-V thin films such as GaN is used as an example.07-04-2013
20130171806THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.07-04-2013
20080220593Nanoparticles - Method for producing a nanoparticle comprised of core, first shell and second shell semiconductor materials. Effecting conversion of a core precursor composition comprising separate first and second precursor species to the core material and then depositing said first and second shells. The conversion is effected in the presence of a molecular cluster compound under conditions permitting seeding and growth of the nanoparticle core. Core/multishell nanoparticles in which at least two of the core, first shell and second shell materials incorporate ions from groups 12 and 15, 14 and 16, or 11, 13 and 16 of the periodic table. Core/multishell nanoparticles in which the second shell material incorporates at least two different group 12 ions and group 16 ions. Core/multishell nanoparticles in which at least one of the core, first and second semiconductor materials incorporates group 11, 13 and 16 ions and the other semiconductor material does not incorporate group 11, 13 and 16 ions.09-11-2008
20130178047Highly Luminescent II-V Semiconductor Nanocrystals - A population of semiconductor nanocrystals can include cores including a II-V semiconductor material, e.g., Cd07-11-2013
20130137244METHOD AND APPARATUS FOR RECONDITIONING A CARRIER WAFER FOR REUSE - The disclosed subject matter pertains to deposition of thin film or thin foil materials in general, but more specifically to deposition of epitaxial monocrystalline or quasi-monocrystalline silicon film (epi film) for use in manufacturing of high efficiency solar cells. In operation, methods are disclosed which extend the reusable life and to reduce the amortized cost of a reusable substrate or template used in the manufacturing process of silicon and other semiconductor solar cells.05-30-2013
20110269297METHOD FOR SYNTHESISING SEMICONDUCTOR QUANTUM DOTS - The invention can be used for producing different luminescent materials and as a basis for producing subminiature light-emitting diodes, white light sources, single-electron transistors, nonlinear optical devices and photosensitive and photovoltaic devices. The inventive method for producing semiconductor quantum dots involves synthesizing nanocrystal nuclei from a chalcogen-containing precursor and a precursor containing a group II or IV metal using an organic solvent and a surface modifier. The method is characterized in that (aminoalkyl)trialkoxysilanes are used as the surface modifier , core synthesis is carried out at a permanent temperature ranging from 150 to 250 C for 15 seconds to 1 hour and in that the reaction mixture containing the nanoclystal is additionally treated by UV-light for 1-10 minutes and by ultrasound for 5-15 minutes. The invention makes it possible to increase the photostability of semiconductor quantum dots up to 34% and the capacity thereof to be dispersed in both non-polar and polar solvents, so that the quantum yields are preserved and increased.11-03-2011
20130095641Method Of Manufacturing Gallium Nitride Film - A method of manufacturing a gallium nitride (GaN) film in which defects in a GaN film that grows can be reduced. The method includes the step of growing a GaN nano-rod on a substrate, the nano-rod having a circumferential groove in an outer periphery thereof, and the step of growing a GaN film on the GaN nano-rod.04-18-2013
20130095640REUSABLE SUBSTRATES FOR ELECTRONIC DEVICE FABRICATION AND METHODS THEREOF - Substrates for electronic device fabrication and methods thereof. A reusable substrate with at least a plurality of grooves for electronic device fabrication includes a substrate body made of one or more substrate materials and including a top planar surface, the top planar surface being divided into a plurality of planer regions by the plurality of grooves, the plurality of grooves including a plurality of bottom planar surfaces. Each of the plurality of grooves includes a bottom planar surface and two side surfaces, the bottom planar surface being selected from the plurality of bottom planar surfaces, the two side surfaces being in contact with the top surface and the bottom surface. The bottom planar surface is associated with a groove width from one of the two side surfaces to the other of the two side surfaces, the groove width ranging from 0.1 μm to 5 mm.04-18-2013
20130115758METHOD FOR MANUFACTURING SILICON CARBIDE SCHOTTKY BARRIER DIODE - The present invention provides a method for manufacturing a silicon carbide Schottky barrier diode. In the method, an n− epitaxial layer is deposited on an n+ substrate. A sacrificial oxide film is formed on the n− epitaxial layer by heat treatment, and then a portion where a composite oxide film is to be formed is exposed by etching. Nitrogen is implanted into the n− epitaxial layer and the sacrificial oxide film using nitrogen plasma. A silicon nitride is deposited on the n− epitaxial layer and the sacrificial oxide film. The silicon nitride is thermally oxidized to form a composite oxide film. An oxide film in a portion where a Schottky metal is to be deposited is etched, and then the Schottky metal is deposited, thereby forming a silicon carbide Schottky barrier diode.05-09-2013
20130102130BULK FIN-FIELD EFFECT TRANSISTORS WITH WELL DEFINED ISOLATION - A fin field-effect-transistor fabricated by forming a dummy fin structure on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. The dielectric layer surrounds the dummy fin structure. The dummy fin structure is removed to form a cavity within the dielectric layer. The cavity exposes a portion of the semiconductor substrate thereby forming an exposed portion of the semiconductor substrate within the cavity. A dopant is implanted into the exposed portion of the semiconductor substrate within the cavity thereby creating a dopant implanted exposed portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate.04-25-2013
201301021352DEG SCHOTTKY DIODE FORMED IN NITRIDE MATERIAL WITH A COMPOSITE SCHOTTKY/OHMIC ELECTRODE STRUCTURE AND METHOD OF MAKING THE SAME - A method for manufacturing a semiconductor device includes preparing a base substrate; forming a semiconductor layer on the base substrate; forming an ohmic electrode part having ohmic electrode lines, on the semiconductor layer; and forming a Schottky electrode part, which is disposed on the semiconductor layer to be spaced apart from the ohmic electrode lines and has Schottky electrode lines parallel to the ohmic electrode lines, wherein forming the ohmic electrode part further comprises forming an ohmic electrode plate connected to one end of the ohmic electrode lines, forming the Schottky electrode part further comprises forming a Schottky electrode plate connected one end of the Schottky electrode lines, and one line of the Schottky electrode lines is disposed between two of the ohmic electrode lines to thereby achieve an interdigited configuration in which the ohmic electrode part and the Schottky electrode part are formed.04-25-2013
20130102132METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS AND RECORDING MEDIUM - A method of manufacturing a semiconductor device includes: accommodating a substrate in a processing chamber; and supplying an organosilicon-based gas into the processing chamber that is heated to form a film including silicon and carbon on the substrate. In the forming of the film including silicon and carbon, a cycle is performed a predetermined number of times. The cycle includes supplying the organosilicon-based gas into the processing chamber and confining the organosilicon-based gas in the processing chamber, maintaining a state in which the organosilicon-based gas is confined in the processing chamber, and exhausting an inside of the processing chamber.04-25-2013
20130102134METHOD FOR PRODUCING SILICON NANOWIRE DEVICES - The invention provides a method for producing silicon nanowire devices, including the following steps: growing SiNW on a substrate; depositing an amorphous carbon layer and dielectric anti-reflectivity coating orderly; removing part of dielectric anti-reflectivity coating and amorphous carbon layer above the SiNW through dry etching to expose the SiNW device area; depositing an oxide film on the surface of the above structure; forming a metal pad connected with the SiNW in the SiNW device area; depositing a passivation layer on the surface of the above structure; applying photolithography and etching technology to form contact holes on the metal pad and to remove the passivation layer, the oxide film and the dielectric anti-reflectivity coating above the SiNW outside the device area, stopping on the amorphous carbon layer; removing the amorphous carbon layer above the SiNW outside the device area through ashing process to expose the SiNW.04-25-2013
20130102133METHOD AND APPARATUS FOR FABRICATING SILICON HETEROJUNCTION SOLAR CELLS - A method for fabricating a semiconductor layer within a plasma enhanced chemical vapor deposition (PECVD) apparatus. The PECVD apparatus includes a plurality of walls defining a processing region, a substrate support, a shadow frame, a gas distribution showerhead, a gas source in fluid communication with the gas distribution showerhead and the processing region, a radio frequency power source coupled to the gas distribution showerhead, and one or more VHF grounding straps electrically coupled to at least one of the plurality of walls. The VHF grounding straps provide a low-impedance current path between at least one of the plurality of walls and at least one of a shadow frame or the substrate support. The method further includes delivering a semiconductor precursor gas and a dopant precursor gas and delivering a very high frequency (VHF) power to generate a plasma to form a first layer on the one or more substrates.04-25-2013
20130102131METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device wherein a film containing Si and Ge is formed on a conducting film over a substrate by using a raw material gas containing Si and a raw material gas containing Ge, includes: forming Si nuclei on the conducting film at a first ratio of a flow rate of the raw material gas containing Ge to a flow rate of the raw material gas containing Si; and forming, on the Si nuclei, a film having Si and Ge at a second ratio of the flow rate of the raw material gas containing Ge to the flow rate of the raw material gas containing Si, the second ratio being greater than the first ratio.04-25-2013
20130115759Methods of Fabricating Semiconductor Devices - Provided are methods of fabricating a semiconductor device that include providing a substrate that includes a first region having a gate pattern and a second region having a first trench and an insulating layer that fills the first trench. A portion of a sidewall of the first trench is exposed by etching part of the insulating layer and a first spacer is formed on a sidewall of the gate pattern. A second spacer is formed on the exposed sidewall of the first trench, wherein the first spacer and the second spacer are formed simultaneously.05-09-2013
20130122691METHOD FOR MAKING SEMICONDUCTOR STRUCTURE - A method for forming a semiconductor structure is provided. First, multiple recesses are formed in a substrate. Second, a precursor mixture is provided to form a non-doped epitaxial layer on the inner surface of the recesses. The precursor mixture includes a silicon precursor, an epitaxial material precursor and a hydrogen-halogen compound. The flow rate ratio of the silicon precursor to the epitaxial material precursor is greater than 1.7. Later, a doped epitaxial layer including Si, the epitaxial material and the dopant is formed and substantially fills up the recess.05-16-2013
20130130477METHOD FOR PRODUCING GALLIUM TRICHLORIDE GAS AND METHOD FOR PRODUCING NITRIDE SEMICONDUCTOR CRYSTAL - According to the invention, there is provided a method for producing a gallium trichloride gas, the method including: a first step of reacting a metallic gallium and a chlorine gas to produce a gallium monochloride gas; and a second step of reacting the produced gallium monochloride gas and a chlorine gas to produce a gallium trichloride gas.05-23-2013
20130130476METHOD FOR CLEANING FILM FORMATION APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for cleaning a hot-wall type film formation apparatus having a batch processing system with industrially high mass productivity is provided. In the method, a carbon film deposited on an inner wall or the like of a reaction chamber of the apparatus is removed efficiently in a short time. To remove the carbon film deposited on the inner wall of the reaction chamber by a thermal CVD method, the reaction chamber is heated at a temperature higher than or equal to 700° C. and lower than or equal to 800° C., and oxygen is introduced into the reaction chamber.05-23-2013
20130130475VAPOR TRANSPORT DEPOSITION METHOD AND SYSTEM FOR MATERIAL CO-DEPOSITION - An improved feeder system and method for continuous vapor transport deposition that includes at least two vaporizers couple to a common distributor through an improved seal for separately vaporizing and collecting at least any two vaporizable materials for deposition as a material layer on a substrate. Multiple vaporizer provide redundancy and allow for continuous deposition during vaporizer maintenance and repair.05-23-2013
20130143393APPARATUS FOR MANUFACTURING COMPOUND SEMICONDUCTOR, METHOD FOR MANUFACTURING COMPOUND SEMICONDUCTOR, AND COMPOUND SEMICONDUCTOR - Provided is an apparatus for manufacturing a compound semiconductor, which forms a compound semiconductor layer using a metal-organic chemical vapor deposition method. The apparatus is characterized in that: the apparatus is provided with a reaction container, a holder, which is disposed in the reaction container and has placed thereon a subject, on which the layer is to be formed, the subject having facing up the subject surface where the layer is to be formed, and a raw material supply port, through which the raw material gas of the compound semiconductor is supplied to the inside of the reaction container from the outside; the holder is in contact with the lower surface of the subject, the contact being inside of the outer circumferential portion of the subject to the center of the upper surface of the holder; and that the holder has a supporting portion, which supports the subject such that a predetermined interval is maintained between the upper surface of the holder and the lower surface of the subject. In the manufacture of the compound semiconductor using the MOCVD method, temperature distribution on the substrate surface to be deposited with a compound semiconductor crystal, and deviation of in-plane averaged light emission wavelength from a target value are suppressed using the apparatus.06-06-2013
20130137243SEMICONDUCTOR PROCESS - First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below −30° C.05-30-2013
20130157444SEMICONDUCTOR DEVICE HAVING SUPER JUNCTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a super junction structure includes: multiple first columns extending in a current flowing direction; and multiple second columns extending in the current flowing direction. The first and second columns are alternately arranged in an alternating direction. Each first column provides a drift layer. The first and second columns have a boundary therebetween, from which a depletion layer expands in case of an off-state. At least one of the first columns and the second columns have an impurity dose, which is inhomogeneous by location with respect to the alternating direction.06-20-2013
20110212599METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SUBSTRATE AND SUBSTRATE PROCESSING APPARATUS - Provided is a method of manufacturing a semiconductor device using a substrate processing apparatus including a reaction chamber in which a plurality of substrates are stacked at a predetermined distance; a first gas supply nozzle installed to extend to a region in which the plurality of substrates are stacked; a second gas supply nozzle installed to extend to a different position from a position at which the first gas supply nozzle is installed in the region in which the plurality of substrates are stacked; a first branch nozzle installed at the first gas supply nozzle in a direction parallel to major surfaces of the plurality of substrates, at least one line of which is branched in a direction of the second gas supply nozzle, and including at least one first gas supply port; and a second branch nozzle installed at the second gas supply nozzle in the direction parallel to the major surfaces of the plurality of substrates, at least one line of which is branched in a direction of the first gas supply nozzle, and including at least one second gas supply port; wherein the first gas supply port and the second gas supply port are installed adjacent to each other in a direction that the plurality of substrates are stacked, the method including the steps of: loading the plurality of substrates into the reaction chamber; and forming SiC films by supplying at least a silicon-containing gas and a chlorine-containing gas or a silicon/chlorine-containing gas through the first gas supply port and supplying at least a carbon-containing gas and a reduction gas through the second gas supply port.09-01-2011
20110223745SELF CLEANING LARGE SCALE METHOD AND FURNACE SYSTEM FOR SELENIZATION OF THIN FILM PHOTOVOLTAIC MATERIALS - According to an embodiment, the present invention provide a method for fabricating a copper indium diselenide semiconductor film using a self cleaning furnace. The method includes transferring a plurality of substrates into a furnace, the furnace comprising a processing region and at least one end cap region disengageably coupled to the processing region, each of the plurality of substrates provided in a vertical orientation with respect to a direction of gravity, the plurality of substrates being defined by a number N, where N is greater than 5, each of the substrates having a copper and indium composite structure. The method also includes introducing a gaseous species including a hydrogen species and a selenium species and a carrier gas into the furnace and transferring thermal energy into the furnace to increase a temperature from a first temperature to a second temperature, the second temperature ranging from about 350 Degrees Celsius to about 450 Degrees Celsius to at least initiate formation of a copper indium diselenide film from the copper and indium composite structure on each of the substrates. The method further includes decomposing residual selenide species from an inner region of the process region of the furnace. The method further includes depositing elemental selenium species within a vicinity of the end cap region operable at a third temperature. Also, the method includes maintaining the inner region substantially free from elemental selenium species by at least the decomposition of residual selenide species from the inner region of the process region.09-15-2011
20110230036USE OF CL2 AND/OR HCL DURING SILICON EPITAXIAL FILM FORMATION - In a first aspect, a method of forming an epitaxial film on a substrate is provided. The method includes (a) providing a substrate; (b) exposing the substrate to a silicon source and a carbon source so as to form a carbon-containing silicon epitaxial film; (c) encapsulating the carbon-containing silicon epitaxial film with an encapsulating film; and (d) exposing the substrate to Cl2 so as to etch the encapsulating film. Numerous other aspects are provided.09-22-2011
20130149844METHOD OF GROWING ZINC OXIDE NANOWIRE - Methods of growing a zinc oxide nanowire are provided. According to the method, developing a photoresist layer and etching a zinc oxide seed layer may be successively performed using a tetramethyl ammonium hydroxide aqueous solution. Thus, change of solutions may not be required, such that the number of processes may be reduced.06-13-2013
20130149845n- and p-Channel Field Effect Transistors with Single Quantum Well for Complementary Circuits - A complementary metal oxide semiconductor (CMOS) device in which a single In06-13-2013
20130149846METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - A film is formed on a substrate by performing a cycle at least twice, the cycle including a nucleus formation process for forming nuclei on the substrate and a nucleus growth suppression process for suppressing growth of the nuclei. A time required for the nucleus growth suppression process is less than or equal to a time required for the nucleus formation process. Alternatively, the nucleus formation process is further performed after the cycle is repeatedly performed a plurality of times.06-13-2013
20110237053Method and Apparatus for the Formation of an Electronic Device - A process of forming an electronic device, by forming the source and drain contacts using photolithography, incorporating a self-assembled monolayer (SAM) over the electrical contacts to form an increased work function of the source and drain electrodes and further forming more favorable charge injection properties or within the channel region to improve film morphology and therefore improve charge transport. The SAM material is added to the photoresist stripper during a step of the photolithography process of forming electrical contacts.09-29-2011
20110256694Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect Transistors, Methods of Forming Semiconductor-On-Insulator Substrates, Methods of Forming a Span Comprising Silicon Dioxide, Methods of Cooling Semiconductor Devices, Methods of Forming Electromagnetic Radiation Emitters and Conduits, Methods of Forming Imager Systems, Methods of Forming Nanofluidic Channels, Fluorimetry Methods, and Integrated Circuitry - Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.10-20-2011
20110256692MULTIPLE PRECURSOR CONCENTRIC DELIVERY SHOWERHEAD - A method and apparatus that may be utilized for chemical vapor deposition and/or hydride vapor phase epitaxial (HVPE) deposition are provided. In one embodiment, the apparatus provides a processing chamber that includes a showerhead with separate inlets and channels for delivering separate processing gases into a processing volume of the chamber without mixing the gases prior to entering the processing volume. In one embodiment, a plurality of concentric tube assemblies are disposed within the showerhead to separately deliver a first gas from a first gas channel and a second gas from a second gas channel into the processing volume of the chamber. In one embodiment, the showerhead further includes a heat exchanging channel through which the plurality of concentric tube assemblies is disposed.10-20-2011
20110275199COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An AlN layer (11-10-2011
20110275198FILM WRAPPED NFET NANOWIRE - A semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire. A method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.11-10-2011
20110275197SEMICONDUCTOR MEMORY DEVICE, METHOD OF FORMING THE SAME, AND MEMORY SYSTEM - A method of forming a semiconductor memory device, a semiconductor memory device, and a memory system, the method including forming a thin film structure on a semiconductor substrate such that the thin film structure includes a plurality of thin films; patterning the thin film structure to form a through region in the thin film structure; forming a first silicon film using a first precursor such that the first silicon film covers the through region; and forming a second silicon film on the first silicon film using a second precursor, wherein the first precursor is different from the second precursor.11-10-2011
20110275196Thermal Evaporation Sources with Separate Crucible for Holding the Evaporant Material - One aspect of the invention comprises a thermal evaporation source comprising an evaporant chamber, a heater for providing heat to the evaporation chamber; and a crucible in thermal communication with the evaporation chamber for containing a volume of evaporant. The evaporant chamber comprises a first material of construction, and the crucible comprises a second material of construction different from the first material of construction and having a lesser porosity with respect to the evaporant than the first material of construction. For example, for a copper evaporant, the evaporant chamber may comprise a sintered material, such as sintered graphite, and the crucible may comprise a pyrolytic material, such as pyrolytic graphite or pyrolytic boron nitride.11-10-2011
20120258582METHOD AND APPARATUS FOR SELECTIVELY GROWING DOPED EPITAXIAL FILM - In one embodiment of the present invention, the processing surface of a substrate having at least a single crystal surface and a dielectric surface is exposed to a first deposition gas containing a source gas and a doping gas to form a first doped thin film on the single crystal surface, whereas supply of the first deposition gas is stopped before a film is formed on the dielectric surface. Next, the processing surface of the substrate is exposed to a second deposition gas containing a source gas and a doping gas to form a second thin film doped with less dopant than the first thin film on the single crystal surface, whereas supply of the second deposition gas is stopped before a film is formed on the dielectric surface. Subsequently, the processing surface of the substrate is exposed to a chlorine-containing gas to be etched.10-11-2012
20100297833COMPLEXES OF CARBON NANOTUBES AND FULLERENES WITH MOLECULAR-CLIPS AND USE THEREOF - Separation of carbon nanotubes or fullerenes according to diameter through non-covalent pi-pi interaction with molecular clips is provided. Molecular clips are prepared by Diels-Alder reaction of polyacenes with a variety of dienophiles. The pi-pi complexes of carbon nanotrubes with molecular clips are also used for selective placement of carbon nanotubes and fullerenes on substrates.11-25-2010
20130183814METHOD OF DEPOSITING A SILICON GERMANIUM TIN LAYER ON A SUBSTRATE - Methods of depositing silicon germanium tin (SiGeSn) layer on a substrate are disclosed herein. In some embodiments, a method may include co-flowing a silicon source, a germanium source, and a tin source comprising a tin halide to a process chamber at a temperature of about 450 degrees Celsius or below and a pressure of about 100 Torr or below to deposit the SiGeSn layer on a first surface of the substrate. In some embodiments, the tin halide comprises tin tetrachloride (SnCl07-18-2013
20100317177METHODS FOR FORMING SILICON GERMANIUM LAYERS - Embodiments of methods for depositing silicon germanium (SiGe) layers on a substrate are disclosed herein. In some embodiments, the method may include depositing a first layer comprising silicon and germanium (e.g., a seed layer) atop the substrate using a first precursor comprising silicon and chlorine; and depositing a second layer comprising silicon and germanium (e.g., a bulk layer) atop the silicon germanium seed layer using a second precursor comprising silicon and hydrogen. In some embodiments, the first silicon precursor gas may comprise at least one of dichlorosilane (H12-16-2010
20100317176METHOD AND SYSTEM FOR THE SYNTHESIS OF SEMICONDUCTOR NANOWIRES - The invention provides a system and method for producing semiconductor nanowires, for example germanium or Silicon, grown by solution decomposition comprising the steps of heating at least one high boiling point solvent to its reaction temperature in a chamber and injecting a precursor directly into the chamber to react with the at least one high boiling solvent to produce a refluxing solvent. Subsequent vapour deposition of a monomer, achieved by the refluxing solvent, onto a locally heated substrate contained within the chamber produces the semiconductor nanowires. The system and method removes the dependency upon the incorporation of metal catalyst for the production of silicon and germanium nanowire, thereby nullifying the adverse effects of metal contamination in the resulting semiconductor nanowires.12-16-2010
20100317175METHODS OF MAKING QUANTUM DOT FILMS - Optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit an array of conductive regions; and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a method of forming a nanocrystalline film includes fabricating a plurality of nanocrystals having a plurality of first ligands attached to their outer surfaces; exchanging the first ligands for second ligands of different chemical composition than the first ligands; forming a film of the ligand-exchanged nanocrystals; removing the second ligands; and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused.12-16-2010
20120282758METHOD FOR MAKING SEMI-CONDUCTOR NANOCRYSTALS - A method for making semi-conductor nanocrystals, including at least the steps of: 11-08-2012
20120282761METHOD FOR REUSE OF WAFERS FOR GROWTH OF VERTICALLY-ALIGNED WIRE ARRAYS - Reusing a Si wafer for the formation of wire arrays by transferring the wire arrays to a polymer matrix, reusing a patterned oxide for several array growths, and finally polishing and reoxidizing the wafer surface and reapplying the patterned oxide.11-08-2012
20120282760ENHANCING INTERFACE CHARACTERISTICS BETWEEN A CHANNEL SEMICONDUCTOR ALLOY AND A GATE DIELECTRIC BY AN OXIDATION PROCESS - In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material.11-08-2012
20120282759METHOD FOR MAKING SEMI-CONDUCTOR NANOCRYSTALS ORIENTED ALONG A PREDEFINED DIRECTION - A method for making a semi-conductor nanocrystals, including at least the steps of: 11-08-2012
20130157441METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device fabricating method includes forming an etch target layer and a first hard mask layer over a substrate, forming a second hard mask pattern having lines over the first hard mask layer, forming a third hard mask layer over the second hard mask pattern, forming a sacrificial pattern over the third hard mask layer, forming a cell spacer on sidewalls of the sacrificial pattern, removing the sacrificial pattern, etching the third hard mask layer using the cell spacer as an etch barrier, etching the first hard mask layer using the third hard mask pattern and the second hard mask pattern as etch barriers, forming an elliptical opening having an axis pointing in a second direction by etching the etch target layer, and forming a silicon layer that fills the elliptical opening.06-20-2013
20130157442DEFECT REDUCTION IN SEEDED ALUMINUM NITRIDE CRYSTAL GROWTH - Bulk single crystal of aluminum nitride (AlN) having an areal planar defect density≦100 cm06-20-2013
20130183813METHOD FOR MANUFACTURING OPTICAL SEMICONDUCTOR DEVICE - A method for manufacturing an optical semiconductor device includes a step of forming a stacked semiconductor layer on a substrate, the stacked semiconductor layer including a plurality of semiconductor layers; a step of forming a mask on a top layer of the stacked semiconductor layer, the mask covering a portion of the top layer; an exposing step of exposing the top layer of the stacked semiconductor layer to an oxygen-containing atmosphere; after the exposing step, a heating step of heating the stacked semiconductor layer to a temperature of 250° C. or more; and after the heating step, a step of forming a semiconductor mesa in the stacked semiconductor layer, the semiconductor mesa being formed by etching the stacked semiconductor layer by a dry etching method using the mask. The top layer of the plurality of semiconductor layers of the stacked semiconductor layer contains arsenic.07-18-2013
20110287610Selenium/Group 3A ink and methods of making and using same - A selenium/Group 3a ink, comprising (a) a selenium/Group 3a complex which comprises a combination of, as initial components: a selenium component comprising selenium; a carboxylic acid component having a formula R—COOH, wherein R is selected from a C11-24-2011
20130122693NITRIDE COMPOUND SEMICONDUCTOR ELEMENT AND PRODUCTION METHOD THEREFOR - A nitride compound semiconductor element according to the present invention is a nitride compound semiconductor element including a substrate 05-16-2013
20110306184METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes: forming an epitaxial layer on a semiconductor substrate; forming a capping layer having a first thickness on the epitaxial layer; and oxidizing the capping layer in an oxygen atmosphere to form a first gate dielectric layer having a second thickness.12-15-2011
20110312163Large Area Nanoenabled Macroelectronic Substrates and Uses Therefor - A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.12-22-2011
20110312162 CHEMICAL VAPOUR DEPOSITION SYSTEM AND PROCESS - A chemical vapour deposition system, including: a process tube for receiving at least one sample, the process tube being constructed of silicon carbide, impregnated with silicon, and coated with silicon carbide; a pumping system to evacuate the process tube to high vacuum; one or more gas inlets for introducing one or more process gases into the evacuated process tube; and a heater to heat the process tube and thereby heat the one or more process gases and the at least one sample within the process tube to cause a material to be deposited onto the at least one sample within the process tube by chemical vapour deposition.12-22-2011
20110312161METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A film of an epitaxial layer that allows the reduction in both the height of a bunching step and crystal defects caused by a failure in migration of reactive species on a terrace is formed on a SiC semiconductor substrate having an off angle of 5 degrees or less. A film of a first-layer epitaxial layer is formed on and in contact with a surface of the SiC semiconductor substrate having an off angle of 5 degrees or less. Subsequently, the temperature in a reactor is lowered. A second-layer epitaxial layer is caused to epitaxially grow on and in contact with a surface of the first-layer epitaxial layer. In the above-described manner, the epitaxial layer is structured with two layers, and the growth temperature for the second epitaxial layer is set lower than the growth temperature for the first epitaxial layer.12-22-2011
20110312160Liquid precursor for deposition of copper selenide and method of preparing the same - Liquid precursors containing copper and selenium suitable for deposition on a substrate to form thin films suitable for semiconductor applications are disclosed. Methods of preparing such liquid precursors and methods of depositing a precursor on a substrate are also disclosed.12-22-2011
20110312159Methods of Fabricating Nitride Semiconductor Structures with Interlayer Structures - A semiconductor structure includes a first layer of a nitride semiconductor material, a substantially unstrained nitride interlayer on the first layer of nitride semiconductor material, and a second layer of a nitride semiconductor material on the nitride interlayer. The nitride interlayer has a first lattice constant and may include aluminum and gallium and may be conductively doped with an n-type dopant. The first layer and the second layer together have a thickness of at least about 0.5 μm. The nitride semiconductor material may have a second lattice constant, such that the first layer may be more tensile strained on one side of the nitride interlayer than the second layer may be on the other side of the nitride interlayer.12-22-2011
20120289031COMPOUND SEMICONDUCTOR GROWTH USING ION IMPLANTATION - A workpiece is implanted to affect growth of a compound semiconductor, such as GaN. Implanted regions of a workpiece increase, reduce, or prevent growth of this compound semiconductor. Combinations of implants may be performed to cause increased growth in certain regions of the workpiece, such as between regions where growth is reduced. Growth also may be reduced or prevented at the periphery of the workpiece.11-15-2012
20110318905SILICON/GERMANIUM NANOPARTICLE INKS, LASER PYROLYSIS REACTORS FOR THE SYNTHESIS OF NANOPARTICLES AND ASSOCIATED METHODS - Laser pyrolysis reactor designs and corresponding reactant inlet nozzles are described to provide desirable particle quenching that is particularly suitable for the synthesis of elemental silicon particles. In particular, the nozzles can have a design to encourage nucleation and quenching with inert gas based on a significant flow of inert gas surrounding the reactant precursor flow and with a large inert entrainment flow effectively surrounding the reactant precursor and quench gas flows. Improved silicon nanoparticle inks are described that has silicon nanoparticles without any surface modification with organic compounds. The silicon ink properties can be engineered for particular printing applications, such as inkjet printing, gravure printing or screen printing. Appropriate processing methods are described to provide flexibility for ink designs without surface modifying the silicon nanoparticles.12-29-2011
20120021590Tellurium Precursors for Film Deposition - Methods and compositions for depositing a tellurium-containing film on a substrate are disclosed. A reactor and at least one substrate disposed in the reactor are provided. A tellurium-containing precursor is provided and introduced into the reactor, which is maintained at a temperature ranging from approximately 20° C. to approximately 100° C. Tellurium is deposited on to the substrate through a deposition process to form a thin film on the substrate.01-26-2012
20120028448Group III-Nitride Layers With Patterned Surfaces - A fabrication method produces a mechanically patterned layer of group III-nitride. The method includes providing a crystalline substrate and forming a first layer of a first group III-nitride on a planar surface of the substrate. The first layer has a single polarity and also has a pattern of holes or trenches that expose a portion of the substrate. The method includes then, epitaxially growing a second layer of a second group III-nitride over the first layer and the exposed portion of substrate. The first and second group III-nitrides have different alloy compositions. The method also includes subjecting the second layer to an aqueous solution of base to mechanically pattern the second layer.02-02-2012
20120028447METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes growing a first GaN layer on a SiC substrate, and forming a second GaN layer on the first GaN layer, the second GaN layer being grown under such conditions that a ratio of a vertical growth rate to a horizontal growth rate is lower than that in the growth of the first GaN layer.02-02-2012
20120028446METHOD FOR FABRICATING GROUP III-NITRIDE SEMICONDUCTOR - A method of fabricating a group III-nitride semiconductor includes the following steps of forming a first patterned mask layer with a plurality of first openings deposited on an epitaxial substrate; epitaxially growing a group III-nitride semiconductor layer over the epitaxial substrate and covering at least part of the first patterned mask layer; etching the group III-nitride semiconductor layer to form a plurality of second openings, which are substantially at least partially aligned with the first openings; and epitaxially growing the group III-nitride semiconductor layer again.02-02-2012
20120028445SUSCEPTOR TREATMENT METHOD AND A METHOD FOR TREATING A SEMICONDUCTOR MANUFACTURING APPARATUS - A susceptor treatment method including placing a first substrate on a susceptor and forming a Si film on the first substrate by epitaxial growth, placing a second substrate on the susceptor in place of the first substrate and forming a SiC film on the second substrate by epitaxial growth, and allowing HCl gas to flow downward from above the susceptor while the susceptor, from which the second substrate has been removed, is heated to a temperature and rotated to remove the remaining crystalline grains derived from the epitaxial growth of Si film and the SiC film on the susceptor.02-02-2012
20120028444DEFECT-FREE HETERO-EPITAXY OF LATTICE MISMATCHED SEMICONDUCTORS - A method includes providing a semiconductor substrate formed of a first semiconductor material; and forming a plurality of insulation regions over at least a portion of the semiconductor substrate, with a plurality of trenches separating the plurality of insulation regions apart from each other. A first epitaxial growth is performed to epitaxially grow a plurality of semiconductor regions in the plurality of trenches, wherein (111) facets are formed and exposed during the step of the first epitaxial growth. When the (111) facets of neighboring ones of the plurality of semiconductor regions touch each other, a second epitaxial growth is performed to continue grow the plurality of semiconductor regions to form (100) planes between the neighboring ones of the plurality of semiconductor regions.02-02-2012
20130196485METHODS OF EPITAXIAL FINFET - Disclosed herein are various methods for better height control of the finFET patterned fins. In one example, this invention begins by depositing or growing an oxide material, for example, silicon dioxide. This oxide material is then patterned and etched to open windows or trenches to the substrate where fins will be grown. If a common channel material is desired, it is epitaxially grown in the windows. Then, some windows are covered and one pole of fins (for example nFET) are epitaxially grown in the exposed windows. The previously masked windows are opened and the newly formed fins are masked. The alternate channel material is then grown. The masked fins are then un-masked and the oxide is recessed to allow the fins to protrude from the oxide. This invention also allows for different channel materials for NMOS and PMOS.08-01-2013
20120295422METHOD FOR FABRICATING InGaN-BASED MULTI-QUANTUM WELL LAYERS - A method for fabricating quantum wells by using indium gallium nitride (InGaN) semiconductor material includes fabricating a potential well on a layered group III-V nitride structure at a first predetermined temperature in a reactor chamber by injecting into the reactor chamber an In precursor gas and a Ga precursor gas. The method further includes, subsequent to the fabrication of the potential well, terminating the Ga precursor gas, maintaining a flow of the In precursor gas, and increasing the temperature in the reactor chamber to a second predetermined temperature while adjusting the In precursor gas flow rate from a first to a second flow rate. In addition, the method includes annealing and stabilizing the potential well at the second predetermined temperature while maintaining the second flow rate. The method also includes fabricating a potential barrier above the potential well at the second predetermined temperature while resuming the Ga precursor gas.11-22-2012
20120295420SEMICONDUCTOR DEVICES WITH REDUCED STI TOPOGRAPHY BY USING CHEMICAL OXIDE REMOVAL - A thermal oxide may be removed in semiconductor devices prior to performing complex manufacturing processes, such as forming sophisticated gate electrode structures, by using a gaseous process atmosphere instead of a wet chemical etch process, wherein the masking of specific device regions may be accomplished on the basis of a resist mask.11-22-2012
20120295419METHODS FOR DEPOSITING A MATERIAL ATOP A SUBSTRATE - Methods for depositing a material atop a substrate are provided herein. In some embodiments, a method of depositing a material atop a substrate may include exposing a substrate to a silicon containing gas and a reducing gas; increasing a flow rate of the silicon containing gas while decreasing a flow rate of the reducing gas to form a first layer; and depositing a second layer atop the first layer.11-22-2012
20120295418METHODS FOR IMPROVED GROWTH OF GROUP III NITRIDE BUFFER LAYERS - Methods are disclosed for growing high crystal quality group III-nitride epitaxial layers with advanced multiple buffer layer techniques. In an embodiment, a method includes forming group III-nitride buffer layers that contain aluminum on suitable substrate in a processing chamber of a hydride vapor phase epitaxy processing system. A hydrogen halide or halogen gas is flowing into the growth zone during deposition of buffer layers to suppress homogeneous particle formation. Some combinations of low temperature buffers that contain aluminum (e.g., AlN, AlGaN) and high temperature buffers that contain aluminum (e.g., AlN, AlGaN) may be used to improve crystal quality and morphology of subsequently grown group III-nitride epitaxial layers. The buffer may be deposited on the substrate, or on the surface of another buffer. The additional buffer layers may be added as interlayers in group III-nitride layers (e.g., GaN, AlGaN, AlN).11-22-2012
20120295417SELECTIVE EPITAXIAL GROWTH BY INCUBATION TIME ENGINEERING - A method of controlling the nucleation rate (i.e., incubation time) of dissimilar materials in an epitaxial growth chamber that can favor high growth rates and can be compatible with low temperature growth is provided. The nucleation rate of dissimilar materials is controlled in an epitaxial growth chamber by altering the nucleation rate for the growth of a given material film, relative to single crystal growth of the same material film, by choosing an appropriate masking material with a given native nucleation characteristic, or by modifying the surface of the masking layer to achieve the appropriate nucleation characteristic. Alternatively, nucleation rate control can be achieved by modifying the surface of selected areas of a semiconductor substrate relative to other areas in which an epitaxial semiconductor material will be subsequently formed.11-22-2012
20120040515Semiconductor Light-Emitting Device, Surface-Emission Laser Diode, and Production Apparatus Thereof, Production Method, Optical Module and Optical Telecommunication System - A semiconductor light-emitting device has a semiconductor layer containing Al between a substrate and an active layer containing nitrogen, wherein Al and oxygen are removed from a growth chamber before growing said active layer and a concentration of oxygen incorporated into said active layer together with Al is set to a level such that said semiconductor light-emitting device can perform a continuous laser oscillation at room temperature.02-16-2012
20100029066SUSCEPTOR, VAPOR PHASE GROWTH APPARATUS, AND METHOD OF MANUFACTURING EPITAXIAL WAFER - An aspect of the present invention relates to a susceptor comprising a counterbored groove receiving a semiconductor wafer in the course of manufacturing an epitaxial wafer by vapor phase growing an epitaxial layer on a surface of the semiconductor wafer, wherein a lateral wall of the counterbored groove is comprised of at least one flat portion and at least one protruding portion being higher than the flat portion, and a height of the flat portion is equal to or greater than a thickness of the semiconductor wafer.02-04-2010
20130203243METHODS FOR ENHANCING P-TYPE DOPING IN III-V SEMICONDUCTOR FILMS - Methods of doping a semiconductor film are provided. The methods comprise epitaxially growing the III-V semiconductor film in the presence of a dopant, a surfactant capable of acting as an electron reservoir, and hydrogen, under conditions that promote the formation of a III-V semiconductor film doped with the p-type dopant. In some embodiments of the methods, the epitaxial growth of the doped III-V semiconductor film is initiated at a first hydrogen partial pressure which is increased to a second hydrogen partial pressure during the epitaxial growth process.08-08-2013
20130203244METHODS FOR PFET FABRICATION USING APM SOLUTIONS - A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing an integrated circuit comprising a p-type field effect transistor (pFET), recessing a surface region of the pFET using an ammonia-hydrogen peroxide-water (APM) solution to form a recessed pFET surface region, and depositing a silicon-based material channel on the recessed pFET surface region.08-08-2013
20130203245METHODS FOR PFET FABRICATION USING APM SOLUTIONS - A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region.08-08-2013
20130203246SEMICONDUCTOR CHIP WITH GRAPHENE BASED DEVICES IN AN INTERCONNECT STRUCTURE OF THE CHIP - A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device.08-08-2013
20120077335METHODS FOR DEPOSITING GERMANIUM-CONTAINING LAYERS - Methods for depositing germanium-containing layers on silicon-containing layers are provided herein. In some embodiments, a method may include depositing a first layer atop an upper surface of the silicon-containing layer, wherein the first layer comprises predominantly germanium (Ge) and further comprises a lattice adjustment element having a concentration selected to enhance electrical activity of dopant elements, wherein the dopant elements are disposed in at least one of the first layer or in an optional second layer deposited atop of the first layer, wherein the optional second layer, if present, comprises predominantly germanium (Ge). In some embodiments, the second layer is deposited atop the first layer. In some embodiments, the second layer comprises germanium (Ge) and dopant elements.03-29-2012
20120083100THERMALIZING GAS INJECTORS FOR GENERATING INCREASED PRECURSOR GAS, MATERIAL DEPOSITION SYSTEMS INCLUDING SUCH INJECTORS, AND RELATED METHODS - Methods of depositing material on a substrate include forming a precursor gas and a byproduct from a source gas within a thermalizing gas injector. The byproduct may be reacted with a liquid reagent to form additional precursor gas, which may be injected from the thermalizing gas injector into a reaction chamber. Thermalizing gas injectors for injecting gas into a reaction chamber of a deposition system may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. A pathway may extend from the inlet, through the thermalizing conduit to an interior space within the liquid container, and from the interior space within the liquid container to the outlet. The thermalizing conduit may have a length that is greater than a shortest distance between the inlet and the liquid container. Deposition systems may include one or more such thermalizing gas injectors.04-05-2012
20120094474METHOD FOR EQUIPPING AN EPITAXY REACTOR - The invention relates to a method for equipping a process chamber in an apparatus for depositing at least one layer on a substrate held by a susceptor in the process chamber, process gases being introduced into the process chamber through a gas inlet element, in particular by means of a carrier gas, the process gases decomposing into decomposition products in the chamber, in particular on hot surfaces, the decomposition products comprising the components that form the layer. In order to improve the apparatus so that thick multi-layer structures can be deposited reproducibly in process steps that follow one another directly, it is proposed that a material is selected for the surface facing the process chamber at least of the wall of the process chamber that is opposite the susceptor, the optical reflectivity, optical absorptivity and optical transmissivity of which respectively correspond to those of the layer to be deposited during the layer growth.04-19-2012
20120094473GROUP III NITRIDE SUBSTRATE, EPITAXIAL LAYER-PROVIDED SUBSTRATE, METHODS OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate (04-19-2012
20120094472METHODS FOR FABRICATING THIN FILM PATTERN AND ARRAY SUBSTRATE - A method for fabricating a thin film pattern and a method for fabricating an array substrate are provided. The method for fabricating a thin film pattern comprises: forming a first film and a second film sequentially; applying a layer of photoresist on the second film; forming a photoresist pattern comprising a totally left region, a partially left region and a totally removed region; performing a first wet etching on the second film in the totally removed region; performing a first dry etching on the first film in the totally removed region to form a first pattern, and etching the photoresist layer to remove the photoresist in the partially left region to expose the second film in the partially left region; performing a second wet etching on the second film in the partially left region; performing a second dry etching to form a second pattern; and removing the residual photoresist.04-19-2012
20130210218METHOD FOR TRANSFERRING A GRAPHENE LAYER - A method transfers a graphene layer from a donor substrate onto a final substrate. The method includes: providing a metal layer on the donor substrate; and growing a graphene layer on the metal layer. The method also includes: laminating a dry film photo-resist on the graphene layer; laminating a tape on the dry film photo-resist; chemically. etching the metal layer, obtaining an initial structure that includes the tape, the dry film photo-resist and the graphene layer; laminating the initial structure on the final substrate; thermally realizing the tape, so as to obtain an intermediate structure that includes the dry film photo-resist, the graphene layer and the final substrate; removing the dry film photo-resist; and obtaining a final structure that includes the final substrate with a transferred graphene layer.08-15-2013
20130210219ANTIMONIDE-BASED COMPOUND SEMICONDUCTOR WITH TITANIUM TUNGSTEN STACK - An apparatus in one example comprises an antimonide-based compound semiconductor (ABCS) stack, an upper barrier layer formed on the ABCS stack, and a gate stack formed on the upper barrier layer. The upper barrier layer comprises indium, aluminum, and arsenic. The gate stack comprises a base layer of titanium and tungsten formed on the upper barrier layer.08-15-2013