Entries |
Document | Title | Date |
20080233716 | Method for fabricating semiconductor device - The principal objects of the present invention are to provide structure of a semiconductor device capable of reducing a bowing of a wafer, and a method for fabricating the semiconductor device. The present invention is applied to a semiconductor device, which is fabricated with a semiconductor substrate having a silicon carbide (SiC) film. The method includes the steps of: forming the SiC film on a semiconductor wafer; discriminating a deformation condition of the semiconductor wafer; and forming grooves in the SiC film, the grooves having a shape determined in accordance with the deformation condition of the semiconductor wafer. | 09-25-2008 |
20090130823 | METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDING TRENCH GATE STRUCTURE - A method of forming a semiconductor device is provided, which may include, but is not limited to, the following processes. Grooves may be formed in an insulating region and in a semiconductor region, while forming burrs near the boundary between the insulating region and the semiconductor region. Protection films may be selectively formed on inside walls of the grooves except on bottom walls of the grooves. A selective thermal process may be carried out in the presence of the protection films, thereby removing the burrs. | 05-21-2009 |
20090130824 | ARSENIC AND PHOSPHORUS DOPED SILICON WAFER SUBSTRATES HAVING INTRINSIC GETTERING - A process for the preparation of low resistivity arsenic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates. | 05-21-2009 |
20090162995 | Semiconductor Device Manufacturing Method and Semiconductor Manufacturing Apparatus - By hydrogen-terminating a semiconductor surface using a solution containing HF | 06-25-2009 |
20090233420 | P-TYPE SILICON WAFER AND METHOD FOR HEAT-TREATING THE SAME - This p-type silicon wafer was subjected to heat treatment to have a resistivity of 10 Ω·cm or more, a BMD density of 5×10 | 09-17-2009 |
20100087048 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It has been difficult to manufacture a semiconductor device equipped with a microstructure having a space, an electric circuit for controlling the microstructure, and the like over one substrate. | 04-08-2010 |
20100105190 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING INSTALLATION - A semiconductor device manufacturing method is provided, including: providing a semiconductor substrate, forming on the semiconductor substrate a layer including a semiconductor compound and a dope additive, and thereafter forming an emitter region and gettering impurities by annealing the semiconductor substrate including the layer. | 04-29-2010 |
20100120231 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device according to the present invention includes the following step: a step (S | 05-13-2010 |
20100136768 | METHOD FOR SIMULTANEOUS DOPING AND OXIDIZING SEMICONDUCTOR SUBSTRATES AND THE USE THEREOF - The invention relates to a method for simultaneous doping and oxidizing semiconductor substrates and also to doped and oxidized semiconductors substrates produced in this manner. Furthermore, the invention relates to the use of this method for producing solar cells. | 06-03-2010 |
20110065263 | METHOD FOR REPROCESSING SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING REPROCESSED SEMICONDUCTOR SUBSTRATE, AND METHOD FOR MANUFACTURING SOI SUBSTRATE - It is an object of the invention is to provide a method suitable for reprocessing a semiconductor substrate having favorable planarity. Another object of the invention is to manufacture a reprocessed semiconductor substrate by using the method suitable for reprocessing a semiconductor substrate having favorable planarity, and to manufacture an SOI substrate by using the reprocessed semiconductor substrate. A projecting portion of a semiconductor substrate is removed using a method capable of selectively removing a semiconductor region which is damaged by ion irradiation or the like. Further, an oxide film is formed on a surface of the semiconductor substrate when the semiconductor substrate is planarized by a polishing treatment typified by a CMP method, whereby the semiconductor substrate is evenly polished at a uniform rate. Moreover, a reprocessed semiconductor substrate is manufactured using the aforementioned method, and an SOI substrate is manufactured using the reprocessed semiconductor substrate. | 03-17-2011 |
20120040511 | AlxInyGa1-x-yN MIXTURE CRYSTAL SUBSTRATE, METHOD OF GROWING SAME AND METHOD OF PRODUCING SAME - Seeds are implanted in a regular pattern upon an undersubstrate. An Al | 02-16-2012 |
20120070961 | LOW TEMPERATURE ETCHANT FOR TREATMENT OF SILICON-CONTAINING SURFACES - Embodiments provide methods for etching and depositing silicon materials on a substrate. In one example, the method includes heating a substrate containing a silicon-containing material to a temperature of about 800° C. or less and removing a portion of the silicon-containing material and a contaminant to reveal an exposed surface of the silicon-containing material during an etching process and depositing a silicon-containing layer on the exposed surface of the silicon-containing material during a deposition process. The method further provides conducting the etching and deposition processes in the same chamber and utilizing chlorine gas and a silicon source gas during the etching and deposition processes. In some examples, the silicon-containing material is removed at a rate within a range from about 2 Å per minute to about 20 Å per minute during the etching process. | 03-22-2012 |
20120122300 | FILM STRESS MANAGEMENT FOR MEMS THROUGH SELECTIVE RELAXATION - An apparatus comprising a microelectromechanical system. The microelectromechanical system includes a crystalline structural element having dislocations therein. For at least about 60 percent of adjacent pairs of the dislocations, direction vectors of the dislocations form acute angles of less than about 45 degrees. | 05-17-2012 |
20120178240 | Thermal Budget Optimization for Yield Enhancement on Bulk Silicon Wafers - A method of nucleating and growing oxygen precipitates of sufficient concentration and size in lightly doped p-type wafers for effective gettering of heavy metals is deep submicron transistor, integrated circuit manufacturing flows. | 07-12-2012 |
20130045586 | Process Of Internal Gettering For Czochralski Silicon Wafer - An internal gettering process for a Czochralski silicon wafers comprises: (1) heating a Cz silicon wafer to 1200-1250° C. at a heating rate of 50-100° C./s under a nitrogen atmosphere, maintaining for 30-150 seconds, cooling the Cz silicon wafer to 800-1000° C. first at a cooling rate of 5-50° C./s, and then cooling the Cz silicon wafer naturally; (2) annealing the Cz silicon wafer obtained in the step (1) at 800-900° C. under an argon atmosphere for a period of 8-16 hours. The present invention only involves two heat treatment steps which require lower temperature and shorter time comparing to the conventional processes. The density of the bulk microdefects and the width of the denuded zone can be easily controlled by the temperature, duration and cooling rate of rapid thermal processing in the first step. | 02-21-2013 |
20130102128 | METHOD FOR TREATING THE DISLOCATION IN A GAN-CONTAINING SEMICONDUCTOR LAYER - A method for treating the threading dislocation within a GaN-containing semiconductor layer is provided. The method includes a substrate is provided. A GaN-containing semiconductor layer with the threading dislocation is formed on the substrate. An etching process with an etching gas is performed to remove the threading dislocation in the GaN-containing semiconductor layer so as to increase the efficiency for the light emitting device. | 04-25-2013 |
20130102129 | PROCESSES FOR SUPPRESSING MINORITY CARRIER LIFETIME DEGRADATION IN SILICON WAFERS - Processes for suppressing minority carrier lifetime degradation in silicon wafers are disclosed. The processes involve quench cooling the wafers to increase the density of nano-precipitates in the silicon wafers and the rate at which interstitial atoms are consumed by the nano-precipitates. | 04-25-2013 |
20130288455 | METHOD OF FORMING A FREESTANDING SEMICONDUCTOR WAFER - A method of forming a freestanding semiconductor wafer includes providing a semiconductor substrate including a semiconductor layer having a back surface and an upper surface opposite the back surface, wherein the semiconductor layer comprises at least one permanent defect between the upper surface and back surface, removing a portion of the back surface of the semiconductor layer and the permanent defect from the semiconductor layer, and forming a portion of the upper surface after removing a portion of the back surface and the permanent defect. | 10-31-2013 |
20140220766 | PLANAR SEMICONDUCTOR GROWTH ON III-V MATERIAL - A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided. | 08-07-2014 |
20140335680 | MULTI-LAYER AMORPHOUS SILICON STRUCTURE WITH IMPROVED POLY-SILICON QUALITY AFTER EXCIMER LASER ANNEAL - The embodiments described herein generally relate to methods for forming a multi-layer amorphous silicon structure that may be used in thin film transistor devices. In one embodiment, a method includes positioning a substrate comprising a buffer layer in a process chamber, the process chamber comprising a processing region, forming a plurality of amorphous silicon layers and annealing the amorphous silicon layers to form a polycrystalline silicon layer. Forming the plurality of layers includes delivering a silicon-containing precursor and a first activation gas to the processing region to deposit a first amorphous silicon layer over the buffer layer, the silicon-containing precursor and the first activation gas being activated by a plasma and maintaining a continuous flow of the silicon-containing precursor while delivering a second activation gas, without the first activation gas, to the processing region to deposit a second silicon layer on the first silicon layer. | 11-13-2014 |
20160035583 | MANUFACTURING METHOD OF EPITAXIAL SILICON WAFER - A manufacturing method of an epitaxial silicon wafer includes: an epitaxial-film-growth step in which an epitaxial film is grown on a silicon wafer in a reaction container, and a temperature reduction step in which a temperature of the epitaxial silicon wafer is reduced from a temperature at which the epitaxial film is grown. In the temperature reduction step, a temperature reduction rate of the epitaxial silicon wafer is controlled to satisfy a relationship represented by R≦2.0×10-4X | 02-04-2016 |
20160049313 | METHOD OF OUTGASSING A MASK MATERIAL DEPOSITED OVER A WORKPIECE IN A PROCESS TOOL - Embodiments of the invention include methods and apparatuses for outgassing a workpiece prior to a plasma processing operation. An embodiment of the invention may comprise transferring a workpiece having a mask to an outgassing station that has one or more heating elements. The workpiece may then be heated to an outgassing temperature that causes moisture from the mask layer to be outgassed. After outgassing the workpiece, the workpiece may be transferred to a plasma processing chamber. In an additional embodiment, one or more outgassing stations may be located within a process tool that has a factory interface, a load lock coupled to the factory interface, a transfer chamber coupled to the load lock, and a plasma processing chamber coupled to the transfer chamber. According to an embodiment, an outgassing station may be located within any of the components of the process tool. | 02-18-2016 |
20160053404 | CONTROLLABLE OXYGEN CONCENTRATION IN SEMICONDUCTOR SUBSTRATE - A method of controlling oxygen concentration in III-V compound semiconductor substrate comprises providing a plurality of III-V crystal substrates in a container, providing a predetermined amount of material in the container. Atoms of the predetermined amount of material having a high chemical reactivity with oxygen atoms. The method further comprises maintaining a predetermined pressure within the container and annealing the plurality of III-V crystal substrates to yield an oxygen concentration in the crystal substrates. The oxygen concentration is associated with the predetermined amount of material. | 02-25-2016 |