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SEMICONDUCTOR SUBSTRATE DICING

Subclass of:

438 - Semiconductor device manufacturing: process

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
438462000 Having specified scribe region structure (e.g., alignment mark, plural grooves, etc.) 131
438463000 By electromagnetic irradiation (e.g., electron, laser, etc.) 98
438464000 With attachment to temporary support or carrier 96
438465000 Having a perfecting coating 17
438461000 Beam lead formation 1
20110201178SEMICONDUCTOR DEVICE AND PROCESS FOR FABRICATING THE SAME - A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer if formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.08-18-2011
Entries
DocumentTitleDate
20110177674PROCESSING OF MULTILAYER SEMICONDUCTOR WAFERS - A method and apparatus for machining, or forming a feature in, a patterned silicon wafer includes removing portions of surface layers on the wafer using a first pulsed laser (07-21-2011
20100009517Process for Inhibiting Corrosion and Removing Contaminant from a Surface During Wafer Dicing and Composition Useful Therefor - Adherence of contaminant residues or particles is suppressed, corrosion of exposed surfaces is substantially reduced or eliminated during the process of dicing a wafer by sawing. A fluoride-free aqueous composition comprising a dicarboxylic acid and/or salt thereof; a hydroxycarboxylic acid and/or salt thereof or amine group containing acid, a surfactant and deionized water is employed.01-14-2010
20110195561ADHESIVE SHEET - An adhesive sheet includes a substrate and an energy-ray curable adhesive layer formed on the substrate. The energy-ray curable adhesive layer includes an energy-ray curable acrylic copolymer and a urethane acrylate. The energy-ray curable acrylic copolymer is formed by copolymerizing at least one of either a dialkyl(meth)acrylamide that has an alkyl group with carbon number of not more than 4, a phenol EO modified (meth)acrylate that has an ethylene glycol chain with a phenyl group bonded to the ethylene glycol chain, a (meth)acryloyl morpholine, or a (meth)acrylate that has an aceto-acetoxyl group, in total of 1 to 30 weight percent of all monomers to form the energy-ray curable acrylic copolymer. The energy-ray curable acrylic copolymer further includes a side chain with an unsaturated group.08-11-2011
20100075482Bonded Wafer Assembly System and Method - A system and method for the removal of superfluous material in a bonded wafer assembly. The method includes cutting a plurality of parallel cuts in a top wafer, the plurality of cuts defining a segment of the top wafer attached to another portion of the top wafer via a tab, inserting a wedge-shaped breaker bar into at least one cut of the plurality of cuts, applying force to the breaker bar to fracture the tab, and removing the segment of the top wafer from the bonded wafer assembly, wherein a bottom wafer remains unsingulated after the removing.03-25-2010
20090042368Wafer processing method - A wafer processing method for dividing, along streets, a wafer having a device area where devices are formed in a plurality of areas sectioned by the plurality of streets arranged in a lattice pattern on the front surface of a substrate and a peripheral extra area and comprising electrodes which are embedded in the substrate of the device area, comprising a dividing groove forming step for forming dividing grooves having a depth corresponding to the final thickness of each device along the streets; an annular groove forming step for forming an annular groove having a depth corresponding to the final thickness of each device along the boundary between the device area and the peripheral extra area; a protective member affixing step for affixing a protective member to the front surface of the wafer; a rear surface grinding step for grinding a rear surface corresponding to the device area of the substrate of the wafer to expose the dividing grooves and the annular groove to the rear surface of the substrate of the wafer and form an annular reinforcing portion in an area corresponding to the peripheral extra area; and a rear surface etching step for etching the rear surface of the substrate of the wafer to project the electrodes from the rear surface of the substrate.02-12-2009
20090042367SAWING METHOD FOR A SEMICONDUCTOR ELEMENT WITH A MICROELECTROMECHANICAL SYSTEM - The present invention relates to a sawing method for a Micro Electro-Mechanical Systems (MEMS) semiconductor device. A gum material is disposed between a wafer having at least one MEMS and a carrier, and the gum material is disposed around the MEMS. The wafer is sawed according to the position correspondingly above the gum material. Finally, the carrier and the gum material are removed. By disposing the gum material between the carrier and the wafer, the MEMS are protected, and the wafer and the MEMS can avoid the pollution of water and foreign material, so that the yield can be improved. Furthermore, the wafer is sawed from the backside till the gum material without sawing through the gum material, so that the carrier is not sawed. Therefore, the carrier can be reused, such that the cost is reduced.02-12-2009
20090117709MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The technology in which lowering of the manufacturing yield of the semiconductor products resulting from contamination impurities can be suppressed is offered.05-07-2009
20130164913SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In a semiconductor device manufacturing method, an insulating layer is formed on a front surface of a semiconductor substrate. Trenches are formed in the substrate by using the insulating layer as a mask so that a first portion of the insulating layer is located on the front surface between the trenches and that a second portion of the insulating layer is located on the front surface at a position other than between the trenches. The entire first portion is removed, and the second portion around an opening of each trench is removed. The trenches are filled with an epitaxial layer by epitaxially growing the epitaxial layer over the front surface side. The front surface side is polished by using the remaining second portion as a polishing stopper.06-27-2013
20120225537METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of: preparing a combined wafer; obtaining a first intermediate wafer by forming an active layer; obtaining a second intermediate wafer by forming a front-side electrode on the first intermediate wafer; supporting the second intermediate wafer by adhering an adhesive tape at the front-side electrode side; removing the supporting layer while supporting the second intermediate wafer using the adhesive tape; forming a backside electrode on the main surfaces of SiC substrates exposedby the removal of the supporting layer; adhering an adhesive tape at the backside electrode side and removing the adhesive tape at the front-side electrode side so as to support the plurality of SiC substrates using the adhesive tape; and obtaining a plurality of semiconductor devices by cutting the SiC substrates with the SiC substrates being supported by the adhesive tape provided at the backside electrode side.09-06-2012
20130065378Method and Apparatus for Plasma Dicing a Semi-conductor Wafer - The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.03-14-2013
20120115306DEFLECTOR ARRAY, CHARGED PARTICLE BEAM DRAWING APPARATUS, DEVICE MANUFACTURING METHOD, AND DEFLECTOR ARRAY MANUFACTURING METHOD - A deflector array includes a first base substrate including a plurality of apertures formed thereon, and a plurality of deflector chips including a plurality of apertures formed thereon and a plurality of electrode pairs disposed at both sides of at least a part of the plurality of apertures. The plurality of deflector chips is fixed to the first base substrate in such a manner that the plurality of apertures of the deflector chips is arranged at positions corresponding to the plurality of apertures of the first base substrate.05-10-2012
20120238072HEAT TRANSFER FOR A HARD-DRIVE PRE-AMP - A substrate for mounting a preamp chip thereupon, fabricated using a stiffener layer made of a conductive material; an insulating layer provided over the circuitry area of the substrate; a circuitry made of a conductive material provided over the insulating layer; and a flap which is an extension of the stiffener layer having no insulating layer provided thereupon. The flap is fabricated to fold over the preamp chip to remove heat therefrom.09-20-2012
20120028442THERMALLY RELEASABLE SHEET-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE, METHOD OF COLLECTING SEMICONDUCTOR ELEMENT, AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - The present invention relates to a thermally releasable sheet-integrated film for semiconductor back surface, which includes: a pressure-sensitive adhesive sheet including a base material layer and a pressure-sensitive adhesive layer, and a film for semiconductor back surface formed on the pressure-sensitive adhesive layer of the pressure-sensitive adhesive sheet, in which the pressure-sensitive adhesive sheet is a thermally releasable pressure-sensitive adhesive sheet whose peel force from the film for semiconductor back surface decreases upon heating.02-02-2012
20110294279WORKING METHOD FOR SAPPHIRE SUBSTRATE - A working method for a sapphire substrate for dividing a sapphire substrate along a set planned dividing line includes a cutting groove forming step of positioning a cutting blade, which includes a cutting edge to which diamond grain is secured by nickel plating, to a planned dividing line of the sapphire substrate and feeding the cutting blade and the sapphire substrate relative to each other for working while rotating the cutting blade to form a cutting groove, which serves as a start point of break, along the planned division line on the sapphire substrate, and a breaking step of applying external force to the sapphire substrate, for which the cutting groove forming step is carried out, to break the sapphire substrate along the planned dividing line along which the cutting groove is formed. The cutting groove forming step is set such that a rotational speed of the cutting blade is 20000 to 35000 rpm, a cutting-in depth of the cutting blade is 5 to 15 μm and a working feeding speed is 50 to 150 mm/second.12-01-2011
20110287606METHOD FOR FABRICATING CHIP ELEMENTS PROVIDED WITH WIRE INSERTION GROOVES - The invention relates to a method for fabricating chip elements provided with a groove from devices formed on a wafer. The method comprises the steps consisting in, depositing a sacrificial film on the wafer so as to leave a central part of each device exposed and to cover an edge of the device at the level of which the groove is to be formed; applying a mold on the sacrificial film; injecting a hardenable material into the mold; hardening the hardenable material; dicing the wafer between the devices; and eliminating the sacrificial film.11-24-2011
20090298262METHOD OF SPLITTING BRITTLE MATERIALS WITH TRENCHING TECHNOLOGY - One aspect of the invention relates to a method for splitting an object made of brittle material into at least two pieces. The object has a first flat surface and a second flat surface opposite to each other. The method includes etching at least one trench in at least one of the surfaces so as to form at least one line on the surface. The method also includes splitting the object into separate pieces along the line.12-03-2009
20090098711MICROMACHINE DEVICE PROCESSING METHOD - A micromachine device processing method for dividing a functional wafer, which has micromachine devices formed in a plurality of regions demarcated by streets formed in a lattice pattern on a face of the functional wafer, along the streets into the individual micromachine devices, each micromachine device having a moving portion and an electrode, comprising: a cap wafer groove forming step of forming dividing grooves, which have a depth corresponding to a finished thickness of a cap wafer for protecting the face of the functional wafer, along regions in one surface of the cap wafer which correspond to areas of the electrodes of the micromachine devices; a cap wafer joining step of joining the one surface of the cap wafer subjected to the cap wafer groove forming step to the face of the functional wafer at peripheries of the moving portions; a cap wafer grinding step of grinding the other surface of the cap wafer joined to the face of the functional wafer to expose the dividing grooves to the outside; and a cutting step of cutting the functional wafer and the cap wafer subjected to the cap wafer grinding step along the streets.04-16-2009
20100112785Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation - Methods and apparatus provide for forming a semiconductor-on-insulator (SOI) structure, including subjecting a implantation surface of a donor semiconductor wafer to an ion implantation step to create a weakened slice in cross-section defining an exfoliation layer of the donor semiconductor wafer; and subjecting the donor semiconductor wafer to a spatial variation step, either before, during or after the ion implantation step, such that at least one parameter of the weakened slice varies spatially across the weakened slice in at least one of X- and Y-axial directions.05-06-2010
20100112786METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor substrate has a plurality of semiconductor chip forming areas and scribe areas including substrate cutting positions arranged between the plurality of semiconductor chip forming areas. An insulating layer having first opening portions, which expose all or a part of the scribe areas respectively, is formed on the semiconductor substrate. A solder resist layer having second opening portions, which expose all or a part of the scribe areas respectively, is formed on the insulating layer. Portions of the semiconductor substrate corresponding to the substrate cutting positions are cut.05-06-2010
20100267218Semiconductor Wafer Processing to Increase the Usable Planar Surface Area - The invention provides a method for increasing the usable surface area of a semiconductor wafer having a substantially planar surface and a thickness dimension at right angles to said substantially planar surface, the method including the steps of selecting a strip thickness for division of the wafer into a plurality of strips, selecting a technique for cutting the wafer into the strips at an angle to the substantially planar surface, in which the combined strip thickness and width of wafer removed by the cutting is less than the thickness of the wafer, cutting the wafer into strips using the selected technique and separating the strips from each other.10-21-2010
20120190173METHOD FOR PACKAGING WAFER - A method for packaging a wafer is provided, which includes: providing a bare wafer; forming a plurality of through silicon vias across through the bare wafer, the through silicon vias being filled with a conducting metal; forming a redistribution layer on the bare wafer, the redistribution layer being connected to each of the through silicon vias; performing a chemical mechanical polishing process to planarize a surface of the bare wafer; performing a wafer forming process to treat the planarized bare wafer; forming a metal layer on the wafer after processed; forming a plurality of connection pads on the metal layer, the connection pads being respectively electrically connected to their corresponding through silicon vias; forming a passivation layer on the metal layer; and forming a plurality of solder balls or metal bumps on a backside surface of the wafer through which the processed wafer is electrically connected to a substrate.07-26-2012
20080206963Cleaving process to fabricate multilayered substrates using low implantation doses - A method of forming substrates, e.g., silicon on insulator, silicon on silicon. The method includes providing a donor substrate, e.g., silicon wafer. The method also includes forming a cleave layer on the donor substrate that contains the cleave plane, the plane of eventual separation. In a specific embodiment, the cleave layer comprising silicon germanium. The method also includes forming a device layer (e.g., epitaxial silicon) on the cleave layer. The method also includes introducing particles into the cleave layer to add stress in the cleave layer. The particles within the cleave layer are then redistributed to form a high concentration region of the particles in the vicinity of the cleave plane, where the redistribution of the particles is carried out in a manner substantially free from microbubble or microcavity formation of the particles in the cleave plane. That is, the particles are generally at a low dose, which is defined herein as a lack of microbubble or microcavity formation in the cleave plane. The method also includes providing selected energy to the donor substrate to cleave the device layer from the cleave layer at the cleave plane, whereupon the selected energy is applied to create a controlled cleaving action to remove the device layer from a portion of the cleave layer in a controlled manner.08-28-2008
20080206962METHOD AND STRUCTURE FOR THICK LAYER TRANSFER USING A LINEAR ACCELERATOR - A method for fabricating free standing thickness of materials using one or more semiconductor substrates, e.g., single crystal silicon, polysilicon, silicon germanium, germanium, group III/IV materials, and others. In a specific embodiment, the present method includes providing a semiconductor substrate having a surface region and a thickness. The method includes subjecting the surface region of the semiconductor substrate to a first plurality of high energy particles generated using a linear accelerator to form a region of a plurality of gettering sites within a cleave region, the cleave region being provided beneath the surface region to defined a thickness of material to be detached, the semiconductor substrate being maintained at a first temperature. In a specific embodiment, the method includes subjecting the surface region of the semiconductor substrate to a second plurality of high energy particles generated using the linear accelerator, the second plurality of high energy particles being provided to increase a stress level of the cleave region from a first stress level to a second stress level. In a preferred embodiment, the semiconductor substrate is maintained at a second temperature, which is higher than the first temperature. The method frees the thickness of detachable material using a cleaving process, e.g., controlled cleaving process.08-28-2008
20080213975Supply Mechanism For the Chuck of an Integrated Circuit Dicing Device - A system for dicing substrates to singulate integrated circuit units within in them includes a dicing machine (Z) which operates with a chuck table (09-04-2008
20080286944Method to Manufacture a Silicon Wafer Electronic Component Protected Against the Attacks and Such a Component - In general, the invention relates to manufacturing a wafer. The method includes manufacturing a wafer that includes a front side and a back side, thinning the wafer down to a thickness suitable for an intended operation of the wafer, polarizing the substrate wafer from the back side, and cutting the wafer. The wafer is polarized such that an attempt to thin the wafer from the backside results in at least one selected from a group consisting of destruction of the wafer and damage to the wafer.11-20-2008
20080286943Motherboard Cutting Method, Motherboard Scribing Apparatus, Program and Recording Medium - A mother substrate cutting method for cutting a plurality of unit substrates out of a mother substrate, comprises the steps of: (a) forming scribe lines on the mother substrate by scribe forming means; and (b) breaking the mother substrate along the scribe lines, wherein the step (a) includes a step of forming a first scribe line for cutting a first unit substrate out of the mother substrate and a second scribe line for cutting a second unit substrate out of the mother substrate by moving a pressure position to the mother substrate without a pressure to the mother substrate by the scribe forming means being interrupted.11-20-2008
20080293218WAFER DIVIDING METHOD - A wafer dividing method is provided that includes a protective plate sticking step of sticking the face of the wafer to the face of a protective plate by a pressure sensitive adhesive material whose adhesive force is decreased by an external stimulus; a degeneration layer formation step of throwing a laser beam, which permeates the wafer, along the street to the back side of the wafer, thereby forming a degeneration layer of a thickness corresponding to at least the finished thickness of the device within the wafer, the degeneration layer starting at the face of the wafer; a back grinding step of grinding the back of the wafer to form the wafer into the finished thickness of the device; a wafer support step of sticking the back of the wafer to a surface of a dicing tape mounted on an annular frame; an adhesive force decreasing step of imparting an external stimulus to the pressure sensitive adhesive material, thereby decreasing the adhesive force of the pressure sensitive adhesive material; a protective plate peeling step of peeling the protective plate from the face of the wafer; and a wafer rupture step of imparting an external force to the wafer, thereby rupturing the wafer along the street.11-27-2008
20090061596EXPANDING TOOL, EXPANDING METHOD, AND MANUFACTURING METHOD OF UNIT ELEMENTS - There is provided an expanding tool used for dividing a wafer on an expanding tape by applying a radial tensile force to the expanding tape. The expanding tool includes a dividing frame having a first opening, an outer expanding ring having a contact portion that can be made contact with the dividing frame, the contact portion being provided at an outer periphery side of the outer expanding ring, and having a second opening smaller than the first opening, and an inner expanding ring having an outer shape smaller than the second opening.03-05-2009
20110223743ELECTRONIC COMPONENT MANUFACTURING METHOD - The objective is to limit pickup defects when chips with a semi-cured adhesive layer are picked up following dicing by lowering the adhesive strength of an ultraviolet curable adhesive beforehand while improving the cohesive force. Provided is a dicing method for semiconductor wafers with a semi-cured adhesive layer that comprises a process to coat the back surface of semiconductor wafers with a paste-like adhesive and semi-cure the paste-like adhesive in a sheet form using heating or ultraviolet irradiation to form a semi-cured adhesive layer, a gluing process to glue an adhesive sheet, wherein an ultraviolet curable adhesive is laminated on a base film, onto the semi-cured adhesive layer, an ultraviolet irradiation process to apply ultraviolet irradiation to the ultraviolet curable adhesive, and a dicing process to dice the semi-cured adhesive layer glued to the adhesive sheet and the semiconductor wafers.09-15-2011
20100248448METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing semiconductor devices by cleaving a semiconductor wafer along a crystal orientation of the semiconductor wafer includes forming a semiconductor layer on the semiconductor wafer, forming an insulating film on the semiconductor layer such that the insulating film includes an insulating film thinned region extending parallel to the crystal orientation and that is thinner than other regions of the insulating film, forming an electrode on the insulating film and that crosses the insulating film thinned region, forming a cut in the insulating film thinned region, the cut serving as a starting point for cleaving, and cleaving the semiconductor wafer such that cleaving starts at the cut and propagates along the insulating film thinned region.09-30-2010
20130217208Method of Processing Wafers for Saving Material and Protecting Environment - A method of processing wafers for saving material and protecting environment is implemented to collect defective or incomplete wafers and perform cutting operation to create a plurality of separate dies. According to the requirement of a specification, the backs of the dies are grinded to allow each die to have a predetermined thickness. Thereafter, the grinded dies with completeness are sequentially placed onto a carrying means. With the method, the defective or incomplete wafers, which would be discarded in general wafer manufacturing, may be reclaimed to go through cutting, grinding, and selecting operations, so that the dies with completeness on the defective wafers can be picked out and processed again, so as to increase the yield, lower the manufacturing cost, reduce the amount of the wafer waste, increase the wafer utilization, and meet the demands of energy saving, carbon reduction, and environmental protection.08-22-2013
20100003806DETERMINISTIC GENERATION OF AN INTEGRATED CIRCUIT IDENTIFICATION NUMBER - The generation of an identification number of a chip supporting at least one integrated circuit, including the step of causing a cutting of at least one conductive section by cutting of the chip among several first conductive sections parallel to one another and perpendicular to at least one edge of the chip, the first sections being individually connected, by at least one of their ends, to the chip, and exhibiting different lengths, the position of the cutting line with respect to the chip edge conditioning the identification number.01-07-2010
20100003805SEMICONDUCTOR DEVICE FABRICATION METHOD - A semiconductor device fabrication method for dividing a semiconductor wafer into individual devices along a plurality of streets. The method includes a masking step of attaching a mask member having a plurality of openings to the back side of the semiconductor wafer, the openings respectively corresponding to the devices formed on the front side of the semiconductor wafer, an electrode forming step of forming a metal layer on the back side of the semiconductor wafer after performing the masking step to thereby form a plurality of electrodes on the back side of the semiconductor wafer so that the electrodes respectively correspond to the devices formed on the front side of the semiconductor wafer, a mask member stripping step of stripping the mask member from the back side of the semiconductor wafer, a modified layer forming step of applying a laser beam having a transmission wavelength to the semiconductor wafer along the streets, thereby forming a modified layer in the semiconductor wafer along each street, and a dividing step of applying an external force to the semiconductor wafer, thereby dividing the semiconductor wafer along each street.01-07-2010
20100197114Methods of die sawing - A structure includes a substrate having a plurality of scribe line areas surrounding a plurality of die areas. Each of the die areas includes at least one first conductive structure formed over the substrate. Each of the scribe line areas includes at least one active region and at least one non-active region. The active region includes a second conductive structure formed therein. The structure further includes at least one first passivation layer formed over the first conductive structure and second conductive structure, wherein at least a portion of the first passivation layer within the non-active region is removed, whereby die-sawing damage is reduced.08-05-2010
20120196426WAFER DICING PRESS AND METHOD AND SEMICONDUCTOR WAFER DICING SYSTEM INCLUDING THE SAME - In a wafer dicing press for reducing time and cost for wafer dicing and for evenly applying a dicing pressure to a whole wafer, a wafer dicing press includes a support unit supporting a first side of a wafer; and a pressurization device applying a pressure, by dispersing the pressure, to a second side of the wafer so that a laser-scribed layer of the wafer operates as a division starting point. Accordingly, the wafer dicing press reduces laser radiation and pressure-application times for dividing a wafer into semiconductor devices. This increased efficiency is achieved without increasing the likelihood of damaging the wafer.08-02-2012
20100240195FABRICATION METHOD FOR DEVICE STRUCTURE HAVING TRANSPARENT DIELECTRIC SUBSTRATE - A semiconductor device has a transparent dielectric substrate such as a sapphire substrate. To enable fabrication equipment to detect the presence of the substrate optically, the back surface of the substrate is coated with a triple-layer light-reflecting film, preferably a film in which a silicon oxide or silicon nitride layer is sandwiched between polycrystalline silicon layers. This structure provides high reflectance with a combined film thickness of less than half a micrometer.09-23-2010
20100055874Layer transfer of films utilizing controlled propagation - A film of material may be formed by providing a semiconductor substrate having a surface region and a cleave region located at a predetermined depth beneath the surface region. During a process of cleaving the film from the substrate, shear in the cleave region is carefully controlled to achieve controlled propagation by either KII or energy propagation control. According to certain embodiments, an in-plane shear component (KII) is maintained near zero by adiabatic heating of silicon through exposure to E-beam radiation. According to other embodiments, a surface heating source in combination with an implanted layer serves to guide fracture propagation through the cleave sequence.03-04-2010
20100221892SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A BGA type semiconductor device having high reliability is offered. A pad electrode is formed on a surface of a semiconductor substrate and a glass substrate is bonded to the surface of the semiconductor substrate. A via hole is formed from a back surface of the semiconductor substrate to reach a surface of the pad electrode. An insulation film is formed on an entire back surface of the semiconductor substrate including an inside of the via hole. A cushioning pad is formed on the insulation film. The insulation film is removed from a bottom portion of the via hole by etching. A wiring connected with the pad electrode is formed to extend from the via hole onto the cushioning pad. A conductive terminal is formed on the wiring. Then the semiconductor substrate is separated into a plurality of semiconductor dice.09-02-2010
20130143388METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a starting-point crack on a cleavage line on a surface of a semiconductor substrate; forming preliminary cracks intermittently along the cleavage line on the surface of the semiconductor substrate; and cleaving the semiconductor substrate along the cleavage line passing through the preliminary cracks, from the starting-point crack, wherein each of the preliminary cracks has a crack joining the cleavage line from outside of the cleavage line, in a direction of a progress of cleaving.06-06-2013
20100261334SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.10-14-2010
20110244656INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to improve a factor which influences productivity such as variation caused by a characteristic defect of a circuit by thinning or production yield when an integrated circuit device in which a substrate is thinned is manufactured. A stopper layer is formed over one surface of a substrate, and an element is formed over the stopper layer, and then, the substrate is thinned from the other surface thereof. A method in which a substrate is ground or polished or a method in which the substrate is etched by chemical reaction is used as a method for thinning or removing the substrate.10-06-2011
20100261333Silicon carbide semiconductor device and manufacturing method therefor - With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle θ of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 μm/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.10-14-2010
20110086493SEMICONDUCTOR CHIP HAVING ISLAND DISPERSION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention has an object to provide a semiconductor chip of high reliability with less risk of breakage. Specifically, the present invention provides a semiconductor chip having a semiconductor silicon substrate including a semiconductor device layer and a porous silicon domain layer, the semiconductor device layer being provided in a main surface region on one surface of the semiconductor silicon substrate, the porous silicon domain layer being provided in a main surface region on a back surface which is the other surface of the semiconductor silicon substrate, and the porous silicon domain layer having porous silicon domains dispersed like islands in the back surface of the semiconductor silicon substrate.04-14-2011
20080213977Vacuum expansion of integrated circuits at sort - A frame and vacuum expansion chuck are used in combination for stretching a tape carrying a plurality of singulated devices to facilitate removal of the devices with reduced risk of contact between a device being removed from the tape and an adjacent device on the tape. The combination includes a frame for holding edges of a tape carrying a plurality of singulated devices, and a vacuum chuck having upper surfaces for contacting an underside of a tape carrying a plurality of singulated devices. The vacuum chuck extends along a perimeter circumscribing the singulated devices, and at least one groove is defined in the upper surface of the vacuum chuck. Conduit for providing fluid communication between the groove and a vacuum source are provided. Upon evacuation of the volume defined between the groove and the tape, the tape is drawn down into the groove and stretched, thereby increasing the separation or gap between adjacent dice and reducing the risk of damage upon removal of the dice.09-04-2008
20110021003SUPPLY MECHANISM FOR THE CHUCK OF AN INTEGRATED CIRCUIT DICING DEVICE - A system for dicing substrates to singulate integrated circuit units within in them includes a dicing machine (Z) which operates with a chuck table (01-27-2011
20100323498Circuit Device and Method of Manufacturing Thereof - A circuit device of preferred embodiments of the present invention includes: a circuit element with electrodes formed in a peripheral part thereof; connecting portions connected to surfaces of the electrodes; and redistribution lines which are continuous to the respective connecting portions and extended in parallel to the main surface of the circuit element. In preferred embodiments of the present invention, the connecting portions and the redistribution lines are integrally formed of one piece of metal. Accordingly, there is no place where different materials are connected in a portion between the connecting portions and the redistribution lines, thus improving a joint reliability of the entire device against a thermal stress or the like.12-23-2010
20120309167METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes preparing a semiconductor substrate having a circuit unit on an upper surface thereof, a metal pad electrically connected to the circuit unit, and a passivation layer that covers the circuit unit and exposes the metal pad, forming a first re-wiring layer that is electrically connected to the metal pad and is formed by a printing method to extend from the metal pad on the passivation layer and forming a second re-wiring layer on the first re-wiring layer using the first re-wiring layer as a seed by using an electro-plating process.12-06-2012
20110306182METHOD OF CUTTING SEMICONDUCTOR SUBSTRATE - Multiphoton absorption is generated, so as to form a part which is intended to be cut 12-15-2011
20120045884PROTECTIVE THIN FILMS FOR USE DURING FABRICATION OF SEMICONDUCTORS, MEMS, AND MICROSTRUCTURES - A method of protecting a substrate during fabrication of semiconductor, MEMS devices. The method includes application of a protective thin film which typically has a thickness ranging from 3 angstroms to about 1,000 angstroms, wherein precursor materials used to deposit the protective thin film are organic-based precursors which include at least one fluorine-comprising functional group at one end of a carbon back bone and at least one functional bonding group at the opposite end of a carbon backbone, and wherein the carbon backbone ranges in length from 4 carbons through about 12 carbons. In many applications at least a portion of the protective thin film is removed during fabrication of the devices.02-23-2012
20120009762Method for Wafer Dicing and Composition Useful Thereof - A solution for semiconductor wafer dicing is disclosed. The solution suppresses the adherence of contamination residues or particles, and reduces or eliminates the corrosion of the exposed metallization areas, during the process of dicing a wafer by sawing. The solution comprises at least one organic acid and/or salt thereof; at least a surfactant and/or at least a base; and deionized water, the composition has a pH is equal or greater than 4. The solution can further comprise, a chelating agent, a defoaming agent, or a dispersing agent.01-12-2012
20120028443METHODS AND APPARATUS FOR PRODUCING SEMICONDUCTOR ON INSULATOR STRUCTURES USING DIRECTED EXFOLIATION - Methods and apparatus provide for forming a semiconductor-on-insulator (SOI) structure, including subjecting a implantation surface of a donor semiconductor wafer to an ion implantation step to create a weakened slice in cross-section defining an exfoliation layer of the donor semiconductor wafer; and subjecting the donor semiconductor wafer to a spatial variation step, either before, during or after the ion implantation step, such that at least one parameter of the weakened slice varies spatially across the weakened slice in at least one of X- and Y- axial directions.02-02-2012
20100279489Semiconductor bond pad patterns and method of formation - In a semiconductor wafer, the polyimide film underneath a power metal structure is partially etched to create corresponding surface depressions of the conformal top power metal. The depressions at the surface of power metal are visible under optical microscopy. Arrangement of the depressions in a pattern facilitates the alignment of probe needles, set-up of automated wire bonding and microscopic inspection for precise alignment of wire bonds.11-04-2010
20120070959MICROELECTRONIC DEVICE WAFERS AND METHODS OF MANUFACTURING - Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched.03-22-2012
20130011998Resin Film Forming Sheet for Chip, and Method for Manufacturing Semiconductor Chip - A sheet for forming a resin film for a chip, with which a semiconductor device is provided with a gettering function, is obtained without performing special treatment to a semiconductor wafer and the chip. The sheet has a release sheet, and a resin film-forming layer, which is formed on the releasing face of the release sheet, and the resin film-forming layer contains a binder polymer component, a curing component, and a gettering agent.01-10-2013
20110092053WIRE DISCHARGE-MACHINING APPARATUS AND WIRE DISCHARGE-MACHINING METHOD, SEMICONDUCTOR WAFER MANUFACTURING APPARATUS AND SEMICONDUCTOR WAFER MANUFACTURING METHOD, AND SOLAR-CELL WAFER MANUFACTURING APPARATUS AND SOLAR-CELL WAFER MANUFACTURING METHOD - A wire machining method includes: a wire electrode set as cutting wires provided in parallel with a distance between the cutting wires of which a predetermined regional part faces a workpiece; a machining power source that generates a pulse-shaped machining voltage; and plural feeder units that are electrically connected to the plural cutting wires respectively of the wire electrode and supply the machining voltage between the cutting wires and the workpiece respectively. The feeder units are arranged such that a direction of a current passed to at least a part of the cutting wires becomes a direction different from a direction of a current passed to other cutting wires.04-21-2011
20110092052METHOD OF FABRICATING SINGLE CRYSTAL GALLIUM NITRIDE SEMICONDUCTOR SUBSTRATE, NITRIDE GALLIUM SEMICONDUCTOR SUBSTRATE AND NITRIDE SEMICONDUCTOR EPITAXIAL SUBSTRATE - A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more single crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction of a predetermined axis. Each predetermined plane is inclined to the predetermined axis. Each substrate has a mirror polished primary surface. The primary surface has a first area and a second area. The first area is between an edge of the substrate and a line 3 millimeter away from the edge. The first area surrounds the second area. An axis perpendicular to the primary surface forms an off-angle with c-axis of the substrate. The off-angle takes a minimum value at a first position in the first area of the primary surface.04-21-2011
20110065259MANUFACTURING METHOD AND METHOD FOR OPERATING TREATMENT APPARATUS - The present invention provides a manufacturing method by which a substrate (typically, a TFT substrate) can be installed directly in a treatment apparatus by using a transfer container without transferring the substrate. It is possible to use the container efficiently and transfer different substrates in size with one container. A manufacturing method in which a substrate is directly installed in an electrostatic-protected transfer container by a substrate supplier, and then the container is directly installed a treatment apparatus by a substrate demander after transferring can be realized, thereby making it possible to transfer substrates such as a TFT substrate. A contamination of a substrate due to particles and electrostatic discharge damage of a TFT substrate can be avoided because a transferring operation is not needed. A manufacturing method in which a substrate holding portion of the container is replaced depending on the size of a substrate and different substrates in size can be transferred with one container may be employed.03-17-2011
20110104872Method of manufacturing a semiconductor device having a heat spreader - A semiconductor device manufacturing method includes cutting a resin sealing body into a plurality of pieces, in which the resin sealing body includes a plurality of semiconductor chips mounted on a wiring board, a heat spreader disposed above the plurality of the semiconductor chips, and a sealing resin filled between the wiring board and the heat spreader. The cutting the resin sealing body includes shaving the resin sealing body from a side of the heat spreader, and shaving the resin sealing body from a side of the wiring board. The shaving the resin sealing body from the side of the heat spreader includes etching the heat spreader.05-05-2011
20100248449Metal-Assisted Chemical Etching of Substrates - Disclosed herein are various embodiments related to metal-assisted chemical etching of substrates on the micron, sub-micron and nano scales. In one embodiment, among others, a method for metal-assisted chemical etching includes providing a substrate; depositing a non-spherical metal catalyst on a surface of the substrate; etching the substrate by exposing the non-spherical metal catalyst and the substrate to an etchant solution including a composition of a fluoride etchant and an oxidizing agent; and removing the etched substrate from the etchant solution.09-30-2010
20120077332SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.03-29-2012
20090042366SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, semiconductor die are singulated from a semiconductor wafer by etching openings completely through the semiconductor wafer.02-12-2009
20100273311ELECTRONIC COMPONENT AND SEMICONDUCTOR DEVICE, METHOD OF MAKING THE SAME AND METHOD OF MOUNTING THE SAME, CIRCUIT BOARD, AND ELECTRONIC INSTRUMENT - A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes (10-28-2010
20090061595METHOD FOR DIVIDING A SEMICONDUCTOR SUBSTRATE AND A METHOD FOR PRODUCING A SEMICONDUCTOR CIRCUIT ARRANGEMENT - A method for dividing a semiconductor substrate involves providing a semiconductor substrate. At least one separating trench is produced at a front side of the semiconductor substrate. A layer is produced at least at the bottom of the at least one separating trench. The semiconductor substrate is thinned at a rear side of the semiconductor substrate at least as far as the layer at the bottom of the at least one separating trench. The layer is severed in order to divide the semiconductor substrate into individual pieces.03-05-2009
20120315739MANUFACTURING METHOD FOR SEMICONDUCTOR WAFER - All treatments performed in machining processes other than a polishing process are performed while pure water free from free abrasive grains is supplied. Thus, an amount of abrasive grains included in a used processing liquid discharged in each process is reduced and semiconductor scraps are collected from the used slurry for recycling.12-13-2012
20110039396Semiconductor device and method of fabricating semiconductor device - A method of fabricating a semiconductor device from a semiconductor wafer, having external connecting terminals on one side of the semiconductor wafer and a cover layer on another side of the semiconductor wafer, includes forming a groove with a first width from the one side to at least an interface between the semiconductor wafer and the cover layer in the semiconductor wafer, and cutting the cover layer with a second width from a bottom side of the groove. The second width is narrower than the first width.02-17-2011
20120270381DIE ATTACH FILM - Provided are a die attach film, a semiconductor wafer, and a semiconductor packaging method. The die attach film can prevent generation of burrs or scattering of chips in a dicing process, and exhibits excellent expandability and pick-up characteristics in a die pressure-sensitive adhesive process. Further, the die attach film can prevent release, shifting, or deflection of a chip in a wire pressure-sensitive adhesive or molding process. Thus, it is possible to improve embeddability, inhibit warpage of a wafer or wiring substrate, and enhance productivity in a semiconductor packaging process.10-25-2012
20120322231SEMICONDUCTOR WAFER PROCESSING METHOD - A semiconductor wafer has a device area where a plurality of semiconductor devices are respectively formed in a plurality of regions partitioned by a plurality of crossing division lines formed on the front side of the semiconductor wafer and a peripheral area surrounding the device area. The back side of the semiconductor wafer corresponding to the device area is ground to thereby form a circular recess and an annular projection surrounding the circular recess. In a chip stacked wafer forming step, a plurality of semiconductor device chips are provided on the bottom surface of the circular recess of the semiconductor wafer at the positions respectively corresponding to the semiconductor devices of the semiconductor wafer. The chip stacked wafer is ground to reduce the thickness of each semiconductor device chip to a finished thickness, and a through electrode is formed in each semiconductor device of the semiconductor wafer.12-20-2012
20120322230METHOD FOR FORMING TWO DEVICE WAFERS FROM A SINGLE BASE SUBSTRATE UTILIZING A CONTROLLED SPALLING PROCESS - The present disclosure provides a method for forming two device wafers starting from a single base substrate. The method includes first providing a structure which includes a base substrate with device layers located on, or within, a topmost surface and a bottommost surface of the base substrate. The base substrate may have double side polished surfaces. The structure including the device layers is spalled in a region within the base substrate that is between the device layers. The spalling provides a first device wafer including a portion of the base substrate and one of the device layers, and a second device wafer including another portion of the base substrate and the other of the device layer.12-20-2012
20120088353SEMICONDUCTOR DEVICE WITH A CHARGE CARRIER COMPENSATION STRUCTURE IN A SEMICONDUCTOR BODY AND METHOD FOR ITS PRODUCTION - A semiconductor device with a charge carrier compensation structure in a semiconductor body and to a method for its production. The semiconductor body includes drift zones of a first conduction type and charge compensation zones of a second conduction type complementing the first conduction type. The drift zones include a semiconductor material applied in epitaxial growth zones, wherein the epitaxial growth zones include an epitaxially grown semiconductor material which is non-doped to lightly doped. Towards the substrate, the epitaxial growth zones are provided with a first conduction type incorporated by ion implantation over the entire surface and with selectively introduced doping material zones of a second, complementary conduction type. Towards the front side, the epitaxial growth zones are provided with a second, complementary conduction type incorporated by ion implantation over the entire surface and with selectively introduced doping material zones of the first conduction type.04-12-2012
20120329245Group III Nitride Crystal and Method for Producing the Same - A method for producing a group III nitride crystal in the present invention includes the steps of cutting a plurality of group III nitride crystal substrates 12-27-2012
20080213976METHODS FOR FABRICATING SEMICONDUCTOR COMPONENTS AND PACKAGED SEMICONDUCTOR COMPONENTS - Packaged semiconductor components and methods for manufacturing packaged semiconductor components. In one embodiment a semiconductor component comprises a die having a semiconductor substrate and an integrated circuit. The substrate has a first side, a second side, a sidewall between the first and second sides, a first indentation at the sidewall around a periphery of the first side, and a second indentation at the sidewall around a periphery of the second side. The component can further include a first exterior cover at the first side and a second exterior cover at the second side. The first exterior cover has a first extension in the first indentation, and the second exterior cover has a second extension in the second indentation. The first and second extensions are spaced apart from each other by an exposed portion of the sidewall.09-04-2008
20130115755METHOD OF SEPARATING SEMICONDUCTOR DIE USING MATERIAL MODIFICATION - A method for separating semiconductor die includes forming a porous region on a semiconductor wafer and separating the die at the porous region using mechanical or other means.05-09-2013
20090191689Method of Arranging Dies in a Wafer for Easy Inkless Partial Wafer Process - In a method and system for fabricating a full wafer (07-30-2009
20130189829DEVICES WITH CRACK STOPS - An apparatus that comprises a device on a substrate and a crack stop in the substrate. Methods of forming a device are also disclosed. The methods may include providing a device, such as a semiconductor device, on a substrate having a first thickness, reducing the thickness of the substrate to a second thickness, and providing a crack stop in the substrate. Reducing the thickness of the substrate may include mounting the substrate to a carrier substrate for support and then removing the carrier substrate. The crack stop may prevent a crack from reaching the device.07-25-2013
20130203237CUTTING METHOD FOR DEVICE WAFER - A cutting method for cutting a device wafer along a plurality of crossing division lines by using a cutting blade, the division lines being formed on the front side of the device wafer to partition a plurality of regions where a plurality of devices are respectively formed. The cutting method includes a hydrophilic property providing step of applying a plasma to the front side of the device wafer to thereby make hydrophilic the front side of the device wafer, and a cutting step of cutting the device wafer along the division lines by using the cutting blade as supplying a cutting fluid to the device wafer after performing the hydrophilic property providing step.08-08-2013
20130203238METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Ineffective chips are formed in the circumference of a semiconductor wafer and effective chips are formed in a region surrounded by the ineffective chips. Dicing lines partition the effective chips and the ineffective chips. Polyimide is formed on an outer circumferential portion of the semiconductor wafer with a predetermined width from an outer circumferential end of the semiconductor wafer such that the polyimide continuously covers the ineffective chips from the outer circumferential end of the semiconductor wafer to the inside and continuously covers a portion which is a predetermined distance away from the outer circumferential end of the semiconductor wafer to the effective chip in the dicing line interposed between the ineffective chips. A metal film is formed on the front electrode formed on the effective chips by plating. The semiconductor wafer is cut into semiconductor chips along the dicing lines by a blade.08-08-2013
20120077333TRENCH SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a trench substrate and a method of manufacturing the same. The trench substrate includes a base substrate, an insulating layer formed on one side or both sides of the base substrate and including trenches formed in a circuit region and a dummy region positioned at a peripheral edge of the trench substrate, and a circuit layer formed in the trenches of the circuit region through a plating process and including a circuit pattern and vias. Thanks to formation of the trenches in the dummy region and the cutting region, deviation in thickness of a plating layer formed on the insulating layer in a plating process is improved upon.03-29-2012
20120094471WAFER PROCESSING TAPE, METHOD OF MANUFACTURING WAFER PROCESSING TAPE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a wafer processing tape, circular or tongue-shaped notched parts facing the center of an adhesive layer, as seen in a plan view, are formed so as to correspond to a pasting region to a wafer ring to a depth that reaches a release base material from the side of a base material film. Due to the formation of the notched parts, when a peeling force acts on the wafer processing tape, portions of a tacky material layer and the base material film which are more outward than the notched parts are peeled off first, and a portion that is more inward than the notched parts remains on the wafer ring in a protruding state. Accordingly, a peeling strength between the wafer processing tape and the wafer ring can be increased. Methods of manufacturing the tape and a semiconductor device are also provided.04-19-2012

Patent applications in class SEMICONDUCTOR SUBSTRATE DICING

Patent applications in all subclasses SEMICONDUCTOR SUBSTRATE DICING