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BONDING OF PLURAL SEMICONDUCTOR SUBSTRATES

Subclass of:

438 - Semiconductor device manufacturing: process

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
438458000 Subsequent separation into plural bodies (e.g., delaminating, dicing, etc.) 297
438459000 Thinning of semiconductor substrate 72
438457000 Warping of semiconductor substrate 6
438456000 Having enclosed cavity 4
20110281419METHOD FOR MANUFACTURING DIELECTRIC ISOLATION TYPE SEMICONDUCTOR DEVICE - A method for manufacturing a dielectric isolation type semiconductor device comprises: forming a plurality of trenches in a first region on a major surface of a semiconductor substrate; forming a first dielectric layer on the major surface of the semiconductor substrate and a first thick dielectric layer in the first region by oxidizing a surface of the semiconductor substrate; bonding a semiconductor layer of a first conductive type to the semiconductor substrate via the first dielectric layer; forming a first semiconductor region by implanting an impurity into a part of the semiconductor layer above the first thick dielectric layer; forming a second semiconductor region by implanting an impurity of a second conductive type into a part of the semiconductor layer so as to surround the first semiconductor region separating from the first semiconductor region.11-17-2011
20080261377METHOD OF FORMING A DEVICE WAFER WITH RECYCLABLE SUPPORT - A method for forming a device wafer with a recyclable support by providing a wafer having first and second surfaces, with at least the first surface of the wafer comprising a semiconductor material that is suitable for receiving or forming electronic devices thereon, providing a supporting substrate having upper and lower surfaces, and providing the second surface of the wafer or the upper surface of the supporting substrate with void features in an amount sufficient to enable a connecting bond therebetween to form a construct wherein the bond is formed at an interface between the wafer and the substrate and is suitable to maintain the wafer and supporting substrate in association while forming or applying electronic devices to the first surface of the wafer, but which connecting bond is severable at the interface due to the void features to separate the substrate from the wafer so that the substrate can be reused.10-23-2008
20090305482SYSTEMS, DEVICES, AND METHODS FOR SEMICONDUCTOR DEVICE TEMPERATURE MANAGEMENT - Devices, systems, and methods for semiconductor die temperature management are described and discussed herein. An IC device is described that includes at least one intra-die cooling structure. In an embodiment, the IC device includes a semiconductor die formed of integral device layers and further includes at least one coolant reservoir and at least one coolant channel. In an embodiment, the at least one coolant reservoir and at least one coolant channel are disposed wholly within the semiconductor die. In various embodiments, at least one coolant reservoir and at least one coolant channel are constructed and arranged to circulate coolant fluid in proximity to at least one IC device structure in order to decrease and or normalize an operating temperature of the IC device. In other embodiments, systems and methods for designing and/or fabricating IC die that include at least one intra-die cooling structure are provided herein.12-10-2009
20130203235CAPPED INTEGRATED DEVICE WITH PROTECTIVE CAP, COMPOSITE WAFER INCORPORATING INTEGRATED DEVICES AND PROCESS FOR BONDING INTEGRATED DEVICES WITH RESPECTIVE PROTECTIVE CAPS - A capped integrated device includes a semiconductor chip, incorporating an integrated device and a protective cap, bonded to the semiconductor chip for protection of the integrated device by means of a bonding layer made of a bonding material. The bonding material forms anchorage elements within recesses, formed in at least one between the semiconductor chip and the protective cap.08-08-2013
Entries
DocumentTitleDate
20100055870MANUFACTURING METHOD OF SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a manufacturing method of a semiconductor substrate and a manufacturing method of a semiconductor device, which prevent reduction in breakdown voltage of a gate oxide film of a device formed in a semiconductor substrate to improve a reliability of the gate oxide film. A manufacturing method of a semiconductor substrate according to the present invention includes: exposing a silicon surface of an active layer substrate 03-04-2010
20100159671Neutron Detection Structure and Method of Fabricating - A method of fabricating a neutron detection structure includes temporarily bonding a carrier to a passivated SOI SRAM wafer, removing a first substrate, depositing a conversion layer where at least a portion of the first substrate was removed, permanently bonding a second substrate to the conversion layer, removing the carrier, and providing at least one electrical contact to the device layer. A method of fabricating a neutron detection structure, corresponding to an alternate embodiment, includes temporarily bonding a carrier to a passivated SOI SRAM wafer, removing a first substrate, depositing a conversion layer onto a second substrate, permanently bonding the coated substrate where at least a portion of the first substrate was removed, removing the carrier, and providing at least one electrical contact to the device layer.06-24-2010
20090162992METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - There are provided a semiconductor device having a structure which can realize not only suppression of a punch-through current but also reuse of a silicon wafer used for bonding, in manufacturing a semiconductor device using an SOI technique, and a manufacturing method thereof. A semiconductor film into which an impurity imparting a conductivity type opposite to that of a source region and a drain region is implanted is formed over a substrate, and a single crystal semiconductor film is bonded to the semiconductor film by an SOI technique to form a stacked semiconductor film. A channel formation region is formed using the stacked semiconductor film, thereby suppressing a punch-through current in a semiconductor device.06-25-2009
20100041209METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, includes: bringing a first major surface of a first substrate into close contact with a second major surface of a second substrate being different in thermal expansion coefficient from the first substrate at a first temperature higher than room temperature; and bonding the first substrate and the second substrate by heating the first substrate and the second substrate to a second temperature higher than the first temperature with the first major surface being in close contact with the second major surface.02-18-2010
20130029472GaN BONDED SUBSTRATE AND METHOD OF MANUFACTURING GaN BONDED SUBSTRATE - A gallium nitride (GaN) bonded substrate and a method of manufacturing a GaN bonded substrate in which a polycrystalline nitride-based substrate is used. The method includes loading a single crystalline GaN substrate and a polycrystalline nitride substrate into a bonder; raising the temperature in the bonder; bonding the single crystalline GaN substrate and the polycrystalline nitride substrate together by pressing the single crystalline GaN substrate and the polycrystalline nitride substrate against each other after the step of raising the temperature; and cooling the resultant bonded substrate.01-31-2013
20130052796METHOD FOR MANUFACTURING A CIRCUIT DEVICE - A semiconductor substrate and a copper sheet stacked with an insulating resin layer are bonded together at a temperature of 130° C. or below (first temperature) so that an element electrode provided on the semiconductor substrate connects to the copper sheet before a thinning process. Then the semiconductor substrate and the copper sheet, on which the insulating resin layer has been stacked, are press-bonded at a high temperature of 170° C. or above (second temperature) with the copper sheet thinned to thickness of a wiring layer. Then the wiring layer (rewiring) is formed by patterning the thinned copper sheet.02-28-2013
20090042361Method for Manufacturing SOI Substrate and SOI Substrate - According to the present invention, there is provided a method for manufacturing an SOI substrate based on a bonding method, comprising at least: forming a silicon oxide film on a surface of at least one of a single-crystal silicon substrate that becomes an SOI layer and a single-crystal silicon substrate that becomes a support substrate; bonding the single-crystal silicon substrate that becomes the SOI layer to the single-crystal silicon substrate that becomes the support substrate through the silicon oxide film; and performing a heat treatment for holding at a temperature falling within the range of at least 950° C. to 1100° C. and then carrying out a heat treatment at a temperature higher than 1100° C. when effecting a bonding heat treatment for increasing bonding strength. As a result, there are provided the method for manufacturing an SOI substrate that can efficiently manufacture an SOI substrate having an excellent gettering ability with respect to metal contamination in an SOI layer, and the SOI substrate.02-12-2009
20130071996JOINT METHOD, JOINT APPARATUS AND JOINT SYSTEM - When joining a processing target substrate and a supporting substrate together by suction-holding the processing substrate and the supporting substrate respectively on a first holding unit and a second holding unit arranged to face each other and pressing the second holding unit toward the first holding unit while heating the substrates by heating mechanisms of the holding units, the present invention preheats at least the processing target substrate before suction-holding the processing target substrate on the first holding unit to suppress generation of particles when joining the processing target substrate and the supporting substrate together so as to properly perform the joining of the processing target substrate and the supporting substrate.03-21-2013
20110014774APPARATUS FOR TEMPORARY WAFER BONDING AND DEBONDING - An improved apparatus for temporary wafer bonding includes a temporary bonder cluster and a debonder cluster. The temporary bonder cluster includes temporary bonder modules that perform electronic wafer bonding processes including adhesive layer bonding, combination of an adhesive layer with a release layer bonding and a combination of a UV-light curable adhesive layer with a laser absorbing release layer bonding. The debonder cluster includes a thermal slide debonder, a mechanical debonder and a radiation debonder.01-20-2011
20090263953METHOD FOR LOW TEMPERATURE BONDING AND BONDED STRUCTURE - A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO10-22-2009
20120115305METHOD AND STRUCTURE FOR WAFER TO WAFER BONDING IN SEMICONDUCTOR PACKAGING - A method for wafer to wafer bonding in semiconductor packaging provides for roughening the bonding surfaces in one embodiment. Also provided is a method for passivating the bonding surfaces with a lower melting point material that becomes forced away from the bonding interface during bonding. Also provided is a method for forming an eutectic at the bonding interface to reduce the impact of any native oxide formation at the bonding interface.05-10-2012
20120238070METHODS FOR PRODUCING SILICON ON INSULATOR STRUCTURES HAVING HIGH RESISTIVITY REGIONS IN THE HANDLE WAFER - Silicon on insulator structures having a high resistivity region in the handle wafer of the silicon on insulator structure are disclosed. Methods for producing such silicon on insulator structures are also provided. Exemplary methods involve creating a non-uniform thermal donor profile and/or modifying the dopant profile of the handle wafer to create a new resistivity profile in the handle wafer. Methods may involve one or more SOI manufacturing steps or electronic device (e.g., RF device) manufacturing steps.09-20-2012
20110244651METHOD AND DEVICE FOR ALTERNATELY CONTACTING TWO WAFERS - A method and device for alternatively contacting two wafer-like component composite arrangements, in which two component composite arrangements, provided with contact metallizations on their opposing contact surfaces, are brought into a coverage position with their contact metallizations to form contact pairs, in which position the contact metallizations to be joined together are pressed against one another, the contact metalllizations being contacted by exposing the rear of one of the component composite arrangements to laser radiation, the wavelength of the laser radiation being selected as a function of the degree of absorption of the component composite arrangement, so that a transmission of the laser radiation through the component composite arrangement exposed to the laser radiation at the rear is essentially suppressed or an absorption of the laser radiation takes place essentially in the contact metallizations of one or both component composite arrangements.10-06-2011
20130164912REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING - Methods and systems for reinforcing the periphery of a semiconductor wafer bonded to a carrier are disclosed. In one embodiment, additional adhesive is applied to the semiconductor wafer prior to bonding. The additional adhesive seeps into a crevice between the carrier and wafer and provides reinforcement. In another embodiment, adhesive is applied to the crevice by a dispenser after the wafer is bonded to the glass carrier.06-27-2013
20120003812METHOD OF MANUFACTURING SEMICONDUCTOR SUBSTRATE - A plurality of silicon carbide substrates and a support portion are heated. A temperature of a first radiation plane facing the plurality of silicon carbide substrates in a first space extending from the plurality of silicon carbide substrates in a direction perpendicular to one plane and away from the support portion is set to a first temperature. A temperature of a second radiation plane facing the support portion in a second space extending from the support portion in a direction perpendicular to one plane and away from the plurality of silicon carbide substrates is set to a second temperature higher than the first temperature. A temperature of a third radiation plane facing the plurality of silicon carbide substrates in a third space extending from a gap among the plurality of silicon carbide substrates along one plane is set to a third temperature lower than the second temperature.01-05-2012
20120003811METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A first silicon carbide substrate has a first front-side surface and a first side surface. A second silicon carbide substrate has a second front-side surface and a second side surface. The second side surface is disposed such that a gap having an opening between the first and second front-side surfaces of the first and second silicon carbide substrates is disposed between the first side surface and the second side surface. A closing portion is provided to close the gap over the opening. By depositing sublimates from the first and second side surfaces onto the closing portion, a connecting portion is formed to connect the first and second side surfaces to each other so as to close the opening. After the step of forming the connecting portion, the closing portion is removed.01-05-2012
20110287604METHODS OF FORMING SEMICONDUCTOR STRUCTURES COMPRISING DIRECT BONDING OF SUBSTRATES - The invention relates to a method of initiating molecular bonding, comprising bringing one face of a first wafer to face one face of a second wafer and initiating a point of contact between the two facing faces. The point of contact is initiated by application to one of the two wafers, for example using a bearing element of a tool, of a mechanical pressure in the range 0,1 MPa to 33.3 MPa.11-24-2011
20110287603METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE - First and second supported portions each made of silicon carbide and a supporting portion made of silicon carbide are arranged such that the first and second supported portions and the supporting portion face each other and a gap is provided between the first and second supported portions. By sublimating and recrystallizing silicon carbide of the supporting portion, the supporting portion is connected to each of the first and second single-crystal substrates. On this occasion, a through hole is formed in the supporting portion so as to be connected to the gap. Accordingly, a path is formed which allows a fluid to pass through the gap and the through hole. By closing this path, the fluid can be prevented from being leaked through the silicon carbide substrate.11-24-2011
20090298258QUASI-HYDROPHOBIC Si-Si WAFER BONDING USING HYDROPHILIC Si SURFACES AND DISSOLUTION OF INTERFACIAL BONDING OXIDE - The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding. Interfacial oxide layers of order of about 2 to about 3 nm are dissolved away by high temperature annealing, for example, an anneal at 1300°-1330° C. for 1-5 hours. The inventive method is used to best advantage when the Si surfaces at the bonded interface have different surface orientations, for example, when a Si surface having a (100) orientation is bonded to a Si surface having a (110) orientation. In a more general aspect of the invention, the similar annealing processes may be used to remove undesired material disposed at a bonded interface of two silicon-containing semiconductor materials. The two silicon-containing semiconductor materials may be the same or different in surface crystal orientation, microstructure (single-crystal, polycrystalline, or amorphous), and composition.12-03-2009
20100035405Method for mounting a thinned semiconductor wafer on a carrier substrate - A method for mounting a thinned semiconductor wafer on a carrier substrate for further processing is disclosed. The method consists of a series of steps, which is based on providing a frame with a double-side tape to mount the thinned wafer on the carrier substrate. The frame is used to support the double-side tape and can be designed to fit the conventional production line for holding, picking and transferring wafers. The carrier substrate can be a sapphire substrate, a quartz substrate or other substrates that can sustain further processing, such as thermal treatments and/or chemical etchings. The method of the present invention not only prevents possible damages to the highly brittle chip after wafer thinning, but also fits the conventional production line for processing semiconductor wafers.02-11-2010
20100003803MANUFACTURING METHOD OF STRAINED SI SUBSTRATE - According to the present invention, there is provided a manufacturing method of a strained Si substrate including at least steps of: forming a lattice-relaxed SiGe layer on a silicon single crystal substrate; flattening a surface of the SiGe layer by CMP; and forming a strained Si layer on the surface of the flattened SiGe layer, wherein the method comprises steps of: subjecting the surface of the SiGe layer to SC1 cleaning, before forming the strained Si layer on the lattice-relaxed SiGe layer surface that is flattened; heat-treating the substrate having the SiGe layer after being subjected to SC1 cleaning in a hydrogen-containing atmosphere at 800° C. or higher; immediately forming a protective Si layer on the SiGe layer surface on the heat-treated substrate, without lowering the temperature below 800° C. after the heat treatment; and forming the strained Si layer on the surface of the protective Si layer at a temperature lower than the temperature of forming the protective Si layer. Thereby, a manufacturing method of a strained Si substrate having low surface roughness, threading dislocation density and low particle level can be provided.01-07-2010
20090098707Method for producing bonded wafer - In a method for producing a bonded wafer by bonding a wafer for active layer to wafer for support layer and then thinning the wafer for active layer, a terrace grinding for forming a terrace portion is carried out prior to a step of exposing the oxygen ion implanted layer to thereby leave an oxide film on a terrace portion of the wafer for support layer.04-16-2009
20090162991PROCESS FOR ASSEMBLING SUBSTRATES WITH LOW-TEMPERATURE HEAT TREATMENTS - The invention relates to a process for producing a bond between a first and a second substrate (06-25-2009
20090149000Combined semiconductor apparatus with thin semiconductor films - A semiconductor apparatus includes two thin semiconductor films bonded to a substrate, and a thin-film interconnecting line electrically connecting a semiconductor device such as a light-emitting device in the first thin semiconductor film to an integrated circuit in the second thin semiconductor film. Typically, the integrated circuit drives the semiconductor device. The two thin semiconductor films are formed separately from the substrate. The first thin semiconductor film may include an array of semiconductor devices. The first and second thin semiconductor films may be replicated as arrays bonded to the same substrate. Compared with conventional semiconductor apparatus comprising an array chip and a separate driver chip, the invented apparatus is smaller and has a reduced material cost.06-11-2009
20080268616SEMICONDUCTOR DEVICE, ITS MANUFACTURE METHOD AND ELECTRONIC COMPONENT UNIT - A LED chip having first and second electrodes on opposite principal surfaces, is bonded to a substrate through a composite bonding layer. The composite bonding layer is formed when a support substrate including the substrate and a first bonding layer is bonded to a lamination structure including the LED, the first electrode and a second bonding layer. The first or second bonding layer contains at least part of eutectic composition. At least one of the support substrate and the lamination structure includes a diffusion material layer. The composite bonding layer is formed in such a manner that eutectic material contents are mixed with the other to form a first mixture, and that the first mixture is mixed with diffusion material to form a second mixture having a melting point higher than a melting point of the first mixture.10-30-2008
20120190171METHOD FOR MANUFACTURING SOI SUBSTRATE - An SOI substrate is manufactured by the following steps: a semiconductor substrate is irradiated with an ion beam in which the proportion of H07-26-2012
20090286382Low-temperature wafer bonding of semiconductor substrates to metal substrates - A method of wafer or substrate bonding a substrate made of a semiconductor material with a substrate made from a metallic material is disclosed. The method allows the bonding of the two substrates together without the use of any intermediate joining gluing, or solder layer(s) between the two substrates. The method allows the moderate or low temperature bonding of the metal and semiconductor substrates, combined with methods to modify the materials so as to enable low electrical resistance interfaces to be realized between the bonded substrates, and also combined with methods to obtain a low thermal resistance interface between the bonded substrates, thereby enabling various useful improvements for fabrication, packaging and manufacturing of semiconductor devices and systems.11-19-2009
20080311725Method For Assembling Substrates By Depositing An Oxide Or Nitride Thin Bonding Layer - A method for assembling by molecular bonding two substrates, at least one of which is made of a semiconductor material characterised in that one of substrates, called a first substrate, includes a surface (A), where at least one portion is flat and provided with an initial surface roughness compatible with the molecular bonding. The inventive method consists in depositing a thin oxide or nitride bonding layer, whose thickness ranges from 10 to 20 nm, on at least one portion of the surface flat part of the first substrate for carrying out a molecular bonding without pre-polishing, in saturating the thin bonding layer with hydroxyl groups, in bringing the thin bonding layer saturated with hydroxyl groups in contact with the second substrate (12-18-2008
20080293216METHOD OF MANUFACTURING AN INKJET HEAD THROUGH THE ANODIC BONDING OF SILICON MEMBERS - In a method of manufacturing an inkjet head, a silicon dioxide (SiO11-27-2008
20080268614Wafer Bonding - A method for providing a stacked wafer configuration is provided. The method includes bonding a first wafer to a second wafer. A filler material is applied in a gap formed along edges of the first wafer and the second wafer. The filler material provides support along the edges during a thinning and transportation process to help reduce cracking or chipping. The filler material may be cured to reduce any bubbling that may have occurred while applying the filler material. Thereafter, the second wafer may be thinned by grinding, plasma etching, wet etching, or the like. In some embodiments of the present invention, this process may be repeated multiple times to create a stacked wafer configuration having three or more stacked wafers.10-30-2008
20080311726Manufacturing method of SOI substrate - There is provided a method of manufacturing an SOI substrate which is practicable even when a supporting substrate having a low allowable temperature limit is used. A separation layer is formed in a region at a certain depth from a surface of a semiconductor substrate, and a first heat treatment is conducted when a semiconductor layer on the separation layer is bonded to the supporting substrate and separated. A second heat treatment is conducted to the supporting substrate to which the semiconductor layer is bonded. The second heat treatment is conducted at a temperature which is equal to or higher than the temperature of the first heat treatment and does not exceed a strain point of the supporting substrate. When the first heat treatment and the second heat treatment are conducted at the same temperature, a treatment time of the second heat treatment may be set to be longer.12-18-2008
20110207291WAFER BONDING DEVICE AND WAFER BONDING METHOD - A wafer bonding method includes: holding a first substrate with an upper holding mechanism 08-25-2011
20080268615Treatment of a Germanium Layer Bonded with a Substrate - The invention relates to a treatment method of a structure comprising a thin Ge layer on a substrate, said layer having been previously bonded with the substrate, the method comprising a treatment to improve the electrical properties of the layer and/or the interface of the Ge layer with the underlying layer, characterised in that said treatment is a heat treatment applied at a temperature between 500° C. and 600° C. for not more than 3 hours.10-30-2008
20090137095METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR SUBSTRATE MANUFACTURING APPARATUS - An object is to provide a uniform semiconductor substrate in which defective bonding is reduced. A further object is to manufacture the semiconductor substrate with a high yield. A first substrate and a second substrate are bonded in a reduced-pressure atmosphere by placing the first substrate at a certain region surrounded by an airtight holding mechanism provided over a support to surround the certain region of a surface of the support; placing the second substrate so as to come to be in contact with the airtight holding mechanism to ensure airtightness of a space surrounded by the support, the airtight holding mechanism, and the second substrate; evacuating the space whose airtightness is secured, thereby reducing an pressure in the space; disposing the second substrate in close contact with the first substrate using difference between the pressure in the space and outside atmpspheric pressure; and performing heat treatment.05-28-2009
20090130821THREE DIMENSIONAL PACKAGING WITH WAFER-LEVEL BONDING AND CHIP-LEVEL REPAIR - A method, a system and a computer readable medium for three dimensional packaging with wafer-level bonding and chip-level repair. A first wafer is provided having a first plurality of chips. A second wafer is provided having a second plurality of chips. At least one chip is removed from the second wafer while retaining the relative alignment of the remaining chips in the second wafer. The first and second wafers are aligned and joined with wafer-to-wafer techniques. Where a bad chip having a relative physical position within the second wafer corresponding to a relative physical position within the first wafer of a good chip is removed, a good chip may be aligned and bonded to the first wafer using die-to-wafer techniques.05-21-2009
20090137096Clamp ring for wafer and method of manufacturing semiconductor apparatus - A clamp ring includes an abutting part abutting on the entire outer periphery of the main surface of a wafer when the wafer is fixed, and a brim part extending from the upper part of the abutting part to the inside of the wafer and provided so as not to abut on the main surface even when the wafer is fixed. The abutting part includes a first abutting section and a second abutting section, and a width of the first abutting section in a radial direction is greater than the width of the second abutting section in a radial direction.05-28-2009
20120094469PROCESS FOR REALISING A CONNECTING STRUCTURE - The present invention relates to a process for realizing a connecting structure in a semiconductor substrate, and the semiconductor substrate realized accordingly. The semi-conductor substrate has at least a first surface, and is foreseen for a 3D integration with a second substrate along the first surface, wherein the 3D integration is subject to a lateral misalignment in at least one dimension having a misalignment value. This process includes growing a diffusion barrier structure for preventing diffusion of elements out of a conductive layer into the rest of the semiconductor substrate, wherein a first end surface, being the most outward surface of the diffusion barrier structure and being substantially parallel to the first surface, along a direction perpendicular to the first surface and going from the substrate toward the first surface, of the diffusion barrier structure can have a length, in the direction of the lateral misalignment, the length being dependent on the misalignment value, wherein the length of the diffusion barrier structure is chosen such that in a 3D integrated structure a diffusion of elements out of a conductive layer of the second substrate is prevented in the integrated state.04-19-2012
20090142903CHIP ON WAFER BONDER - The present disclosure provides a bonding apparatus. The bonding apparatus includes a cleaning module designed for cleaning chips; and a chip-to-wafer bonding chamber configured to receive the chips from the cleaning module and designed for bonding the chips to a wafer.06-04-2009
20090325362METHOD OF RECYCLING AN EPITAXIED DONOR WAFER - A method for forming a semiconductor structure that includes a thin layer of semiconductor material on a receiver wafer is disclosed. The method includes removing a thickness of material from a donor wafer, which comprises a support substrate and an epitaxial layer, for surface preparation and transferring a portion of the epitaxial layer from the donor wafer to the receiver wafer. The thickness removed during the surface preparation is adapted to enable formation of a new semiconductor structure from the remaining epitaxial portion of the donor wafer.12-31-2009
20080233710METHODS FOR FORMING SINGLE DIES WITH MULTI-LAYER INTERCONNECT STRUCTURES AND STRUCTURES FORMED THEREFROM - A method for forming a single die includes forming at least one first active device over a first substrate and at least one first metallic layer coupled to the first active device. At least one second metallic layer is formed over a second substrate, wherein the second substrate does not include any active device The at least one fist metallic layer is bonded with the at least one second metallic layer such that the first substrate and the second substrate constitute a single die.09-25-2008
20090181518MANUFACTURING METHOD AND MANUFACTURING APPARATUS OF SEMICONDUCTOR SUBSTRATE - It is an object to provide a homogeneous semiconductor substrate in which defective bonding is reduced. Such a semiconductor substrate can be formed by the steps of: disposing a first substrate in a substrate bonding chamber which includes a substrate supporting base where a plurality of openings is provided, substrate supporting mechanisms provided in the plurality of openings, and raising and lowering mechanisms which raise and lower the substrate supporting mechanisms; disposing a second substrate over the first substrate so as not to be in contact with the first substrate; and bonding the first substrate to the second substrate by using the raising and lowering mechanisms to raise the substrate supporting mechanisms.07-16-2009
20110143520TWO-CHAMBER SYSTEM AND METHOD FOR SERIAL BONDING AND EXFOLIATION OF MULTIPLE WORKPIECES - A system for treating distinct batches of workpieces to serial procedures comprises first and second multi-site structures. In each multi-site structure the sites are rotatable for alignment in turn with loading and unloading stations together constituting treatment or process stations. Workpieces of a batch are loaded onto all of the treatment sites and then simultaneously and identically treated by operation of treatment stations with which the process sites are aligned. After treatment in the first structure, workpieces of a batch are transferred from the unloading stations of the first structure to the loading stations of the second structure for further processing.06-16-2011
20090081848WAFER BONDING ACTIVATED BY ION IMPLANTATION - A method for wafer bonding two substrates activated by ion implantation is disclosed. An in situ ion bonding chamber allows ion activation and bonding to occur within an existing process tool utilized in a manufacturing process line. Ion activation of at least one of the substrates is performed at low implant energies to ensure that the wafer material below the thin surface layers remains unaffected by the ion activation.03-26-2009
20090197390LOCK AND KEY STRUCTURE FOR THREE-DIMENTIONAL CHIP CONNECTION AND PROCESS THEREOF - A method positions a first wafer with respect to a second wafer such that key studs on the first wafer are fit (positioned) within lock openings in the second wafer. The key studs contact conductors within the second wafer. The edges of the first wafer are tacked to the edges of the second wafer. Then the wafers are pressed together and heat is applied to bond the wafers together. One feature of embodiments herein is that because the lock openings extend through an outer oxide (instead of a polyimide) the first wafer can be attached to the second wafer by using processing that occurs in the middle-of-the-line (MOL).08-06-2009
20090246934METHOD FOR MANUFACTURING SOI SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing an SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced is provided. An oxide film containing halogen is formed on each of surfaces of a single crystal semiconductor substrate and of a semiconductor substrate provided with a single crystal semiconductor layer separated from the single crystal semiconductor substrate, whereby impurities that exist on the surfaces of and inside the substrates are decreased. In addition, the single crystal semiconductor layer provided over the semiconductor substrate is irradiated with a laser beam, whereby crystallinity of the single crystal semiconductor layer is improved and planarity is improved.10-01-2009
20090253245Wafer Bonding method and wafer structure - A wafer bonding method includes providing a primary wafer and a plurality of secondary wafers, wherein the primary wafer is larger than the secondary wafers. An intermediate material layer is formed on at least one of a bonding surface of the primary wafer and bonding surfaces of the secondary wafers. The intermediate material layer has a thermal expansion coefficient greater than the thermal expansion coefficient of the primary wafer and the thermal expansion coefficient of the secondary wafers. The secondary wafers are bonded onto the primary wafer.10-08-2009
20090246933METHOD OF PRODUCING A STRAINED LAYER - A method of producing a strained layer on a substrate includes assembling a layer with a first structure or first means of straining including at least one substrate or one layer capable of being deformed within a plane thereof under the influence of an electric or magnetic field or a photon flux. The layer is strained by modifying the electric or magnetic field or the photon flux. The strained layer is assembled with a transfer substrate and all or part of the first straining structure is removed.10-01-2009
20100261332WAFER CLEANING METHOD AND WAFER BONDING METHOD USING THE SAME - The present invention relates to a wafer cleaning and a wafer bonding method using the same that can improve a yield of cleaning process and bonding property in bonding the cleaned wafer by cleaning the wafer using atmospheric pressure plasma and cleaning solution. The wafer cleaning method includes the steps of providing a process chamber with a wafer whose bonding surface faces upward, cleaning and surface-treating the bonding surface of the wafer by supplying atmospheric pressure plasma and a cleaning solution to the bonding surface of the wafer, and withdrawing out the wafer from the process chamber. The wafer bonding method includes the steps of: providing a first process chamber with a first wafer whose bonding surface faces upward; cleaning and surface-treating the bonding surface of the first wafer by supplying atmospheric pressure plasma and a cleaning solution to the bonding surface of the first wafer; withdrawing out the first wafer from the first process chamber and providing a second process chamber with the first wafer; providing a third process chamber with a second wafer whose bonding surface faces upward; cleaning and surface-treating the bonding surface of the second wafer by supplying atmospheric pressure plasma and a cleaning solution to the bonding surface of the second wafer; withdrawing out the second wafer from the third process chamber and providing the second process chamber with the second wafer whose bonding surface faces to the bonding surface of the first wafeη and bonding the bonding surfaces of the first and second wafers to each other.10-14-2010
20110111574METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A nitride-based semiconductor crystal and a second substrate are bonded together. In this state, impact is applied externally to separate the low-dislocation density region of the nitride-based semiconductor crystal along the hydrogen ion-implanted layer, thereby transferring (peeling off) the surface layer part of the low-dislocation density region onto the second substrate. At this time, the lower layer part of the low-dislocation density region stays on the first substrate without being transferred onto the second substrate. The second substrate onto which the surface layer part of the low-dislocation density region has been transferred is defined as a semiconductor substrate available by the manufacturing method of the present invention, and the first substrate on which the lower layer part of the low-dislocation density region stays is reused as a substrate for epitaxial growth.05-12-2011
20080280419METHOD FOR NANOSTRUCTURING OF THE SURFACE OF A SUBSTRATE - Under consideration here is a method for the production of periodic nanostructuring on one of the surfaces of a substrate (11-13-2008
20090111241WAFER BONDING METHOD - A method includes steps of providing first and second substrates, and forming a bonding interface between them using a conductive bonding region. A portion of the second substrate is removed to form a mesa structure. A vertically oriented semiconductor device is formed with the mesa structure. A portion of the conductive bonding region is removed to form a contact. The vertically oriented semiconductor device is carried by the contact.04-30-2009
20110129986NITROGEN-PLASMA SURFACE TREATMENT IN A DIRECT BONDING METHOD - Two plates, each comprising a thin layer of silicon or silicon oxide at a surface thereof, are bonded by subjecting the thin layer of at least one of the plates to a surface treatment step forming a silicon oxynitride superficial thin film with a thickness of less than 5 nm. The thin film is performed with a nitrogen-based plasma generated by an inductively coupled plasma source. Furthermore, a potential difference applied between the plasma and a substrate holder supporting said plate during the surface treatment step is less than 50 V, advantageously less than 15 V and preferably zero. This enables a defect-free bonding interface to be obtained irrespective of a temperature of any heat treatment carried out after a contacting step between the respective thin layers of the two plates.06-02-2011
20100297827METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An adhesion layer and a supporting substrate are provided on the entire surface of the first surface side of a substrate with a metal seed film provided on the first surface side of the substrate. After the removal of the adhesion layer and the supporting substrate provided on the first surface of the substrate, an exposed part of the metal seed film is removed. After this, a plurality of semiconductor chips is stacked and first reflow is performed to the semiconductor chips.11-25-2010
20110086492REPROCESSING METHOD OF SEMICONDUCTOR SUBSTRATE, MANUFACTURING METHOD OF REPROCESSED SEMICONDUCTOR SUBSTRATE, AND MANUFACTURING METHOD OF SOI SUBSTRATE - An object of an embodiment of the disclosed invention is to provide a method suitable for reprocessing a semiconductor substrate which is reused to manufacture an SOI substrate. A semiconductor substrate is reprocessed in the following manner: etching treatment is performed on a semiconductor substrate in which a step portion including a damaged semiconductor region and an insulating layer exists in a peripheral portion, whereby the insulating layer is removed; etching treatment is performed on the semiconductor substrate with the use of a mixed solution including a substance that oxidizes a semiconductor material included in the semiconductor substrate, a substance that dissolves the oxidized semiconductor material, and a substance that controls oxidation speed of the semiconductor material and dissolution speed of the oxidized semiconductor material, whereby the damaged semiconductor region is selectively removed with a non-damaged semiconductor region left; and heat treatment under an atmosphere including hydrogen is performed.04-14-2011
20100035406METHOD OF MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR LAYER BONDED SUBSTRATE - The present method of manufacturing a group III nitride semiconductor layer bonded substrate includes the steps of: implanting ions I of at least any of hydrogen and helium in a region having a prescribed depth D from one main surface of a group III nitride semiconductor substrate; bonding a different-composition substrate with the main surface of the group III nitride semiconductor substrate; obtaining a group III nitride semiconductor layer bonded substrate by separating the group III nitride semiconductor substrate at a region implanted with the ions I; and annealing the group III nitride semiconductor layer bonded substrate at a temperature not lower than 700° C. in an atmosphere of a nitrogen-containing gas N. Thus, a group III nitride semiconductor layer bonded substrate high in crystallinity of a group III nitride semiconductor layer is provided.02-11-2010
20120244678SEMICONDUCTOR DEVICE WAFER BONDING METHOD - A semiconductor device wafer bonding method bonds a first semiconductor device wafer having a plurality of semiconductor devices with a plurality of projecting electrodes to a second semiconductor device wafer having a plurality of electrodes respectively corresponding to the projecting electrodes of the first semiconductor device wafer. An insulator is applied and fills the spacing between adjacent projecting electrodes. The first semiconductor device wafer is planarized to expose the end surfaces of the projecting electrodes, and the first semiconductor device wafer is bonded to the second semiconductor device wafer with an anisotropic conductor interposed between the projecting electrodes of the first semiconductor device wafer and the electrodes of the second semiconductor device wafer, to thereby respectively connect the electrodes through the anisotropic conductor.09-27-2012
20120244677METHOD AND APPARATUS FOR SELECTIVELY REMOVING ANTI-STICTION COATING - The present disclosure provides various methods for removing an anti-stiction layer. An exemplary method includes forming an anti-stiction layer over a substrate, including over a first substrate region of a first material and a second substrate region of a second material, wherein the second material is different than the first material; and selectively removing the anti-stiction layer from the second substrate region of the second material without using a mask.09-27-2012
20090035919IN-PLACE BONDING OF MICROSTRUCTURES - A method for bonding microstructures to a semiconductor substrate using attractive forces, such as, hydrophobic, van der Waals, and covalent bonding is provided. The microstructures maintain their absolute position with respect to each other and translate vertically onto a wafer surface during the bonding process. The vertical translation of the micro-slabs is also referred to herein as “in-place bonding”. Semiconductor structures which include the attractively bonded microstructures and substrate are also disclosed.02-05-2009
20100055871MEMORY IN LOGIC CELL - Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate, and a third gate, e.g., a control gate, a back gate, and a floating gate, as a memory in logic cell. The method includes programming the floating gate to a first state to cause the memory in logic cell to operate as a first logic gate type. The method further includes programming the floating gate to a second state to cause the memory in logic cell to operate as a second logic gate type.03-04-2010
20090317960WAFER BONDING APPARATUS - Provided is a wafer bonding apparatus which performs pressurization and heating and eliminates nonuniformity of wafer thickness by changing the shape of a pressurizing surface so that planarity of a wafer bonding surface is improved. The wafer bonding apparatus places a plurality of wafers to be bonded between an upper unit (12-24-2009
20120276715METHOD FOR MANUFACTURING COMBINED SUBSTRATE HAVING SILICON CARBIDE SUBSTRATE - A connected substrate having a supporting portion and first and second silicon carbide substrates is prepared. The first silicon carbide substrate has a first backside surface connected to the supporting portion, a first front-side surface, and a first side surface connecting the first backside surface and the first front-side surface to each other. The second silicon carbide substrate has a second backside surface connected to the supporting portion, a second front-side surface, and a second side surface connecting the second backside surface and the second front-side surface to each other and forming a gap between the first side surface and the second side surface. A filling portion for filling the gap is formed. Then, the first and second front-side surfaces are polished. Then, the filling portion is removed. Then, a closing portion for closing the gap is formed.11-01-2012
20080254594STRAINED SILICON CMOS ON HYBRID CRYSTAL ORIENTATIONS - Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.10-16-2008
20120122298METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - Defects in a semiconductor substrate are reduced. A semiconductor substrate with fewer defects is manufactured with high yield. Further, a semiconductor device is manufactured with high yield. A semiconductor layer is formed over a supporting substrate with an oxide insulating layer interposed therebetween, adhesiveness between the supporting substrate and the oxide insulating layer in an edge portion of the semiconductor layer is increased, an insulating layer over a surface of the semiconductor layer is removed, and the semiconductor layer is irradiated with laser light, so that a planarized semiconductor layer is obtained. For increasing the adhesiveness between the supporting substrate and the oxide insulating layer in the edge portion of the semiconductor layer, laser light irradiation is performed from the surface of the semiconductor layer.05-17-2012
20110053343METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - There are provided a semiconductor device having a structure which can realize not only suppression of a punch-through current but also reuse of a silicon wafer used for bonding, in manufacturing a semiconductor device using an SOI technique, and a manufacturing method thereof. A semiconductor film into which an impurity imparting a conductivity type opposite to that of a source region and a drain region is implanted is formed over a substrate, and a single crystal semiconductor film is bonded to the semiconductor film by an SOI technique to form a stacked semiconductor film. A channel formation region is formed using the stacked semiconductor film, thereby suppressing a punch-through current in a semiconductor device.03-03-2011
20110053342SEMICONDUCTOR SUBSTRATE SURFACE PREPARATION METHOD - The invention relates to a method for preparing a surface of a semiconductor substrate by oxidizing the surface of the semiconductor substrate to thereby transform the natural oxide into an artificial oxide and then removing the artificial oxide, in particular to obtain an oxide-free substrate surface.03-03-2011
20110027967METHOD FOR INSERTION BONDING AND DEVICE THUS OBTAINED - A method for insertion bonding and a device thus obtained are disclosed. In one aspect, the device includes a first substrate having a front main surface and at least one protrusion at the front main surface. The device includes a second substrate having a front main surface and at least one hole extending from the front main surface into the second substrate. The protrusion of the first substrate is inserted into the hole of the second substrate. The hole is formed in a shape wherein the width is reduced in the depth direction and wherein the width of at least a part of the hole is smaller than the width of the protrusion at the location of the metal portion thereof. The protrusion is deformed during insertion thereof in the hole to provide a bond between the part of the hole and the metal portion.02-03-2011
20110189834SURFACE TREATMENT FOR MOLECULAR BONDING - A method of bonding a first substrate to a second substrate by molecular bonding by forming an insulating layer on the bonding face of the first substrate, chemical-mechanical polishing of the insulating layer, activating a bonding surface of the second substrate by plasma treatment, etching an exposed surface of the insulating layer, and bonding together the two substrates together by molecular bonding wherein the etching is conducted after the chemical-mechanical polishing and before the bonding.08-04-2011
20100120222Methods and apparatus for bonding wafers - In a method of and apparatus for bonding wafers, the method includes heating a first wafer having a first coefficient of thermal expansion (CTE) until the first wafer reaches a first temperature, heating a second wafer having a second CTE that is different from the first CTE until the second wafer reaches a second temperature that is different from the second temperature, and bonding the first wafer and the second wafer to each other.05-13-2010
20100330776BONDING APPARATUS AND METHOD - A bonding apparatus and method holds first and second bodies peripherally, one above the other, on respective shelves. A lower heat-transfer body is configured to lift the first body from below and press the first and second bodies against an upper heat-transfer body to enable bonding between the first and second bodies.12-30-2010
20090170284Adhesive Composition, Adhesive Sheet and Production Process for Semiconductor Device - The object of the present invention is to provide an adhesive composition which can form a thinner adhesive layer, which has good storage stability and which can actualize high package reliability even when exposed to severe reflow conditions in a semiconductor package in which a semiconductor chip being reduced in a thickness is mounted, and an adhesive sheet having an adhesive layer comprising the adhesive composition.07-02-2009
20120252189METHODS FOR BONDING SEMICONDUCTOR STRUCTURES INVOLVING ANNEALING PROCESSES, AND BONDED SEMICONDUCTOR STRUCTURES AND INTERMEDIATE STRUCTURES FORMED USING SUCH METHODS - Methods of bonding together semiconductor structures include annealing metal of a feature on a semiconductor structure prior to directly bonding the feature to a metal feature of another semiconductor structure to form a bonded metal structure, and annealing the bonded metal structure after the bonding process. The thermal budget of the first annealing process may be at least as high as a thermal budget of a later annealing process. Additional methods involve forming a void in a metal feature, and annealing the metal feature to expand the metal of the feature into the void. Bonded semiconductor structures and intermediate structures are formed using such methods.10-04-2012
20120156857CONTINUOUS METAL SEMICONDUCTOR ALLOY VIA FOR INTERCONNECTS - Methods of forming a semiconductor structure including a semiconductor nanowire or epitaxial semiconductor material which extends from at least a surface of source region and the drain region are provided. The methods include converting an upper portion of the source region and the drain region and the semiconductor nanowire or epitaxial semiconductor material into a continuous metal semiconductor alloy. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each of the source region and the drain region, and a vertical pillar portion extending upwardly from the lower portion.06-21-2012
20110092049METHOD AND APPARATUS FOR SUBSTRATE BONDING - Methods for bonding a first substrate to a second substrate are described. A surface of the first substrate is coated with an adhesive layer. The adhesive layer is cured to b-stage. The surface of the first substrate is positioned in contact with the second substrate. An edge of the first substrate is pressed to an edge of the second substrate to initiate Van der Waals bonding. The first and second substrates are allowed to come together by Van der Waals bonding. The bonded first and second substrates are subjected to a sufficient heat for a sufficient time period to cure completely the adhesive layer.04-21-2011
20100093152METHOD OF BONDING TWO SUBSTRATES - The invention relates to a method of forming a structure comprising a thin layer of semiconductor material transferred from a donor substrate onto a second substrate, wherein two different atomic species are co-implanted under certain conditions into the donor substrate so as to create a weakened zone delimiting the thin layer to be transferred. The two different atomic species are implanted so that their peaks have an offset of less than 200 Å in the donor substrate, and the substrates are bonded together after roughening at least one of the bonding surfaces.04-15-2010
20120077329DIRECT BONDING METHOD WITH REDUCTION IN OVERLAY MISALIGNMENT - A method for the direct bonding of a first wafer having an intrinsic curvature before bonding to a second wafer having an intrinsic curvature before bonding, at least one of the two wafers comprising at least one series of microcomponents. The method includes of bringing the two wafers into contact with each other so as to initiate the propagation of a bonding wave therebetween while imposing a predefined bonding curvature in the form of a paraboloid of revolution on one of the two wafers depending at least upon the intrinsic curvature before bonding of the wafer that includes the microcomponents, with the other wafer being free to conform to the predefined bonding curvature.03-29-2012
20120214290SUBSTRATE HOLDER, PAIR OF SUBSTRATE HOLDERS, SUBSTRATE BONDING APPARATUS AND METHOD FOR MANUFACTURING DEVICES - Provided is a substrate holder pair comprising a first substrate holder that has a first holding portion holding a first substrate; a second substrate holder that has a second holding portion holding a second substrate to be bonded with the first substrate and that, together with the first substrate holder, sandwiches the first substrate and the second substrate; an engaging member that causes the first substrate holder to engage with the second substrate holder; and a dust inhibiting section inhibits dust generated by the engaging of the engaging member from entering between the first holding portion and the second holding portion.08-23-2012
20100009514METHOD OF FABRICATING MICRO-VERTICAL STRUCTURE - A method of fabricating a micro-vertical structure is provided. The method includes bonding a second crystalline silicon (Si) substrate onto a first crystalline Si substrate by interposing an insulating layer pattern and a cavity, etching the second crystalline Si substrate using a deep reactive ion etch (DRIE) process along a [111] crystal plane vertical to the second crystalline Si substrate, and etching an etched vertical surface of the second crystalline Si substrate using a crystalline wet etching process to improve the surface roughness and flatness of the etched vertical surface. As a result, no morphological defects occur on the etched vertical surface. Also, footings do not occur at an etch end-point due to the insulating layer pattern. In addition, the micro-vertical structure does not float in the air but is fixed to the first crystalline Si substrate, thereby facilitating subsequent processes.01-14-2010
20120220101INTERNAL CONDUCTIVE LAYER - The invention provides advances in the arts with useful and novel methods for assembling multi-layer semiconductor structures having one or more internal conductive layers. The disclosed structures provide advantages in terms of resistance to Single Event Effects (SEE) particularly useful in electronics designed for radiation hardness. Disclosed methods include steps for providing two semiconductor layers, each having a conductive surface, and bonding them together with their conductive surfaces adjoining in order to form an internal conductive layer within a completed multi-layer structure. The conductive surfaces may include metals selected for their superior conductivity, refractory metals, selected primarily for their heat-resistance, or conductive dopants. In alternative embodiments, vertical interconnects are also included.08-30-2012
20120258579DESIGN, LAYOUT, AND MANUFACTURING TECHNIQUES FOR MULTIVARIANT INTEGRATED CIRCUITS - Techniques for the integral design, layout, and manufacture of integrated circuits include designing an integrated circuit that includes one variant having a plurality of a modular circuits communicatively coupled together and a second variant having a sub-set of the plurality of modular circuits. The modular circuits are then laid out on a wafer for fabricating each of the variants of the integrated circuit. The layout includes primary scribe boundaries separating each set of the plurality of modular circuits of the first variant. The layout also includes secondary scribe boundaries separating the sub-set of the plurality of modular circuits of the second variant from the other modular circuits in the first variant. The layout further includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last. Fabricating the integrated circuit is then started, up to but not including the one or more metallization layers to be fabricated last, according to the layout. A demand for each of the integrated circuit variants is predicted during fabrication of the integrated circuit up to but not including the one or more metallization layers to be fabricated last. One or more of the plurality of variants of the integrated circuit is selected based upon the predicted demand. Fabrication then continues with the last one or more metallization layers of the integrated circuit according to the layout of the selected one or more variants of the integrated circuit. The wafer is then singulated into a plurality of integrated circuit die according to the layout of the selected one or more variants of the integrated circuit.10-11-2012
20110045653BONDING METHOD AND BONDING APPARATUS - [Object] To facilitate bonding of articles at a low temperature without degrading electrical contact between the articles.02-24-2011
20100233866METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A nitride-based semiconductor crystal and a second substrate are bonded together. In this state, impact is applied externally to separate the low-dislocation density region of the nitride-based semiconductor crystal along the hydrogen ion-implanted layer, thereby transferring (peeling off) the surface layer part of the low-dislocation density region onto the second substrate. At this time, the lower layer part of the low-dislocation density region stays on the first substrate without being transferred onto the second substrate. The second substrate onto which the surface layer part of the low-dislocation density region has been transferred is defined as a semiconductor substrate available by the manufacturing method of the present invention, and the first substrate on which the lower layer part of the low-dislocation density region stays is reused as a substrate for epitaxial growth.09-16-2010
20120088350METHOD FOR MOLECULAR BONDING OF SILICON AND GLASS SUBSTRATES - The present invention concerns a method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates.04-12-2012
20120329241SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR MANUFACTURING METHOD - According to one embodiment, a semiconductor manufacturing apparatus is provided. The semiconductor manufacturing apparatus includes a stage, a substrate supporter, first and second pushers, and a controller. The stage is configured to support outer periphery portions of the first semiconductor substrate from below. The substrate supporter is configured to hold the back of the second semiconductor substrate. The first and second pushers are configured to bring the first and second semiconductor substrates in contact. The controller is configured to form the bonding initiation point between the first and second semiconductor substrates.12-27-2012
20100167498SUBSTRATE LEVEL BONDING METHOD AND SUBSTRATE LEVEL PACKAGE - Disclosed are a substrate level bonding method and a substrate level package formed thereby. The substrate level package includes a plurality of unit substrate sections, a base substrate, and a plurality of substrate adhesion sections. The unit substrate sections are separated from each other by holes. The base substrate is disposed to face the unit substrate sections. The substrate adhesion sections are interposed between the unit substrate sections and the base substrate to bond the unit substrate sections to the base substrate and which are formed of DFR material, whose at least one portion is uncured.07-01-2010
20090239353Methods For Forming Multi-layer Three-Dimensional Structures - The embodiments of the present invention are directed to the formation of multi-layer three-dimensional structures by forming and attaching a plurality of individual layers where each of the layers comprises one or more materials forming a desired pattern. In one embodiment, a multi-layer three-dimensional structure is formed by forming a plurality of individual layers and attaching at least them together. In another embodiment, a multi-layer three-dimensional structure is formed by 1) forming one or more individual layers, 2) attaching the one or more formed layers onto a substrate, 3) if desired, forming new structures on the attached one or more layers. In still another embodiment, a multi-layer three-dimensional structure is formed by 1) attaching a layer of a material onto a substrate; 2) processing the attached layer to form a desired pattern; 3) attaching another layer of a material onto the previously formed layer; 4) processing the new attached layer to form a desired pattern, and 5) if desired, repeating the steps of 3) and 4) one or more times.09-24-2009
20080227270LOW TEMPERATURE FUSION BONDING WITH HIGH SURFACE ENERGY USING A WET CHEMICAL TREATMENT - Described is a wet chemical surface treatment involving NH09-18-2008
20130115752Pick-and-Place Tool for Packaging Process - An apparatus includes a guide ring, and a bond head installed on the guide ring. The bond head is configured to move in loops along the guide ring. The bond head is configured to pick up dies and place the dies during the loops05-09-2013
20080200009Methods of Forming Stacked Semiconductor Devices with Single-Crystal Semiconductor Regions - Spaced apart bonding surfaces are formed on a first substrate. A second substrate is bonded to the bonding surfaces of the first substrate and cleaved to leave respective semiconductor regions from the second substrate on respective ones of the spaced apart bonding surfaces of the first substrate. The bonding surfaces may include surfaces of at least one insulating region on the first substrate, and at least one active device may be formed in and/or on at least one of the semiconductor regions. A device isolation region may be formed adjacent the at least one of the semiconductor regions.08-21-2008
20080200008BONDING INTERFACE QUALITY BY COLD CLEANING AND HOT BONDING - The invention relates to improvements in a method for molecularly bonding first and second substrates together by placing them in surface to surface contact. The improvement includes, prior to placing the substrates in contact, cleaning the surface of one or both of the substrates in a manner to provide a cleaned surface that is slightly roughened compared to a conventionally polished surface, and heating at least one or both of the substrates prior to placing the substrates in contact while retaining the heating at least until the substrates are in surface to surface contact.08-21-2008
20130149839APPARATUS FOR BONDING SUBSTRATES TO EACH OTHER - An apparatus for bonding at least two substrates to each other comprises a plurality of substrate bonding machines arranged adjacent to one another and an input transporter extending adjacent to the plurality of substrate bonding machines which is operative to deliver the substrates to each of the substrate bonding machines. The input transporter is supplied with substrates by an onloading station. An output transporter extending adjacent to the plurality of substrate bonding machines is operative to receive bonded substrates from each of the substrate bonding machines and deliver the bonded substrates to an offloading station for removal from the apparatus.06-13-2013
20110275191Method of Manufacturing Semiconductor Device - A method of forming a semiconductor device is provided, including a step of forming a layer which absorbs light over one face of a first substrate, a step of providing a second substrate over the layer which absorbs light, a step of providing a mask to oppose the other face of the first substrate, and a step of transferring the part of the layer which absorbs light to the second substrate by irradiating the layer which absorbs light with a laser beam through the mask.11-10-2011
20110275192FUSION BONDING PROCESS AND STRUCTURE FOR FABRICATING SILICON-ON-INSULATION (SOI) SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor-on-insulator device including: providing a first semiconductor wafer having an about 500 angstrom thick oxide layer thereover; etching the first semiconductor wafer to raise a pattern therein; doping the raised pattern of the first semiconductor wafer through the about 500 angstrom thick oxide layer; providing a second semiconductor wafer having an oxide thereover; and, bonding the first semiconductor wafer oxide to the second semiconductor wafer oxide at an elevated temperature.11-10-2011
20130157438SUBSTRATE HOLDING UNIT, SUBSTRATE BONDING APPARATUS, MULTI-LAYERED SUBSTRATE MANUFACTURING APPARATUS, SUBSTRATE BONDING METHOD, MULTI-LAYER SUBSTRATE MANUFACTURING METHOD, AND MULTI-LAYERED SEMICONDUCTOR APPARATUS MANUFACTURING METHOD - Provided is a substrate holding unit that holds a pair of substrates that are aligned and layered, comprising a first holding member that holds one of the substrates; a plurality of members to be joined that are connected to the first holding member; a second holding member that holds the other of the substrates to face the one of the substrates; a plurality of joining members that exert an adhesion force on the members to be joined and are connected to the second holding member at positions corresponding to positions of the members to be joined; and an adhesion restricting section that restricts the adhesion force until the substrates are aligned.06-20-2013
20120015497Preparing a Surface of a Sapphire Substrate for Fabricating Heterostructures - A method of fabricating a heterostructure comprising at least a first substrate (01-19-2012
20120295415METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, comprising bonding a first principal surface of a substrate to a supporting substrate through a light-to-heat conversion film, and removing a portion of the light-to-heat conversion film exposed on the supporting substrate. A method of manufacturing a semiconductor device, comprising forming a light-to-heat conversion film on a supporting substrate, bonding a semiconductor substrate to the supporting substrate, so that the light-to-heat conversion film extends outside the semiconductor substrate, performing an anti-contamination treatment on the light-to-heat conversion film, and separating the supporting substrate and the semiconductor substrate from each other.11-22-2012
20120070958METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device of an embodiment, at room temperature, a first substrate including a semiconductor laminate body is adhered to a second substrate with a smaller thermal expansion coefficient than that of the first substrate. Then, the first substrate and the second substrate are heated with the first substrate heated at a temperature higher than that of the second substrate. Thus the first substrate and the second substrate are bonded together. The first substrate is either a sapphire substrate including a nitride-based semiconductor layer, or a GaAs substrate including a phosphorus-based semiconductor layer. The second substrate is a silicon substrate, a GaAs substrate, a Ge substrate, or a metal substrate.03-22-2012

Patent applications in class BONDING OF PLURAL SEMICONDUCTOR SUBSTRATES

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