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Grooved and refilled with deposited dielectric material

Subclass of:

438 - Semiconductor device manufacturing: process

438400000 - FORMATION OF ELECTRICALLY ISOLATED LATERAL SEMICONDUCTIVE STRUCTURE

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
438435000 Multiple insulative layers in groove 68
438430000 And deposition of polysilicon or noninsulative material into groove 50
438425000 Combined with formation of recessed oxide by localized oxidation 36
438427000 Refilling multiple grooves of different widths or depths 27
438433000 Dopant addition 21
438429000 And epitaxial semiconductor formation in groove 15
438438000 Reflow of insulator 5
20090098706Methods of Forming Integrated Circuit Devices Having Ion-Cured Electrically Insulating Layers Therein - Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1004-16-2009
20080242047METHOD OF FORMING ISOLATION STRUCTURE OF SEMICONDUCTOR MEMORY DEVICE - The present invention relates to a method of forming isolation layers of a semiconductor memory device. According to a method of forming isolation layers of a semiconductor memory device in accordance with an aspect of the present invention, a tunnel dielectric layer, a conductive layer for a floating gate, a buffer oxide layer, and a pad nitride layer are sequentially formed over a semiconductor substrate. A trench is formed by selectively etching the pad nitride layer, the buffer oxide layer, the conductive layer for the floating gate, the tunnel dielectric layer, and the semiconductor substrate. The trench is gap-filled by forming a dielectric layer over the entire structure including the trench. A curing process is performed using a pre-heated curing gas. A height of the isolation layers is controlled by performing a cleaning process.10-02-2008
20110027966Method for Fabricating Isolation Layer in Semiconductor Device - A method for fabricating an isolation layer in a semiconductor device, comprising: forming a trench in a semiconductor substrate; forming a flowable insulation layer on the trench and the semiconductor substrate; converting the flowable insulation layer to a silicon oxide layer by implementing a curing process comprising continuously heating the flowable insulation layer; and forming an isolation layer by planarizing the silicon oxide layer.02-03-2011
20110129985METHODS FOR FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES - A shallow isolation trench structure and methods of forming the same wherein the method of formation comprises a layered structure of a buffer film layer over a dielectric layer that is atop a semiconductor substrate. The buffer film layer comprises a material that is oxidation resistant and can be etched selectively to oxide films. The layered structure is patterned with a resist material and etched to form a shallow trench. A thin oxide layer is formed in the trench and the buffer film layer is selectively etched to move the buffer film layer back from the corners of the trench. An isolation material is then used to fill the shallow trench and the buffer film layer is stripped to form an isolation structure. When the structure is etched by subsequent processing step(s), a capped shallow trench isolation structure that covers the shallow trench corners is created.06-02-2011
20100105189METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE - A method of fabricating a semiconductor device includes applying a coating oxide film to a surface of a substrate including a semiconductor substrate so that a recess formed in the surface is filled with the coating oxide film, applying a steam oxidation treatment to the substrate at a first temperature, soaking the substrate in heated water while applying a megasonic wave to the substrate in the heated water, and applying a steam oxidation treatment to the substrate at a second temperature higher than the first temperature.04-29-2010
Entries
DocumentTitleDate
20110177671METHODS OF FORMING A SEMICONDUCTOR CELL ARRAY REGION, METHOD OF FORMING A SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTOR CELL ARRAY REGION, AND METHOD OF FORMING A SEMICONDUCTOR MODULE INCLUDING THE SEMICONDUCTOR DEVICE - Methods of forming a semiconductor cell array region, a method of forming a semiconductor device including the semiconductor cell array region, and a method of forming a semiconductor module including the semiconductor device are provided, the methods of forming the semiconductor cell array region include preparing a semiconductor plate. A semiconductor layer may be formed over the semiconductor plate. The semiconductor layer may be etched to form semiconductor pillars over the semiconductor plate.07-21-2011
20120202335METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES INCLUDING VOIDS BETWEEN ACTIVE REGIONS AND RELATED DEVICES - A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.08-09-2012
20090197388METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including at leasty one of the following steps: sequentially forming a first oxide layer, a nitride layer, a second oxide layer, a bottom anti-reflect coating and a photo-resist pattern over a semiconductor substrate; exposing the uppermost surface of the semiconductor substrate by performing a first reactive ion etch process; and then forming a trench in the uppermost surface of the semiconductor substrate by performing a second reactive ion etch process.08-06-2009
20080299739METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a first insulating film over a rear surface of a plurality of silicon substrates, annealing the plurality of silicon substrates to degas the oxide species in the first insulating film, and oxidizing the surface of the plurality of silicon substrates in a batch process after annealing the silicon substrates.12-04-2008
20100151655METHOD OF FORMING A FINE PATTERN OF A SEMICONUCTOR DEVICE USING A DOUBLE PATTERNING TECHNIQUE - A method of forming a fine pattern of a semiconductor device uses a double patterning technique. A first mask pattern is formed on a first hard mask layer disposed on a substrate. A conformal buffer layer is formed over the first mask pattern. A second mask pattern is formed such that segments of the buffer layer are interposed between the first and second mask patterns, and each topographical feature of the second mask pattern is disposed between two adjacent ones of each respective pair of topographical features of the first mask pattern. A first hard mask pattern is formed by etching the first hard mask layer using the first mask pattern, the second mask pattern, and/or the buffer layer as an etch mask. A trench is formed by etching the substrate using the first hard mask pattern as an etch mask. An isolation layer, of a material that is different from that of first hard mask pattern, is formed in the trench.06-17-2010
20110195558NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a non-volatile semiconductor memory device including previously forming a recess in a first peripheral region on a semiconductor substrate, forming a first gate insulator having a first thickness in the recess, forming a second gate insulator having a second thickness less than the first thickness in an array region and a second peripheral region on the semiconductor substrate, successively depositing first and second gate electrode films and first and second mask insulators on each of the first and second gate insulators, forming an isolation trench on a surface of the semiconductor substrate to correspond to each position between the array region and the first and second regions of the peripheral region, depositing a buried insulator on the entire surface, and polishing an upper surface of the buried insulator so that the upper surface can be planarized.08-11-2011
20100081249Method to reduce leakage in a protection diode structure - A method for forming a protection diode utilizes processing operations and materials used in the formation of the CMOS integrated circuit device and provides a protection diode used in CMOS integrated circuit devices to direct charged particles to benign locations and prevent damage to the devices. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations.04-01-2010
20120178236METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION - A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfO07-12-2012
20100075479Semiconductor Device and Method of Forming the Same - A method of forming a semiconductor device includes forming a trench on a semiconductor substrate to define an active region, forming a radical oxide layer on a sidewall and a bottom surface of the trench, and forming a nitride layer on the radical oxide layer. The conduction band offset of the radical oxide layer is greater than the conduction band offset of a thermal oxide layer having the same thickness as the radical oxide layer.03-25-2010
20130084686DISCONTINUOUS THIN SEMICONDUCTOR WAFER SURFACE FEATURES - A semiconductor wafer has a semiconductor substrate and films on the substrate. The substrate and/or the films have at least one etch line creating a discontinuous surface that reduces residual stress in the wafer. Reducing residual stress in the semiconductor wafer reduces warpage of the wafer when the wafer is thin. Additionally, isolation plugs may be used to fill a portion of the etch lines to prevent shorting of the layers.04-04-2013
20130078783FORMING A PROTECTIVE FILM ON A BACK SIDE OF A SILICON WAFER IN A III-V FAMILY FABRICATION PROCESS - Provided is a method of fabricating a semiconductor device. The method includes forming a first dielectric layer over a first surface and a second surface of a silicon substrate. the first and second surfaces being opposite surfaces. A first portion of the first dielectric layer covers the first surface of the substrate, and a second portion of the first dielectric layer covers the second surface of the substrate. The method includes forming openings that extend into the substrate from the first surface. The method includes filling the openings with a second dielectric layer. The method includes removing the first portion of the first dielectric layer without removing the second portion of the first dielectric layer.03-28-2013
20130137239SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor storage device includes: memory cells including a transistor and a capacitor; bit lines; word lines; and sense amplifiers including first and second sense amplifiers, wherein the memory cells includes: a first memory cell group sharing a first auxiliary word line; and a second memory cell group sharing a second auxiliary word line, wherein the word lines includes a first word line coupled to the first auxiliary word line and a second word line coupled to the second auxiliary word line, the first word line is coupled to the first auxiliary word line in a first word line contact region, the second word line is coupled to the second auxiliary word line in a second word line contact region, the bit lines includes first and second bit lines coupled to the first sense amplifier on both sides of the first word line contact region.05-30-2013
20130034948Method of Manufacturing a Semiconductor Device - A method for fabricating a semiconductor device is disclosed. An exemplary method includes a providing substrate. A dielectric layer is formed over the semiconductor substrate and a stop layer is formed over the dielectric layer. The stop layer and the dielectric layer comprise a different material. The method further includes forming a patterned hard mask layer over the stop layer and etching the semiconductor substrate through the patterned hard mask layer to form a plurality of trenches. The method also includes depositing an isolation material on the semiconductor substrate and substantially filling the plurality of trenches. Thereafter, performing a CMP process on the semiconductor substrate, wherein the CMP process stops on the stop layer.02-07-2013
20090155977Methods for Forming a Gate and a Shallow Trench Isolation Region and for Planarizating an Etched Surface of Silicon Substrate - There is provide a method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, including the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. there are also provided a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region by improving the etching uniformity of sidewalls and bottom surface of the shallow trench, and a method for planarizating an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.06-18-2009
20100041206METHOD OF MANUFACTURING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to a method of manufacturing a MONOS nonvolatile semiconductor memory device, a tunnel insulating film, a charge storage layer, a block insulating film containing a metal oxide and a control gate electrode are stacked on a semiconductor substrate. Heat treatment is carried out in an atmosphere containing an oxidizing gas after the tunnel insulating film, the charge storage layer and the block insulating film are stacked on the semiconductor substrate. Thereafter, the control gate electrode is formed on the block insulating film.02-18-2010
20100041205METHOD FOR SIMULTANEOUSLY TENSILE AND COMPRESSIVE STRAINING THE CHANNELS OF NMOS AND PMOS TRANSISTORS RESPECTIVELY - A method of forming a microelectronic device comprising, on a same support: at least one semi-conductor zone strained according to a first strain, and at least one semi-conductor zone strained according to a second strain, different to the first strain, comprising: the formation of semi-conductor zones above a pre-strained layer, then trenches extending through the thickness of the pre-strained layer, the dimensions and the layout of the semi-conductor zones as a function of the layout and the dimensions of the trenches being so as to obtain semi-conductor zones having a strain of the same type as that of the pre-strained layer and semi-conductor zones having a strain of a different type to that of the pre-strained layer.02-18-2010
20090124060Method for manufacturing silicon carbide semiconductor apparatus - A method for manufacturing a silicon carbide semiconductor apparatus is disclosed. According to the method, an element structure is formed on a front surface side of a semiconductor substrate. A rear surface of the semiconductor substrate is grinded or polished in a direction parallel to a flat surface of a table. A front surface of the semiconductor substrate is grinded and polished in a direction parallel to the rear surface after the rear surface of the semiconductor substrate is grinded or polished.05-14-2009
20090124059METHOD FOR FORMING A SEMICONDUCTOR DEVICE - A method for forming a semiconductor device, includes the steps of providing a substrate; forming a patterned stack on the substrate including a first dielectric layer on the substrate, a first conductive layer on the first dielectric layer and a mask layer on the first conductive layer, wherein a width of the mask layer is smaller than a width of the first conductive layer; forming a second dielectric layer on the sidewall of the patterned stack; forming a third dielectric layer on the substrate; forming a second conductive layer over the substrate; and removing the mask layer and a portion of the first conductive layer covered by the mask layer to form an opening so as to partially expose the first conductive layer.05-14-2009
20090325359INTEGRATED CIRCUIT SYSTEM EMPLOYING A MODIFIED ISOLATION STRUCTURE - An integrated circuit system that includes: providing a substrate; forming a trench within the substrate; forming a liner on a sidewall of the trench; and forming a dielectric material at a trench bottom with a dielectric width dimension that exceeds that of a width dimension of the trench.12-31-2009
20110003455METHODS FOR FABRICATING IMPROVED GATE DIELECTRICS - Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPDX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPDX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.01-06-2011
20100099235Tunnel Dielectric Comprising Nitrogen For Use With A Semiconductor Device And A Process For Forming The Device - A method used during semiconductor device fabrication comprises forming at least two types of transistors. A first transistor type may comprise a CMOS transistor comprising gate oxide and having a wide active area and/or a long channel, and the second transistor type may comprise a NAND comprising tunnel oxide and having a narrow active area and/or short gate length. The transistors are exposed to a nitridation ambient. Various process embodiments and completed structures are disclosed.04-22-2010
20100099234SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION THEREOF - A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step of depositing the first silicon layer the first silicon layer is an undoped silicon layer and in the step of depositing the second silicon layer the second silicon layer is a doped silicon layer or an undoped silicon layer subsequently having an impurity introduced thereinto or the like and thermally diffused through subsequent thermal hysteresis into the first silicon layer.04-22-2010
20100099233METHOD FOR PRODUCING STACKED AND SELF-ALIGNED COMPONENTS ON A SUBSTRATE - The invention relates to a method for producing stacked and self-aligned components on a substrate, comprising the following steps: 04-22-2010
20090093101Method for Manufacturing a Transistor of a Semiconductor Memory Device - A transistor of a semiconductor memory device including a semiconductor substrate having a plurality of active regions and a device isolation region, a plurality of first and second trench device isolation layers, which are arranged alternately with each other on the device isolation region of the semiconductor substrate, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height, a recess region formed in each of the active regions by a predetermined depth to have a stepped profile at a boundary portion thereof, the recess region having a height higher than that of the second trench device isolation layers to have an upwardly protruded portion between adjacent two second trench device isolation layers, a gate insulation layer, and a plurality of gate stacks formed on the gate insulation layer to overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region.04-09-2009
20130183807METHOD OF MANUFACTURING A SEMICONDUCTOR APPARATUS AND ELECTRONIC EQUIPMENT - In the method of manufacturing a semiconductor apparatus of the present invention, after forming trench isolation regions 07-18-2013
20110014773METHOD FOR FABRICATING A METAL GATE STRUCTURE - A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the first gate is located on the active region and the second gate at least partially overlaps with the isolation region; forming an inter-layer dielectric material covering the gates; planarizing the inter-layer dielectric material until exposing the gates and forming an inter layer-dielectric layer; performing an etching process to remove the gates to form a first recess and a second recess within the inter-layer dielectric layer; forming a gate dielectric material on a surface of each of the recesses; forming at least a metal material within the recesses; and performing a planarization process.01-20-2011
20090269905Tapered Through-Silicon Via Structure - An integrated circuit structure includes a substrate; a through-silicon via (TSV) in the substrate, the TSV being tapered; a hard mask region extending from a top surface of the substrate into the substrate, wherein the hard mask encircles a top portion of the TSV; dielectric layers over the substrate; and a metal post extending from a top surface of the dielectric layers to the TSV, wherein the metal post comprises same materials as the TSV.10-29-2009
20120115304ISOLATION STRUCTURE AND FORMATION METHOD THEREOF - An isolation structure comprising a substrate is provided. A trench is in the substrate. A sidewall of the trench has a first inclined surface and a second inclined surface. The first inclined surface is located on the second inclined surface. The slope of the first inclined surface is different from the slope of the second inclined surface. A length of the first inclined surface is greater than 15 nanometers.05-10-2012
20090011569ELECTRICAL DEVICE AND METHOD FOR FABRICATING THE SAME - A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.01-08-2009
20100087043HYBRID SHALLOW TRENCH ISOLATION FOR HIGH-K METAL GATE DEVICE IMPROVEMENT - A method for fabricating a semiconductor device with improved performance is disclosed. The method comprises providing a substrate including a first region and a second region; forming at least one isolation region having a first aspect ratio in the first region and at least one isolation region having a second aspect ratio in the second region; performing a high aspect ratio deposition process to form a first layer over the first and second regions of the substrate; removing the first layer from the second region; and performing a high density plasma deposition process to form a second layer over the first and second regions of the substrate.04-08-2010
20110230033FABRICATION OF FINNED MEMORY ARRAYS - Methods and apparatus are provided. For an embodiment, a plurality fins is formed in a substrate so that the fins protrude from a substrate. After the plurality fins is formed, the fins are isotropically etched to reduce a width of the fins and to round an upper surface of the fins. A first dielectric layer is formed overlying the isotropically etched fins. A first conductive layer is formed overlying the first dielectric layer. A second dielectric layer is formed overlying the first conductive layer. A second conductive layer is formed overlying the second dielectric layer.09-22-2011
20090221128NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE - Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.09-03-2009
20100203703Deep Trench Isolation Structures and Methods of Formation Thereof - Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.08-12-2010
20110281417VAPOR DEPOSITION OF SILICON DIOXIDE NANOLAMINATES - This invention relates to materials and processes for thin film deposition on solid substrates. Silica/alumina nanolaminates were deposited on heated substrates by the reaction of an aluminum-containing compound with a silanol. The nanolaminates have very uniform thickness and excellent step coverage in holes with aspect ratios over 40:1. The films are transparent and good electrical insulators. This invention also relates to materials and processes for producing improved porous dielectric materials used in the insulation of electrical conductors in microelectronic devices, particularly through materials and processes for producing semi-porous dielectric materials wherein surface porosity is significantly reduced or removed while internal porosity is preserved to maintain a desired low-k value for the overall dielectric material. The invention can also be used to selectively fill narrow trenches with low-k dielectric material while at the same time avoiding deposition of any dielectric on the surface area outside of the trenches.11-17-2011
20110281416Manufacturing method of semiconductor device - The present invention provides a manufacturing method of a semiconductor device including: a step of forming a shallow trench on a semiconductor substrate; a step of forming an insulating layer in the shallow trench; and a step of forming a deep trench in the shallow trench, the deep trench penetrating through the insulating layer and being deeper than the shallow trench; wherein the step of forming the deep trench includes to form a first deep trench including an inner side face having a first taper angle with respect to the semiconductor substrate; and form a second deep trench including an inner side face having a second taper angle with respect to the semiconductor substrate, wherein the second taper angle is different from the first taper angle.11-17-2011
20110300688METHODS FOR FORMING A GATE AND A SHALLOW TRENCH ISOLATION REGION AND FOR PLANARIZING AN ETCHED SURFACE OF SILICON SUBSTRATE - A method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, includes the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. The present invention further provides a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region, and a method for planarizing an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.12-08-2011
20100062579SELF-ALIGNED TRENCH FORMATION - Methods for forming a semiconductor device include forming self-aligned trenches, in which a first set of trenches is used to align a second set trenches. Methods taught herein can be used as a pitch doubling technique, and may therefore enhance device integration. Further, employing a very thin CMP stop layer, and recessing surrounding materials by about an equal amount to the thickness of the CMP stop layer, provides improved planarity at the surface of the device.03-11-2010
20090098705METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device according to one embodiment includes: forming a gate electrode by shaping a semiconductor film formed above a semiconductor substrate; forming a protective film on a side face of the gate electrode by plasma discharge of a first gas or a second gas, the first gas containing at least one of HBr, Cl04-16-2009
20090209082Semiconductor Device and Method for Fabricating the Same - A semiconductor device and a method for fabricating the same may improve the isolation characteristics without deterioration of the junction diode characteristics and an increase in a threshold voltage of a MOS transistor. The device includes a semiconductor substrate; an STI layer in a predetermined portion of the semiconductor substrate, dividing the semiconductor substrate into an active region and a field region; and a field channel stop ion implantation layer in the semiconductor substrate under the STI layer.08-20-2009
20130189826Reduced Corner Leakage in SOI Structure and Method - A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.07-25-2013
20100197107METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a first film on a processed film, patterning the first film into a pattern with smaller width and a space with larger width, forming a second film along upper and side surfaces of first film and an upper surface of second film, etching the second film thereby to expose upper surfaces of first film and processed film while part of second film remains along the side surface of first film, etching the first film under the condition that the first film has higher etch selectivity than the second film, etching an upper part of second film under the condition that the second film has a higher etch selectivity than the processed film, after the first film has been etched, and etching the processed film with the second film serving as mask after the upper part of second film has been etched.08-05-2010
20080268608METHOD OF FABRICATING A FLASH MEMORY DEVICE - In a method of fabricating a flash memory device, after an isolation trench is formed, a bottom surface and sidewalls of the trench are gap-filled with a HARP film having a favorable step coverage. A wet etch process is performed such that the HARP film remains on the sidewalls of a tunnel dielectric layer, thereby forming a wing spacer. Accordingly, the tunnel dielectric layer can be protected and an interference phenomenon can be reduced because a control gate to be formed subsequently is located between floating gates.10-30-2008
20100022067DEPOSITION METHODS FOR RELEASING STRESS BUILDUP - A deposition method for releasing a stress buildup of a feature over a semiconductor substrate with dielectric material is provided. The feature includes lines separated by a gap. The method includes forming a liner layer over the feature on the semiconductor substrate in a chamber. A stress of the liner layer over the feature is released to substantially reduce bending of the lines of the feature. A dielectric film is deposited over the stress-released liner layer to substantially fill the gap of the feature.01-28-2010
20120190168METHOD FOR FORMING TRENCHES AND TRENCH ISOLATION ON A SUBSTRATE - A method for forming trench isolation on a substrate includes providing a substrate having thereon a pad layer and a hard mask; forming a first shallow trench in a first area and a second trench in a second area on the substrate; forming a resist layer covering the first area while exposing the second area; etching the second shallow trench to form a deep trench; forming oxide liner within the first shallow trench and the deep trench; and filling the shallow trench and the deep trench with an oxide layer.07-26-2012
20120034756Method of Forming a Deep Trench Isolation Structure Using a Planarized Hard Mask - A number of deep trench openings are formed in a semiconductor wafer to have substantially equal depths and no oxide undercut by forming a number of shallow trench openings, forming a mask structure in the shallow trench openings where the mask structure has a substantially planar top surface, forming a number of mask openings in the mask structure, and etching the semiconductor wafer through the mask openings to form the deep trench openings.02-09-2012
20120034755METHOD AND MANUFACTURE FOR HIGH VOLTAGE GATE OXIDE FORMATION AFTER SHALLOW TRENCH ISOLATION FORMATION - A method and manufacture for fabrication of flash memory is provided. In fabricating the periphery region of the flash memory, the low voltage gate oxides and high voltage gate oxides are grown to the same height as each other prior to STI etching. After STI etching and gap fill, the nitride above the high voltage gate oxide regions are etched, and the oxide in high voltage gate oxide regions is grown to the appropriate thickness for a high voltage gate oxide.02-09-2012
20100120219Method for Fabricating Semiconductor Device - A method for fabricating a semiconductor device is disclosed. The method includes forming a first oxide film, a nitride film, and a second oxide film on a semiconductor substrate in succession, etching the second oxide film and the nitride film to form a second oxide film pattern and a nitride film pattern, exposing a portion of the first oxide film, performing at least one nitrogen implantation into the semiconductor substrate to form a nitrogen injection region under the exposed portion of the first oxide film, forming a third oxide film over the second oxide film pattern, the nitride film pattern, and the semiconductor substrate, forming a trench that is deeper than the nitrogen ion injection region by etching the semiconductor substrate using the second oxide film pattern as a mask, and filling the trench with an oxide film to form a device isolating film.05-13-2010
20090087960METHOD FOR FABRICATING RECESS GATE IN SEMICONDUCTOR DEVICE - A method for fabricating a recess gate in a semiconductor device includes etching a silicon substrate to form a trench that defines an active region, forming a device isolation layer that gap-fills the trench, forming a hard mask layer over the silicon substrate, the hard mask layer comprising a stack of an oxide layer and an amorphous carbon layer, wherein the hard mask layer exposes a channel target region of the active region, and forming a recess region with a dual profile by first etching and second etching the channel target region using the hard mask layer as an etch barrier, wherein the second etching is performed after removing the amorphous carbon layer.04-02-2009
20090053873METHOD OF FORMING SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure is provided. The method includes providing a substrate and forming a mask layer on the substrate. Next, dielectric isolations are formed in the mask layer and the substrate, wherein the dielectric isolations extend above the substrate. Then, the mask layer is removed to expose a portion of the substrate, and a dielectric layer is formed on the exposed portion of the substrate. Subsequently, a first conductive layer is formed on the dielectric layer, and a portion of the dielectric isolation is removed, wherein a top surface of the remaining dielectric isolation is lower than a top surface of the first conductive layer. Moreover, a conformal layer is formed over the substrate, and a second conductive layer is formed on the conformal layer.02-26-2009
20120129317METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In the present invention, in the exposure to light of a memory cell array or the like of a semiconductor memory or the like, when a group of unit openings for etching the STI trench regions in which the unit openings for etching the STI trench regions each having a rectangular shape are arranged in rows and columns are transferred by the exposure onto a negative resist film, multiple exposure is appropriately used which includes a first exposure step using a first optical mask having a group of first linear openings extending in a column direction and a second exposure step using a second optical mask having a group of second linear openings extending in a row direction.05-24-2012
20110201172METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.08-18-2011
20090258473Nonvolatile memory device and method of manufacturing the same - Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.10-15-2009
20090258472Semiconductor array and method for manufacturing a semiconductor array - Method for manufacturing a semiconductor array, in which 10-15-2009
20080206954METHODS OF REDUCING IMPURITY CONCENTRATION IN ISOLATING FILMS IN SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device includes forming a lower device on a lower semiconductor substrate, and forming an interlayer insulating film on the lower device. An upper semiconductor substrate is formed on the interlayer insulating film such that the interlayer insulating film is between the lower and upper semiconductor substrates. Upper trenches are formed within the upper semiconductor substrate. An upper device isolating film is formed within the upper trenches. The upper device isolating film is irradiated with ultraviolet light having a wavelength configured to break chemical bonds of impurities in the upper device isolating film to reduce an impurity concentration thereof.08-28-2008
20080206955Method of Forming an Isolation Film in a Semiconductor Device - A method of forming an isolation film in a semiconductor device is disclosed. The disclosed method includes performing a patterning process on a predetermined region of a semiconductor substrate in which a patterned pad film is formed, forming a trench defining an inactive region and an active region, forming a liner film on the entire surface including the trench, forming an insulating film for trench burial only within the trench, stripping the remaining liner film formed except for the inside of the trench and the patterned pad film formed below the liner film, forming a sacrificial film on the entire surface, and performing a polishing process on the entire surface in which the sacrificial film is formed until the semiconductor substrate of the active region is exposed, thereby forming the isolation film having no topology difference with the semiconductor substrate of the active region.08-28-2008
20090280618Method of Planarizing a Semiconductor Device - A process of forming a semiconductor process fabricated device which contains a trench, hole or gap filled with a conformally deposited material is disclosed. A sacrificial planarizing layer is formed on the fill material, and the device is planarized using a selective RIE process which etches the fill material faster than the sacrificial planarizing layer. An overetch step completes the planarization process.11-12-2009
20110207287METHOD OF MANUFACTURING NONVOLATILE MEMORY DEVICE - A method of manufacturing a nonvolatile memory device includes forming a tunnel insulating layer over a semiconductor substrate, forming a charge trap layer, including first impurity ions of a first concentration, over the tunnel insulating layer, forming a compensation layer, including second impurity ions of a second concentration, over the charge trap layer, diffusing the second impurity ions within the compensation layer toward the charge trap layer, removing the compensation layer, forming a dielectric layer on surfaces of the charge trap layer, and forming a conductive layer for a control gate on the dielectric layer.08-25-2011
20100144115NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a non-volatile semiconductor memory device including previously forming a recess in a first peripheral region on a semiconductor substrate, forming a first gate insulator having a first thickness in the recess, forming a second gate insulator having a second thickness less than the first thickness in an array region and a second peripheral region on the semiconductor substrate, successively depositing first and second gate electrode films and first and second mask insulators on each of the first and second gate insulators, forming an isolation trench on a surface of the semiconductor substrate to correspond to each position between the array region and the first and second regions of the peripheral region, depositing a buried insulator on the entire surface, and polishing an upper surface of the buried insulator so that the upper surface can be planarized.06-10-2010
20090170278METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided that can comprise: forming a hard mask on a semiconductor substrate; forming a trench by etching the semiconductor substrate using the hard mask; performing a Chemical Mechanical Polishing (CMP) process after insulating film is buried in the trench; removing the hard mask; forming a protective film on the semiconductor substrate including a moat region of the semiconductor substrate adjacent to the insulating film, the moat region being further projected than the insulating film; implanting impurity ion onto the semiconductor substrate on which the protective film is formed; and removing the protective film using cleansing solution through a cleansing process before a gate insulating film is formed in an active region of the semiconductor substrate.07-02-2009
20080213969METHOD OF FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE - The present invention is related to a method of forming an isolation layer in a semiconductor device and comprises the steps of forming a tunnel insulating layer and conductive layer patterns on an active area of a semiconductor substrate, the width of an upper portion of the conductive layer patterns being narrower than that of a lower portion; forming a trench between the conductive layer patterns on the semiconductor substrate; forming an insulating layer to fill a portion of the trench with the insulating layer; and performing an etching process to remove an overhang of the insulating layer formed at an upper edge of the conductive layer patterns. Here, the step of forming the insulating layer and the step of performing the etching process are repeatedly performed until a space between the conductive layer patterns and the trench are filled with the insulating layer.09-04-2008
20100279486NONVOLATILE MEMORY HAVING CONDUCTIVE FILM BETWEEN ADJACENT MEMORY CELLS - A floating gate MOS transistor having a conductive floating gate electrode insulated from a semiconductor material having a main surface by a gate dielectric layer. At least one isolation region formed lateral to the gate electrode. An evacuation is formed in the isolation region and beneath the main surface of the semiconductor material layer. A conductive material fills the evacuation. A conductive control gate electrode is formed above the floating gate electrode. The floating gate electrode is laterally aligned to at least one isolation region.11-04-2010
20100144114Method for Producing a Semiconductor Component with Two Trenches - A method, in which a first isolating trench, filled with a dielectric material, and a second conducting trench, filled with an electrically conductive material, can be produced. To this end, the first and second trenches are etched with different trench widths, so that the first trench is filled completely with the dielectric material after a deposition of a dielectric layer over the entire surface with the edges covered, whereas the wider second trench is covered by the dielectric layer only on the inside walls. By anisotropic back-etching of the dielectric layer, the semiconductor substrate is exposed at the bottom of the second trench. Subsequently, the second trench is filled with an electrically conductive material and then represents a low-ohmic connection from the substrate surface to the buried structure located below the second trench.06-10-2010
20110269294METHOD OF FORMING A HARD MASK AND METHOD OF FORMING A FINE PATTERN OF SEMICONDUCTOR DEVICE USING THE SAME - A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.11-03-2011
20110207288SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME AND DESIGNING THE SAME - There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP08-25-2011
20090137094METHOD OF FILLING A TRENCH IN A SUBSTRATE - A method of filling a trench includes: providing a substrate having an upper surface, and a trench extending therein from the upper surface; forming a deposition layer on the substrate in a manner in which the layer partially fills the trench and has a portion which overhangs the trench at the upper surface of the substrate; etching, in a processing chamber, the portion of the deposition layer which overhangs the trench, including by inducing a reaction in the processing chamber using plasma; and subsequently depositing material on the substrate within the partially filled trench, including by inducing a reaction in the processing chamber using plasma.05-28-2009
20100003802METHOD FOR FABRICATING FIN TRANSISTOR - A method for fabricating a fin transistor includes patterning a first pad layer provided over a substrate using an isolation mask, etching the substrate using the isolation mask and the first pad layer to form trenches, filling the trenches with an insulating material to form isolation structures, etching the isolation structures within the trenches using a gas having a high selectivity ratio of the insulating material to the first pad layer to form fin structures, forming a gate insulating layer over the fin structures, and forming a conductive layer over the gate insulating layer.01-07-2010
20090004814METHOD OF FABRICATING FLASH MEMORY DEVICE - The invention relates to a method of fabricating a flash memory device. According to the method, select transistors and memory cells are formed on, and junctions are formed in a semiconductor substrate. The semiconductor substrate between a select transistor and an adjacent memory cell are over etched using a hard mask pattern. Accordingly, migration of electrons can be prohibited and program disturbance characteristics can be improved. Further, a void is formed between the memory cells. Accordingly, an interference phenomenon between the memory cells can be reduced and, therefore, the reliability of a flash memory device can be improved.01-01-2009
20090325360Method of Forming Trench of Semiconductor Device - The invention relates to a method of forming a trench of a semiconductor device. According to the method, a semiconductor substrate including a first region and a second region is provided. A gate insulating layer, a gate conductive layer, and a hard mask pattern are formed over the semiconductor substrate. First trenches are simultaneously formed in respective isolation areas of the first region and the second region by etching the gate conductive layer, the gate insulating layer, and the semiconductor substrate using an etch process employing the hard mask pattern. A second trench having a recess is formed on a bottom of the first trench formed in the second region. The recess is formed by widening the first trench by further etching the first trench.12-31-2009
20130217205METHODS FOR FABRICATING SEMICONDUCTOR DEVICES WITH ISOLATION REGIONS HAVING UNIFORM STEPHEIGHTS - Methods for fabricating semiconductor devices are provided. In an embodiment, a method for fabricating a semiconductor device includes forming a planarization stop layer overlying a semiconductor substrate. A trench is etched through the planarization stop layer and into the semiconductor substrate and is filled with an isolation material. The isolation material is planarized to establish a top surface of the isolation material coplanar with the planarization stop layer. In the method, a dry deglaze process is performed to remove a portion of the planarization stop layer and a portion of the isolation material to lower the top surface of the isolation material to a desired stepheight above the semiconductor substrate.08-22-2013
20090081847METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a nonvolatile semiconductor memory device comprising: forming a trench in a silicon substrate; forming a silicon dioxide film along an internal surface of the trench of the silicon substrate; removing the silicon dioxide film formed on a bottom surface of the trench of the silicon substrate by an anisotropic etching process; and forming an ozone tetraethyl orthosilicate (O03-26-2009
20090081846METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE - A method of fabricating a semiconductor device includes applying a coating oxide film to a surface of a substrate including a semiconductor substrate so that a recess formed in the surface is filled with the coating oxide film, applying a steam oxidation treatment to the substrate at a first temperature, soaking the substrate in heated water while applying a megasonic wave to the substrate in the heated water, and applying a steam oxidation treatment to the substrate at a second temperature higher than the first temperature.03-26-2009
20090068815SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device in which a main current flows in a direction of the thickness of a semiconductor substrate, to attain desirable electric characteristics. P type semiconductor regions and N type semiconductor regions are alternately provided with an interval therebetween, both regions in a surface of a second main surface of a semiconductor substrate. Between the P type semiconductor regions and the N type semiconductor regions, trenches formed in the surface of the semiconductor substrate are filled with insulators, thereby forming trench isolation structures. Moreover, a second main electrode is formed in contact with both the P type semiconductor regions and the N type semiconductor regions.03-12-2009
20090191688Shallow Trench Isolation Process Using Two Liners - A method for making STI structure includes etching a STI trench through a nitride layer, through an oxide layer, and into a silicon layer. The method also includes forming a sacrificial liner, pulling-back the nitride layer, and removing a remaining portion of the sacrificial liner. Furthermore, the method includes forming a STI liner and forming a STI fill coupled to the STI liner.07-30-2009
20090017595RELIABLE GAP-FILLING PROCESS AND APPARATUS FOR PERFORMING THE PROCESS IN THE MANUFACTURING OF SEMICONDUCTOR DEVICES - A reliable gap-filling process is performed in the manufacturing of a semiconductor device. An apparatus for performing the gap-filling process includes a chamber in which a wafer chuck is disposed, a plasma generator for generating plasma used to etch the wafer, an end-point detection unit for detecting the point at which the etching of the wafer is to be terminated, and a controller connected to the end-point detection unit. The end-point detection unit monitors the structure being etched at a region outside the opening that is to be filled, and generates in real time data representative of the layer that is being etched. As soon as an underlying layer is exposed and begins to be etched, an end-point detection signal is generated and the etching process is terminated. In the case in which the layer being etched is an oxide layer, a uniform etching is achieved despite any irregularity that exists in the thickness to which the oxide layer is formed.01-15-2009
20090017594NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - There is provided a non-volatile semiconductor memory device exhibiting excellent electrical characteristics and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having two trenches, an isolation oxide film provided in the trench, a floating gate electrode, an ONO film, and a control gate electrode. The isolation oxide film has an upper surface with a region having a curvature protruding downward. The floating gate electrode has a flat upper surface and extends from a main surface of the semiconductor substrate between the two trenches to the two isolation oxide films. The ONO film extends from the upper surface of the floating gate electrode to a side surface of the floating gate electrode. The control gate electrode is provided on the ONO film to extend from the upper surface of the floating gate electrode to the side surface of the floating gate electrode.01-15-2009
20090017593METHOD FOR SHALLOW TRENCH ISOLATION - Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described.01-15-2009
20080318391METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device that may include steps of forming a pad oxide layer and an insulating layer on a semiconductor substrate; and then performing a first etching process on the semiconductor device to form an insulating layer pattern exposing a portion of the pad oxide layer in a trench area; and then performing a second etching process with respect to the pad oxide layer by using the insulating layer pattern as a mask; and then performing a blanket ion implantation process with respect to the insulating layer pattern and the exposed portion of the pad oxide layer to form an ion layer in the semiconductor substrate; and then performing a third etching process with respect to the semiconductor substrate to simultaneously form a pad oxide layer pattern and a trench in the semiconductor substrate; and then forming an insulating layer on the semiconductor substrate including the trench; and then performing a planarization process with respect to the semiconductor substrate including the insulating material and removing the pad oxide layer pattern and the insulating layer pattern, thereby forming an isolation layer in the trench.12-25-2008
20090117705METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR MEMORY DEVICE - The present invention relates to a method of forming isolation layers of a semiconductor device. According to a method of forming isolation layers of a semiconductor device in accordance with an aspect of the present invention, a tunnel insulating layer, a charge trap layer, and a hard mask layer are sequentially formed over a semiconductor substrate. First trenches are formed by etching the hard mask layer, the charge trap layer, the tunnel insulating layer, and the semiconductor substrate. A spacer layer is formed on the entire surface including the first trenches. Second trenches are formed by etching the spacer layer, which is formed at a bottom of the first trenches, and the semiconductor substrate. An insulating layer for isolation is formed on the entire surface including the second trenches.05-07-2009
20090253242Method of Fabricating Non-Volatile Memory Device - A method of fabricating a non-volatile memory device includes: forming a tunnel insulation layer pattern and a floating gate electrode layer pattern over a semiconductor substrate; forming an isolation trench by etching an exposed portion of the semiconductor substrate so that the isolation trench is aligned with the tunnel insulation layer pattern and the floating gate electrode layer pattern; forming an isolation layer by filling the isolation trench with a filling insulation layer; forming a hafnium-rich hafnium silicon oxide layer over the isolation layer and the floating gate electrode layer pattern; forming a hafnium-rich hafnium silicon oxynitride layer by carrying out a first nitridation on the hafnium-rich hafnium silicon oxide layer; forming a silicon-rich hafnium silicon oxide layer over the hafnium-rich hafnium silicon oxynitride layer; forming a silicon-rich hafnium silicon oxynitride layer by carrying out a second nitridation on the silicon-rich hafnium silicon oxide layer; and forming a control gate electrode layer over the silicon-rich hafnium silicon oxynitride layer.10-08-2009
20090253241METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - Disclosed herein is a method for manufacturing a semiconductor device that includes: etching a semiconductor substrate to form a recess region; forming a device isolation trench in a portion of the etched semiconductor substrate including a portion of the recess region; and forming a device isolation film in the device isolation trench. The recess region is formed before the device isolation film, which can prevent a gate subsequently formed over the device isolation film from leaning. As a result, a subsequent landing plug contact hole is opened, which can improve process defects.10-08-2009
20100015777METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device, includes forming an amorphous silicon film above a semiconductor substrate, partially removing each of the amorphous silicon film and the semiconductor substrate, thereby forming an element isolation trench in a surface of the semiconductor substrate, forming an insulating film above the amorphous silicon film so that the element isolation trench is filled with the insulating film, polishing the insulating film by a chemical-mechanical polishing method with the amorphous silicon film serving as a stopper, thereby planarizing an upper surface of the insulating film, and thermally-treating the amorphous silicon film, thereby converting to a polysilicon film after polishing the insulating film.01-21-2010
20100015776Shallow Trench Isolation Corner Rounding - A method for rounding the corners of a shallow trench isolation is provided. A preferred embodiment comprises filling the trench with a dielectric and recessing the dielectric to expose a portion of the sidewalls of the trench adjacent to the surface of the substrate. The substrate is then annealed in a hydrogen ambient, which rounds the corners of the shallow trench isolation through silicon migration.01-21-2010
20090305481METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - Disclosed are methods for manufacturing a semiconductor memory device. According to an embodiment, a method includes forming a trench to form an isolation layer performing an annealing process to reduce an amount of a leakage current in an active layer, and performing a gap-fill process with respect to the trench. Another method in accordance with an embodiment includes performing a lithography process to form an active layer, in which a line critical dimension (CD) in the active layer is increased by about 3 nm to about 6 nm as compared with a line CD in a Process of Record (POR).12-10-2009
20130217204METHODS FOR FABRICATING INTEGRATED CIRCUITS - Methods are provided for forming semiconductor devices. One method includes forming a first layer overlying a bulk semiconductor substrate. A second layer is formed overlying the first layer. A first plurality of trenches is etched into the first and second layers. The first plurality of trenches is filled to form a plurality of support structures. A second plurality of trenches is etched into the first and second layers. Portions of the second layer disposed between adjacent trenches of the first and second pluralities of trenches define a plurality of fins. The first layer is etched to form gap spaces between the bulk semiconductor substrate and the plurality of fins. The plurality of fins is supported in position adjacent to the gap spaces by the plurality of support structures. The gap spaces are filled with an insulating material.08-22-2013
20100144113METHOD OF FORMING SEMICONDUCTOR DEVICES - A method of forming semiconductor devices includes providing a semiconductor substrate in which gate insulating patterns and first conductive patterns are formed, performing a first etch process to narrow a width of each of the first conductive patterns, forming an auxiliary layer on the first conductive patterns, the gate insulating patterns, and an exposed surface of the semiconductor substrate, and forming trenches by etching the auxiliary layer and the semiconductor substrate between the first conductive patterns.06-10-2010
20110237046METHOD OF MANUFACTURING A FINNED SEMICONDUCTOR DEVICE STRUCTURE - A method of manufacturing a finned semiconductor device structure is provided. The method begins by providing a substrate having bulk semiconductor material. The method continues by forming a semiconductor fin structure from the bulk semiconductor material, depositing an insulating material overlying the semiconductor fin structure such that the insulating material fills space adjacent to the semiconductor fin structure, and planarizing the deposited insulating material and the semiconductor fin structure to create a flat surface. Thereafter, a replacement gate procedure is performed to form a gate structure transversely overlying the semiconductor fin structure.09-29-2011
20100221890METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In forming an element isolation trench, an insulating film formed above a semiconductor substrate is etched such that relatively thin insulating film situated in the memory cell region is fully removed whereas relatively thick insulating film situated in the peripheral circuit region is etched so as to leave a remainder insulating film. Then, using the remainder insulating film in the peripheral circuit region as an etch stopper, the semiconductor substrate is etched, whereafter the remainder insulating film in the peripheral circuit region is fully removed to subsequently etch the semiconductor substrate.09-02-2010
20100197108METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE STRUCTURE - A non-volatile semiconductor manufacturing method comprises the steps of making element isolation/insulation films that partitions element-forming regions in a semiconductor substrate; stacking a floating gate on the semiconductor substrate via a first gate insulating film; stacking a second gate insulating film formed on the floating gate, and stacking a control gate formed on the floating gate via the second gate insulating film, and self-aligning source and drain diffusion area with the control gate. In the process of stacking a floating gate by partially etching a field oxide film in a select gate area, followed by floating gate formed in a element-forming region and select gate region, and followed by a chemical mechanical polish(CMP) process, both floating gate and select gate is hereby formed simultaneously. Thereby, when memory cells are miniaturized, the invention allows the process to be simple and reduce the defect density.08-05-2010
20100197106SEMICONDUCTOR EMBEDDED RESISTOR GENERATION - A method for generating an embedded resistor in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including forming a shallow trench isolation (STI) region in a substrate; forming a pad oxide on the STI region and substrate; depositing a silicon layer on the pad oxide; forming a photo-resist mask on a portion of the silicon layer disposed substantially above the STI region.; etching the silicon layer to yield a polyconductor (PC) disposed substantially above the STI region; oxidizing the PC; depositing at least one of an oxide material or a metal gate material on the oxidized surface; depositing a silicon layer on the at least one oxide material or metal gate material; depositing additional silicon on a portion of the silicon layer disposed substantially above the STI region; patterning a transistor gate with a photo-resist mask disposed on another portion of the silicon layer disposed substantially away from the STI region; and etching the silicon layer to yield at least one transistor structure disposed substantially away from the STI region and at least one resistor structure disposed substantially above the STI region.08-05-2010
20110129983METHOD FOR FABRICATING A DUAL-ORIENTATION GROUP-IV SEMICONDUCTOR SUBSTRATE - The present invention relates to method for fabricating a dual-orientation group-IV semiconductor substrate and comprises in addition to performing a masked amorphization on a DSB-like substrate only in first lateral regions of the surface layer, and a solid-phase epitaxial regrowth of the surface layer in only the first lateral regions so as to establish their (100)-orientation. Subsequently, a cover layer on the surface layer is fabricated, followed by fabricating isolation regions, which laterally separate (1 1θ)-oriented first lateral regions and (100)-oriented second lateral regions from each other. Then the cover layer is removed in a selective manner with respect to the isolation regions so as to uncover the surface layer in the first and second lateral regions and a refilling of the first and second lateral regions between the isolation regions is performed using epitaxy.06-02-2011
20110129984METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In the present invention, in the exposure to light of a memory cell array or the like of a semiconductor memory or the like, when a group of unit openings for etching the STI trench regions in which the unit openings for etching the STI trench regions each having a rectangular shape are arranged in rows and columns are transferred by the exposure onto a negative resist film, multiple exposure is appropriately used which includes a first exposure step using a first optical mask having a group of first linear openings extending in a column direction and a second exposure step using a second optical mask having a group of second linear openings extending in a row direction.06-02-2011
20130137238METHOD FOR FORMING HIGH MOBILITY CHANNELS IN III-V FAMILY CHANNEL DEVICES - Provided is a method of fabricating a semiconductor device. The method includes forming a buffer layer over a surface of a silicon substrate. The method further includes forming openings that extend into the buffer layer. The method includes forming a shallow trench isolation (STI) structures in each of the openings. The method includes removing a predetermined amount of a top surface of the buffer layer relative to a top surface of the STI structures. The method includes forming an insulator layer over the top surface of the buffer layer and forming a channel layer over the insulator layer.05-30-2013
20090035915METHOD OF HIGH DENSITY PLASMA GAP-FILLING WITH MINIMIZATION OF GAS PHASE NUCLEATION - A method of high density plasma (HDP) gap-filling with a minimization of gas phase nucleation (GPN) is provided. The method includes providing a substrate having a trench in a reaction chamber. Next, a first deposition step is performed to partially fill a dielectric material in the trench. Then, an etch step is performed to partially remove the dielectric material in the trench. Thereafter, a second deposition step is performed to partially fill the dielectric material in the trench. A reaction gas used in the second deposition step includes a carrier gas, an oxygen-containing gas, a silicon-containing gas, and a hydrogen-containing gas. After the carrier gas and oxygen-containing gas are introduced into the reaction chamber and a radio frequency (RF) power is turned on for a period of time, the silicon-containing gas and hydrogen-containing gas are introduced into the reaction chamber.02-05-2009
20110034005METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device whereby the process is simplified and high performance can be obtained in both a trench-gate transistor and a planar transistor that has a thin gate insulating film when the two transistors are formed on the same semiconductor substrate. In a state in which the gate insulating film (02-10-2011
20110034004METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device, the method including forming a buffer oxide layer in a first region and a second region of a semiconductor substrate; forming a plurality of first preliminary mask patterns on the buffer oxide layer in the first region; forming a plurality of second preliminary mask patterns between every two adjacent first preliminary mask patterns from among the plurality of first preliminary mask patterns, respectively; forming a plurality of first mask patterns and a plurality of second mask patterns by trimming the plurality of first preliminary mask patterns and the plurality of second preliminary mask patterns; forming a plurality of first active region mask patterns for exposing the semiconductor substrate; defining a plurality of active regions in the semiconductor substrate by forming a trench including a plurality of first trench spaces having same width as the first space and a plurality of second trench spaces under the second space in the first region; and forming a first liner layer on the semiconductor substrate having the trench therein such that the plurality of first trench spaces are completely filled with the first liner layer.02-10-2011
20110086491Growing a III-V Layer on Silicon using Aligned Nano-Scale Patterns - A method of forming an integrated circuit structure includes providing a wafer having a silicon substrate; forming a plurality of shallow trench isolation (STI) regions in the silicon substrate; and forming recesses by removing top portions of the silicon substrate between opposite sidewalls of the plurality of STI regions. Substantially all long sides of all recesses in the silicon substrate extend in a same direction. A III-V compound semiconductor material is then epitaxially grown in the recesses.04-14-2011
20100035404Methods of Forming Trench Isolation and Methods of Forming Arrays of FLASH Memory Cells - This invention includes methods of forming trench isolation. In one implementation, isolation trenches are provided within a semiconductor substrate. A liquid is deposited and solidified within the isolation trenches to form a solidified dielectric within the isolation trenches. The dielectric comprises carbon and silicon, and can be considered as having an elevationally outer portion and an elevationally inner portion within the isolation trenches. At least one of carbon removal from and/or oxidation of the outer portion of the solidified dielectric occurs. After such, the dielectric outer portion is etched selective to and effective to expose the dielectric inner portion. After the etching, dielectric material is deposited over the dielectric inner portion to within the isolation trenches.02-11-2010
20100055867STRUCTURED STRAINED SUBSTRATE FOR FORMING STRAINED TRANSISTORS WITH REDUCED THICKNESS OF ACTIVE LAYER - In a strained SOI semiconductor layer, the stress relaxation which may typically occur during the patterning of trench isolation structures may be reduced by selecting an appropriate reduced target height of the active regions, thereby enabling the formation of transistor elements on the active region of reduced height, which may still include a significant amount of the initial strain component. The active regions of reduced height may be advantageously used for forming fully depleted field effect transistors.03-04-2010
20100055864Method of forming isolation structure for semiconductor integrated circuit substrate - Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.03-04-2010
20100062580Fabrication processes for forming dual depth trenches using a dry etch that deposits a polymer - Trench isolation structures and methods to form same for use in the manufacture of semiconductor devices are described. The trench isolation structures are formed using several processing schemes that utilize disclosed dry etching processes to form a significant depth Δ between an array trench depth and a periphery trench depth. One etching method creates a trench delta depth utilizing a single dry etch step, while two other etching methods create a trench Δ depth by utilizing three dry etch steps.03-11-2010
20090035916METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING FIN GATE - When manufacturing a semiconductor device, an isolation layer is formed on a semiconductor substrate to define an active region that includes gate forming area. Portions of the isolation layer that are adjacent to the gate forming area of the active region are etching by a dry cleaning process which utilizes NH02-05-2009
20100055865METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a hardmask pattern over a substrate, forming a line type first photoresist pattern over the hardmask pattern, etching the hardmask pattern using the first photoresist pattern, removing the first photoresist pattern, forming a line type second photoresist pattern that cross the first photoresist pattern over the hardmask pattern, etching the hardmask pattern using the second photoresist pattern as an etch barrier, removing the second photoresist pattern, forming a trench by etching the substrate using the etched hardmask pattern as an etch barrier, and forming a device isolation region by filling the trench with an insulation layer.03-04-2010
20100068865METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION LAYER OF SEMICONDUCTOR DEVICE - An electrical device, such as a semiconductor device, and methods of manufacturing the same. A semiconductor device having a shallow trench isolation (STI) layer may include a pad oxide layer formed over a semiconductor substrate, a trench formed over the substrate, a liner insulating layer formed over the trench, a gap-fill insulating layer formed over the liner insulating layer and a gate layer formed over the substrate. The gap-fill insulating layer may have a relatively and/or substantially planar polished surface. Methods of fabricating a semiconductor device having a shallow trench isolation (STI) layer may include performing a first chemical mechanical polishing over a gap-fill insulating layer to expose and/or target a portion of a liner insulating layer and performing a second chemical mechanical polishing over a gap-fill insulating layer to remove a portion of a liner insulating layer.03-18-2010
20100055866METHOD OF FORMING TRANSISTOR IN SEMICONDUCTOR DEVICE - A method of forming a transistor in a semiconductor device includes forming device isolation structures in a substrate to define an active region. An oxide-based layer and a nitride-based layer are then formed between the active region and the device isolation structures. A predetermined gate region is etched in the active region to form a recess region. The damage layers are formed by a tilted ion implantation process using neutral elements on portions of the oxide-based layer exposed at the sidewalls of the recess region and other portions of the oxide-based layer below the recess region. The damage layers are then removed, thus causing a portion of the active region exposed at the bottom of the recess region to protrude.03-04-2010
20100062581METHOD OF FABRICATING NON-VOLATILE MEMORY DEVICE - Provided is a method of fabricating a non-volatile semiconductor device. The method includes: forming a first hard mask layer over a substrate; etching the first hard mask layer and the substrate to form a plurality of isolation trenches extending in parallel to one another in a first direction; burying a dielectric layer in the isolation trenches to form a isolation layer; forming a plurality of floating gate mask patterns extending in parallel to one another in a second direction intersecting with the first direction over a resulting structure where the isolation layer is formed; etching the first hard mask layer by using the floating gate mask patterns as an etch barrier to form a plurality of island-shaped floating gate electrode trenches; and burying a conductive layer in the floating gate electrode trenches to form a plurality of island-shaped floating gate electrodes.03-11-2010
20100240193METHODS OF FABRICATING FLASH MEMORY DEVICES INCLUDING SUBSTANTIALLY UNIFORM TUNNEL OXIDE LAYERS - A method of forming a flash memory device in a memory cell region of a substrate includes forming a first insulating layer on the substrate, forming a first conductive layer on the first insulating layer, forming trench isolation regions in the substrate extending through the first conductive layer and the first insulating layer to define an active region in the memory cell region between the trench isolation regions, and selectively removing the first conductive layer and the first insulating layer from the memory cell region of the substrate to expose a surface of the active region between the trench isolation regions.09-23-2010
20110081766METHOD FOR DOPING A SELECTED PORTION OF A DEVICE - A method includes forming a protective layer with an opening over a substrate, thereafter implanting a dopant into a substrate region through the opening, the protective layer protecting a different substrate region, and reducing thickness of the protective layer. A different aspect includes etching a substrate to form a recess therein, thereafter implanting a dopant into a substrate region within the recess and through an opening in a protective layer provided over the substrate, and reducing thickness of the protective layer. Another aspect includes forming a protective layer over a substrate, forming photoresist having an opening over the protective layer, etching the protective layer through the opening to expose the substrate, etching the substrate to form a recess in the substrate, implanting a dopant into a substrate portion, the protective layer protecting a different substrate portion thereunder, and etching the protective layer to reduce its thickness.04-07-2011
20110076834Semiconductor device and method for semiconductor device - A semiconductor device includes a semiconductor substrate, a memory cell region provided on the semiconductor substrate, a word line provided on the memory cell region, a first gate insulating film provided in the memory cell region beneath the word line, a first floating gate electrode provided on the first gate insulating film, a second gate insulating film provided in the memory cell region beneath the word line, the second gate insulating film being different from the first gate insulating film in thickness, and a second floating gate electrode provided on the second gate insulating film.03-31-2011
20110070720METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a method of manufacturing a semiconductor device comprising: forming a first layer on a sidewall of a trench formed on a main surface of a semiconductor substrate, filling up the trench with a protective film, etching back the protective film by a dry etching method so that a height of a surface of the protective film is lower than an opening of the trench and removing the first layer exposed by the etching-back.03-24-2011
20120149170METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method includes forming first insulating films on first and second faces of a substrate, removing the first insulating film on the second face, forming polysilicon films on the first insulating film on the first face and the second face, forming second insulating films on the polysilicon films on the first face and the second face, etching the second insulating film on the first face using a mask including an opening, removing the second insulating films on the first face and the second face, removing the polysilicon film on the side of the first face and forming a passivation film which protects the polysilicon film on the side of the second face so that the polysilicon film on the side of the second face is not removed in the polysilicon film removing step, after the polysilicon film forming step and before the polysilicon film removing step.06-14-2012
20120149171Shallow Trench Isolation with Improved Structure and Method of Forming - A shallow trench isolation (STI) structure and methods of forming a STI structure are disclosed. An embodiment is a method for forming a semiconductor structure. The method includes forming a recess in a semiconductor substrate; forming a first material on sidewalls of the recess; forming a widened recessed portion through a bottom surface of the recess; removing the first material from the sidewalls of the recess; and forming a dielectric material in the recess and the widened recessed portion. The bottom surface of the recess is exposed through the first material, and the bottom surface of the recess has a first width. The widened recessed portion has a second width. The second width is greater than the first width.06-14-2012
20080248626SHALLOW TRENCH ISOLATION SELF-ALIGNED TO TEMPLATED RECRYSTALLIZATION BOUNDARY - A hybrid orientation direct-semiconductor-bond (DSB) substrate with shallow trench isolation (STI) that is self-aligned to recrystallization boundaries is formed by patterning a hard mask layer for STI, a first amorphization implantation into openings in the hard mask layer, lithographic patterning of portions of a top semiconductor layer, a second amorphization implantation into exposed portions of the DSB substrate, recrystallization of the portions of the top semiconductor layer, and formation of STI utilizing the pattern in the hard mask layer. The edges of patterned photoresist for the second amorphization implantation are located within the openings in the patterned hard mask layer. Defective boundary regions formed underneath the openings in the hard mask layer are removed during the formation of STI to provide a leakage path free substrate. Due to elimination of a requirement for increased STI width, device density is increased compared to non-self-aligning process integration schemes.10-09-2008
20100105187ULTRATHIN SOI CMOS DEVICES EMPLOYING DIFFERENTIAL STI LINERS - An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions of the buried insulator layer is recessed and the top semiconductor layer is undercut. A thick thermal silicon oxide liner is formed on the exposed sidewalls and bottom peripheral surfaces of a PFET active area to apply a high laterally compressive stress. A second portion of the shallow trench is formed by lithographic masking of a PFET region including the PFET active area. A thin thermal silicon oxide or no thermal silicon oxide is formed on exposed sidewalls of the NFET active area, which is subjected to a low lateral compressive stress or no lateral compressive stress.04-29-2010
20110177672METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO07-21-2011
20080305610METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION STRUCTURE - A method of forming a shallow trench isolation structure includes steps of providing a substrate having a patterned mask layer formed thereon, wherein a trench is located in the substrate and the patterned mask layer exposes the trench. Thereafter, a dielectric layer is formed over the substrate to fill the trench. Then, a main polishing process with a first polishing rate is performed to remove a portion of the dielectric layer. An assisted polishing process is performed to remove the dielectric layer and a portion of the mask layer. The assisted polishing process includes steps of providing a slurry in a first period of time and then providing a solvent and performing a polishing motion of a second polishing rate in a second period of time. The second polishing rate is slower than the first polishing rate. Further, the mask layer is removed.12-11-2008
20080305609METHOD FOR FORMING A SEAMLESS SHALLOW TRENCH ISOLATION - A method for fabricating a seamless shallow trench isolation includes providing a semiconductor substrate having at least a shallow trench that is filled by a dielectric layer with a seam, forming a dielectric layer filling the shallow trench with a seam, forming at least one healing layer on the dielectric layer, and performing a low-temperature steam annealing process to eliminate the seam.12-11-2008
20090029521METHOD OF FORMING ISOLATION STRUCTURE OF SEMICONDUCTOR DEVICE FOR PREVENTING EXCESSIVE LOSS DURING RECESS GATE FORMATION - An isolation structure of a semiconductor device is formed by forming a hard mask layer on a semiconductor substrate having active and field regions to expose the field region. A trench is defined by etching the exposed field region of the semiconductor substrate using the hard mask as an etch mask. An SOG layer is formed in the trench partially filling the trench. An amorphous aluminum oxide layer is formed on the resultant substrate including the SOG layer. An HDP layer is formed on the amorphous aluminum oxide layer to completely fill the trench. The HDP layer and the amorphous aluminum oxide layer are subjected to CMP to expose the hard mask. The hard mask and portions of the amorphous aluminum oxide layer that are formed on the HDP layer are removed. The amorphous aluminum oxide layer is crystallized.01-29-2009
20090029520METHODS OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device, where the method may include forming a first trench in a semiconductor substrate, forming first device isolation patterns that fill the first trench, forming spacers on sidewalls of the first device isolation patterns, forming a second trench in the semiconductor substrate between first device isolation patterns, and forming second device isolation patterns that fill the second trench. The second trench is formed using an etching process adopting the first device isolation pattern and the spacer as a mask.01-29-2009
20110256687Method for Fabricating Through Substrate Microchannels - A method of forming large microchannels in an integrated circuit by etching an enclosed trench into the substrate and later thinning the backside to expose the bottom of the trenches and to remove the material enclosed by the trench to form the large microchannels. A method of simultaneously forming large and small microchannels. A method of forming structures on the backside of the substrate around a microchannel to mate with another device.10-20-2011
20080254592Method of forming isolation structure for semiconductor integrated circuit substrate - Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.10-16-2008
20100120218METHOD FOR FABRICATING PARTIAL SOI SUBSTRATE - A method for fabricating a partial silicon-on-insulator (SOI) substrate is disclosed. The method for fabricating a partial silicon-on-insulator (SOI) substrate includes forming an insulation pattern over a first silicon layer, forming a second silicon layer over the substrate structure including the insulation pattern, etching the second silicon layer to form trenches, and forming device isolation regions filling the trenches.05-13-2010
20110053340METHOD OF FORMING A TRENCH ISOLATION - A method of forming a trench isolation, comprising the steps of: 03-03-2011
20110053339METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a method for manufacturing a semiconductor device includes forming a first conductor layer on a surface of a semiconductor layer via a tunnel insulating film. The method includes forming an isolation trench extending from a surface of the first conductor layer to the semiconductor layer to form a plurality of conductive plates on the tunnel insulating film. The method includes filling the isolation trench with an element insulation insulating film from bottom of the isolation trench to an intermediate portion of a side surface of each of the conductive plates. The method includes forming a silicon nitride film on an exposed surface of the each of the conductive plates not covered with the element insulation insulating film. In addition, the method includes filling an upper portion of the isolation trench by forming a second conductor layer above the conductive plates and the element insulation insulating film.03-03-2011
20110053338FLASH MEMORY AND METHOD OF FABRICATING THE SAME - In a method of fabricating a flash memory, a substrate with isolation structures formed therein and a dielectric layer and a floating gate formed thereon between isolation structures is provided. A mask layer is formed on the substrate, covering the isolation structures in a periphery region and the isolation structure in a cell region adjacent to the periphery region. The isolation structures in the cell region not covered by the mask layer are partially removed. Therefore, a first height difference is between surfaces of the isolation structures in the periphery region and a surface of the dielectric layer, and between a surface of the isolation structure in the cell region adjacent to the periphery region and the surface of the dielectric layer. A second height difference smaller than the first height difference is between surfaces of other isolation structures in the cell region and the surface of the dielectric layer.03-03-2011
20100285654SEMICONDUCTOR DEVICE HAVING REDUCED DIE-WARPAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same reduce die-warpage. The semiconductor device includes a substrate and a first layer of material extending substantially over the entire surface of the substrate. A stress-relieving pattern exists in and traverses the first layer so as to partition the first layer into at least two discrete sections. The stress-relieving pattern may be in the form of an interface between the discrete sections of the first layer, or a wall of material different from the material of the first layer.11-11-2010
20110076833METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device for planarizing a silicon oxide film with chemical mechanical polishing using a silicon film formed on a semiconductor substrate as a stopper film, a surface modification film for hydrophilizing the surface of the silicon film is formed on an upper layer of the polysilicon film, and slurry for the chemical mechanical polishing contains cerium oxide particles, a surface active agent, and resin particles having a cationic or anionic functional group.03-31-2011
20110076832DUAL ETCH METHOD OF DEFINING ACTIVE AREA IN SEMICONDUCTOR DEVICE - A method of forming a hardmask for defining shallow trench isolation regions in a semiconductor substrate layer includes the steps of: depositing a hardmask layer over the semiconductor substrate layer; depositing and patterning a first photoresist layer over the hardmask layer; etching the hardmask layer after patterning the first photoresist layer to form an interim hardmask layer having at least one line feature; depositing and patterning a second photoresist layer over the interim hardmask layer; and forming a hardmask, the forming step including etching the interim hardmask layer after patterning the second photoresist layer to define a line end of the at least one line feature.03-31-2011
20110117720METHOD FOR PREPARING CERIUM OXIDE, CERIUM OXIDE PREPARED THEREFROM AND CMP SLURRY COMPRISING THE SAME - The present invention relates to a method for preparing cerium oxide which enables preparation of cerium oxide showing improved polishing performance, cerium oxide prepared therefrom, and CMP slurry comprising the same.05-19-2011
20120231605METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING A RECESSED CHANNEL - A method including forming an isolation trench; forming first and second liners on the isolation trench; filling the isolation trench an insulating material to form an isolation region and an active region; forming a preliminary gate trench including a first region across the isolation region to expose the first liner, the second liner, and the insulating material, and a second region across the active region to expose a portion of the substrate, the first region having a first sidewall with a planar shape, and the second region having a second sidewall with a concave central area such that an interface between the first and second regions has a pointed portion; removing a portion of the first liner exposed by the first region to form a dent having a first depth by which the pointed portion protrudes; removing the pointed portion to form a gate trench; and forming a gate electrode.09-13-2012
20110076835SEMICONDUCTOR DEVICE HAVING AN EXPANDED STORAGE NODE CONTACT AND METHOD FOR FABRICATING THE SAME - A semiconductor device is disclosed that stably ensures an area of a storage node contact connected to a junction region in an active region of the semiconductor device and is thus able to improve the electrical properties of the semiconductor device and enhance a yield, and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having an active region including a gate, a storage node contact region, and an isolation region that defines the active region. A passing gate and an isolation structure surrounding the passing gate are formed in the isolation region. A silicon epitaxial layer is selectively formed over an upper portion of the passing gate to expand the storage node contact region.03-31-2011
20100167495SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE AND WAFER - A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation potion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.07-01-2010
20120309165SEMICONDUCTOR DEVICE HAVING GATE TRENCH AND MANUFACTURING METHOD THEREOF - Disclosed herein is a semiconductor device that includes a trench formed across active regions and the element isolation regions. A conductive film is formed at a lower portion of the trench, and a cap insulating film is formed at an upper portion of the trench. The cap insulating film has substantially the same planer shape as that of the conductive film.12-06-2012
20100159669METHOD FOR FORMING DEEP TRENCH IN SEMICONDUCTOR DEVICE - A method for forming a deep trench in a semiconductor device includes: forming a hard mask over a substrate, forming a hard mask pattern over the substrate through etching the hard mask to thereby expose an upper portion of the substrate, forming a first trench through a first etching the exposed substrate using a gas containing bromide and a gas containing chloride and forming a second trench through a second etching the first trench using of a gas containing sulfur and fluorine, wherein a depth of the second trench is deeper than a depth of the first trench.06-24-2010
20100022068STI FILM PROPERTY USING SOD POST-TREATMENT - A method of forming a shallow trench isolation region includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; filling a precursor into the opening using spin-on; performing a steam cure to the precursor to generate a dielectric material; after the steam cure, performing a chemical mechanical polish (CMP) to the dielectric material; and after the CMP, performing a steam anneal to the dielectric material.01-28-2010
20100022069METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An oxide film and a liner film are formed on an inner wall of a trench in a semiconductor substrate. After filling an SOD film in the trench, a heat treatment is carried out. Part of the liner film in contact with the SOD film is removed to expose part of the SOD film. A heat treatment is carried out on the SOD film. An isolating region is formed by filling an insulating film in the trench.01-28-2010
20130011996METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device having improved reliability at an improved production yield.01-10-2013
20110306179MOCVD for Growing III-V Compound Semiconductors on Silicon Substrates - A device includes providing a silicon substrate; annealing the silicon substrate at a first temperature higher than about 900° C.; and lowering a temperature of the silicon substrate from the first temperature to a second temperature. A temperature lowering rate during the step of lowering the temperature is greater than about 1° C./second. A III-V compound semiconductor region is epitaxially grown on a surface of the silicon substrate using metal organic chemical vapor deposition (MOCVD).12-15-2011
20120045882SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes: removing an insulating film on a semiconductor substrate by etching and subsequently oxidizing a surface of the semiconductor substrate by using a liquid oxidation agent without exposing this surface to an atmosphere, thereby forming a first insulating film containing an oxide of a constituent element of the semiconductor substrate on the surface of the semiconductor substrate; forming a second insulating film containing an aluminum oxide on the first insulating film; forming a third insulating film containing a rare earth oxide on the second insulating film; forming a high-k insulating film on the third insulating film; introducing nitrogen into the high-k insulating film to thereby make it a fourth insulating film; and conducting heat treatment to change the first through third insulating films into a insulating film made of a mixture containing aluminum, a rare earth element, the constituent element of the semiconductor substrate, and oxygen.02-23-2012
20120003810SEMICONDUCTOR DEVICE HAVING REDUCED SUB-THRESHOLD LEAKAGE - A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.01-05-2012
20120208345METHOD FOR FORMING A SELF-ALIGNED ISOLATION STRUCTURE UTILIZING SIDEWALL SPACERS AS AN ETCH MASK AND REMAINING AS A PORTION OF THE ISOLATION STRUCTURE - The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be formed substantially conformably over the oxide and remaining portions of the dielectric material. Spacers may be formed from the insulating material. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal material may be formed substantially conformably over the spacer, over the remaining portions of the dielectric material, and substantially filling the isolation trench. Planarization of the conformal material may follow.08-16-2012
20110081765METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION - A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfO04-07-2011
20120252186SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a semiconductor substrate including an active area defined by an device isolation region, a buried gate formed on both side walls of a trench formed in the semiconductor substrate, and a storage node contact which is buried between the buried gates, and is connected to the active region of a middle portion of the trench and the device isolation region.10-04-2012
20120156856PROCESS MARGIN ENGINEERING IN CHARGE TRAPPING FIELD EFFECT TRANSISTORS - Embodiments of the present technology are directed toward charge trapping region process margin engineering for charge trapping field effect transistor. The techniques include forming a plurality of shallow trench isolation regions on a substrate, wherein the tops of the shallow trench isolation regions extend above the substrate by a given amount. A portion of the substrate is oxidized to form a tunneling dielectric region. A first set of one or more nitride layers are deposited on the tunneling dielectric region and shallow trench isolation regions, wherein a thickness of the first set of nitride layers is approximately half of the given amount that the tops of the shallow trench isolation regions extend above the substrate. A portion of the first set of nitride layers is etched back to the tops of the trench isolation regions. A second set of one or more nitride layers is deposited on the etched back first set of nitride layers. The second set of nitride layers is oxidized to form a charge trapping region on the tunneling dielectric region and a blocking dielectric region on the charge trapping region. A gate region is then deposited on the blocking dielectric region.06-21-2012
20110092047Strained Semiconductor Using Elastic Edge Relaxation, a Buried Stressor Layer and a Sacrificial Stressor Layer - The present invention relates to creating an active layer of strained semiconductor using a combination of buried and sacrificial stressors. That is, a process can strain an active semiconductor layer by transferring strain from a stressor layer buried below the active semiconductor layer and by transferring strain from a sacrificial stressor layer formed above the active semiconductor layer. As an example, the substrate may be silicon, the buried stressor layer may be silicon germanium, the active semiconductor layer may be silicon and the sacrificial stressor layer may be silicon germanium. Elastic edge relaxation is preferably used to efficiently transfer strain to the active layer.04-21-2011
20090142902Methods Of Etching Trenches Into Silicon Of A Semiconductor Substrate, Methods Of Forming Trench Isolation In Silicon Of A Semiconductor Substrate, And Methods Of Forming A Plurality Of Diodes - A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask comprising trenches formed there-through. Plasma etching is conducted to form trenches into the silicon of the semiconductor substrate using the mask. In one embodiment, the plasma etching includes forming an etching plasma using precursor gases which include SF06-04-2009
20120164816METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes groove-like regions that are formed between two adjacent bit lines among a plurality of bit lines each having upper and side surfaces covered with a cap insulating film and a side-wall insulating film, respectively, a SiON film that contains more O (oxygen) than N (nitrogen) and continuously covers inner surfaces of the groove-like regions, and a silicon dioxide film formed by reforming polysilazane and filled in the groove-like regions with the SiON film interposed therebetween.06-28-2012
20110104867FABRICATING VIAS OF DIFFERENT SIZE OF A SEMICONDUCTOR DEVICE BY SPLITTING THE VIA PATTERNING PROCESS - When forming a complex metallization system in which vias of different lateral size have to be provided, a split patterning sequence may be applied. For this purpose, a lithography process may be specifically designed for the critical via openings and a subsequent second patterning process may be applied for forming the vias of increased lateral dimensions, while the critical vias are masked. In this manner, superior process conditions may be established for each of the patterning sequences.05-05-2011
20120122295SEMICONDUCTOR DEVICE WITH RECESS AND FIN STRUCTURE - The semiconductor device includes an active region, a recess, a Fin channel region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess is formed by etching the active region and its neighboring device isolation structure using an island shaped recess gate mask as an etching mask. The Fin channel region is formed on the semiconductor substrate at a lower part of the recess. The gate insulating film is formed over the active region including the Fin channel region and the recess. The gate electrode is formed over the gate insulating film to fill up the Fin channel region and the recess.05-17-2012
20120122294METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a method of manufacturing a semiconductor device includes successively forming first and second films to be processed on a semiconductor substrate. The method further includes removing a predetermined region of the second film by etching, to form a slit part including sidewall parts and a bottom part, the sidewall parts including side surfaces of the second film, and the bottom part including an upper surface of the first film. The method further includes supplying oxidizing ions or nitriding ions contained in plasma, generated by a microwave, a radio-frequency wave, or electron cyclotron resonance, to the sidewall parts and the bottom part of the slit part by applying a predetermined voltage to the semiconductor substrate, thereby performing anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the slit part.05-17-2012
20120164815METHOD OF FORMING ELEMENT ISOLATION LAYER - There is provided a method of forming an element isolation layer, the method including: forming a pad oxide layer and a nitride layer in succession on a front face of a semiconductor substrate; forming a trench so as to penetrate through the pad oxide layer and the nitride layer and into the semiconductor substrate; forming an in-fill oxide layer so as to fill the trench and cover the nitride layer; polishing the in-fill oxide layer using a first polishing agent so as to leave in-fill oxide layer remaining over the nitride layer; and polishing the in-fill oxide layer using a second polishing agent having a polishing selectivity ratio of the in-fill oxide layer to the nitride layer greater than that of the first polishing agent, so as to expose the nitride layer and flatten the exposed faces of the nitride layer and the in-fill oxide layer.06-28-2012
20100093151OXIDE ETCH WITH NH4-NF3 CHEMISTRY - The present invention generally provides apparatus and methods for selectively removing various oxides on a semiconductor substrate. One embodiment of the invention provides a method for selectively removing an oxide on a substrate at a desired removal rate using an etching gas mixture. The etching gas mixture comprises a first gas and a second gas, and a ratio of the first gas and a second gas is determined by the desired removal rate.04-15-2010
20090130819METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes a device isolation layer. In the method, a hard mask may be formed on a semiconductor substrate, and the semiconductor substrate may be etched using the hard mask as a mask to form a trench. The hard mask may be removed, and a device isolation layer may be formed in the trench. A shallow trench isolation pattern having an excellent layer quality may be formed by reducing an aspect ratio of the trench in the semiconductor device and gap-filling a dielectric. Thus, the number of defects may be decreased.05-21-2009
20090130818METHOD FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR PREPARING RECESSED GATE STRUCTURE USING THE SAME - A method for preparing a recessed gate structure comprises the steps of: forming a shallow trench isolation structure surrounding an active area in a silicon substrate, wherein an etching barrier layer is formed on the surface of the shallow trench isolation structure; forming a plurality of gate trenches in the active area of the silicon substrate by performing an etching process; and forming a recessed gate structure by filling the gate trench with a predetermined height.05-21-2009
20090130817METHOD TO ELIMINATE RE-CRYSTALLIZATION BORDER DEFECTS GENERATED DURING SOLID PHASE EPITAXY OF A DSB SUBSTRATE - A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation, a second crystal orientation, and a border region disposed between the first and second crystal orientations. The border region further has a defect associated with an interface of the first crystal orientation and second the second crystal orientation, wherein the defect generally extends a distance into the semiconductor body from a surface of the body. A sacrificial portion of the semiconductor body is removed from the surface thereof, wherein removing the sacrificial portion at least partially removes the defect. The sacrificial portion can be defined by oxidizing the surface at low temperature, wherein the oxidation at least partially consumes the defect. The sacrificial portion can also be removed by CMP. An STI feature may be further formed over the defect after removal of the sacrificial portion, therein consuming any remaining defect.05-21-2009
20110183491SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME - A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+07-28-2011
20110183490SEMICONDUCTOR STRUCTURE FORMED WITHOUT REQUIRING THERMAL OXIDATION - Briefly, in accordance with one or more embodiments, a semiconductor device is manufactured by forming at least two or more cavities below a surface of a semiconductor substrate wherein the at least two or more cavities are spaced apart from each other by a selected distance, filling at least a portion of the at least two or more cavities with a dielectric material to form at least two or more dielectric structures, removing a portion of the substrate between the at least two or more dielectric structures to form at least one additional cavity, and covering the at least one additional cavity.07-28-2011
20100178748Methods of Etching Trenches Into Silicon of a Semiconductor Substrate, Methods of Forming Trench Isolation in Silicon of a Semiconductor Substrate, and Methods of Forming a Plurality of Diodes - A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask comprising trenches formed there-through. Plasma etching is conducted to form trenches into the silicon of the semiconductor substrate using the mask. In one embodiment, the plasma etching includes forming an etching plasma using precursor gases which include SF07-15-2010
20120171842STRESS-GENERATING SHALLOW TRENCH ISOLATION STRUCTURE HAVING DUAL COMPOSITION - A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut.07-05-2012
20120077328NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, METHOD OF FABRICATING THE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROCESS OF WRITING DATA ON THE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a semiconductor substrate, a plurality of first element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a first cell array region into a band shape, a plurality of second element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a second cell array region into a band shape. Each first element isolation insulating film has a level from a surface of the semiconductor substrate, the first charge storage layer has a level from the surface of the semiconductor substrate, and each second element isolation insulating film has a level from the surface of the semiconductor substrate, the level of each first element isolation insulating film being lower than the level of the first charge storage layer and higher than the level of each second element isolation insulating film.03-29-2012
20120077327Formation of a Shallow Trench Isolation Structure - A method of forming a shallow trench isolation structure such that the shoulders of the wall formations on either side of the trench are rounded, whilst the walls and floor of the trench as well as the top surface of the formations on either side of the trench remain flat. This is achieved by anchoring the walls and floors with a partial gap fill, which may be achieved either by fully filling the gap and then reducing the level to below that of the formations on either side a the trench by polishing and etching steps, or by not completely filling the trench in the first place. The tops of the formations on either side of the trench meanwhile are protected by an oxide layer, which is pared back from the edge of the trench, for example by means of an isotropic etching process.03-29-2012
20100009513SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming a gate insulating film on a semiconductor substrate, forming a gate electrode film on the gate insulating film, and forming a plurality of trenches by etching the gate electrode film, the gate insulating film and the semiconductor substrate so that an upper portion of the gate electrode film includes a tapered side surface and a lower portion of the gate electrode film includes a side surface perpendicular to a surface of the semiconductor substrate. The method also includes forming an element isolation insulating film in the trenches, including forming a deposition type insulating film in the trenches and forming a coating type insulating film on the deposition type insulating film, and removing the element isolation insulating film by a dry etching method so that the tapered side surfaced of the gate electrode film is exposed and the perpendicular side surface of the gate electrode film is covered by the element isolation insulating film.01-14-2010
20120315738METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides a method of manufacturing a semiconductor device. An insulating-separating portion, which surrounds an electrode penetrating a substrate, is filled with a stacked structure of at least two stages, including a first stage of insulating film and a second stage of insulating film. When at least one of the first and second stages of insulating films has a seam, the seam is stopped by the region in the bottom of the second stage of insulating film that does not have a seam in at least the bottom thereof, thereby increasing mechanical strength. It is possible to prevent the inner region of the insulating-separating portion from being isolated.12-13-2012
20120083096SEMICONDUCTOR DEVICE HAVING A SIMPLIFIED STACK AND METHOD FOR MANUFACTURING TEHREOF - Embodiments of the present invention are directed to provide a semiconductor device including a semiconductor chip formed of a conductive material, a connector terminal around the semiconductor chip, which is formed of a same material for forming the semiconductor chip, an insulating member for electrically insulating the semiconductor chip from the connector terminal, and a first connection member for electrically coupling the semiconductor chip with the connector terminal Simplified step of manufacturing the connector terminal may further simplify the steps of manufacturing the semiconductor device.04-05-2012
20120083095METHOD OF FABRICATING SEMICONDUCTOR DEVICE BY THINNING HARDMASK LAYERS ON FRONTSIDE AND BACKSIDE OF SUBSTRATE - The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.04-05-2012
20120083094INTEGRATED CIRCUIT GUARD RINGS - Integrated circuits with guard rings are provided. Integrated circuits may include internal circuitry that is sensitive to external noise sources. A guard ring may surround the functional circuitry to isolate the circuitry from the noise sources. The guard ring may include first, second, and third regions. The first and third regions may include p-wells. The second region may include an n-well. Stripes of diffusion regions may be formed at the surface of a substrate in the three regions. Areas in the guard ring that are not occupied by the diffusion regions are occupied by shallow trench isolation (STI) structures. Stripes of dummy structures may be formed over respective STI structures and may not overlap the diffusion regions. The diffusion regions in the first and third regions may be biased to a ground voltage. The diffusion regions in the second section may be biased to a positive power supply voltage.04-05-2012
20100167493METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes a process of forming a STI trench in a substrate, a process of forming a thermal oxide film on a sidewall and a bottom surface of the STI trench, a process of performing a plasma treatment on a surface of the thermal oxide film that is located at a bottom portion of the STI trench, and a process of forming an insulating film in the STI trench using a CVD method07-01-2010
20110124177SIMULTANEOUSLY FORMED ISOLATION TRENCH AND THROUGH-BOX CONTACT FOR SILICON-ON-INSULATOR TECHNOLOGY - A semiconductor fabrication method comprises providing a structure which includes a semiconductor substrate having a plurality of subsurface layers, the substrate comprising a top surface and the subsurface layers comprising a top subsurface layer below the top surface of the substrate. A protective material is patterned on the top surface of the device and a material removal process is performed to simultaneously form a contact trench and an isolation trench, the material removal process removing at least a portion of the top surface and the top subsurface layer such that the contact trench and the isolation trench are formed within the subsurface layer. An insulator is then formed within the isolation trench and the contact trench is lined with the insulator. The contact trench is then filled with a conductive material such that the conductive material is deposited over the insulator.05-26-2011
20100297826Method of Manufacturing Nonvolatile Memory Device - In one embodiment of a method of manufacturing a nonvolatile memory device, a tunnel insulating layer and a charge trap layer are first formed over a semiconductor substrate that defines active regions and isolation regions. The tunnel insulating layer, the charge trap layer, and the semiconductor substrate formed in the isolation regions are etched to form trenches for isolation in the respective isolation regions. The trenches for isolation are filled with an insulating layer to form isolation layers in the respective trenches. A lower passivation layer is formed over an entire surface including top surfaces of the isolation layers. A first oxide layer is formed over an entire surface including the lower passivation layer. Meta-stable bond structures within the lower passivation layer are removed. A nitride layer, a second oxide layer, and an upper passivation layer are sequentially formed over an entire surface including the first oxide layer.11-25-2010
20120231606MULTI-LAYER STRUCTURES AND PROCESS FOR FABRICATING SEMICONDUCTOR DEVICES - The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing.09-13-2012
20090215241MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES - A polysilazane perhydride solution, prepared by dispesing polysilazane perhydride in a solvent containing carbon, is applied on a semiconductor substrate (08-27-2009
20100203705SEMICONDUCTOR DEVICE WITH IMPROVED OVERLAY MARGIN AND METHOD OF MANUFACTURING THE SAME - Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed.08-12-2010
20100203704SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes: removing an insulating film on a semiconductor substrate by etching and subsequently oxidizing a surface of the semiconductor substrate by using a liquid oxidation agent without exposing this surface to an atmosphere, thereby forming a first insulating film containing an oxide of a constituent element of the semiconductor substrate on the surface of the semiconductor substrate; forming a second insulating film containing an aluminum oxide on the first insulating film; forming a third insulating film containing a rare earth oxide on the second insulating film; forming a high-k insulating film on the third insulating film; introducing nitrogen into the high-k insulating film to thereby make it a fourth insulating film; and conducting heat treatment to change the first through third insulating films into a insulating film made of a mixture containing aluminum, a rare earth element, the constituent element of the semiconductor substrate, and oxygen.08-12-2010
20100203702METHOD FOR FORMING ISOLATION LAYER AND METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE USING THE SAME - A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming a protection layer by transforming a portion of a sidewall of the hard mask pattern, forming a trench by etching the substrate using the hard mask pattern and the protection layer as an etch barrier, forming an isolation layer by filling the trench with an insulation material, removing the hard mask pattern, and performing a cleaning process. By forming the protection layer, it is possible to prevent the isolation layer from being lost during the removing of the hard mask pattern and the cleaning process and thus prevent generation of a moat.08-12-2010
20110003457SEMICONDUCTOR COMPONENT WITH TRENCH INSULATION AND CORRESPONDING PRODUCTION METHOD - The invention relates to a semiconductor component with trench isolation and to an associated fabrication method, a trench isolation (STI, TTI) having a deep isolation trench with a covering insulation layer (01-06-2011
20110003456SILICON CARBIDE AND RELATED WIDE-BANDGAP TRANSISTORS ON SEMI INSULATING EPITAXY - A method of making a semi-insulating epitaxial layer includes implanting a substrate or a first epitaxial layer formed on the substrate with boron ions to form a boron implanted region on a surface of the substrate or on a surface of the first epitaxial layer, and growing a second epitaxial layer on the boron implanted region of the substrate or on the boron implanted region of the first epitaxial layer to form a semi-insulating epitaxial layer.01-06-2011
20110045651SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION THEREOF - A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step of depositing the first silicon layer the first silicon layer is an undoped silicon layer and in the step of depositing the second silicon layer the second silicon layer is a doped silicon layer or an undoped silicon layer subsequently having an impurity introduced thereinto or the like and thermally diffused through subsequent thermal hysteresis into the first silicon layer.02-24-2011
20120276712SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - According to one embodiment, a semiconductor device having a Ge— or SiGe-fin structure includes a convex-shaped active area formed along one direction on the surface region of a Si substrate, a buffer layer of Si11-01-2012
20120088349METHODS OF FABRICATING FIN STRUCTURES - There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.04-12-2012
20120329240MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - An improvement is provided in a manufacturing yield of a semiconductor device including transistors in which gate insulating films have different thicknesses. After a high-breakdown-voltage insulating film is formed over a silicon substrate, a surface of the high-breakdown-voltage insulating film is abraded for a reduction in the thickness thereof so that a middle-breakdown-voltage insulating film is formed to be adjacent to the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed by a thermal oxidation method so as to extend from an inside of the main surface of the silicon substrate to an outside thereof. The middle-breakdown-voltage insulating film is formed so as to be thinner than the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed as the gate insulating film of a high-breakdown-voltage MIS transistor, while the middle-breakdown-voltage insulating film is formed as the gate insulating film of a middle-breakdown-voltage MIS transistor.12-27-2012
20120329239METHODS OF FABRICATING A SEMICONDUCTOR IC HAVING A HARDENED SHALLOW TRENCH ISOLATION (STI) - Methods and provided for fabricating a semiconductor IC having a hardened shallow trench isolation (STI). In accordance with one embodiment the method includes providing a semiconductor substrate and forming an etch mask having an opening exposing a portion the semiconductor substrate. The exposed portion is etched to form a trench extending into the semiconductor substrate and an oxide is deposited to at least partially fill the trench. At least the surface portion of the oxide is plasma nitrided to form a nitrided oxide layer and then the etch mask is removed.12-27-2012
20100167494Selective Etching Method and Method for Forming an Isolation Structure of a Memory Device - A disclosed selective etching method comprises mixing a polymer with carbon nanotubes, applying the mixture to an etching target layer to form a carbon nanotube-polymer composite layer, forming a hard mask by patterning the carbon nanotube-polymer composite layer, such that a part of the etching target layer is selectively exposed, and selectively etching the etching target layer exposed through the hard mask. The polymer preferably includes a photoresist. Also disclosed is a method for forming an isolation structure of a memory device using the selective etching method.07-01-2010
20100129981THROUGH-VIA AND METHOD OF FORMING - In one embodiment, a method of forming a via includes providing a semiconductor substrate, wherein the semiconductor substrate comprises a through-via region, forming isolation openings and a sacrificial feature in the through-via region, filling the isolation openings to form isolation regions, forming a dielectric layer over the semiconductor substrate after filling the isolation openings, forming a first portion of a through-via opening in the dielectric layer, forming a second portion of the through-via opening in the semiconductor substrate, wherein forming the second portion of the through-via opening comprises removing the sacrificial feature, and forming a conductive material in the first portion and the second portion of the through-via opening.05-27-2010
20130017665METHODS OF FORMING ISOLATION STRUCTURE AND SEMICONDUCTOR STRUCTUREAANM Yin; HaizhouAACI PoughkeepsieAAST NYAACO USAAGP Yin; Haizhou Poughkeepsie NY USAANM Zhu; HuilongAACI PoughkeepsieAAST NYAACO USAAGP Zhu; Huilong Poughkeepsie NY USAANM Luo; ZhijiongAACI PoughkeepsieAAST NYAACO USAAGP Luo; Zhijiong Poughkeepsie NY US - The present invention relates to a method of forming an isolation structure and a semiconductor structure. The method of forming the isolation structure comprises the steps of: providing a silicon substrate having a (110) crystal plane or a (112) crystal plane and determining the [111] direction of the silicon substrate; forming first trenches in the silicon substrate by wet etching the silicon substrate, the extension direction of the first trenches being substantially perpendicular to the [111] direction; filling the first trenches with a first insulating material to form a first isolator; forming second trenches in the silicon substrate by dry etching the silicon substrate, the extension direction of the second trenches being perpendicular to the extension direction of the first trenches; filling the second trenches with a second insulating material to form a second isolator.01-17-2013
20110159664METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED GATES - A method for fabricating a semiconductor device includes sequentially stacking a pad oxide layer and a hard mask layer over a substrate, forming a device isolation layer over the substrate, forming a capping layer pattern configured to open a first region of the substrate and cover a second region of the substrate, removing the hard mask layer, removing the capping layer pattern, and removing the pad oxide layer.06-30-2011
20080233709METHOD FOR REMOVING MATERIAL FROM A SEMICONDUCTOR - A method for removing a material from a trench in a semiconductor. The method includes placing the semiconductor in a vacuum chamber, admitting a reactant into the chamber at a pressure to form a film of the reactant on a surface of the material, controlling the composition and residence time of the film on the surface of the material to etch at least a portion of the material, and removing any unwanted reactant and reaction product from the chamber or the surface of the material.09-25-2008
20080227267Stop mechanism for trench reshaping process - An opening, such as a trench, on a semiconductor substrate is annealed to smooth edges and corners of the opening. The anneal causes reflow of the material forming the walls of the opening, thereby smoothing out the edges and corners of the opening. After a desired amount of reflow is accomplished, the substrate is exposed to an oxidant such as O09-18-2008
20080227266Method of STI corner rounding using nitridation and high temperature thermal processing - One embodiment of the present invention relates to a method of forming an isolation structure with rounded corners in a semiconductor substrate, comprising forming an isolation trench within the semiconductor substrate, performing an oxidation blocking nitridation process on exposed surfaces of the trench, performing corner rounding by oxidizing the exposed surfaces after the oxidation blocking nitridation process, and filling the trench with a dielectric material.09-18-2008
20080220585METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprises forming a silicon film, converting a surface of the silicon film into a hydrophilic surface, forming an insulating film over the silicon film, and polishing the insulating film formed over the silicon film.09-11-2008
20080220584Methods of Forming Integrated Circuit Structures Using Insulator Deposition and Insulator Gap Filling Techniques - Methods of forming integrated circuit devices include depositing an electrically insulating layer onto an integrated circuit substrate having integrated circuit structures thereon. This deposition step results in the formation of an electrically insulating layer having an undulating surface profile, which includes at least one peak and at least on valley adjacent to the at least one peak. A non-uniform thickening step is then performed. This non-uniform thickening step includes thickening a portion of the electrically insulating layer by redepositing portions of the electrically insulating layer from the least one peak to the at least one valley. This redeposition occurs using a sputter deposition technique that utilizes the electrically insulating layer as a sputter target.09-11-2008
20130178044SEMICONDUCTOR DEVICES COMPRISING A PLURALITY OF GATE STRUCTURES - Methods for forming semiconductor memory structures including a gap between adjacent gate structures are provided. The methods may include forming an insulation layer between the adjacent gate structures. In some embodiments, the methods may include subsequently removing a portion of the insulation layer to leave the gap between the adjacent gate structures.07-11-2013
20120252185METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES - A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are etched to partially remove the etch mask pattern from the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region.10-04-2012
20130095635METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE - A method for fabricating a nonvolatile memory device includes forming a first insulation layer and a first conductive layer on a substrate including a first region and a second region, forming a first isolation trench in the first region by etching the first conductive layer, the first insulation layer, and the substrate, forming a first isolation layer filled in the first isolation trench, forming a second insulation layer and a conductive capping layer, etching the capping layer and the second insulation layer, forming a second conductive layer, and forming first gate patterns by etching the second conductive layer, the capping layer, the second insulation layer, the first conductive layer, and the first insulation layer of the first region, and forming a second isolation trench in the second region by etching the second conductive layer, the first conductive layer, the first insulation layer, and the substrate.04-18-2013
20130115751BORON-CONTAINING HYDROGEN SILSESQUIOXANE POLYMER, INTEGRATED CIRCUIT DEVICE FORMED USING THE SAME, AND ASSOCIATED METHODS - A composition includes a boron-containing hydrogen silsesquioxane polymer having a structure that includes: silicon-oxygen-silicon units, and oxygen-boron-oxygen linkages in which the boron is trivalent, wherein two silicon-oxygen-silicon units are covalently bound by an oxygen-boron-oxygen linkage therebetween.05-09-2013
20130122685Method of Manufacturing a Semiconductor Device - A method of manufacturing a semiconductor device, the method including: forming a plurality of first trenches extending in one direction in at least a part of a substrate; forming a plurality of first filling layers for filling the plurality of first trenches and having protrusion portions extended from the substrate from the plurality of first trenches; forming spacers on side walls of the protrusion portions of the plurality of first filling layers so that a part of the substrate is exposed between the plurality of first filling layers; and forming a plurality of second trenches extending in parallel to the plurality of first trenches by etching the substrate exposed through the spacers.05-16-2013
20080200005STRUCTURE AND METHOD OF FABRICATING A TRANSISTOR HAVING A TRENCH GATE - An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The sidewalls of the gate trench are formed of the nonconductive material and are substantially free of unetched substrate material. As a result, the sidewalls of the gate trench do not form an undesired conductive path between the source and the drain of the transistor, thereby advantageously reducing the amount of parasitic current that flows between the source and drain during operation.08-21-2008
20100304547REDUCTION OF STI CORNER DEFECTS DURING SPE IN SEMICONDCUTOR DEVICE FABRICATION USING DSB SUBSTRATE AND HOT TECHNOLOGY - A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.12-02-2010
20130157436FORMING THROUGH SUBSTRATE VIAS - A method is provided for establishing through substrate vias (TSVs) within a substrate. The method includes: forming at least one recess in a front-side of a wafer; filling, at least partially, the at least one recess with a sacrificial material from the front-side of the wafer; thinning the wafer from a back-side to reveal the at least one recess at least partially filled with the sacrificial material; removing from the back-side of the wafer the sacrificial material from the at least one recess; and filling the at least one recess from the back-side of the wafer with a conductive material to provide the at least one through substrate via.06-20-2013
20130157437PATTERN FORMING METHOD - According to one embodiment, firstly, an inversion pattern having a periodic pattern in which a first line pattern and a space are inversed and a non-periodic pattern arranged at an interval which is substantially equal to the width of the first line pattern from the end of the periodic pattern is formed above a processing object so as to correspond to the plurality of spaces between a plurality of first line patterns in a first pattern and the space between the first pattern and a second pattern. Next, a sidewall film is formed around the inversion pattern, and the periodic pattern is removed selectively. Thereafter, the processing object is etched using the sidewall pattern formed of the sidewall film and the non-periodic pattern surrounded by the sidewall film as masks.06-20-2013
20120282755METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE - A method for fabricating a nonvolatile memory device includes forming a substrate structure having a tunnel dielectric layer and a floating-gate conductive layer formed over an active region defined by a first isolation layer forming a first inter-gate dielectric layer and a first control-gate conductive layer over the substrate structure, forming a trench by etching the first control-gate conductive layer, the first inter-gate dielectric layer, the floating-gate conductive layer, the tunnel dielectric layer, and the active region to a given depth, forming a second isolation layer to fill the trench; and forming a second control-gate conductive layer over the resultant structure having the second isolation layer formed therein.11-08-2012
20110281418SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: first device regions divided by first isolation films and second device regions divided by second isolation films a gate insulating film formed on the semiconductor substrate; a first element including: a first gate formed on the gate insulating film in the first device regions, a first inter-electrode insulating film formed on the first gate and on the first isolation films, and a second gate formed on the first inter-electrode insulating film; and a second element including: a third gate formed on the gate insulating film in the second device regions, and a fourth gate formed on the third gate and on the second isolation films; wherein a thickness of the third gate is larger than a thickness of the first gate.11-17-2011
20120094466SEMICONDUCTOR DEVICE FABRICATION METHOD FOR IMPROVED ISOLATION REGIONS AND DEFECT-FREE ACTIVE SEMICONDUCTOR MATERIAL - A fabrication method for a semiconductor device structure is provided. The device structure has a layer of silicon and a layer of silicon dioxide overlying the layer of silicon, and the method begins by forming an isolation recess by removing a portion of the silicon dioxide and a portion of the silicon. The isolation recess is filled with stress-inducing silicon nitride and, thereafter, the silicon dioxide is removed such that the stress-inducing silicon nitride protrudes above the silicon. Next, the exposed silicon is thermally oxidized to form silicon dioxide hardmask material overlying the silicon. Thereafter, a first portion of the silicon dioxide hardmask material is removed to reveal an accessible surface of the silicon, while leaving a second portion of the silicon dioxide hardmask material intact. Next, silicon germanium is epitaxially grown from the accessible surface of the silicon.04-19-2012
20120094465INTEGRATED PLANAR AND MULTIPLE GATE FETS - A multiple gate field effect transistor and a planar field effect transistor formed in the same substrate each have a top planar surface underneath each corresponding gate that are co-planar with one another and also co-planar with a top surface of a shallow trench isolation region located therebetween. The relatively older planar FET fabrication technology has added to it the relatively newer MUGFET fabrication technology without disruption to the planar fabrication technology and with relatively little added cost.04-19-2012

Patent applications in class Grooved and refilled with deposited dielectric material

Patent applications in all subclasses Grooved and refilled with deposited dielectric material