Class / Patent application number | Description | Number of patent applications / Date published |
438423000 | Implanting to form insulator | 24 |
20080227265 | Methods for Fabricating Semiconductor Devices - Methods of fabricating a gate-insulating layer of a dual-gate semiconductor device are disclosed. A disclosed method comprises sequentially forming a buffer oxide layer and a nitride layer on a semiconductor substrate having at least one high voltage device area and at least one low voltage device area; forming at least one trench by selectively removing at least one portion of the buffer oxide layer, the nitride layer and the semiconductor substrate; forming at least one device isolation layer by depositing an oxide layer in the trench and planarizing the oxide layer; removing the nitride layer and the buffer oxide layer remaining on the high voltage device area; forming a first gate-insulating layer on the high voltage device area; removing the nitride layer and the buffer oxide layer remaining on the low voltage device area; and forming a second gate-insulating layer on the low voltage device area. | 09-18-2008 |
20090130816 | METHOD FOR MANUFACTURING SIMOX WAFER AND SIMOX WAFER MANUFACTURED THEREBY - This method for manufacturing a SIMOX wafer, includes: implanting oxygen ions in a silicon wafer; cleaning said silicon wafer into which said oxygen ions are implanted; and forming a buried oxide film within an interior of said silicon wafer by subjecting said cleaned silicon wafer to a heat treatment, wherein said method further includes immersing said silicon wafer in an aqueous solution of hydrofluoric acid and etching a SiO | 05-21-2009 |
20090186462 | Semiconductor device and Fabrication method - A semiconductor device in one embodiment has a first connection region, a second connection region and a semiconductor volume arranged between the first and second connection regions. Provision is made, within the semiconductor volume, in the vicinity of the second connection region, of a field stop zone for spatially delimiting a space charge zone that can be formed in the semiconductor volume, and of an anode region adjoining the first connection region. The dopant concentration profile within the semiconductor volume is configured such that the integral of the ionized dopant charge over the semiconductor volume, proceeding from an interface of the anode region which faces the second connection region, in the direction of the second connection region, reaches a quantity of charge corresponding to the breakdown charge of the semiconductor device only near the interface of the field stop zone which faces the second connection region. | 07-23-2009 |
20090191687 | METHOD OF FILLING A TRENCH AND METHOD OF FORMING AN ISOLATING LAYER STRUCTURE USING THE SAME - A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are then implanted into a portion of the preliminary insulating layer adjacent the top of the first trench to form a first insulating layer having a doped region and an undoped region. The doped region is removed to form a first insulating layer pattern at the bottom and sides of the first trench, and which first insulating layer pattern defines a second trench. The second trench is then filled with insulating material. | 07-30-2009 |
20090203186 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device, including: forming a first well of a second conduction type and a second well of a first conduction type on a semiconductor substrate of the first conduction type, forming a gate oxide corresponding to each element on a surface of the semiconductor substrate, forming trenches by etching at forming locations of first and second trench isolating regions respectively at a first depth larger than a depth of a diffusion layer formed in a memory-cell forming region within the second well and smaller than a depth of a diffusion layer of a transistor of a peripheral circuit region, executing additional etching at a forming location of the second trench isolating region so that a second depth larger than the first depth is obtained and doping the trenches at the forming locations of the first and second trench isolating regions respectively, with a doping agent, thereby executing a planarization process. | 08-13-2009 |
20090203187 | Method of Manufacturing SOI Substrate - To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. | 08-13-2009 |
20090258471 | Application of Different Isolation Schemes for Logic and Embedded Memory - The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic. | 10-15-2009 |
20100022066 | METHOD FOR PRODUCING HIGH-RESISTANCE SIMOX WAFER - A method for producing a high-resistance SIMOX wafer wherein oxygen diffused inside of a wafer by the heat treatment at a high temperature in an oxidizing atmosphere can be reduced to suppress the occurrence of thermal donor. In one embodiment, a heating-rapid cooling treatment is conducted after the heat treatment at a high temperature in an oxidizing atmosphere to implant vacancies from a surface of a wafer into an interior thereof to thereby easily precipitate oxygen diffused inside the wafer during the heat treatment. | 01-28-2010 |
20100190317 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SILICON OXIDE FILM FORMING METHOD - A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches. | 07-29-2010 |
20100311220 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND NAND-TYPE FLASH MEMORY - A method for manufacturing semiconductor device has forming a plurality of trenches having at least two kinds of aspect ratios on a semiconductor substrate, filling the plurality of trenches with a coating material containing silicon, forming a mask on the coating material in a part of the trenches among the plurality of trenches filled with the coating material, implanting an ion for accelerating oxidation of the coating material into the coating material in the trenches on which the mask is not formed, forming a first insulating film by oxidizing the coating materials into which the ion is implanted, removing the coating material from the part of the trenches after removing the mask and forming a second insulating film in the part of the trenches from which the coating material is removed. | 12-09-2010 |
20100323494 | NARROW CHANNEL WIDTH EFFECT MODIFICATION IN A SHALLOW TRENCH ISOLATION DEVICE - A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation. | 12-23-2010 |
20110070719 | TUNING OF SOI SUBSTRATE DOPING - A method of manufacturing a semiconductor device, the method comprising: taking an SOI substrate comprising a bulk substrate, a buried insulating layer and an active layer, and implanting the bulk substrate from the side of and through the insulating layer and the active layer so as to generate an area having an increased doping concentration in the bulk substrate at the interface between the bulk substrate and the insulating layer. | 03-24-2011 |
20110143518 | HETEROGENEOUS INTEGRATION OF LOW NOISE AMPLIFIERS WITH POWER AMPLIFIERS OR SWITCHES - A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier having a substrate wafer selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb), the substrate having a first end and a second end, a conducting layer above the first end of the substrate, an isolation implant providing lateral isolation in the conducting layer, a first active layer deposited above the conducting layer and configured for the low-noise amplifier, and a buffer layer deposited above the conducting layer and configured for the low-noise amplifier. | 06-16-2011 |
20110306178 | SEMICONDUCTOR DEVICE HAVING A SADDLE FIN SHAPED GATE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a saddle fin gate and a method for manufacturing the same are presented. The semiconductor device includes a semiconductor substrate, an isolation structure, and gates. The semiconductor substrate is defined with first grooves in gate forming areas. The isolation structure is formed in the semiconductor substrate and is defined with second grooves which expose front and rear surfaces of the gate forming areas. The gates are formed within the first grooves in the gate forming areas. Gates are also formed in the second grooves of the isolation structure to cover the exposed front and rear surfaces of the gate forming areas. The second grooves are wider at the lower portions that at the upper portions. | 12-15-2011 |
20120034754 | SEMICONDUCTOR DEVICE MANUFACATURING METHOD AND SILICON OXIDE FILM FORMING METHOD - A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches. | 02-09-2012 |
20120094464 | Method of Fabricating Semiconductor Device Isolation Structure - A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation. | 04-19-2012 |
20120135582 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Semiconductor device manufacturing method includes forming a first mask, having a first opening to implant ion into semiconductor substrate and being used to form first layer well, on semiconductor substrate; forming first-layer well having first and second regions by implanting first ion into semiconductor substrate using first mask; forming second mask, having second opening to implant ion into semiconductor substrate and being used to form second layer well, on semiconductor substrate; and forming second-layer well below first layer well by implanting second ion into semiconductor substrate using second mask. First region is formed closer to an edge of first-layer well than second region. Upon implanting first ion, first ion deflected by first inner wall of first mask is supplied to first region. Upon implanting second ion, second ion deflected by second inner wall of second mask is supplied to second region. | 05-31-2012 |
20120214289 | Method for Forming Semiconductor Substrate Isolation - The present invention provides a method for forming a semiconductor substrate isolation, comprising: providing a semiconductor substrate; forming a first oxide layer and a nitride layer sequentially on the semiconductor substrate; forming openings in the nitride layer and in the first oxide layer to expose parts of the semiconductor substrate; implanting oxygen ions into the semiconductor substrate from the openings; performing annealing to form a second oxide layer on at least top portions of the exposed parts of the semiconductor substrate; and removing the nitride layer and the first oxide layer. Compared to the conventional STI process, said method enables a more simply and easy process flow and is applicable to common semiconductor substrates and SOI substrates. | 08-23-2012 |
20120302036 | SEMICONDUCTOR DEVICE HAVING SOI SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region. | 11-29-2012 |
20130130471 | MANUFACTURING METHOD OF VERTICAL CHANNEL TRANSISTOR ARRAY - A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts. | 05-23-2013 |
20140349463 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a method for improving anti-radiation performance of SOI structure comprising following steps: implementing particle implantations of high-energy neutrons, protons and γ-rays to an SOI structure, and then performing annealing process. The present invention aims to improving anti-radiation performance of SOI devices by means of introducing displacement damage into a buried oxide layer through implantation of high-energy particles. | 11-27-2014 |
20150064874 | DUMMY FIN FORMATION BY GAS CLUSTER ION BEAM - FinFET structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (GCIB) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide. Unlike some prior art techniques, where some fins are removed prior to fin merging, in embodiments of the present invention, fins are not removed. Instead, semiconductor (silicon) fins are converted to dielectric (nitride/oxide) fins where it is desirable to have isolation between groups of fins that comprise various finFET devices on an integrated circuit (IC). | 03-05-2015 |
20160099168 | METHOD FOR DEFINING AN ISOLATION REGION(S) OF A SEMICONDUCTOR STRUCTURE - Methods for defining an isolation region of a semiconductor structure are provided. The method includes, for instance: providing a semiconductor structure with a recess therein; disposing an insulator layer conformally within the recess in the semiconductor structure to partially fill the recess; modifying at least one material property of the insulator layer to obtain a densified insulator layer within the recess, where the modifying reduces a thickness of the densified insulator layer compared to that of the insulator layer; and depositing at least one additional insulator layer within the recess over the densified insulator layer, where the densified insulator layer within the recess defines, at least in part, an isolation region of the semiconductor structure. | 04-07-2016 |
20160133506 | Method of Fabricating Semiconductor Device Isolation Structure - A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation. | 05-12-2016 |