Class / Patent application number | Description | Number of patent applications / Date published |
438421000 | Having air-gap dielectric (e.g., groove, etc.) | 54 |
20080268607 | Method of Fabricating Semiconductor Device - This patent relates to a method of fabricating a semiconductor device. Gate insulating layer patterns and gate electrode layer patterns may be formed over a semiconductor substrate. A photoresist pattern through which part of a region between the gate electrode layer patterns is exposed may be formed over the semiconductor substrate including the gate electrode layer patterns. A passivation film, having an etch rate slower than that of the semiconductor substrate, may be formed on the photoresist pattern. A first trench may be formed in the semiconductor substrate using an etch process by employing the passivation film and the photoresist pattern as an etch mask. An ion implantation process may be performed on the semiconductor substrate in which the first trench is formed. | 10-30-2008 |
20090004812 | METHOD FOR PRODUCING SHALLOW TRENCH ISOLATION - The present invention provides a method for producing a shallow trench isolation, comprises: forming a plurality of first grooves on a silicon substrate with a mask etching method, wherein the silicon substrate comprises a silicon layer, an oxide layer and a first polysilicon layer; conducting oxidation process on an inner peripheral portion of the second grooves to form an insulting layer. The depth of the insulating layer on the periphery of the first polysilicon layer formed by the oxidation process is larger than the depths of the insulating layers that are formed on the silicon layer and on the oxidation layer through the oxidation process; filling high density plasma oxide layer into the second grooves to form a plurality of high density plasma oxide layer fillers; removing the first polysilicon layer by etching; covering the silicon substrate with a second polysilicon layer by deposition; and polishing the second polysilicon layer to form a plurality of self-aligned floating gate. | 01-01-2009 |
20090004813 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR - A method and system are provided for fabricating a semiconductor device that includes a vertical channel transistor. An area of a buried bit line is uniformly formed by an isolation trench. The width of the isolation trench is adjusted by controlling the thickness of spacers. Consequently, the area of the buried bit line is relatively large compared with that of a typical buried bit line. The resistance characteristics of the buried bit line are improved and stability and reliability of the semiconductor device are ensured. | 01-01-2009 |
20090093100 | METHOD FOR FORMING AN AIR GAP IN MULTILEVEL INTERCONNECT STRUCTURE - The present invention generally provides a method for forming multilevel interconnect structures, including multilevel interconnect structures that include an air gap. One embodiment provides a method for forming conductive lines in a semiconductor structure comprising forming trenches in a first dielectric layer, wherein air gaps are to be formed in the first dielectric layer, depositing a conformal dielectric barrier film in the trenches, wherein the conformal dielectric barrier film comprises a low k dielectric material configured to serve as a barrier against a wet etching chemistry used in forming the air gaps in the first dielectric layer, depositing a metallic diffusion barrier film over the conformal low k dielectric layer, and depositing a conductive material to fill the trenches. | 04-09-2009 |
20090137093 | METHOD OF FORMING FINFET DEVICE - A method of forming a FINFET device includes providing a substrate with a plurality of trench devices arranged in array therein, each of the trench devices comprising a plug protruding above the substrate; forming a plurality of isolation structures along a first direction in the substrate adjacent to the trench devices so as to define an active area exposing the substrate; forming a spacer on each of the plug to define a reactive area between the active area and the spacer; and removing the isolation structures on the reactive area to form a fin structure in the active area. | 05-28-2009 |
20090170275 | Method for Manufacturing a Semiconductor Device - A method for manufacturing a semiconductor device includes forming a spin-on-carbon (SOC) film that facilitates a low temperature baking process, can prevent collapse of vertical transistors while forming a bit line, thereby providing a more simple manufacturing method and improving manufacturing yields. | 07-02-2009 |
20090170276 | Method of Forming Trench of Semiconductor Device - The present invention relates to a method of forming trenches of a semiconductor device. According to the method, a hard mask pattern is formed on a semiconductor substrate so that an isolation region of the semiconductor substrate is opened. First trenches are formed in the isolation region by performing a first etch process employing the hard mask pattern. A spacer is formed on sidewalls of the first trenches. Second trenches, having a depth deeper than that of the first trenches, are formed in the isolation region by performing a second etch process employing the hard mask pattern. | 07-02-2009 |
20090170277 | IMPLANT DAMAGE OF LAYER FOR EASY REMOVAL AND REDUCED SILICON RECESS - A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer. | 07-02-2009 |
20090246932 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure. | 10-01-2009 |
20090298256 | SEMICONDUCTOR INTERCONNECT AIR GAP FORMATION PROCESS - A semiconductor package including an interconnect air gap and method for making the same. The semiconductor package includes a dielectric layer, a metallic interconnect, an air gap disposed between the dielectric layer and interconnect, and a spacer interspersed between the metallic interconnect and air gap. The metallic interconnect is laterally supported by and isolated from the air gap by the spacer. A method for making the same is also provided. | 12-03-2009 |
20100047994 | FABRICATION OF INTEGRATED CIRCUITS WITH ISOLATION TRENCHES - After forming a stack of layers ( | 02-25-2010 |
20100144112 | Methods of Manufacturing Semiconductor Devices - Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region. | 06-10-2010 |
20110076831 | Solving Via-Misalignment Issues in Interconnect Structures Having Air-Gaps - An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; and a metallization layer over the semiconductor substrate. The metallization layer includes a conductive line; a low-k dielectric region adjacent and horizontally spaced apart from the conductive line by a space; and a filler dielectric material filling at least a portion of the space, wherein the filler dielectric material and the low-k dielectric region are formed of different materials. The integrated circuit structure further includes a capping layer over and adjoining the filler dielectric material and the low-k dielectric region. The filler dielectric material has a dielectric constant (k value) less than a k value of the capping layer. | 03-31-2011 |
20110092046 | Method of forming semiconductor devices in wafer assembly - An apparatus and method for holding a semiconductor device in a wafer. A bar is connected to the wafer. A first sidewall comprises a first end and a second, and is connected to the bar at its first end. A first tab comprises a first end and a second end, and is connected to the second end of the first sidewall at its first end and connected to the first side of the semiconductor device at its second end. The thickness of the first tab is less than the thickness of the bar and the thickness of the first sidewall. | 04-21-2011 |
20110104866 | ENHANCED ADHESION OF PECVD CARBON ON DIELECTRIC MATERIALS BY PROVIDING AN ADHESION INTERFACE - Amorphous carbon material may be deposited with superior adhesion on dielectric materials, such as TEOS based silicon oxide materials, in complex semiconductor devices by applying a plasma treatment, such as an argon treatment and/or forming a thin adhesion layer based on silicon dioxide, carbon-doped silicon dioxide, prior to depositing the carbon material. Consequently, the hard mask concept based on amorphous carbon may be applied with an increased degree of flexibility, since a superior adhesion may allow a higher degree of flexibility in selecting appropriate deposition parameters for the carbon material. | 05-05-2011 |
20110159663 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING SPACER PATTERNING TECHNIQUE - A method for fabricating a semiconductor device using optical proximity correction to form high integrated cell patterns that are less prone to bridge defects. The method includes: obtaining a target layout of cell patterns, which form rows in a cell region, and peripheral patterns of a peripheral region; forming oblique patterns, which are alternately overlapped in the rows of the cell patterns, and a reverse pattern of the peripheral patterns; attaching spacers to sidewalls of the oblique patterns and the reverse pattern; forming first burying patterns between the oblique patterns and a second burying pattern around the reverse pattern by filling gaps between the spacers; and forming the cell patterns by cutting and dividing the middle portions of the oblique patterns and the first burying patterns, and setting the peripheral pattern with the second burying pattern by removing the reverse pattern. | 06-30-2011 |
20110189833 | SILICA-BASED FILM FORMING MATERIAL FOR FORMATION OF AIR GAPS, AND METHOD FOR FORMING AIR GAPS - Provided is a silica-based film forming material for formation of air gaps, the material being capable of forming air gaps without employing a CVD method. A silica-based film forming material for formation of air gaps including (a) a certain siloxane polymer, (b) an alkanolamine, and (c) an organic solvent is used when a silica-based film is formed with a spin coating method. According to this silica-based film forming material for formation of air gaps, air gaps with a great degree of opening can be formed even when coated with a spin coating method, without filling the recessed parts. | 08-04-2011 |
20110223739 | METHOD FOR FABRICATING A PHASE-CHANGE MEMORY CELL - A substrate having buried address lines and a first dielectric layer is provided. A conductive electrode is formed in the first conductive layer. A top portion of the conductive electrode is exposed. A second dielectric layer is deposited on surface of the exposed top portion. The second dielectric layer defines a recess around the top portion. A third dielectric layer is deposited over the second dielectric layer. A portion of the third dielectric layer and a portion of the second dielectric layer are removed, thereby exposing a top surface of the top portion of the conductive electrode. The top portion of the conductive electrode is salicidized to form a heating stem. The remaining third dielectric layer is selectively removed from the recess. A phase-change material layer covers the heating stem and the second dielectric layer. The phase-change material layer is etched, thereby forming a phase-change storage cap. | 09-15-2011 |
20110269293 | Reduced STI Loss for Superior Surface Planarity of Embedded Stressors in Densely Packed Semiconductor Devices - A reduction in material loss of trench isolation structures prior to forming a strain-inducing semiconductor alloy in transistor elements may result in superior device uniformity, for instance with respect to drive current and threshold voltage. To this end, at least one etch process using diluted hydrofluoric acid may be omitted when forming the shallow trench isolations, while at the same time providing a high degree of compatibility with conventional process strategies. | 11-03-2011 |
20110281415 | METHODS OF FORMING AN ISOLATION LAYER AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING AN ISOLATION LAYER - In a method of forming an isolation layer, first and second trenches are formed on a substrate. The first and the second trenches have first and second widths, respectively, and the second width is greater than the first width. A second isolation layer pattern partially fills the second trench. A first isolation layer pattern and the third isolation layer pattern are formed. The first isolation layer pattern fills the first trench, and the third isolation layer pattern is formed on the second isolation layer pattern and fills a remaining portion of the second trench. | 11-17-2011 |
20120003809 | ISOLATION METHOD IN SEMICONDUCTOR DEVICE - The present invention discloses an isolation process in a semiconductor device. In the present invention, when a SPT process is used for isolation, ISO cut patterns for cutting spacers for SPT in the unit of a specific length are first formed, and ISO partition patterns defining partition regions for forming the spacers are then formed over the ISO cut patterns. Accordingly, there are advantages in that the SPT process can be simplified and costs can be reduced according to the simplified process because the isolation process is simplified. | 01-05-2012 |
20120129316 | METHOD FOR FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE - A method for forming fine pattern includes sequentially forming a first thin film and a second thin film over a target layer for patterning, forming a partition over the second thin film, removing the partition after forming spacers on sidewalls of the partition, forming first pattern of the second thin film by etching the second thin film of a first region and the second thin film of a second region while exposing the spacers, forming second pattern of the second thin film by using the spacers as masks and etching the first pattern of the second thin film in the first region, forming first thin film pattern by using the first and second patterns of the second thin film as masks in the first and second regions and etching the first thin film, and etching the pattern target layer. | 05-24-2012 |
20120156855 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device includes forming a plurality of strings spaced a first distance from each other, each string including first preliminary gate structures spaced a second distance, smaller than the first distance, between second preliminary gate structures, forming a first insulation layer to cover the first and second preliminary gate structures, forming an insulation layer structure to fill a space between the strings, forming a sacrificial layer pattern to partially fill spaces between first and second preliminary gate structures, removing a portion of the first insulation layer not covered by the sacrificial layer pattern to form a first insulation layer pattern, reacting portions of the first and second preliminary gate structures not covered by the first insulation layer pattern with a conductive layer to form gate structures, and forming a capping layer on the gate structures to form air gaps between the gate structures. | 06-21-2012 |
20120178235 | Air Isolation In High Density Non-Volatile Memory - Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Air gaps are formed at least partially in isolation regions between active areas of the substrate. The air gaps may further extend above the substrate surface between adjacent layer stack columns. A sacrificial material is formed at least partially in the isolation regions, followed by forming a dielectric liner. The sacrificial material is removed to define air gaps prior to forming the control gate layer and then etching it and the layer stack columns to form individual control gates and columns of non-volatile storage elements. | 07-12-2012 |
20120276711 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING SPACER WITH AIR GAP - A semiconductor device having a spacer with an air gap is manufactured by forming a first conductive pattern over a semiconductor substrate; forming a spacer on sidewalls of the first conductive pattern; forming a sacrifice layer on sidewall of the spacer, the sacrifice layer having a different etching selectivity with the spacer; forming a second conductive pattern to fill a space between the first conductive pattern and the first conductive pattern; and forming an air gap between the first and second conductive patterns by selectively removing the sacrifice layer. | 11-01-2012 |
20130157435 | Materials and Methods of Forming Controlled Void - The present invention is a process for forming an air gap within a substrate, the process comprising: providing a substrate; depositing a sacrificial material by deposition of at least one sacrificial material precursor; depositing a composite layer; removal of the porogen material in the composite layer to form a porous layer and contacting the layered substrate with a removal media to substantially remove the sacrificial material and provide the air gaps within the substrate; wherein the at least one sacrificial material precursor is selected from the group consisting of: an organic porogen; silicon, and a polar solvent soluble metal oxide and mixtures thereof. | 06-20-2013 |
20140120692 | Air Gap Isolation In Non-Volatile Memory - Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided. | 05-01-2014 |
20140295641 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer. | 10-02-2014 |
20140363950 | Materials and Methods of Forming Controlled Void - The present invention is a process for forming an air gap within a substrate, the process comprising: providing a substrate; depositing a sacrificial material by deposition of at least one sacrificial material precursor; depositing a composite layer; removal of the porogen material in the composite layer to form a porous layer and contacting the layered substrate with a removal media to substantially remove the sacrificial material and provide the air gaps within the substrate; wherein the at least one sacrificial material precursor is selected from the group consisting of: an organic porogen; silicon, and a polar solvent soluble metal oxide and mixtures thereof. | 12-11-2014 |
20150087132 | WAFER PROCESSING - Semiconductor device and method for forming a semiconductor device are presented. A substrate having top and bottom pad stacks is provided. Each pad stack includes at least first and second pad layers. The second pad layer of the bottom pad stack is removed by a batch process. Trench isolation regions are formed in the substrate. | 03-26-2015 |
20150099343 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of auxiliary patterns formed over a semiconductor substrate, a plurality of gate line patterns disposed in parallel with one another over the semiconductor substrate between the plurality of auxiliary patterns, and an air gap formed between the plurality of gate line patterns and between each of the plurality of gate line patterns and each of the auxiliary patterns. | 04-09-2015 |
20150332953 | BARRIER LAYER STACK FOR BIT LINE AIR GAP FORMATION - Air gaps are formed between conductive metal lines that have an inner barrier layer and an outer barrier layer. An etch step to remove sacrificial material is performed under a first set of process conditions producing a byproduct that suppresses further etching. A byproduct removal step performed under a second set of process conditions removes the byproduct. | 11-19-2015 |
20150348980 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate including a plurality of active regions divided by a plurality of trenches, a plurality of tunnel insulating layer patterns formed over the active regions, a plurality of conductive film patterns formed over the tunnel insulating film patterns, a plurality of first isolation layers formed on sidewalls and bottom surfaces of the trenches, and a plurality of second isolation layers formed between the conductive film patterns. | 12-03-2015 |
20150380421 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Provided are a semiconductor memory device and a method of fabricating the same. the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench. | 12-31-2015 |
20160035614 | INTEGRATED BIT-LINE AIRGAP FORMATION AND GATE STACK POST CLEAN - Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called “2-d flat cell” flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents. | 02-04-2016 |
20160172196 | Method of Semiconductor Integrated Circuit Fabrication | 06-16-2016 |
20160181377 | SEMICONDUCTOR DEVICE HAVING DUAL WORK FUNCTION GATE STRUCTURE, METHOD FOR FABRICATING THE SAME, MEMORY CELL HAVING THE SAME, AND ELECTRONIC DEVICE HAVING THE SAME | 06-23-2016 |
438422000 | Enclosed cavity | 17 |
20090148998 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material using an orientation-dependent etch to form a first cavity, a second cavity, wherein the first cavity is isolated from the second cavity, a first protrusion is between the first cavity and the second cavity, and the semiconductor material comprises silicon. The method further includes performing a thermal oxidation to convert a portion of the silicon of the semiconductor material to silicon dioxide and forming a first dielectric material over the first cavity, over the second cavity, over at least a portion of the semiconductor material, and over at least a portion of the first protrusion. Other embodiments are described and claimed. | 06-11-2009 |
20090233415 | Semiconductor Devices with Sealed, Unlined Trenches and Methods of Forming Same - A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches. | 09-17-2009 |
20090263951 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes the steps of forming an insulating film on a semiconductor substrate, forming a plurality of wiring trenches in the insulating film, forming a plurality of wirings in the plurality of wiring trenches, forming a resist mask having an opening for selectively exposing one of regions between the plurality of wirings, on the insulating film and the plurality of wirings, forming an air gap trench by removing the insulating film from the selectively exposed one of the regions between the plurality of wirings by etching using the resist mask, and forming an air gap in the air gap trench by depositing an inter-layer insulating film over the plurality of wirings after removal of the resist mask. | 10-22-2009 |
20090269904 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate, a first diffusion region formed in the semiconductor substrate, a semiconductor element formed in the first diffusion region, and a channel formed in the first diffusion region to receive a cooling fluid. | 10-29-2009 |
20090305480 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND STORAGE MEDIUM - A method of manufacturing a semiconductor device, including an interlayer insulating layer having a dielectric constant of about 1, includes at least one of hydrophobically modifying an interlayer insulating film for insulating lines from each other, before forming air gaps in the interlayer insulating film, and hydrophobically modifying the lines, after forming the air gaps in the interlayer insulating film. | 12-10-2009 |
20100035403 | Integrated Circuit Structure, Design Structure, and Method Having Improved Isolation and Harmonics - Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation. | 02-11-2010 |
20100129980 | Methods Of Forming Diodes - Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed. | 05-27-2010 |
20100248443 | Method of integrating an air gap structure with a substrate - A method for forming an air gap structure on a substrate is described. The method comprises depositing a sacrificial layer on a substrate, forming an adhesion-promoting layer between the sacrificial layer and the substrate, and depositing a capping layer over the sacrificial layer. The sacrificial layer and the capping layer are patterned and metalized. Thereafter, the sacrificial layer is decomposed and removed through the capping layer. | 09-30-2010 |
20100273308 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a structure includes a dielectric material and a void below a surface of a substrate. The structure further includes a doped dielectric material over the dielectric material, over the first void, wherein at least a portion of the dielectric material is between at least a portion of the substrate and at least a portion of the doped dielectric material. Other embodiments are described and claimed. | 10-28-2010 |
20120070957 | AIR GAP FORMATION - A method of forming air gaps between adjacent raised features on a substrate includes forming a carbon-containing material in a bottom region between the adjacent raised features using a flowable deposition process. The method also includes forming a silicon-containing film over the carbon-containing material using a flowable deposition process, where the silicon-containing film fills an upper region between the adjacent raised features and extends over the adjacent raised features. The method also includes curing the carbon-containing material and the silicon-containing material at an elevated temperature for a period of time to form the air gaps between the adjacent raised features. | 03-22-2012 |
20120264275 | FIELD EFFECT TRANSISTOR WITH AIR GAP DIELECTRIC - A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane. | 10-18-2012 |
20130102124 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a method of manufacturing a semiconductor device includes forming an isolation trench in a substrate, and forming an amorphous layer on a sidewall surface of the isolation trench. The method further includes forming a sacrificial layer in the isolation trench via the amorphous layer, and forming an air gap layer on the sacrificial layer. The method further includes forming an air gap in the isolation trench under the air gap layer by removing the sacrificial layer after forming the air gap layer. | 04-25-2013 |
20130337630 | Methods of Forming a Span Comprising Silicon Dioxide - Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures. | 12-19-2013 |
20140248754 | CONTROLLED AIR GAP FORMATION - A method of forming and controlling air gaps between adjacent raised features on a substrate includes forming a silicon-containing film in a bottom region between the adjacent raised features using a flowable deposition process. The method also includes forming carbon-containing material on top of the silicon-containing film and forming a second film over the carbon-containing material using a flowable deposition process. The second film fills an upper region between the adjacent raised features. The method also includes curing the materials at an elevated temperature for a period of time to form the air gaps between the adjacent raised features. The thickness and number layers of films can be used to control the thickness, vertical position and number of air gaps. | 09-04-2014 |
20140248755 | METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES INCLUDING VOIDS BETWEEN ACTIVE REGIONS AND RELATED DEVICES - A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed. | 09-04-2014 |
20160093523 | SEMICONDUCTOR STRUCTURE WITH AIRGAP - A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap. | 03-31-2016 |
20160133507 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An object of the invention is to provide a semiconductor device having improved performance. A method of manufacturing a semiconductor device includes: forming a trench and then forming a first insulating film made of a silicon oxide film through CVD using a gas containing an O | 05-12-2016 |