Class / Patent application number | Description | Number of patent applications / Date published |
438401000 | Having substrate registration feature (e.g., alignment mark) | 62 |
20080200004 | Method of fabricating semiconductor optical device - In a method of fabricating a semiconductor optical device, insulating structures for an alignment mark for use in electron beam exposure is formed on a primary surface of a first III-V semiconductor region. After forming the insulating structures, a second III-V semiconductor region is grown on the first III-V semiconductor region to form an epitaxial wafer. The height of the insulating structures is larger than thickness of the second III-V semiconductor region. After forming the second III-V semiconductor region, alignment for the electron beam exposure is performed. After the alignment, a resist is exposed to electron beam to form a resist mask. The resist mask has a pattern for a diffraction grating, and the resist is on the epitaxial wafer. | 08-21-2008 |
20080242043 | METHOD FOR CHECKING ALIGNMENT ACCURACY USING OVERLAY MARK - A method for checking the alignment accuracy using an overlay mark is provided. The overlay mark includes an inner mark and an outer mark formed on a wafer. The outer mark is formed in a lower layer on the wafer when the lower layer is patterned. The inner mark is formed within the outer mark over the lower layer when a lithography process for defining an upper layer is performed. A measurement process is conducted to obtain a first relation between each of the interior profiles of the outer marks and a second relation between each of the inner marks. Alternatively, a third relation between each of the interior profiles of the outer marks and each of the inner marks is obtained. The X-directional alignment accuracy and y-directional alignment accuracy are computed according to the first and the second relations, or the third relation. | 10-02-2008 |
20080318389 | METHOD OF FORMING ALIGNMENT KEY OF SEMICONDUCTOR DEVICE - The formation of an alignment key for overlay measurement of a semiconductor device formed by sequentially forming an inter-metal dielectric layer and a capping layer over a semiconductor substrate, and patterning the inter-metal dielectric layer and a capping layer at an alignment key region to thereby form an alignment key hole. A metal layer may then be deposited over the semiconductor substrate including alignment key hole and then an uppermost surface of the deposited metal layer may then be polished to thereby form the alignment key having a step. Accordingly, a dishing phenomenon occurring at the time of polishing using a capping layer can be prevented and an alignment key having a desired step can be formed. | 12-25-2008 |
20090011567 | Method for manufacturing display substrate - A method for manufacturing a display substrate is disclosed, which includes the following steps: providing a substrate; forming a plurality of bumps on an active area of the substrate and at least one marking pattern on a non-active area of the substrate; and staining the marking pattern or filling a material having low transmittance ratio into the marking pattern. The present invention further discloses a method for making a display substrate, including the steps: providing a substrate; forming a shadow layer on a non-active area of the substrate; forming a plurality of bumps on an active area of the substrate and at least one marking pattern on the shadow layer of the non-active area on the substrate; and removing a part of the shadow layer not covered by the marking pattern. | 01-08-2009 |
20090023266 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, includes forming a structure wherein a first alignment mark is provided in a first alignment-mark arrangement area of a first layer, a second alignment mark is provided in a second alignment-mark arrangement area of a second layer, a dummy pattern is provided above the first alignment-mark arrangement area, and substantially no dummy pattern is provided above the second alignment-mark arrangement area, and aligning a third layer provided above the structure by using the second alignment mark. | 01-22-2009 |
20090042355 | SEMICONDUCTOR WAFER AND MANUFACTURING METHOD THEREFOR - A plurality of IC regions are formed on a semiconductor wafer, which is cut into individual chips incorporating ICs, wherein wiring layers and insulating layers are sequentially formed on a silicon substrate. In order to reduce height differences between ICs and scribing lines, a planar insulating layer is formed to cover the overall surface with respect to ICs, seal rings, and scribing lines. In order to avoid occurrence of breaks and failures in ICs, openings are formed to partially etch insulating layers in a step-like manner so that walls thereof are each slanted by prescribed angles ranging from 20° to 80°. For example, a first opening is formed with respect to a thin-film element section, and a second opening is formed with respect to an external-terminal connection pad. | 02-12-2009 |
20090061590 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device capable of eliminating additional processes for forming an alignment key, thereby shortening the manufacturing process and lowering the manufacturing costs. The method includes forming an insulating layer including wiring regions and an alignment key region over a substrate; forming a first trench and a second trench on the wiring regions and alignment key region of the insulating layer, respectively; laminating a metal layer over the insulating layer including the first trench and second trench, the metal layer completely filling the first trench and partially filling in the second trench and having a height difference between the wiring region and alignment key region; forming a damascene metal wiring in the first trench and forming an alignment mark layer in the second trench by polishing the metal layer; and forming an MIM capacitor over the entire surface of the insulating layer including the metal wiring and alignment mark layer using the alignment mark layer as an alignment key. Since it is not necessary to perform a process for repeatedly forming the alignment key during manufacturing an MIM capacitor, a process for aligning the serial masks is not necessary. Therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced. | 03-05-2009 |
20090075451 | Method for manufacturing semiconductor substrate - The present invention provides a method for manufacturing a semiconductor substrate in which a semiconductor wafer, formed of a material less likely to increase the hole diameter, is processed to a semiconductor substrate actually applicable to an existing manufacture line. An SiC wafer | 03-19-2009 |
20090075452 | SUBSTRATE PROVIDED WITH AN ALIGNMENT MARK IN A SUBSTANTIALLY TRANSMISSIVE PROCESS LAYER, MASK FOR EXPOSING SAID MARK, DEVICE MANUFACTURING METHOD, AND DEVICE MANUFACTURED THEREBY - A substrate provided with an alignment mark in a substantially transmissive process layer overlying the substrate, said mark comprising high reflectance areas for reflecting radiation of an alignment beam of radiation, and low reflectance areas for reflecting less radiation of the alignment beam, wherein the high reflectance areas comprise at least one substantially linear sub-grating. In one example, a substantially linear sub-grating comprises a plurality of spaced square regions. | 03-19-2009 |
20090087959 | METHOD FOR FORMING A PATTERN OF A SEMICONDUCTOR DEVICE - In a method for forming a fine pattern of a semiconductor device, forming a spacer for double patterning of a cell region is performed separate from forming a mask pattern that defines a dummy pattern for a pad of a peripheral circuit region. | 04-02-2009 |
20090137092 | Method for manufacturing semiconductor device - A method for manufacturing a semiconductor device includes forming a plurality of trenches for element isolation and a plurality of trenches for alignment mark on a substrate. The substrate has an active region. The method also includes laminating an oxide film on the substrate and over both of the trenches. The method also includes etching the oxide film using a resist mask that masks the element isolation trenches, so that the oxide film laminated in the active region and the oxide film laminated in the alignment mark trenches are removed. The method also includes polishing a surface of the substrate to planarize or smooth the surface of the substrate. Accordingly, those portions of the oxide film which project from the substrate surface are eliminated and the oxide film remains only inside the element isolation trenches. This divides the active region into a plurality of individual active regions for the respective semiconductor elements. The method also includes positioning the resist mask using the alignment mark trenches. The resist mask is used to fabricate the semiconductor elements in the active regions of the substrate. | 05-28-2009 |
20090148997 | PROCESS FOR MANUFACTURING SEMICONDUCTOR DEVICE - Reduction of damage to a semiconductor device due to a marking process while inhibiting deterioration of a mark can not be achieved in conventional processes for manufacturing semiconductor devices. A process for manufacturing the semiconductor device | 06-11-2009 |
20090233414 | Method for fabricating group III-nitride high electron mobility transistors (HEMTs) - A method of manufacturing a transistor comprises providing a wafer; growing a group III-nitride semiconductor material on a first side of the wafer; creating alignment marks on a second side of the wafer, the second side of the wafer being positioned opposite to the first side of the wafer; etching the first side of the wafer to create free standing walls on the first side of the wafer; growing pendeo-epitaxy regrowth regions on the free standing walls; and forming mesa isolated regions in the pendeo-epitaxy regrowth regions. The method may further comprise positioning a patterned mask on the first side of the wafer; and aligning the patterned mask with the alignment marks located on the second side of the wafer. | 09-17-2009 |
20090298254 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In a semiconductor device manufacturing method, a surface of a substrate structure including a semiconductor layer is covered with a first film including first and second openings. The first opening is configured as an alignment mark. The second opening is configured as an opening for introducing an impurity into a first predetermined position of the semiconductor layer. In this method, a third opening is formed in the first film, using a photo mask aligned with the first opening used as an alignment mark. The third opening is configured as an opening for introducing an impurity into a second predetermined position of the semiconductor layer. | 12-03-2009 |
20090311844 | ALIGNMENT MARK AND METHOD FOR FABRICATING THE SAME AND ALIGNMENT METHOD OF SEMICONDUCTOR - An alignment mark, disposed on a substrate, is provided. The alignment mark includes a first dielectric layer and a metal layer. The first dielectric layer is disposed on the substrate and includes an alignment trench and a contact hole. The metal layer is disposed in the alignment trench and the contact hole, wherein a surface of the metal layer is even with a surface of the first dielectric layer. Because the metal layer and the first dielectric layer have different reflection indexes and different refraction indexes, an alignment light detects the alignment mark according to these differences. | 12-17-2009 |
20100112779 | METHOD AND APPARATUS FOR INDICATING DIRECTIONALITY IN INTEGRATED CIRCUIT MANUFACTURING - An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit. | 05-06-2010 |
20100197105 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area. | 08-05-2010 |
20100203701 | Crack Stop and Moisture Barrier - A design for a crack stop and moisture barrier for a semiconductor device includes a plurality of discrete conductive features formed at the edge of an integrated circuit proximate a scribe line. The discrete conductive features may comprise a plurality of staggered lines, a plurality of horseshoe-shaped lines, or a combination of both. | 08-12-2010 |
20100210088 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes the steps of: forming first and second alignment marks by forming first and second alignment mark grooves on a first surface of a semiconductor substrate and filling the grooves with a material different from the semiconductor substrate; forming a first element on the first surface in alignment using the first alignment mark; bonding a support substrate to the first surface; reversing a bonded structure of the support substrate and the semiconductor substrate around a predetermined axis and thinning the semiconductor substrate from a second surface side of the semiconductor substrate at least until a thickness with which a position of the second alignment mark is detected by reflected light obtained by application of alignment light from the second surface side of the semiconductor substrate is obtained; and forming a second element on the second surface in alignment using the second alignment mark. | 08-19-2010 |
20100227451 | Method for manufacturing semiconductor device - A semiconductor device manufacturing method includes: forming an element-isolating insulating film in an element-forming region, and an underlying insulating film in a peripheral region; forming a gate material film; etching the gate material film to form a gate pattern and removing the gate material film on the underlying insulating film to form an alignment mark-forming region; forming an interlayer insulating film; etching the interlayer insulating film to form a contact hole, and a mark hole in the alignment mark-forming region; forming a first conductive film so as to fill the contact hole but not to fill the mark hole; removing the first conductive film outside the contact hole and the mark hole; forming a second conductive film so as not to fill the mark hole; and performing lithographic alignment by taking advantage of a level difference created by a recess left inside the mark hole. | 09-09-2010 |
20100240192 | ALIGNMENT MARK, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND MASK SET - An alignment mark formed by using a first mask used in forming a same memory cell pattern on a substrate and formed together with the memory cell pattern includes: a first pattern for position detection used for alignment in forming a first wiring pattern; and a first irregular reflection prevention mark that suppresses, when a position detection signal is irradiated as alignment in forming a second wiring pattern further on an upper layer side than the first wiring pattern, irregular reflection of a position detection signal from a second pattern for position detection formed further in a lower layer than the first pattern for position detection. | 09-23-2010 |
20100291749 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks. | 11-18-2010 |
20100304546 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR THIN FILM, WHICH IS SUBJECTED TO HEAT TREATMENT TO HAVE ALIGNMENT MARK, CRYSTALLIZING METHOD FOR THE SEMICONDUCTOR THIN FILM, AND CRYSTALLIZING APPARATUS FOR THE SEMICONDUCTOR THIN FILM - Exact alignment of a recrystallized region, which is to be formed in an amorphous or polycrystalline film, is facilitated. An alignment mark is formed, which is usable in a step of forming an electronic device, such as a thin-film transistor, in the recrystallized region. In addition, in a step of obtaining a large-grain-sized crystal-phase semiconductor from a semiconductor film, a mark structure that is usable as an alignment mark in a subsequent step is formed on the semiconductor film in the same exposure step. Thus, the invention includes a light intensity modulation structure that modulates light and forms a light intensity distribution for crystallization, and a mark forming structure that modulates light and forms a light intensity distribution including a pattern with a predetermined shape, and also forms a mark indicative of a predetermined position on a crystallized region. | 12-02-2010 |
20110014772 | ALIGNING METHOD OF PATTERNED ELECTRODE IN A SELECTIVE EMITTER STRUCTURE - An aligning method of patterned electrode in a selective emitter structure includes the following steps. A substrate is provided. A barrier layer is then formed on the substrate. The barrier layer is patterned, and thus the substrate is partially exposed to form a patterned electrode region. Thereafter, the surface property of the substrate located in the patterned electrode region is changed, so as to form a visible patterned mark. Subsequently, the barrier layer is removed, and the visible patterned mark is used as alignment mark. | 01-20-2011 |
20110053337 | SELF-ALIGNMENT METHOD FOR RECESS CHANNEL DYNAMIC RANDOM ACCESS MEMORY - A self-alignment method for a recess channel dynamic random access memory includes providing a substrate with a target layer, a barrier layer and a lining layer, wherein the target layer has shallow trench isolation structures; patternizing the lining layer, barrier layer and target layer to form recess trench channels; depositing a dielectric layer onto the recess trench channel; forming an ion doped region in the target layer; removing a portion of the dielectric layer to expose a portion of the recess trench channel; forming a filler layer covered onto the recess trench channel; removing a portion of the filler layer to expose a portion of the recess trench channel; forming a passivation layer onto the recess trench channel; removing the passivation layer on the lining layer; and removing the lining layer to form a plurality of structural monomers disposed at the recess trench channel and protruded from the target layer. | 03-03-2011 |
20110065254 | Semiconductor device fabrication method and pattern formation mold - According to the present invention, there is provided a semiconductor device fabrication method comprising, bringing a mold having a predetermined pattern into contact with at least a portion of an imprinting material formed on a substrate to be processed, and forming the pattern on the substrate to be processed by sequentially transferring the pattern for each shot, wherein one of a dicing region and a monitor pattern formation region of the substrate to be processed is coated with the imprinting material. | 03-17-2011 |
20110076830 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A semiconductor substrate is provided in which an alignment mark is formed that can be used for an aligment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N | 03-31-2011 |
20110117719 | METHODS OF PROCESSING SEMICONDUCTOR SUBSTRATES IN FORMING SCRIBE LINE ALIGNMENT MARKS - A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features. Individual of the photoresist blocks have an opposing pair of second pattern edges in the cross-section that self-align laterally outward of the first pattern edges to the laterally innermost sidewalls of the features during the patterning. | 05-19-2011 |
20110151641 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes the following processes. A first groove is formed in a semiconductor substrate. An insulating film is formed in the first groove. An interlayer insulating film is formed over the semiconductor substrate. A removing process is performed to remove a part of the interlayer insulating film and a part of the insulating film to form an alignment mark in the first groove. | 06-23-2011 |
20110177670 | THROUGH SILICON VIA LITHOGRAPHIC ALIGNMENT AND REGISTRATION - A method of manufacturing an integrated circuit structure forms a first opening in a substrate and lines the first opening with a protective liner. The method deposits a material into the first opening and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. The method removes the material from the first opening through the second opening in the protective material. The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material. | 07-21-2011 |
20110244647 | Mark Structure for Coarse Wafer Alignment and Method for Manufacturing Such a Mark Structure - A method for forming a mark structure on a substrate comprising a plurality of lines. The lines extend parallel to each other in a first direction and are arranged with a pitch between each pair of lines that is directed in a second direction perpendicular to the first direction. The pitch between each pair of selected lines differs from the pitch between each other pair of selected lines. | 10-06-2011 |
20110250732 | ORIENTATION OF AN ELECTRONIC CMOS STRUCTURE WITH RESPECT TO A BURIED STRUCTURE IN THE CASE OF A BONDED AND THINNED-BACK STACK OF SEMICONDUCTOR WAFERS - The invention is based on a method for aligning an electronic CMOS structure with respect to a buried structure in the case of a bonded and thinned back stack of semiconductor wafers. The method is intended to avoid “front side to rear side” alignments. The proposed method for aligning the electronic CMOS structure uses the formation of alignment marks ( | 10-13-2011 |
20110294278 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device which prevents damage to alignment marks used for alignment between a superjunction structure and process layers at subsequent steps. In the related art, recesses are made in a semiconductor substrate before the formation of the superjunction structure and used as alignment marks and in order to prevent damage to the alignment marks, the alignment marks are covered by an insulating film such as a silicon oxide film during the subsequent process of forming the superjunction structure, but the inventors have found that damage may penetrate the cover film, reach the semiconductor substrate and destroy the marks. In the method according to the invention, alignment marks for alignment between the superjunction structure and process layers at subsequent steps are formed after the formation of the superjunction structure. | 12-01-2011 |
20110306176 | ALIGNMENT MARK FOR OPAQUE LAYER - An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process. | 12-15-2011 |
20120028436 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing a semiconductor wafer, the method including: providing a base wafer including a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of the metal layers, wherein the monocrystalline layer includes second alignment marks; and performing a lithography using at least one of the first alignment marks and at least one of the second alignment marks. | 02-02-2012 |
20120058620 | EXPOSURE MASK AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A method for manufacturing a semiconductor device comprises performing an exposing and developing process using an exposure mask including shading patterns and assistant patterns arranged in parallel to the shading patterns to prevent a scum phenomenon generated when a main pattern is formed in a cell region over a semiconductor substrate, thereby improving characteristics, reliability and yield of the semiconductor device. As a result, the method enables high-integration of the semiconductor device. | 03-08-2012 |
20120129315 | Method for fabricating semiconductor package - A method for fabricating a semiconductor package includes the steps of: providing an alignment board having a plurality of openings and a plurality of alignment marks corresponding to the openings, respectively; disposing a plurality of chips on the alignment board at positions corresponding to the openings according to the alignment marks; pressing the alignment board with a carrier board having a soft layer disposed on one surface thereof so as to embed the chips in the soft layer of the carrier board; and removing the alignment board. As such, the positions of the chips are accurately positioned according to the alignment marks on the alignment board. | 05-24-2012 |
20120208343 | METHOD FOR MANUFACTURING A MICRO-ELECTRO-MECHANICAL DEVICE, IN PARTICULAR AN OPTICAL MICROSWITCH, AND MICRO-ELECTRO-MECHANICAL DEVICE THUS OBTAINED - A method for manufacturing a micro-electro-mechanical device, which has supporting parts and operative parts, includes providing a first semiconductor wafer, having a first layer of semiconductor material and a second layer of semiconductor material arranged on top of the first layer, forming first supporting parts and first operative parts of the device in the second layer, forming temporary anchors in the first layer, and bonding the first wafer to a second wafer, with the second layer facing the second wafer. After bonding the first wafer and the second wafer together, second supporting parts and second operative parts of said device are formed in the first layer. The temporary anchors are removed from the first layer to free the operative parts formed therein. | 08-16-2012 |
20120270379 | METHOD OF FABRICATING A DUMMY GATE STRUCTURE IN A GATE LAST PROCESS - A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate. | 10-25-2012 |
20130149836 | METHOD OF DOUBLE-SIDED PATTERNING - A method of double-sided patterning including positioning a first silicon wafer with its back side facing upwards and forming one or more deep trenches serving as alignment marks on the back side of the first silicon wafer; performing alignment with respect to the alignment marks and forming a back-side pattern on the first silicon wafer; depositing a polishing stop layer on the back side of the first silicon wafer; flipping over the first silicon wafer and bonding its back side with the front side of a second silicon wafer; polishing the front side of the first silicon wafer to expose the alignment marks from the front side; performing alignment with respect to the alignment marks and forming a front-side pattern on the first silicon wafer; removing the second silicon wafer and the polishing stop layer to obtain a double-sided patterned structure on the first silicon wafer. | 06-13-2013 |
20130164908 | MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY SUBSTRATE - A manufacturing method for a TFT array substrate includes providing a substrate; defining a plurality of normal alignment regions and a plurality of abnormal alignment regions on the substrate; forming an insulating layer and a transparent conductive layer on the substrate; performing a patterning process to at least one of the insulating layer and the transparent conductive layer to form a plurality of alignment structures in each abnormal alignment region; forming an alignment material layer on the substrate, the alignment material layer having a plurality of first alignment slits formed along the alignment structures in each of the abnormal alignment regions; and performing a rubbing alignment process to form a plurality of second alignment slits on the alignment material layer in each of the normal alignment regions along a alignment direction. | 06-27-2013 |
20130210213 | METHOD FOR FORMING SELF-ALIGNED OVERLAY MARK - A method for forming a self-aligned overlay mark is disclosed. First, a first region, a second region and a main feature which is disposed between the first region and the second region all disposed on the substrate are provided. The first region defines a first edge and the second region defines a second edge. Second, a cut mask layer is formed to respectively cover the first region and the second region to expose the main feature. Next, the cut mask layer is determined if it is self-aligned with the second edge or the first edge, and creates a self-aligned overlay mark. Later, a main feature etching step is carried out to transfer the main feature into the substrate when the cut mask layer is determined to be self-aligned with the second edge or the first edge. | 08-15-2013 |
20130230964 | MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A method for manufacturing a semiconductor integrated circuit device includes the step of forming an SOI device region and a bulk device region on an SOI type semiconductor wafer. The method includes: removing a BOX layer and an SOI layer in a bulk device region; and thereafter forming an STI region in both the SOI device region and the bulk device region. In the method, the STI region in the SOI device region is formed to extend through the BOX layer. | 09-05-2013 |
20130330904 | OVERLAY MARK ASSISTANT FEATURE - A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector. | 12-12-2013 |
20130330905 | EDGE CONNECT WAFER LEVEL STACKING - A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements, then forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements, then forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces and dicing the assembly into packages. Additional embodiments include methods for creating stacked packages using substrates and having additional traces that extend to both the top and bottom of the package. | 12-12-2013 |
20140030867 | METHODS OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming an etch-target layer on a substrate having an alignment key, forming a transparent first pattern on the etch-target layer to face the alignment key, forming an opaque second pattern on the etch-target layer to be adjacent to the first pattern, and etching the etch-target layer using the first pattern and the second pattern as an etch mask. | 01-30-2014 |
20140051224 | METHOD OF BACK-SIDE PATTERNING - A method of back-side patterning of a silicon wafer is disclosed, which includes: depositing a protective layer on a front side of a silicon wafer; forming one or more deep trenches through the protective layer and extending into the silicon wafer by a depth greater than a target thickness of the silicon wafer; flipping over the silicon wafer and bonding the front side of the silicon wafer with a carrier wafer; polishing a back side of the silicon wafer; performing alignment by using the one or more deep trench alignment marks and performing back-side patterning process on the back side of the silicon wafer; and de-bonding the silicon wafer with the carrier wafer. | 02-20-2014 |
20140065793 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - An alignment mark is formed on a substrate including a first region and a second region. The alignment mark is formed in the second region. An etch target layer including a crystalline material is formed on the alignment mark and the substrate. The etch target layer in the first region is partially amorphized. The amorphized etch target layer is etched to form an opening. | 03-06-2014 |
20140094015 | ALIGNMENT MEASUREMENT SYSTEM, OVERLAY MEASUREMENT SYSTEM, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, an alignment measurement system is configured to measure a position of a mark having the highest identifiability of a plurality of marks formed in a substrate. The plurality of marks are made of mutually different patterns. A device pattern is formed in the substrate using directed self-assembly after the plurality of marks is formed. | 04-03-2014 |
20140094016 | Alignment for Backside Illumination Sensor - Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces. | 04-03-2014 |
20140147984 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THROUGH SILICON VIA STRUCTURE - A method of fabricating a through silicon via structure includes the following steps. At first, a substrate is provided, and a dielectric layer is formed on the substrate. Subsequently, at least one first opening is formed in the dielectric layer, and the substrate exposed by the first opening is partially removed to form at least one via opening. A conductive material layer is then formed to fill the via opening and the first opening, and the conductive material layer is planarized. | 05-29-2014 |
20140206172 | ALIGNMENT MARK AND METHOD OF MANUFACTURING THE SAME - An alignment mark includes a plurality of mark units. Each mark unit includes a first element and a plurality of second elements. Each second element includes opposite first and second end portions. The plurality of second elements are arranged along a direction. The first element extends adjacent to the first end portions of the plurality of second elements and parallel to the direction of the plurality of second elements. | 07-24-2014 |
20140206173 | METHOD FOR PROCESSING SEMICONDUCTORS USING A COMBINATION OF ELECTRON BEAM AND OPTICAL LITHOGRAPHY - Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a Schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as TaN and the semiconductor device is a GaN semiconductor device. A semiconductor structure having a metal alignment mark on a zero layer of the structure, the metal alignment mark is a TaN and the semiconductor is GaN. | 07-24-2014 |
20140287566 | METHOD OF MAKING A SEMICONDUCTOR CHIP INCLUDING IDENTIFYING MARKS - A semiconductor chip includes a first mark for identifying a position of the chip within an exposure field. The semiconductor chip includes a first matrix in a first layer of the chip and a second mark within the first matrix identifying a position of the exposure field on a wafer. | 09-25-2014 |
20140342525 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N | 11-20-2014 |
20140342526 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N | 11-20-2014 |
20140349462 | METHOD FOR PRODUCING THIN SEMICONDUCTOR COMPONENTS - A semiconductor substrate ( | 11-27-2014 |
20140370685 | METHOD FOR FORMING A GROOVE ON A SURFACE OF FLAT PLATE FORMED OF A NITRIDE SEMICONDUCTOR CRYSTAL - Provided is a novel method for forming a groove composed of two smooth inclined surfaces on a surface of a flat plate formed of a nitride semiconductor crystal having an A, C, M-axes. In the present invention, a disk-shaped dicing blade is moved along a direction of the A-axis to form first and second inclined surfaces on the surface of the flat plate. The following mathematical formulae (I)-(III) are satisfied: 45 degrees≦θb−a≦60 degrees (I) 45 degrees≦θb+a≦60 degrees (II), 0 degrees≦|a|≦7.5 degrees, where angle θb represents an angle formed between a surface of the edge and a radial direction of the dicing blade in a cross-sectional view which includes the M-axis and the C-axis. The angle a represents an angle formed between the principal surface and the M-axis. | 12-18-2014 |
20150087131 | METHOD FOR PROCESSING A CHIP - A method for processing a chip is provided. The method may include: providing a chip having a front side and a back side; and forming an orientation marker on the back side of the chip by forming a hole into the chip from the front side of the chip, the hole forming the orientation marker. | 03-26-2015 |
20150346605 | Method of Designing Metrology Targets, Substrates Having Metrology Targets, Method of Measuring Overlay, and Device Manufacturing Method - Metrology targets are formed by a lithographic process, each target comprising a bottom grating and a top grating. Overlay performance of the lithographic process can be measured by illuminating each target with radiation and observing asymmetry in diffracted radiation. Parameters of metrology recipe and target design are selected so as to maximize accuracy of measurement of overlay, rather than reproducibility. The method includes calculating at least one of a relative amplitude and a relative phase between (i) a first radiation component representing radiation diffracted by the top grating and (ii) a second radiation component representing radiation diffracted by the bottom grating after traveling through the top grating and intervening layers. The top grating design may be modified to bring the relative amplitude close to unity. The wavelength of illuminating radiation in the metrology recipe can be adjusted to bring the relative phase close to π/2 or 3π/2. | 12-03-2015 |
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20180026189 | MASK FRAME ASSEMBLY | 01-25-2018 |