Entries |
Document | Title | Date |
20080206951 | HIGH PERFORMANCE FIELD EFFECT TRANSISTORS ON SOI SUBSTRATE WITH STRESS-INDUCING MATERIAL AS BURIED INSULATOR AND METHODS - The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure achieves performance enhancement from uniaxial stress, and the stress in the channel is not dependent on the layout design of the local contacts. In broad terms, the present invention relates to a semiconductor structure that comprises an upper semiconductor layer and a bottom semiconductor layer, wherein said upper semiconductor layer is separated from said bottom semiconductor layer in at least one region by a stress-inducing insulator having a preselected geometric shape, said stress-inducing insulator exerting a strain on the upper semiconductor layer. | 08-28-2008 |
20080254590 | Fabrication process for silicon-on-insulator field effect transistors using high temperature nitrogen annealing - Disclosed is a method of fabricating a silicon-on-insulator (SOI) device that enables high device densities and mitigates variances in carrier mobility and saturation drain current (Id | 10-16-2008 |
20080261374 | SEPARATE LAYER FORMATION IN A SEMICONDUCTOR DEVICE - A semiconductor device is formed. A first gate dielectric layer is formed over the semiconductor layer. A first conductive layer is formed over the first gate dielectric. A first separation layer is formed over the first conductive layer. A trench is formed in the semiconductor layer to separate the first mesa and the second mesa. The trench is filled with an isolation material to a height above a top surface of the first conductive layer. The first conductive layer is removed from the second mesa. A second conductive layer is formed over the first separation layer of the first mesa and over the second mesa. A planarizing etch removes the second conductive layer from over the first mesa. A first transistor of a first type is formed in the first mesa, and a second transistor of a second type is formed in the second mesa. | 10-23-2008 |
20080261375 | Method of Forming a Semiconductor Device Having a Dummy Feature - A method for forming a semiconductor device includes identifying an area that comprises an active device region, wherein the area has a perimeter at a first location and at least a portion of the edge of the active device region is coincident with at least a portion of the perimeter, expanding the perimeter to a first distance away from the first location, wherein the first distance defines a first point of a dummy feature, determining a second point of the dummy feature, adding the dummy feature to a layout using the first point and the second point, and using the layout to form a layer in a semiconductor device. | 10-23-2008 |
20090162988 | METHOD OF FORMING LOW CAPACITANCE ESD DEVICE AND STRUCTURE THEREFOR - In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage. | 06-25-2009 |
20090197387 | METHOD OF FORMING A GATE STACK STRUCTURE - A method of forming an integrated circuit structure on a substrate, the substrate includes a primary region and a secondary region. A first layer of a first material of a first thickness is formed over the substrate. A portion of the first layer is removed over the primary region to expose the substrate. The structure is exposed to an oxidizing medium. This forms a second layer, for example, of an oxide material primary region of the substrate. The second layer has a second thickness. Additionally, at least a portion of said first layer is converted to a third layer, for example, of an oxynitride material. The third layer has a third thickness. | 08-06-2009 |
20090209081 | Silicon Dioxide Thin Films by ALD - Methods are provided for depositing silicon dioxide containing thin films on a substrate by atomic layer deposition ALD. By using disilane compounds as the silicon source, good deposition rates and uniformity are obtained. | 08-20-2009 |
20090233413 | Method for fabricating semiconductor device - A method for fabricating a semiconductor device using a SOI substrate, includes the steps of: preparing a SOI substrate, comprises a semiconductor support layer; an insulating layer formed on the semiconductor support layer; and a SOI layer formed on the insulating layer; forming an active region on the SOI layer, so that a part of the semiconductor support layer is exposed; and forming a specific mark on the exposed part of the semiconductor support layer. | 09-17-2009 |
20100015775 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH RECESS GATE - A method for fabricating a semiconductor device with a recess gate includes providing a substrate, forming an isolation layer over the substrate to define an active region, forming mask patterns with a first width opening exposing a region where recess patterns are to be formed, and a second width opening smaller than the first width and exposing the isolation layer, forming a passivation layer along a height difference of the mask patterns, etching the substrate using the passivation layer and the mask patterns as an etch barrier to form recess patterns, removing the passivation layer and the mask patterns, and forming gate patterns protruding from the substrate to fill the recess patterns. | 01-21-2010 |
20100029057 | SILICONE RESIN COMPOSITION AND METHOD OF FORMING A TRENCH ISOLATION - A silicone resin which is represented by the following rational formula (1) and solid at 120° C.: | 02-04-2010 |
20100047993 | INTEGRATION OF HIGH-K METAL-GATE STACK INTO DIRECT SILICON BONDING (DSB) HYBRID ORIENTATION TECHNOLOGY (HOT) PMOS PROCESS FLOW - A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation layer, and a second crystal orientation layer, and a border region disposed between the first and second crystal orientations. A high-k metal gate stack is deposited over the first crystal orientation layer that comprises an insulation layer, a high-k dielectric layer, a first metal layer, and a second metal layer thereon. | 02-25-2010 |
20100112778 | NANOSCALE FLOATING GATE AND METHODS OF FORMATION - A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer. | 05-06-2010 |
20100120217 | Methods of Forming SRAM Devices having Buried Layer Patterns - An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed. | 05-13-2010 |
20100129979 | SEMICONDUCTOR DEVICE HAVING INCREASED ACTIVE REGION WIDTH AND METHOD FOR MANUFACTURING THE SAME - The disclosed semiconductor device includes a plurality of active patterns including first active patterns which protrude from a semiconductor substrate and have a first width and second active patterns which are connected to upper ends of the respective first active patterns and have a second width greater than the first width. The semiconductor device further includes isolation patterns respectively located between the active patterns to insulate the active patterns from one another. | 05-27-2010 |
20100167490 | Method of Fabricating Flash Memory Device - Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed. | 07-01-2010 |
20100167491 | METHOD FOR FABRICATING FLASH MEMORY DEVICE - A method for fabricating a flash memory device includes forming device isolation films in a semiconductor substrate, defining active regions between the device isolation films, and patterning floating gates on the semiconductor substrate to correspond to the active regions. Portions where the active regions and the floating gates are not overlap with one another are within reference offset ranges, respectively. | 07-01-2010 |
20100173469 | METHODS OF MANUFACTURING CHARGE TRAP-TYPE NON-VOLATILE MEMORY DEVICES - Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern. A blocking insulating layer is formed that covers the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate interposed between the charge trap patterns. A gate electrode pattern is formed on the blocking insulating layer to face the charge trap layer pattern. This manufacturing process may reduce charge spreading between unit memory cells and/or may prevent/avoid reduction in the breakdown voltage of the blocking insulating layer. | 07-08-2010 |
20100184267 | METHOD OF FORMING SILICON OXIDE FILM AND METHOD OF PRODUCTION OF SEMICONDUCTOR MEMORY DEVICE USING THIS METHOD - To form a good quality silicon oxide film provided with both a superior Qbd characteristic and Rd characteristic, a wafer W is loaded into a plasma treatment apparatus where the surface of a silicon layer | 07-22-2010 |
20100184268 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE HAVING A PORTION IN WHICH A GROOVE IS EMBEDDED WITH AN OXIDE FILM - A coating composition for forming an oxide film, which can suppress the phenomenon of an increased wet etching rate caused by a part of the SOG film embedded inside a groove becoming low-density, and which can suppress the volume expansion coefficient to a low level, and a method for producing a semiconductor device using the same are provided. An oxide film is formed inside a groove by: coating a coating composition for forming an oxide film, which contains a polysilazane or a hydrogenated silsesquioxane, and a polysilane, on a substrate having a groove; and thereafter heat treatment in an oxidizing atmosphere. This method is suitable for forming a device isolation region and a wiring interlayer dielectric film. | 07-22-2010 |
20100203700 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes preparing a substrate having a recessed area. A silicon oxide layer is formed at the recessed area. A catalytic nitridation treatment is performed for an upper portion of the silicon oxide layer to form a nitridation reactant on the upper portion of the silicon oxide layer. A dielectric layer is formed on the silicon oxide layer where the nitridation reactant is formed. The dielectric layer is annealed. According to the foregoing method, recession of the dielectric layer is prevented to fabricate a high-quality semiconductor device. | 08-12-2010 |
20100330773 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - Provided is a substrate processing method, which can fill an insulating film in a groove having a small width with a high aspect ratio and improve the productivity. The substrate processing method comprises loading a substrate into a processing chamber, supplying silicon compound gas including carbon and hydrogen into the processing chamber, irradiating ultraviolet light on the silicon compound gas supplied into the processing chamber to process the substrate, unloading the processed substrate from the processing chamber, and processing the inside of the processing chamber with excited oxygen-containing gas. Accordingly, an adhered matter generated when irradiating the ultraviolet light on the silicon compound gas to process the substrate and adhered to a structure such as an inner wall of the processing chamber can be processed with the excited oxygen-containing gas to modify it. | 12-30-2010 |
20110177669 | METHOD OF CONTROLLING TRENCH MICROLOADING USING PLASMA PULSING - Methods and apparatus for controlling microloading, such as within cell microloading between adjacent cells or isolated/dense microloading between areas of isolated or dense features during shallow trench isolation (STI) fabrication processes, or other trench fabrication processes, are provided herein. In some embodiments, a method for fabricating STI structures may include providing a substrate having a patterned mask layer formed thereon corresponding to one or more STI structures to be etched; etching the substrate through the patterned mask layer using a plasma formed from a process gas to form one or more STI structure recesses on the substrate; and pulsing the plasma for at least a portion of etching the substrate to control at least one of a depth or width of the one or more STI structure recesses. | 07-21-2011 |
20110250731 | PREFERENTIAL DIELECTRIC GAPFILL - Aspects of the disclosure pertain to methods of preferentially filling narrow trenches with silicon oxide while not completely filling wider trenches and/or open areas. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively dense first portion of a silicon oxide layer followed by a more porous (and more rapidly etched) second portion of the silicon oxide layer. Narrow trenches are filled with dense material whereas open areas are covered with a layer of dense material and more porous material. Dielectric material in wider trenches may be removed at this point with a wet etch while the dense material in narrow trenches is retained. | 10-13-2011 |
20110312153 | METHOD OF MAKING A FLOATING GATE NON-VOLATILE MOS SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED CAPACITIVE COUPLING AND DEVICE THUS OBTAINED - A method of making a non-volatile MOS semiconductor memory device includes a formation phase, in a semiconductor material substrate, of isolation regions filled by field oxide and of memory cells separated each other by said isolation regions The memory cells include an electrically active region surmounted by a gate electrode electrically isolated from the semiconductor material substrate by a first dielectric layer; the gate electrode includes a floating gate defined. simultaneously to the active electrically region. A formation phase of said floating gate exhibiting a substantially saddle shape including a concavity is proposed. | 12-22-2011 |
20110318901 | SEMICONDUCTOR DEVICE WITH GATE-UNDERCUTTING RECESSED REGION - A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure. | 12-29-2011 |
20110318902 | METHODS OF FABRICATING FLASH MEMORY DEVICES HAVING SHARED SUB ACTIVE REGIONS - Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region. | 12-29-2011 |
20120028434 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING ACID DIFFUSION - A method of manufacturing a semiconductor device includes forming a resist pattern on a first region on a substrate, bringing a descum solution including an acid source into contact with the resist pattern and with a second region of the substrate, decomposing resist residues remaining on the second region of the substrate by using acid obtained from the acid source in the descum solution and removing the decomposed resist residues and the descum solution from the substrate. | 02-02-2012 |
20120028435 | SEMICONDUCTOR DEVICE INCLUDING DUMMY GATE PART AND METHOD OF FABRICATING THE SAME - In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions. | 02-02-2012 |
20120083093 | ISOLATION STRUCTURE FOR A MEMORY CELL USING AL2O3 DIELECTRIC - The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between adjacent active areas of an integrated circuit structure, for example a DRAM memory cell. An aluminum oxide (Al2O3) is used as a gate dielectric, rather than a conventional gate oxide layer, to create a hole-rich accumulation region under and near the trench isolation region. Another exemplary embodiment of the invention provides an aluminum oxide layer utilized as a liner in a shallow trench isolation (STI) region to increase the effectiveness of the isolation region. The embodiments may also be used together at an isolation region. | 04-05-2012 |
20120190167 | MECHANISMS OF DOPING OXIDE FOR FORMING SHALLOW TRENCH ISOLATION - The embodiments described provide mechanisms for doping oxide in the STIs with carbon to make etch rate in the narrow and wide structures equal and also to make corners of wide STIs strong. Such carbon doping can be performed by ion beam (ion implant) or by plasma doping. The hard mask layer can be used to protect the silicon underneath from doping. By using the doping mechanism, the even surface topography of silicon and STI enables patterning of gate structures and ILD0 gapfill for advanced processing technology. | 07-26-2012 |
20120196425 | High-K Metal Gate Electrode Structures Formed by a Replacement Gate Approach Based on Superior Planarity of Placeholder Materials - When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, superior process uniformity may be achieved by implementing at least one planarization process after the deposition of the placeholder material, such as the polysilicon material, and prior to actually patterning the gate electrode structures. | 08-02-2012 |
20120208341 | Alignment Marks for Polarized Light Lithography and Method for Use Thereof - Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality of elements comprised of a second component type, wherein the second component type has a second polarization, wherein the first polarization and the second polarization are orthogonal, wherein adjacent elements are of different component types. The alignment marks can be used in an intensity based or a diffraction based alignment process. | 08-16-2012 |
20120208342 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching. | 08-16-2012 |
20120264274 | TRANSISTOR OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is a transistor of a semiconductor device and a method for fabricating the same. A transistor of a semiconductor device may include: a semiconductor substrate having an active region defined by an isolation layer; a recess trench formed in the active region and disposed to cross the semiconductor substrate in one direction; and a gate line formed in a straight line pattern, overlapping the recess trench and disposed to cross the recess trench at approximately right angles. | 10-18-2012 |
20120270378 | Method for Producing Silicon Semiconductor Wafers Comprising a Layer for Integrating III-V Semiconductor Components - The invention relates to a method for producing silicon semiconductor wafers and components having layer structures of III-V layers for integrating III-V semiconductor components. The method employs SOI silicon semiconductor wafers having varying substrate orientations, and the III-V semiconductor layers are produced in trenches ( | 10-25-2012 |
20120276707 | METHOD FOR FORMING TRENCH ISOLATION - A method for forming a trench isolation is disclosed, comprising, providing a substrate comprising a trench, forming a polysilicon layer in the trench, and subjecting the substrate to a treating process to convert the polysilicon layer to an isolating layer, wherein the treating process is fine tuned for the isolating layer on opposite sidewalls of the trench to expand to contact with each other so that the isolating layer fills the trench. | 11-01-2012 |
20120276708 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method includes: forming an device isolation region in a substrate to divide the device isolation region into first and second diffusion regions; forming a target film on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer by using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer for isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer. | 11-01-2012 |
20120276709 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method includes: forming an device isolation region in a substrate to divide the device isolation region into a first and a second diffusion regions; forming a target film on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer for isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer. | 11-01-2012 |
20120295414 | METHODS FOR PRODUCING STACKED ELECTROSTATIC DISCHARGE CLAMPS - Methods are provided for producing stacked electrostatic discharge (ESD) clamps. In one embodiment, the method includes providing a semiconductor substrate in which first and second serially-coupled transistors are formed. The first transistor includes a first well region having a first lateral edge partially forming the first transistor's base. The second transistor including a second well region having a second lateral edge partially forming the second transistor's base. Third and fourth well regions are formed in the first and second transistors, respectively, and extend a different distance into the substrate than do the well regions of the first and second transistors. The third well region has a third lateral edge separated from the first lateral edge by a first spacing dimension D1. The fourth well region has a fourth lateral edge separated from the second lateral edge by a second spacing dimension D2, which is different than D1. | 11-22-2012 |
20120302034 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided. The method includes providing a substrate having a protruding channel region, forming a gate insulation layer surrounding the protruding channel region, forming a sacrificial layer having an etch selectivity varying in a thickness direction of the sacrificial layer, on the gate insulation layer, and performing a gate-last process to form a gate electrode on the gate insulation layer in place of the sacrificial layer. | 11-29-2012 |
20120302035 | SEMICONDUCTOR DEVICE HAVING AN OXIDE FILM FORMED ON A SEMICONDUCTOR SUBSTRATE SIDEWALL OF AN ELEMENT REGION AND ON A SIDEWALL OF A GATE ELECTRODE - A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film. | 11-29-2012 |
20120322226 | SEMICONDUCTOR DEVICE PRODUCTION METHOD - A semiconductor device production method includes: treating a wafer which contains a silicon substrate with dilute hydrofluoric acid in a bath; introducing water into the bath while discharging the dilute hydrofluoric acid from the bath; and introducing H | 12-20-2012 |
20120329238 | Method For Forming A Transient Voltage Suppressor Having Symmetrical Breakdown Voltages - A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS. | 12-27-2012 |
20130071992 | SEMICONDUCTOR PROCESS - A semiconductor process is provided. An insulating layer is formed on a semiconductor substrate. A portion of the insulating layer is removed, so as to form a plurality of isolation structures and a mesh opening disposed between the isolation structures and exposing the semiconductor substrate. By performing a selective growth process, a semiconductor layer is formed from a surface of the semiconductor substrate exposed by the mesh opening, so that the isolation structures are disposed in the semiconductor layer. | 03-21-2013 |
20130122684 | SEMICONDUCTOR PROCESS FOR REMOVING OXIDE LAYER - A semiconductor process for removing oxide layers comprises the steps of providing a substrate having an isolation structure and a pad oxide layer, performing a dry cleaning process and a wet cleaning process to remove said pad oxide layer, forming a sacrificial oxide layer on said substrate, and performing an ion implantation process to form doped well regions on both sides of the isolation structure. | 05-16-2013 |
20130143385 | STRESS IN TRIGATE DEVICES USING COMPLIMENTARY GATE FILL MATERIALS - Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device. | 06-06-2013 |
20130149835 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a first device isolation pattern defining a first active region, a second device isolation pattern defining a second active region, a first gate disposed on the first active region, the first gate including a gate insulating pattern of a first thickness and a second gate disposed on the second active region, the second gate including a gate insulating pattern of a second thickness greater than the first thickness. A top surface of the first device isolation pattern is curved down toward the first active region such that the first active region has an upper portion protruded from the top surface and rounded corners. | 06-13-2013 |
20130164906 | FULL WAFER PROCESSING BY MULTIPLE PASSES THROUGH A COMBINATORIAL REACTOR - Overlapping combinatorial processing can offer more processed regions, better particle performance and simpler process equipment. In overlapping combinatorial processing, one or more regions are processed in series with some degrees of overlapping between regions. In some embodiments, overlapping combinatorial processing can be used in conjunction with non-overlapping combinatorial processing and non-combinatorial processing to develop and investigate materials and processes for device processing and manufacturing. | 06-27-2013 |
20130164907 | METHODS OF FORMING A THIN FILM AND METHODS OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING USING THE SAME - Provided are methods of forming a thin film and methods of fabricating a semiconductor device including the same. The thin film forming methods may include supplying an organic silicon source to form a silicon seed layer on a lower layer, the silicon seed layer including silicon seed particles adsorbed on the lower layer, and supplying an inorganic silicon source to deposit a silicon film on the lower layer adsorbed with the silicon atoms. | 06-27-2013 |
20130171801 | SEMICONDUCTOR DEVICES HAVING NITRIDED GATE INSULATING LAYER AND METHODS OF FABRICATING THE SAME - Semiconductor devices, and methods of fabricating the same, include forming device isolation regions in a substrate to define active regions, forming gate trenches in the substrate to expose the active regions and device isolation regions, conformally forming a preliminary gate insulating layer including silicon oxide on the active regions exposed in the grate trenches, nitriding the preliminary gate insulating layer using a radio-frequency bias having a frequency of about 13.56 MHz and power between about 100 W and about 300 W to form a nitrided preliminary gate insulating layer including silicon oxynitride, forming a gate electrode material layer on the nitride preliminary gate insulating layer, partially removing the nitrided preliminary gate insulating layer and the gate electrode material layer to respectively form a gate insulating layer and a gate electrode layer, and forming a gate capping layer on the gate electrode layer to fill the gate trenches. | 07-04-2013 |
20130171802 | FULL WAFER PROCESSING BY MULTIPLE PASSES THROUGH A COMBINATORIAL REACTOR - Overlapping combinatorial processing can offer more processed regions, better particle performance and simpler process equipment. In overlapping combinatorial processing, one or more regions are processed in series with some degrees of overlapping between regions. In some embodiments, overlapping combinatorial processing can be used in conjunction with non-overlapping combinatorial processing and non-combinatorial processing to develop and investigate materials and processes for device processing and manufacturing. | 07-04-2013 |
20130178043 | Integrated Circuit Including DRAM and SRAM/Logic - A method includes providing a substrate having an N+ type layer; forming a P type region in the N+ type layer disposed within the N+ type layer; forming a first deep trench isolation structure extending through a silicon layer and into the N+ type layer to a depth that is greater than a depth of the P type layer; forming a dynamic RAM FET in the silicon layer, forming a first logic/static RAM FET in the silicon layer above the P type region, the P type region being functional as a P-type back gate of the first logic/static RAM FET; and forming a first contact through the silicon layer and an insulating layer to electrically connect to the N+ type layer and a second contact through the silicon layer and the insulating layer to electrically connect to the P type region. | 07-11-2013 |
20130189825 | METHOD OF PRODUCING INSULATION TRENCHES IN A SEMICONDUCTOR ON INSULATOR SUBSTRATE - A method for producing one or plural trenches in a device comprising a substrate of the semiconductor on insulator type formed by a semiconductive support layer, an insulating layer resting on the support layer and a semiconductive layer resting on said insulating layer, the method comprising steps of:
| 07-25-2013 |
20130196481 | METHOD OF PATTERNING FOR A SEMICONDUCTOR DEVICE - A method that includes forming a masking element on a semiconductor substrate and overlying a defined space. A first feature and a second feature are each formed on the semiconductor substrate. The space interposes the first and second features and extends from a first end of the first feature to a first end of the second feature. A third feature is then formed adjacent and substantially parallel the first and second features. The third feature extends at least from the first end of the first feature to the first end of the second feature. | 08-01-2013 |
20130196482 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including performing a first thermal processing a silicon substrate in a first atmosphere and at a first temperature to remove an oxide film above a surface of the silicon substrate, and after the first thermal processing, performing a second thermal processing the silicon substrate in a second atmosphere containing hydrogen and at a second temperature lower than the first temperature to terminate the surface of the silicon substrate with hydrogen. | 08-01-2013 |
20130210212 | Semiconductor Device Manufacturing Methods - Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a protective material over a bottom surface and edges of the workpiece. A top surface of the workpiece is processed. The protective material protects the edges and the bottom surface of the workpiece during the processing of the top surface of the workpiece. | 08-15-2013 |
20130244396 | FIELD EFFECT TRANSISTORS HAVING AN EPITAXIAL LAYER ON A FIN AND METHODS OF FABRICATING THE SAME - A method of fabricating a fin field effect transistor may include forming a fin portion protruding from a substrate, forming a device isolation layer to cover a lower sidewall of the fin portion, forming a semiconductor layer using an epitaxial method to cover an upper sidewall and a top surface of the fin portion, selectively etching an upper portion of the device isolation layer to form a gap region between a top surface of the device isolation layer and a bottom surface of the semiconductor layer, and forming a gate electrode pattern on the semiconductor layer to fill the gap region. Related devices are also described. | 09-19-2013 |
20130273709 | METHODS OF RECESSING AN ACTIVE REGION AND STI STRUCTURES IN A COMMON ETCH PROCESS - Generally, the present disclosure is directed to various methods of recessing an active region and an adjacent isolation structure in a common etch process. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active area in the substrate, forming a patterned masking layer above the substrate, wherein the patterned masking layer exposes the active area and at least a portion of the isolation structure for further processing, and performing a non-selective dry etching process on the exposed active area and the exposed portion of the isolation structure to define a recess in the substrate and to remove at least some of the exposed portions of the isolation structure. | 10-17-2013 |
20130273710 | SUBSTRATE FINS WITH DIFFERENT HEIGHTS - A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas. | 10-17-2013 |
20130309836 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an isolation layer formed on a semiconductor substrate; an active region defined by the isolation layer; at least one gate line formed to overlap with the active region; at least one first active tab formed on a first interface of the active region which overlaps with the gate line; and a first gate tab formed on a second interface facing away from the first interface in such a way as to project from the gate line. | 11-21-2013 |
20130316513 | FIN ISOLATION FOR MULTIGATE TRANSISTORS - Multigate transistor devices and methods of their fabrication are disclosed. In one method, a substrate including a semiconductor upper layer and a lower layer beneath the upper layer is provided. The lower layer has a rate of transformation into a dielectric that is higher than a rate of transformation into a dielectric of the upper layer when the upper and lower layers are subjected to dielectric transformation conditions. Fins are formed in the upper layer, and the lower layer beneath the fins is transformed into a dielectric material to electrically isolate the fins. In addition, a gate structure is formed over the fins to complete the multigate transistor device. | 11-28-2013 |
20140030866 | METHOD AND APPARATUS FOR PREPARING POLYSILAZANE ON A SEMICONDUCTOR WAFER - A method for depositing a polysilazane on a semiconductor wafer is provided. The method includes steps of disposing a silazane onto the semiconductor wafer, and heating the silazane to form the polysilazane on the semiconductor wafer. An apparatus for preparing a polysilazane on a semiconductor wafer is also provided. | 01-30-2014 |
20140120691 | METHOD OF THIN SILICON DEPOSITION FOR ENHANCEMENT OF ON CURRENT AND SURFACE CHARACTERISTICS OF SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. A fin portion protruding from a substrate is formed. A sacrificial layer is formed to cover top and side surfaces of the fin portion. A gate dielectric is formed on the fin portion by oxidizing the sacrificial layer. | 05-01-2014 |
20140213033 | METHODS FOR FABRICATING ELECTRICALLY-ISOLATED FINFET SEMICONDUCTOR DEVICES - Fabrication methods for semiconductor device structures are provided. In an exemplary embodiment, a method of fabricating an electrically-isolated FinFET semiconductor device includes the steps of forming a silicon oxide layer over a semiconductor substrate including a silicon material and forming a first hard mask layer over the silicon oxide layer. The method further includes the steps of forming a first plurality of void spaces in the first hard mask layer and forming a second hard mask layer in the first plurality of void spaces. Still further, the method includes the steps of removing the remaining portions of the first hard mask layer, thereby forming a second plurality of void spaces in the second hard mask layer, extending the second plurality of void spaces into the silicon oxide layer, and forming a plurality of fin structures in the extended second plurality of void spaces. | 07-31-2014 |
20140273397 | METHODS OF FABRICATING NON-PLANAR TRANSISTORS INCLUDING CURRENT ENHANCING STRUCTURES - Methods of fabricating non-planar transistors including current enhancing structures are provided. The methods may include forming first and second fin structures directly adjacent each other overlying a substrate including an isolation layer. The methods may further include forming a spacer on the isolation layer including first and second recesses exposing upper surfaces of the first and second fin structures respectively. The spacer may cover an upper surface of the isolation layer between the first and second recesses. The methods may also include forming first and second current enhancing structures contacting the first and second fin structures, respectively, in the first and second recesses. | 09-18-2014 |
20140273398 | Methods for Forming Semiconductor Materials in STI Trenches - A method includes annealing a silicon region in an environment including hydrogen (H | 09-18-2014 |
20140315370 | Full Wafer Processing By Multiple Passes Through A Combinatorial Reactor - Overlapping combinatorial processing can offer more processed regions, better particle performance and simpler process equipment. In overlapping combinatorial processing, one or more regions are processed in series with some degrees of overlapping between regions. In some embodiments, overlapping combinatorial processing can be used in conjunction with non-overlapping combinatorial processing and non-combinatorial processing to develop and investigate materials and processes for device processing and manufacturing. | 10-23-2014 |
20150044854 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a method of fabricating a semiconductor device. The method of fabricating a semiconductor device includes preparing a substrate in which a scribe lane region and a chip region are defined, forming a trench in the scribe lane region of the substrate, forming a stopper layer in a part in the trench, and forming an alignment mark material on the stopper layer. | 02-12-2015 |
20150056780 | Full Wafer Processing By Multiple Passes Through A Combinatorial Reactor - Overlapping combinatorial processing can offer more processed regions, better particle performance and simpler process equipment. In overlapping combinatorial processing, one or more regions are processed in series with some degrees of overlapping between regions. In some embodiments, overlapping combinatorial processing can be used in conjunction with non-overlapping combinatorial processing and non-combinatorial processing to develop and investigate materials and processes for device processing and manufacturing. | 02-26-2015 |
20150099342 | Mechanism of Forming a Trench Structure - Forming a shallow trench isolation (STI) structure filled with a flowable dielectric layer involves performing an implant to generate passages in the upper portion of the flowable dielectric layer. The passages enable oxygen source in a thermal anneal to reach the flowable dielectric layer near the bottom of the STI structure during the thermal anneal to convert a SIONH network of the reflowable dielectric layer to a network of SiOH and SiO. The passages also help to provide escape paths for by-products produced during another thermal anneal to convert the network of SiOH and SiO to SiO | 04-09-2015 |
20150104922 | INTEGRATED DEVICE WITH DEFINED HEAT FLOW - An integrated device includes at least one heat generating component which generates heat when operated, at least one temperature-sensitive component, and one or more hollow insulation regions arranged between the at least one heat generating component and the at least one temperature-sensitive component. The hollow insulation region may be provided as a vacuum gap. | 04-16-2015 |
20150294895 | LOCALIZED REGION OF ISOLATED SILICON OVER DIELECTRIC MESA - An integrated circuit is formed by forming an isolation mesa over a single crystal substrate which includes silicon, and forming a first epitaxial layer on the substrate by a selective epitaxial process so that a top surface of the first epitaxial layer is coplanar with the top surface of the isolation mesa. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on the first epitaxial layer and non-crystalline silicon-based material on the isolation mesa. A cap layer is formed over the second epitaxial layer, and a radiantly-induced recrystallization process causes the non-crystalline silicon-based material to form single-crystalline semiconductor over the isolation mesa. | 10-15-2015 |
20150303183 | METHOD OF MANUFACTURING FIN DIODE STRUCTURE - A method of manufacturing a fin diode structure includes providing a substrate, forming a doped well in said substrate, forming at least one doped region of first conductivity type or at least one doped region of second doped type in said doped well, performing an etching process to said doped region of first conductivity type or said doped region of second conductivity type to form a plurality of fins on said doped region of first conductivity type or on said doped region of second conductivity type, forming shallow trench isolations between said fins, and performing a doping process to said fins to form fins of first conductivity type and fins of second conductivity type. | 10-22-2015 |
20150311384 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming an insulation pattern including a mask region and an open region on a gallium nitride substrate, growing gallium nitride semiconductor layers to cover the insulation pattern, and patterning the semiconductor layers to form a plurality of semiconductor stacks separated from each other, the plurality of semiconductor stacks being electrically isolated from the gallium nitride substrate by the insulation pattern. | 10-29-2015 |
20150364358 | METHOD OF FORMING ISOLATION LAYER - According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure. | 12-17-2015 |
20150380247 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first mask layer is formed in contact with a first main surface of the silicon carbide substrate. The first mask layer includes a first layer disposed in contact with the first main surface, an etching stop layer disposed in contact with the first layer and made of a material different from that for the first layer, and a second layer disposed in contact with a surface of the etching stop layer opposite to the surface in contact with the first layer. A recess is formed in the first mask layer by etching the second layer and the etching stop layer. A first impurity region is formed in the silicon carbide substrate using the first mask layer with the recess. The first mask layer does not include a metallic element. | 12-31-2015 |
20160020145 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH BLOCKING LAYER PATTERNS - A semiconductor device includes a circuit device on a substrate and a first insulating interlayer on the substrate and covering the circuit device. An electrode structure extends through the first insulating interlayer and at least partially through the substrate. An etch-stop layer pattern is disposed on a sidewall of the electrode structure on a side of the first insulating layer opposite the substrate. A blocking layer pattern is disposed on the etch-stop layer pattern. The device further includes an interconnection structure including a via portion passing through the blocking layer pattern to contact the through electrode structure and a wiring portion on the via portion and having a different width than the via portion. The semiconductor device may further include a contact plug electrically connected to the circuit device through the first insulating interlayer. The contact plug and the through electrode structure may include different metals. | 01-21-2016 |
20160020277 | THREE-DIMENSIONAL ELECTROSTATIC DISCHARGE SEMICONDUCTOR DEVICE - Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current. | 01-21-2016 |
20160043003 | MECHANISMS FOR FORMING FINFETS WITH DIFFERENT FIN HEIGHTS - Methods for forming a semiconductor device are provided. The method includes forming a first fin and a second fin over a substrate and forming a first isolation structures and a second isolation structure adjacent to the substrate. The first fin is partially surrounded by the first isolation structure and a second fin is partially surrounded by the second isolation structure, and the first isolation structure has a dopant concentration higher than that of the second isolation structure. | 02-11-2016 |
20160071757 | Mechanism of Forming a Trench Structure - Embodiments of a mechanism for forming a shallow trench isolation (STI) structure filled with a flowable dielectric layer are provided. The mechanism involves using one or more low-temperature thermal anneal processes with oxygen sources and one or more microwave anneals to convert a flowable dielectric material to silicon oxide. The low-temperature thermal anneal processes with oxygen sources and the microwave anneals are performed at temperatures below the ranges that could cause significant dopant diffusion, which help dopant profile control for advanced manufacturing technologies. In some embodiments, an implant to generate passages in the upper portion of the flowable dielectric layer is also used in the mechanism. | 03-10-2016 |
20160148997 | SEMICONDUCTOR DEVICE HAVING LOCALIZED CHARGE BALANCE STRUCTURE AND METHOD - In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then formed adjacent the localized superjunction structure to create a charge imbalance therein. In one embodiment, the doped region can be an ion implanted region formed within the localized superjunction structure. In another embodiment, the doped region can be an epitaxial layer having a graded dopant profile adjoining the localized superjunction structure. The charge imbalance can improve, among other things, unclamped inductive switching (UIS) performance. | 05-26-2016 |
20160163715 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack structure and a second gate stack structure on a substrate, and the first gate stack structure includes a first spacer adjacent to the second gate stack structure. The method also includes forming an U-shaped capping layer between the first gate stack structure and the second gate stack structure, and a lateral sidewall of the U-shaped capping layer is in direct contact with the first spacer of the first gate stack structure. A top of the lateral sidewall of the U-shaped capping layer is below a top of the first spacer of the first gate stack structure. | 06-09-2016 |
20160254265 | THREE-DIMENSIONAL DEVICES HAVING REDUCED CONTACT LENGTH | 09-01-2016 |