Class / Patent application number | Description | Number of patent applications / Date published |
438399000 | Having contacts formed by selective growth or deposition | 10 |
20080293212 | METHOD FOR FORMING STORAGE NODE OF CAPACITOR IN SEMICONDUCTOR DEVICE - A method for forming a capacitor in a semiconductor device comprises forming an inter-layer layer on a semi-finished substrate; etching the inter-layer insulation layer to form a plurality of first contact holes; forming a first insulation layer on sidewalls of the first contact holes; forming a plurality of storage-node contact plugs filled into the first contact holes; forming a second insulation layer with a different etch rate from the first insulation layer over the storage-node contact plugs; forming a third insulation layer on the second insulation layer; sequentially etching the third insulation layer and the second insulation layer to form a plurality of second contact holes exposing the storage-node contact plugs; and forming the storage node on each of the second contact holes. | 11-27-2008 |
20090004810 | Method of Fabricating Memory Device - Disclosed herein is a method of fabricating a memory device. The method includes forming an etch stop layer, bit lines, and a first hard mask pattern over a semiconductor substrate. A first SNC plug is formed between the bit lines, and an etch process is performed to reduce the height of the first hard mask pattern and the first SNC plug, to increase a top width of the first hard mask pattern, and to reduce a top width of the first SNC plug. The method also includes forming a second hard mask pattern on the first hard mask pattern, and forming a second SNC plug between the second hard mask patterns. | 01-01-2009 |
20090275187 | METHODS OF FORMING CAPACITORS - A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield is etched through within the opening. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode | 11-05-2009 |
20100009512 | METHODS OF FORMING A PLURALITY OF CAPACITORS - A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two masking steps is used to form an array of first openings over a plurality of storage node contacts. A later of the two masking steps is used to form an array of second openings received partially over and partially offset from the array of first openings. Overlapping portions of the first and second openings are received over the storage node contacts. After both of the two masking steps, conductive material of the individual capacitor electrodes is deposited into the overlapping portions of each of the first and second openings. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated. | 01-14-2010 |
20100112777 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes forming a bottom electrode having a top surface and a side surface on a semiconductor substrate, performing a tilted ion implantation process to supply ions to the top surface of the bottom electrode and to a portion of the side surface of the bottom electrode, and forming a dielectric layer on the bottom electrode. The formation of the dielectric layer is delayed at the ion-supplied top surface of the bottom electrode and the ion-supplied portion of the side surface of the bottom electrode. | 05-06-2010 |
20110070718 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and methods of fabricating the same, wherein insulation layers are interposed to sequentially dispose the semiconductor device on a semiconductor substrate. The semiconductor device includes a first conductive plate, a second conductive plate, a third conductive plate, and a fourth conductive plate. At least two of the first, second, third and fourth conductive plates are electrically connected and constitute at least two capacitors. | 03-24-2011 |
20120115303 | METHOD OF FABRICATING DAMASCENE STRUCTURES - Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor. | 05-10-2012 |
20140038384 | Forming Metal-Insulator-Metal Capacitors Over a Top Metal Layer - A plurality of metal layers includes a top metal layer. An Ultra-Thick Metal (UTM) layer is disposed over the top metal layer, wherein no additional metal layer is located between the UTM layer and the top metal layer. A Metal-Insulator-Metal (MIM) capacitor is disposed under the UTM layer and over the top metal layer. | 02-06-2014 |
20140113431 | METHODS OF FABRICATING A STORAGE NODE IN A SEMICONDUCTOR DEVICE AND METHODS OF FABRICATING A CAPACITOR USING THE SAME - Methods of forming a storage node in a semiconductor device are provided. The method includes forming an interlayer insulation layer on a substrate, forming an etch stop layer and a first sacrificial layer on the interlayer insulation layer, patterning the first sacrificial layer and the etch stop layer to form a first sacrificial layer pattern and an etch stop layer pattern that define a storage node contact hole, forming a recessed first storage node conductive pattern that conformally covers a lower sidewall and a bottom surface of the storage node contact hole, forming a second storage node conductive pattern that includes a first portion surrounded by the recessed first storage node conductive pattern and a second portion conformally covering an upper sidewall of the storage node contact hole, and removing the first sacrificial layer pattern. The recessed first storage node conductive pattern and the second storage node conductive pattern constitute a storage node. | 04-24-2014 |
20140273396 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A METAL-INSULATOR-METAL CAPACITOR - A method comprises forming a first layer of an electrically insulating material over a semiconductor structure. A recess is formed in the first layer of electrically insulating material. A capacitor layer stack is deposited over the first layer of electrically insulating material. The capacitor layer stack includes one or more bottom electrode layers, a dielectric layer and a top electrode layer, wherein a first portion of the capacitor layer stack is arranged in the recess and a second portion of the capacitor layer stack is arranged over a portion of the first layer of electrically insulating material adjacent the recess. A chemical mechanical polishing process is performed. The chemical mechanical polishing process removes the second portion of the capacitor layer stack, wherein the first portion of the capacitor layer stack is not removed. | 09-18-2014 |