Class / Patent application number | Description | Number of patent applications / Date published |
438393000 | Planar capacitor | 39 |
20080261372 | METHOD OF MANUFACTURING VIBRATING MICROMECHANICAL STRUCTURES - A method for fabrication of single crystal silicon micromechanical resonators using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, a capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of the base wafer; the active layer of the resonator wafer is bonded directly to the active layer of the base wafer; the handle and dielectric layers of the resonator wafer are removed; viewing windows are opened in the active layer of the resonator wafer; masking the single crystal silicon semiconductor material active layer of the resonator wafer with photoresist material; a single crystal silicon resonator is machined in the active layer of the resonator wafer using silicon dry etch micromachining technology; and the photoresist material is subsequently dry stripped. | 10-23-2008 |
20080305606 | HIGH CAPACITANCE DENSITY VERTICAL NATURAL CAPACITORS - Disclosed are embodiments of a capacitor with inter-digitated vertical plates and a method of forming the capacitor such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back end of the line processing by masking connecting points with nodes, by etching the dielectric material from between the vertical plates and by etching a sacrificial material from below the vertical plates. Etching of the dielectric material from between the plates forms air gaps and various techniques can be used to cause the plates to collapse in on these air gaps, once the sacrificial material is removed. Any remaining air gaps can be filled by depositing a second dielectric material (e.g., a high k dielectric), which will further increase the capacitance density and will encapsulate the capacitor in order to make the reduced distance between the vertical plates permanent. | 12-11-2008 |
20090004809 | Method of Integration of a MIM Capacitor with a Lower Plate of Metal Gate Material Formed on an STI Region or a Silicide Region Formed in or on the Surface of a Doped Well with a High K Dielectric Material - A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by side wall spacers. | 01-01-2009 |
20090017592 | Siloxane polymer composition, method of forming a pattern using the same, and method of manufacturing a semiconductor using the same - A siloxane polymer composition includes an organic solvent in an amount of about 93 percent by weight to about 98 percent by weight, based on a total weight of the siloxane polymer composition, and a siloxane complex in an amount of about 2 percent by weight to about 7 percent by weight, based on the total weight of the siloxane polymer composition, the siloxane complex including a siloxane polymer with an introduced carboxylic acid and being represented by Formula 1 below, | 01-15-2009 |
20090023264 | METHOD OF MAKING PLANAR-TYPE BOTTOM ELECTRODE FOR SEMICONDUCTOR DEVICE - A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers. | 01-22-2009 |
20090029519 | METHOD OF MANUFACTURING MIM CAPACITOR - Embodiments relate to a method of manufacturing an MIM capacitor, which is capable of obtaining a desired capacitance by controlling a k value of insulator thin film formed between bottom and top electrodes by adjusting a plasma doping condition. An MIM capacitor may be manufactured by forming a bottom electrode over a semiconductor substrate. An insulator thin film may be formed over the bottom electrode. A k value of the insulator thin film may be adjusted to an optional range by performing a plasma nitridation doping process on the insulator thin film. A top electrode may be formed over the insulator thin film. | 01-29-2009 |
20090035913 | HIGH-CAPACITANCE DENSITY THIN FILM DIELECTRICS HAVING COLUMNAR GRAINS FORMED ON BASE-METAL FOILS - Deposited thin-film dielectrics having columnar grains and high dielectric constants are formed on heat treated and polished metal foil. The sputtered dielectrics are annealed at low oxygen partial pressures. | 02-05-2009 |
20090075449 | INTEGRATED HIGH VOLTAGE CAPACITOR HAVING CAPACITANCE UNIFORMITY STRUCTURES AND A METHOD OF MANUFACTURE THEREFOR - The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate ( | 03-19-2009 |
20090130815 | Semiconductor device and method for fabricating the same - The semiconductor device comprises a capacitor formed over a semiconductor substrate | 05-21-2009 |
20090148996 | METHOD OF MAKING A SEMICONDUCTOR ELEMENT - A method of producing a capacitor that includes producing a first electrode having a first surface; forming a recess in an element, walls of the element and the first surface of the first electrode defining the recess, the element having a first surface exterior of the recess; forming a dielectric layer on the element, the dielectric layer oriented against the first surface of the element and against the walls of the element within the recess; polishing off at least a portion of the dielectric layer oriented against the first surface of the element to electrically isolate the portion of the dielectric layer located in the recess from any portion of the dielectric layer remaining outside the recess; and producing a second electrode, the second electrode oriented at least partially within the recess with the dielectric layer oriented between the first electrode and the second electrode. | 06-11-2009 |
20090155975 | METHOD FOR MANUFACTURING METAL-INSULATOR-METAL CAPACITOR OF SEMICONDUCTOR DEVICE - A method for manufacturing a metal-insulator-metal capacitor of a semiconductor device method for manufacturing a semiconductor device. In one example embodiment, a method for manufacturing a semiconductor device includes various steps. First, a logic metal and a capacitor lower metal is formed on a first insulating film that is formed on a semiconductor substrate. Next, a portion of the capacitor lower metal is selectively etched to a predetermined depth. Then, a second insulating film is formed over an entire upper surface of the logic metal, the first insulating film, and the capacitor lower metal. Next, a capacitor upper metal is formed on the second insulating film in a region corresponding to the etched portion of the capacitor lower metal. Finally, a third insulating film is formed on an entire upper surface of the second insulating film and the capacitor upper metal. | 06-18-2009 |
20090155976 | ATOMIC LAYER DEPOSITION OF DY-DOPED HFO2 FILMS AS GATE DIELECTRICS - The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO | 06-18-2009 |
20090162987 | METHOD FOR FABRICATING MIM STRUCTURE CAPACITOR - A method for fabricating a metal/insulator/metal (MIM) structure capacitor includes forming a nitride film that is an insulating layer on a bottom electrode metal layer; forming titanium/titanium nitride (Ti/TiN) that is a top electrode metal layer on the nitride film; coating photo-resist on the top electrode metal layer and patterning a photo-resist layer; selectively etching the top metal electrode layer so that the nitride film remains using the patterned photo-resist layer as an etching mask and using the nitride film as an end point; and removing the remaining nitride film. | 06-25-2009 |
20090246930 | METAL CAPACITOR INCLUDING LOWER METAL ELECTRODE HAVING HEMISPHERICAL METAL GRAINS - Disclosed is a metal capacitor including a lower electrode having hemispherical metal grains thereon. The metal capacitor includes a lower metal electrode containing Ti, hemispherical metal grains containing Pd and formed on the lower metal electrode containing Ti, a dielectric layer formed on the lower metal electrode containing Ti and the hemispherical metal grains containing Pd, and an upper metal electrode formed on the dielectric layer. | 10-01-2009 |
20090269901 | CAPACITOR ELEMENT MANUFACTURING JIG AND CAPACITOR ELEMENT MANUFACTURING METHOD - The invention relates to a jig for producing capacitor elements, which is formed of resin material and is used for accommodate a plurality of capacitor element substrates therein to thereby batch-process the substrates. The jig is characterized in that portions of the jig at which the jig is supported during the process are protected with metal material. According to the invention, a group of capacitors each having a semiconductor layer serving as one electrode can be simultaneously produced with narrow variety in capacitance and with good precision, repeatedly, by using the jig having a high durability. | 10-29-2009 |
20090305478 | METHOD FOR MANUFACTURING CAPACITOR OF SEMICONDUCTOR DEVICE - A method for manufacturing a capacitor of a semiconductor device includes forming a lower metal layer over a substrate, forming a dielectric layer over the lower metal layer, forming an upper metal layer over the dielectric layer, forming an upper electrode and a dielectric layer pattern by performing a reactive ion etching process with respect to the upper metal layer using the dielectric layer as an etch stop layer, and exposing a top surface of the lower metal layer, and performing a chemical down-stream etch (CDE) process to remove a by-product of a sidewall of the upper electrode. | 12-10-2009 |
20090305479 | CONVENTIONALLY PRINTABLE NON-VOLATILE PASSIVE MEMORY ELEMENT AND METHOD OF MAKING THEREOF - A non-volatile passive memory element comprising on a single surface a first electrode system and a second electrode system together with an insulating system, unless the insulating system is the surface, wherein the first electrode system is insulated from the second electrode system, the first and the second electrode systems are pattern systems and at least one conductive or semiconducting bridge is present between the first and second electrode systems, and wherein the non-volatile passive memory device is exclusive of metallic silicon and the systems and the conductive or semiconducting bridges are printable using conventional printing processes with the optional exception of the insulating system if the insulating system is the surface. A non-volatile passive memory device comprising a support and on at least one side of the support the above-mentioned non-volatile passive memory element. A process for providing the above-mentioned non-volatile passive memory device, comprising the realization on a single surface of the support of the steps of: providing a first electrode system pattern, optionally providing an insulating pattern, providing a second electrode system pattern, and providing at least one conductive or semiconducting bridge between the first electrode system pattern and the second electrode system pattern at predesignated points, wherein at least one of the steps is realized with a conventional printing process and two of said steps are optionally performed simultaneously. | 12-10-2009 |
20100035402 | Method for manufacturing semiconductor device - A method for manufacturing a semiconductor device includes forming a first interlayer insulating film over a semiconductor substrate; forming a first opening in the first interlayer insulating film; forming a second interlayer insulating film on the first interlayer insulating film such that the first opening is not filled; and forming a second opening in the second interlayer insulating film such that the second opening is connected to the first opening. | 02-11-2010 |
20100055862 | METHOD FOR PRODUCING AN INTEGRATED CIRCUIT ARRANGEMENT WITH CAPACITOR IN AN INTERCONNECT LAYER - A method produces integrated circuit arrangement that includes an undulating capacitor in a conductive structure layer. The surface area of the capacitor is enlarged in comparison with an even capacitor. The capacitor is interlinked with dielectric regions at its top side and/or its underside, so that it can be produced by methods which may not have to be altered in comparison with conventional CMP methods. | 03-04-2010 |
20100093150 | METHOD OF MANUFACTURING CAPACITOR - One capacitor fabrication process of the invention comprises a noble metal layer formation step of forming a noble metal layer on one surface of a substrate, a dielectric layer formation step of forming a dielectric layer on the noble metal layer, a metal foil formation step of forming a metal foil of 10 μm or greater in thickness on the dielectric layer, a separation step of separating the noble metal layer from the dielectric layer at an interface, and an electrode layer formation step of forming an electrode layer on the second surface of the dielectric layer separated off by the separation step, wherein the second surface faces away from the first surface of the dielectric layer with the metal foil formed thereon. | 04-15-2010 |
20100129978 | Method of fabricating semiconductor device having MIM capacitor - A method of fabricating a semiconductor device includes forming a first insulating layer on a semiconductor substrate including a first region, forming an electrode pattern embedded in the first insulating layer on the first region, forming a second insulating layer on the first insulating layer and the electrode pattern; forming a recess portion that defines a capacitor region on the first region by etching the first and second insulating layers, wherein the electrode pattern is arranged in the recess portion and a portion of the electrode pattern protrudes from a bottom surface of the recess portion, and forming a dielectric layer and an upper electrode layer on the bottom surface of the recess portion and the protruded portion of the electrode pattern. | 05-27-2010 |
20100159665 | CAPACITOR FORMED ON A RECRYSTALLIZED POLYSILICON LAYER - The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, among other elements, includes a recrystallized polysilicon layer | 06-24-2010 |
20100159666 | INTEGRATION OF CAPACITIVE ELEMENTS IN THE FORM OF PEROVSKITE CERAMIC - The use of a conductive bidimensional perovskite as an interface between a silicon, metal, or amorphous oxide substrate and an insulating perovskite deposited by epitaxy, as well as an integrated circuit and its manufacturing process comprising a layer of an insulating perovskite deposited by epitaxy to form the dielectric of capacitive elements having at least an electrode formed of a conductive bidimensional perovskite forming an interface between said dielectric and an underlying silicon, metal, or amorphous oxide substrate. | 06-24-2010 |
20100167489 | MIM CAPACITOR AND METHOD OF FABRICATING THE SAME - A method of fabricating an MIM capacitor may include a first electrode formed on and/or over a semiconductor substrate, a dielectric layer composed of an oxygen material formed on and/or over the first electrode under an oxygen atmosphere. A second electrode is formed on and/or over the dielectric layer. Because the dielectric layer is formed under an oxygen atmosphere, an oxygen composition ratio of the dielectric layer is increased. | 07-01-2010 |
20100190314 | Methods Of Forming Semiconductor Structures - Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode. | 07-29-2010 |
20100297825 | Passive Components in the Back End of Integrated Circuits - Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members. | 11-25-2010 |
20110053336 | METHOD FOR SELECTIVE DEPOSITION OF DIELECTRIC LAYERS ON SEMICONDUCTOR STRUCTURES - A method for forming a capacitor and a transistor device on different surface portions of a semiconductor structure includes forming a passivation dielectric layer for the device; forming a bottom electrode for the capacitor; forming a removable layer extending over the bottom electrode and over the passivation dielectric layer with a window therein, such window exposing said bottom electrode; depositing a capacitor dielectric layer of the same or different material as the passivation dielectric layer over the removable layer with first portions passing through the window onto the exposed bottom electrode and second portions being over the removable layer, the thickness of the deposited layer being different from the thickness of the passivation layer; removing the removable layer with the second portions thereon while leaving said first portions on the bottom electrode; and forming a top electrode for the capacitor on the second portions remaining on the bottom electrode. | 03-03-2011 |
20110070717 | CAPACITORS AND METHODS WITH PRASEODYMIUM OXIDE INSULATORS - Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties. | 03-24-2011 |
20110269291 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING CAPACITIVE ELEMENTS - A technology capable of reducing the fraction defective of a MOS capacitor without the need to perform a screening is provided. | 11-03-2011 |
20120156854 | METHOD OF FORMING STACKED METAL OXIDE LAYERS - This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor or DRAM cell. In such a device, a high-K zirconia-based layer may be used as the primary dielectric together with a relatively inexpensive metal electrode based on titanium nitride. To prevent corruption of the electrode during device formation, a thin barrier layer can be used seal the electrode prior to the use of a high temperature process and a (high-concentration or dosage) ozone reagent (i.e., to create a high-K zirconia-based layer). In some embodiments, the barrier layer can also be zirconia-based, for example, a thin layer of doped or un-doped amorphous zirconia. Fabrication of a device in this manner facilitates formation of a device with dielectric constant of greater than 40 based on zirconia and titanium nitride, and generally helps produce less costly, increasingly dense DRAM cells and other semiconductor structures. | 06-21-2012 |
20140295640 | CAPACITOR ARRAYS FOR MINIMIZING GRADIENT EFFECTS AND METHODS OF FORMING THE SAME - Methods of forming semiconductor devices. The method includes forming a capacitor array comprising a plurality of cells in a two-dimensional grid. The step of forming includes forming a plurality of operational capacitors in a first subset of the plurality of cells along a diagonal of the array, the plurality of operational capacitors comprising a first operational capacitor formed in a cell at a first edge of the capacitor array and at a first edge of the diagonal of the capacitor array. The step of forming also includes forming a plurality of dummy patterns about the plurality of operational capacitors in the capacitor array in a second subset of the plurality of cells to achieve symmetry in the grid about the diagonal. The method also includes electrically coupling each one of the plurality of operational capacitors to another one of the plurality of operational capacitors. | 10-02-2014 |
20140377933 | METHOD FOR PRODUCING A METAL STRUCTURE IN A SEMICONDUCTOR SUBSTRATE - A method for producing a metal structure in a semiconductor substrate includes: producing an opening in the rear side of the semiconductor substrate in the area of the metal structure to be produced, which extends to the front side layer structure; filling the opening at least partially with a metal so that a metal structure is created which extends from the rear side of the semiconductor substrate to the front side layer structure; masking the rear side of the semiconductor substrate for a trench process for exposing the metal structure in such a way that the trench mask includes a lattice structure in an area adjacent to the metal structure; producing an isolation trench adjacent to the metal structure, the metal structure acting as a lateral etch stop and the lattice structure being laterally undercut in the trench mask; and applying a sealing layer to the mask. | 12-25-2014 |
20150037960 | METHOD OF MANUFACTURING A CAPACITOR - A method of forming a device comprises forming a through via extending from a surface of a substrate into the substrate. The method also comprises forming a first insulating layer over the surface of the substrate. The method further comprises forming a first metallization layer in the first insulating layer, the first metallization layer electrically connecting the through via. The method additionally comprises forming a capacitor over the first metallization layer. The capacitor comprises a first capacitor dielectric layer over the first metallization layer and a second capacitor dielectric layer over the first capacitor dielectric layer. The method also comprises forming a second metallization layer over and electrically connecting the capacitor. | 02-05-2015 |
20160027642 | Methods of Forming Capacitors - A method of forming a capacitor includes depositing a dielectric metal oxide layer of a first phase to a thickness no greater than 75 Angstroms over an inner conductive capacitor electrode material. The first phase dielectric metal oxide layer has a k of at least 15. Conductive RuO | 01-28-2016 |
20160254187 | Disposable Pillars for Contact Information | 09-01-2016 |
438394000 | Including doping of semiconductive region | 4 |
20100151654 | NITRIDE FILM FORMING METHOD, SEMICONDUCTOR DEVICE FABRICATION METHOD, CAPACITOR FABRICATION METHOD AND NITRIDE FILM FORMING APPARATUS - The nitride film forming method comprises the first step of loading a semiconductor substrate | 06-17-2010 |
20100273307 | METHOD OF MAKING A DEVICE INCLUDING A CAPACITIVE STRUCTURE - A method for making a device including a capacitive structure is disclosed. One embodiment provides a carrier layer having a surface. A first dielectric layer is formed on the surface. A silicon layer including silicon grains is formed on the first dielectric layer using a deposition process. A second dielectric layer is formed on the second silicon layer. A layer of an electrically conductive material is formed on the dielectric layer. A temperature process for heating at least the first dielectric layer is performed. The temperature and duration of the temperature process is selected such that the first dielectric layer is modified so that the silicon layer is electrically connected to the carrier layer. | 10-28-2010 |
20110092045 | BURIED DECOUPLING CAPACITORS, DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS OF FABRICATION - A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit. | 04-21-2011 |
20120302033 | CAPACITOR AND METHOD FOR FABRICATING THE SAME, AND SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The semiconductor device comprises a device isolation region formed in a semiconductor substrate, a lower electrode formed in a device region defined by the device isolation region and formed of an impurity diffused layer, a dielectric film of a thermal oxide film formed on the lower electrode, an upper electrode formed on the dielectric film, an insulation layer formed on the semiconductor substrate, covering the upper electrode, a first conductor plug buried in a first contact hole formed down to the lower electrode, and a second conductor plug buried in a second contact hole formed down to the upper electrode, the upper electrode being not formed in the device isolation region. The upper electrode is not formed in the device isolation region, whereby the short-circuit between the upper electrode and the lower electrode in the cavity can be prevented. | 11-29-2012 |