Class / Patent application number | Description | Number of patent applications / Date published |
438384000 | Deposited thin film resistor | 31 |
20080200003 | Method for Forming Multi-Layered Binary Oxide Film for Use in Resistance Random Access Memory - The invention relates to a method for forming a multi-layered binary oxide film for ReRAM. The method includes forming a lower electrode layer on a substrate; forming a metal layer on the lower electrode layer in a vacuum atmosphere; oxidizing the metal layer into a binary oxide film in a vacuum atmosphere; repeating the steps of forming and oxidizing the metal layer to form a desired thickness of the multi-layered binary oxide film; and forming an upper electrode layer on the multi-layered film. The method allows a nonvolatile memory device more efficient than the conventional perovskite structure in a simple process without concerns for surface contamination since the metal layer is formed and oxidized in a vacuum atmosphere. | 08-21-2008 |
20090017591 | Local Oxidation of Silicon Planarization for Polysilicon Layers Under Thin Film Structures - In accordance with the teachings described herein, a method for fabricating a patterned polysilicon layer having a planar surface may include the steps of: depositing a polysilicon film above a substrate material; depositing an oxide-resistant mask over the polysilicon film; patterning and etching the oxide-resistant mask to form a patterned mask layer over the polysilicon film, such that the polysilicon film includes masked and unmasked portions; etching the unmasked portions of the polysilicon film for a first amount of time; oxidizing the etched polysilicon film for a second amount of time to form an oxide layer that defines the patterned polysilicon layer; and removing the patterned mask layer; wherein the first and second amounts of time are selected such that the oxide layer and the patterned polysilicon layer have about the same thickness and form a planar surface. | 01-15-2009 |
20090023263 | METHOD TO MANUFACTURE A THIN FILM RESISTOR - A method for manufacturing a semiconductor device that method comprises forming a thin film resistor by a process that includes depositing a resistive material layer on a semiconductor substrate. The process also includes depositing an insulating layer on the resistive material layer, and performing a first dry etch process on the insulating layer to form an insulative body. The process further includes performing a second dry etch process on the resistive material layer to form a resistive body. The resistive body and the insulative body have substantially identical perimeters. | 01-22-2009 |
20090317958 | METHOD FOR FORMING MEMRISTOR MATERIAL AND ELECTRODE STRUCTURE WITH MEMRISTANCE - Ion Implantation is used to form the memristor material and electrode structure with memristance. First, numerous electron-rich element atoms are implanted into a layer made of transition metal or non-metal. Then, a treating process (such as annealing) is proceeded to expel some electron-rich element atoms away the layer. After that, some electron-rich element vacancy rich regions are formed inside the layer, and then a memristor material is formed. Significantly, the usage of ion implantation can precisely control and flexibly adjust the distribution of the implanted atoms, and then both the amount and distribution of these depleted regions can be effectively adjusted. Hence, the quality of the memristor material is improved. | 12-24-2009 |
20100041202 | Methods For Forming Back-End-Of-Line Resistive Semiconductor Structures - In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines. | 02-18-2010 |
20100136764 | METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT - A method of manufacturing an integrated circuit comprises depositing a electrically resistive layer of a material for serving as a thin film resistor (TFR), depositing an electrically insulating layer on the resistor layer, removing the electrically insulating layer from outside an electrically active area of the resistor layer corresponding to a target TFR area, and depositing an electrically conductive layer of an electrically conductive material such that the conductive layer overlaps the target TFR area and the conductive layer electrically contacts the resistor layer outside the target TFR area. | 06-03-2010 |
20100291748 | METHOD FOR MAKING PMC TYPE MEMORY CELLS - A microelectronic device includes: at least one cell or element including at least one first electrode, at least one second electrode, and at least one stack of thin layers between the first electrode and the second electrode. The stack includes at least one doped chalcogenide layer capable of forming a solid electrolyte, the doped chalcogenide layer being provided on and in contact with the first electrode; at least one interface layer provided on and in contact with the doped chalcogenide layer, the interface layer being based on a material different from the chalcogenide, the material being carbon or carbon comprising a metallic additive or a semiconducting additive; and at least one metallic ion donor layer provided on and in contact with the interface layer, the metallic ion donor layer being an ion source for the solid electrolyte. | 11-18-2010 |
20110086488 | PLASMA ETCH FOR CHROMIUM ALLOYS - A reactive ion etching (RIE) process comprising a chlorine source gas and an oxygen source gas with an atomic ratio of chlorine to oxygen in the plasma of at least 6 to 1 is used to etch chromium alloy films such as SiCr, SiCrC, SiCrO, SiCrCO, SiCrCN, SiCrON, SiCrCON, CrO, CrN, CrON, and NiCr for example. Additionally, a fluorine source may be added to the etch chemistry. | 04-14-2011 |
20110171811 | METHOD FOR FABRICATING A RESISTOR FOR A RESISTANCE RANDOM ACCESS MEMORY - A method for fabricating a resistor for a resistance random access memory (RRAM) includes: (a) forming a first electrode over a substrate; (b) forming a variable resistance layer of zirconium oxide on the first electrode under a working temperature, which ranges from 175° C. to 225° C.; and (c) forming a second electrode of Ti on the variable resistance layer. | 07-14-2011 |
20110177668 | METHOD OF MAKING A THIN FILM RESISTOR - A method of making a thin film resistor includes: forming a doped region in a semiconductor substrate; forming a dielectric layer over the substrate; forming a thin film resistor over the dielectric layer; forming a contact hole in the dielectric layer before annealing the thin film resistor, wherein the contact hole exposes a portion of the doped region; and performing rapid thermal annealing on the thin film resistor after forming the contact hole. | 07-21-2011 |
20110195557 | METHOD FOR FORMING LOW RESISTANCE AND UNIFORM METAL GATE - The present disclosure provides a method that includes forming a high k dielectric layer on a semiconductor substrate; forming a polysilicon layer on the high k dielectric layer; patterning the high k dielectric layer and polysilicon layer to form first and second dummy gates in first and second field effect transistor (FET) regions, respectively; forming an inter-level dielectric (ILD); applying a first CMP process to the semiconductor substrate, exposing the first and second dummy gates; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a first metal electrode in the first gate trench; applying a second CMP process; forming a mask covering the first FET region and exposing the second dummy gate; thereafter removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a second metal electrode in the second gate trench; and applying a third CMP process. | 08-11-2011 |
20110312151 | PILLAR STRUCTURE FOR MEMORY DEVICE AND METHOD - A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure. | 12-22-2011 |
20110318898 | HARD MASK FOR THIN FILM RESISTOR MANUFACTURE - Methods of fabricating an integrated circuit device, such as a thin film resistor, are disclosed. An exemplary method includes providing a semiconductor substrate; forming a resistive layer over the semiconductor substrate; forming a hard mask layer over the resistive layer, wherein the hard mask layer includes a barrier layer over the resistive layer and a dielectric layer over the barrier layer; and forming an opening in the hard mask layer that exposes a portion of the resistive layer. | 12-29-2011 |
20120184080 | COMPACT THERMALLY CONTROLLED THIN FILM RESISTORS UTILIZING SUBSTRATE CONTACTS AND METHODS OF MANUFACTURE - A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate, and forming at least one dielectric layer over the resistor. The method also includes forming a substrate contact through the at least one dielectric layer, through the resistor, through the insulator layer, and into the substrate. The substrate contact comprises a high thermal conductivity material. | 07-19-2012 |
20120225535 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Provided is a resistance element which is, when forming the resistance element including a resistor having a small thickness, less liable to cause disconnection of the resistor. Tip regions of electrodes which are formed by stacking a barrier metal film and an aluminum electrode film are formed so as to be single-layer barrier metal electrodes, and the resistor for electrically connecting the parallel barrier metal electrodes to each other is formed by lift-off. | 09-06-2012 |
20130034947 | ATOMIC LAYER DEPOSITION OF METAL OXIDES FOR MEMORY APPLICATIONS - Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent. | 02-07-2013 |
20130230962 | METHODS FOR FORMING NICKEL OXIDE FILMS FOR USE WITH RESISTIVE SWITCHING MEMORY DEVICES/US - Methods for forming a NiO film on a substrate for use with a resistive switching memory device are presenting including: preparing a nickel ion solution; receiving the substrate, where the substrate includes a bottom electrode, the bottom electrode utilized as a cathode; forming a Ni(OH) | 09-05-2013 |
20140113429 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane. | 04-24-2014 |
20140273395 | METHODS OF FORMING A THIN LAYER AND METHODS OF MANUFACTURING A PHASE CHANGE MEMORY DEVICE USING THE SAME - A method of forming a thin layer and a method of manufacturing a phase change memory device, the method of forming a thin layer including providing a first deposition source onto a substrate, the first deposition source not including tellurium; and providing a second deposition source onto the substrate, the second deposition source including a first tellurium precursor represented by the following Formula 1 and a second tellurium precursor represented by following the Formula 2: | 09-18-2014 |
20140357047 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer. | 12-04-2014 |
20160013407 | SEMICONDUCTOR MEMORY DEVICE | 01-14-2016 |
20160071838 | EMBEDDED TUNGSTEN RESISTOR - A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A high TCR tungsten resistor embedded in a intermetal dielectric layer above a lower interconnect layer and below an upper interconnect layer. A method of forming a high TCR tungsten resistor on a reverse biased Schottky diode. A method of forming high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A method of forming high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A method of forming high TCR tungsten resistor embedded in a inter metal dielectric layer above a lower interconnect layer and below an upper interconnect layer. | 03-10-2016 |
20160254144 | LOW TEMPERATURE FABRICATION OF LATERAL THIN FILM VARISTOR | 09-01-2016 |
20180025909 | THIN FILM, METHOD OF FABRICATING THE SAME, AND APPARATUS FOR FABRICATING THE SAME | 01-25-2018 |
438385000 | Altering resistivity of conductor | 7 |
20100124810 | Nonvolatile Memory Device and Fabrication Method Thereof - A nonvolatile memory device and its fabrication method of the present invention may ensure a margin of the threshold drive voltage during a design process of the device by forming a resistance layer determining phase of ReRAM along an upper edge of a lower electrode, and improve operating characteristics of the device | 05-20-2010 |
20100190313 | METHOD FOR MANUFACTURING NONVOLATILE STORAGE ELEMENT AND METHOD FOR MANUFACTURING NONVOLATILE STORAGE DEVICE - A method for manufacturing a nonvolatile storage element that minimizes shape shift between an upper electrode and a lower electrode, and which includes: depositing, in sequence, a connecting electrode layer which is conductive, a lower electrode layer and a variable resistance layer which are made of a non-noble metal nitride and are conductive, an upper electrode layer made of noble metal, and a mask layer; forming the mask layer, into a predetermined shape; forming the upper electrode layer, the variable resistance layer, and the lower electrode layer into the predetermined shape by etching using the mask layer as a mask; and removing, simultaneously, the mask and a region of the connecting electrode layer that has been exposed by the etching. | 07-29-2010 |
20100240189 | Methods of Fabricating Semiconductor Devices - Methods of fabricating semiconductor devices are provided including forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein. A metal pattern is formed in the opening. An oxidization process is performed on the metal pattern to form a conductive metal oxide pattern, and the conductive metal oxide pattern is planarized. Related semiconductor devices are also provided. | 09-23-2010 |
20100248442 | METHODS OF FORMING A PHASE CHANGE MEMORY DEVICE - Provided are methods of forming a phase change memory device. A semiconductor device having a lower electrode and an interlayer insulating layer may be prepared. The lower electrode may be surrounded by the interlayer insulating layer. Source gases, a reaction gas and a purge gas may be injected into a process chamber of a semiconductor fabrication device to form a phase change material layer on a semiconductor substrate. The source gases may be simultaneously injected into the process chamber. The phase change material layer may be in contact with the lower electrode through the interlayer insulating layer. The phase change material layer may be etched to form a phase change memory cell in the interlayer insulating layer. An upper electrode may be formed on the phase change memory cell. | 09-30-2010 |
20110014771 | Method of making damascene diodes using selective etching methods - A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first conductivity type semiconductor layer in the plurality of openings, forming a second conductivity type semiconductor layer over the first conductivity type semiconductor layer in the plurality of openings, and selectively etching the second conductivity type semiconductor layer using an upper surface of the first conductivity type semiconductor layer as a stop to form a recess in the plurality of openings. | 01-20-2011 |
20140065791 | ALLOTROPIC OR MORPHOLOGIC CHANGE IN SILICON INDUCED BY ELECTROMAGNETIC RADIATION FOR RESISTANCE TURNING OF INTEGRATED CIRCUITS - An electronic device includes a semiconductor substrate and a dielectric layer over the substrate. A resistive link located over the substrate includes a first resistive region and a second resistive region. The first resistive region has a first resistivity and a first morphology. The second resistive region has a second resistivity and a different second morphology. | 03-06-2014 |
20140113430 | METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a semiconductor device according to the present invention includes: forming a lower electrode above a substrate; forming, above the lower electrode, a first variable resistance layer comprising a first metal oxide; forming a step region in the first variable resistance layer by collision of ions excited by plasma; removing residue of the first variable resistance layer created in the forming of the step region; forming a second variable resistance layer which covers the step region of the first variable resistance layer, comprises a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide, and has a bend on a step formed along an edge of the step region; and forming an upper electrode above the second variable resistance layer. | 04-24-2014 |