Class / Patent application number | Description | Number of patent applications / Date published |
438305000 | Plural doping steps | 71 |
20080200001 | METHOD OF PRODUCING A TRANSISTOR - Method of producing a transistor, comprising in particular the steps of: | 08-21-2008 |
20080206948 | Semiconductor device and method of fabricating the same - An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region. | 08-28-2008 |
20080213965 | METHOD FOR MANUFACTURING DMOS DEVICE - A method for manufacturing a semiconductor device is provided. The semiconductor device may be a drain extended metal-oxide-semiconductor (DMOS) device. The method includes: forming a gate insulating film on a semiconductor substrate having an active region; forming a gate on the gate insulating film; forming a low-concentration source region and a low-concentration drain region over the semiconductor substrate by implanting low-concentration impurity ions using the gate as a mask; forming a spacer on sides of the gate; forming a silicide area block (SAB) pattern over the semiconductor substrate, covering a portion of the gate and the low-concentration drain region; and forming a high-concentration source region and a high-concentration drain region over the semiconductor substrate by implanting high-concentration impurity ions using the SAB pattern as a mask. | 09-04-2008 |
20080242039 | METHOD OF ENHANCING DOPANT ACTIVATION WITHOUT SUFFERING ADDITIONAL DOPANT DIFFUSION - A method of enhancing dopant activation without suffering additional dopant diffusion, includes forming shallow and lightly-doped source/drain extension regions in a semiconductor substrate, performing a first anneal process on the source/drain extension regions, forming deep and heavily-doped source/drain regions in the substrate adjacent to the source/drain extension regions, and performing a second anneal process on source/drain regions. The first anneal process is a flash anneal process performed for a time of between about 1 millisecond and 3 milliseconds, and the second anneal process is a rapid thermal anneal process performed for a time of between about 1 second and 30 seconds. | 10-02-2008 |
20080242040 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate. | 10-02-2008 |
20080242041 | Selective Deposition of Germanium Spacers on Nitride - A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface. | 10-02-2008 |
20080268602 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers each having a first inner spacer and a second outer spacer on sidewalls of the gate stack; forming a protective layer on sidewalls of the spacers, covering a part of the semiconductor substrate, wherein an etching selectivity of the protective layer is higher than that of the first inner spacer. | 10-30-2008 |
20080274601 | METHOD OF FORMING A TRANSISTOR HAVING MULTIPLE TYPES OF SCHOTTKY JUNCTIONS - A gate electrode is formed overlying a substrate. A first angled metal implant is performed at a first angle into the substrate followed by performing a second angled metal implant at a second angle. The first angled metal implant and the second angled metal implant form a first current electrode and a second current electrode. Each of the first current electrode and the second current electrode has at least two regions of differing metal composition. A metal layer is deposited overlying the gate electrode, the first current electrode and the second current electrode. The metal layer is annealed to form two Schottky junctions in each of the first current electrode and the second current electrode. The two Schottky junctions have differing barrier levels. | 11-06-2008 |
20080280413 | METHODS FOR FORMING A TRANSISTOR - Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon carbide material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon carbide material to form a source/drain region having a second conductivity. | 11-13-2008 |
20080311721 | Semiconductor device manufacture method including process of implanting impurity into gate electrode independently from source/drain and semiconductor device manufactured by the method - A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electrode. After impurities are implanted, the mask member is removed. Source and drain regions are formed by implanting impurities into the surface layer of the semiconductor substrate on both sides of the gate electrode. It is possible to reduce variations of cross sectional shape of gate electrodes and set an impurity concentration of the gate electrode independently from an impurity concentration of the source and drain regions. | 12-18-2008 |
20080318387 | Activation of CMOS Source/Drain Extensions by Ultra-High Temperature Anneals - A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount of the dopant remaining in a dielectric layer adjacent the gate electrode. The substrate is annealed at a temperature of about 1000° C. or greater to cause at least a portion of the amount of the dopant to diffuse into the semiconductor substrate. | 12-25-2008 |
20090035912 | Semiconductor Device and Fabrication Method Thereof - In order to diversify a current control method of a semiconductor device, improve performance (including a current drive performance) of the semiconductor device, and reduce a size of the semiconductor device, a second gate may be formed inside a substrate that forms a channel upon applying a bias voltage thereto. In one aspect, the semiconductor device includes: a well region of a first conductivity; source and drain regions of a second conductivity in the well region; a first gate on an oxide layer above the well region, controlling a first channel region of a second conductivity between the source region and the drain region; and a second gate under the first channel region. | 02-05-2009 |
20090042351 | METHOD FOR MAKING A TRANSISTOR WITH A STRESSOR - A method for forming a semiconductor device on a semiconductor material layer includes forming a gate structure over the semiconductor material layer. The method further includes forming a first nitride spacer adjacent to the gate structure and forming source/drain extensions in the semiconductor material layer. The method further includes forming an oxide liner overlying the gate structure and the source/drain extensions. The method further includes forming a second nitride spacer adjacent to the oxide liner. The method further includes forming source/drain regions in the semiconductor material layer. The method further includes using an etching process that is selective to the oxide liner, removing the second nitride spacer. The method further includes using an etching process that is selective to the first nitride spacer, at least partially removing the oxide liner. The method further includes forming silicide regions overlying the source/drain regions and the gate structure. | 02-12-2009 |
20090117701 | METHOD FOR MANUFACTURING A MOS TRANSISTOR - A method for manufacturing a MOS transistor includes performing a thermal treatment to repair damaged substrate before forming source/drain extension regions, accordingly negative bias temperature instability (NBTI) is reduced. Since the thermal treatment is performed before forming the source/drain extension regions, heat budget for forming the source/drain extension regions and junction depth and junction profile of the source/drain extension would not be affected. Therefore the provided method for manufacturing a MOS transistor is capable of reducing short channel effect and possesses a superior process compatibility. | 05-07-2009 |
20090155973 | SEMICONDUCTOR DEVICE HAVING MOSFET WITH OFFSET-SPACER, AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a gate insulating film which is formed on the major surface of a semiconductor substrate, a gate electrode which is formed on the gate insulating film, a first offset-spacer which is formed in contact with one side surface of the gate electrode, a first spacer which is formed in contact with the other side surface of the gate electrode, a second spacer which is formed in contact with the first offset-spacer, and source and drain regions which are formed apart from each other in the major surface of the semiconductor substrate below the first and second spacers so as to sandwich the gate electrode and the first offset-spacer. The source region is formed at a position deeper than the drain region. The dopant concentration of the source region is higher than that of the drain region. | 06-18-2009 |
20090197383 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths. | 08-06-2009 |
20090203182 | Method of manufacturing transistor having metal silicide and method of manufacturing a semiconductor device using the same - In a method of manufacturing a transistor and a method of manufacturing a semiconductor device using the same, the method may include forming a preliminary metal silicide pattern on a single-crystalline silicon substrate and on a polysilicon pattern, and partially etching the preliminary metal silicide pattern to form a first metal silicide pattern on the substrate and a second metal silicide pattern on the polysilicon pattern, the second metal silicide pattern having a line width the same as or smaller than that of the polysilicon pattern. The method may include the transistor having no metal silicide residue on the spacer. Accordingly, an operation failure due to the residue may be prevented or reduced. | 08-13-2009 |
20090221123 | METHOD FOR INCREASING PENETRATION DEPTH OF DRAIN AND SOURCE IMPLANTATION SPECIES FOR A GIVEN GATE HEIGHT - The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions. | 09-03-2009 |
20090246926 | METHOD FOR CREATING TENSILE STRAIN BY APPLYING STRESS MEMORIZATION TECHNIQUES AT CLOSE PROXIMITY TO THE GATE ELECTRODE - After forming the outer drain and source regions of an N-channel transistor, the spacer structure may be removed on the basis of an appropriately designed etch stop layer so that a rigid material layer may be positioned more closely to the gate electrode, thereby enhancing the overall strain-inducing mechanism during a subsequent anneal process in the presence of the material layer and providing an enhanced stress memorization technique (SMT). In some illustrative embodiments, a selective SMT approach may be provided. | 10-01-2009 |
20090246927 | INCREASING STRESS TRANSFER EFFICIENCY IN A TRANSISTOR BY REDUCING SPACER WIDTH DURING THE DRAIN/SOURCE IMPLANTATION SEQUENCE - By forming a single spacer element and reducing the size thereof by a well-controllable etch process, a complex lateral dopant profile may be obtained at reduced process complexity compared to conventional triple spacer approaches in forming drain and source regions of advanced MOS transistors. | 10-01-2009 |
20090269900 | SEMICONDUCTOR DEVICE AND MANUFACTURE METHOD THEREOF - An object is to provide an element structure of a semiconductor device for increasing an etching margin for various etching steps and a method for manufacturing the semiconductor device having the element structure. An island-shaped semiconductor layer is provided over an insulator having openings. The island-shaped semiconductor layer includes embedded semiconductor layers and a thin film semiconductor layer. The embedded semiconductor layers have a larger thickness than that of the thin film semiconductor layer. | 10-29-2009 |
20090280614 | Method of making a P-type metal-oxide semiconductor transistor and method of making a complementary metal-oxide semiconductor transistor - A method is disclosed to make a strained-silicon PMOS or CMOS transistor, in which, a compressive stress film is formed by reacting a silane having at least one substituent selected from the group consisting of hydrocarbyl, hydrocarboxy, carbonyl, formyl, carboxylic group, ester group, and halo group and ammonia, or a conventional compressive stress film is implanted with fluorine atoms, oxygen atoms, or carbon atoms, so as to improve the properties of negative bias temperature instability (NBTI). | 11-12-2009 |
20090286376 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Ni silicide is formed through simple steps. After forming a semiconductor film over a substrate, a Ni film is deposited over the semiconductor film while heating the substrate, thereby forming Ni suicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, a Ni film is deposited over the semiconductor film while heating the substrate up to 450° C. or higher, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, a Ni film is deposited with a thickness of 10 nm or more over the semiconductor film while heating the substrate to 450° C. or higher, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, and removing an oxide film on the semiconductor film, a Ni film is deposited over the semiconductor film while heating the substrate up to 450° C. or higher, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, and removing an oxide film on the semiconductor film, a Ni film is deposited with a thickness of 10 nm or more over the semiconductor film while heating the substrate up to 450° C. or higher, thereby forming Ni silicide on the semiconductor film. | 11-19-2009 |
20100003799 | METHOD FOR FORMING P-TYPE LIGHTLY DOPED DRAIN REGION USING GERMANIUM PRE-AMORPHOUS TREATMENT - A method for forming a MOS device with an ultra shallow lightly doped diffusion region. The method includes providing a semiconductor substrate including a surface region. The method provides a gate dielectric layer overlying the surface region and forms a gate structure overlying a portion of the gate dielectric layer. The method includes performing a first implant process using a germanium species to form an amorphous region within a lightly doped drain region in the semiconductor substrate using the gate structure as a mask. In a specific embodiment, the method includes performing a second implant process in the lightly doped drain region using a P type impurity and a carbon species using the gate structure as a mask. The method includes performing a first thermal process to activate the P type impurity in the lightly doped drain region. The method includes forming side wall spacers overlying a portion of the gate structure and performing a third implant process using a first impurity to form active source/drain regions in a vicinity of the surface region of the semiconductor substrate adjacent to the gate structure using the gate structure and the side wall spacer as a masking layer. The method then performs a second thermal process to activate the first impurity in the active source/drain regions. | 01-07-2010 |
20100041201 | Methods of Fabricating MOS Transistors Having Recesses with Elevated Source/Drain Regions - Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques. | 02-18-2010 |
20100144110 | Method of forming a MOS transistor - A method of forming a MOS transistor, in which, a co-implantation is performed to implant a carbon co-implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect, and the carbon co-implant is from a precursor comprising CO or CO | 06-10-2010 |
20100151650 | METHOD FOR MANUFACTURING A POWER SEMICONDUCTOR DEVICE - A method of manufacturing a power semiconductor device is provided. A first oxide layer is produced on a first main side of a substrate of a first conductivity type. A structured gate electrode layer with at least one opening is then formed on the first main side on top of the first oxide layer. A first dopant of the first conductivity type is implanted into the substrate on the first main side using the structured gate electrode layer as a mask, and the first dopant is diffused into the substrate. A second dopant of a second conductivity type is then implanted into the substrate on the first main side, and the second dopant is diffused into the substrate. After diffusing the first dopant into the substrate and before implanting the second dopant into the substrate, the first oxide layer is partially removed. The structured gate electrode layer can be used as a mask for implanting the second dopant. | 06-17-2010 |
20100167487 | MASK ROM DEVICES AND METHODS FOR FORMING THE SAME - A mask read only memory (MROM) device includes first and second gate electrodes formed at on-cell and off-cell regions of a substrate, respectively. A first impurity region is formed at the on-cell region of the substrate so as to be adjacent the first gate electrode. A second impurity region including the same conductivity type as that of the first impurity region is formed at the off-cell region of the substrate so as to be spaced apart from a sidewall of the second gate electrode. A fourth impurity region is formed at the off-cell region to extend from the second impurity region and to overlap with the sidewall of the second gate electrode. The fourth impurity region has a conductivity type opposite to that of the second impurity region and a depth greater than that of the second impurity region. | 07-01-2010 |
20100197103 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device can include forming gate structures for transistors on a semiconductor substrate in a cell region and in a peripheral circuit region, forming an offset spacer of a first material on the gate structure, performing first ion implantation for source/drain region formation using the gate structures and the offset spacer as an ion implantation mask, forming a material layer of a second material on the semiconductor substrate and the gate structures, forming a material layer of a third material, which has an etch selectivity with respect to the second material, on the material layer made of the second material, etching-back the material layer made of the third material using the material layer made of the second material as an etch stop layer to form a multi-layered spacer comprising the second material and the third material, performing second ion implantation for source/drain region formation using the gate structures and the multi-layered spacer as an ion implantation mask, and removing the material layer of the third material. | 08-05-2010 |
20100203698 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate. | 08-12-2010 |
20100248441 | MULTI-BIT HIGH-DENSITY MEMORY DEVICE AND ARCHITECTURE AND METHOD OF FABRICATING MULTI-BIT HIGH-DENSITY MEMORY DEVICES - A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins. | 09-30-2010 |
20100279480 | METHOD OF MAKING SMALL GEOMETRY FEATURES - A method of forming a small geometry feature. The method includes forming a source layer on a top surface of a substrate; forming a mandrel on a top surface of the source layer, the mandrel having a sidewall; sputtering material from the source layer onto the sidewall of the mandrel to form a sidewall layer on the sidewall of the mandrel; and removing the mandrel. Also methods to forming wires and field effect transistors of integrated circuits. | 11-04-2010 |
20100291746 | Shared contact structure, semiconductor device and method of fabricating the semiconductor device - A shared contact structure, semiconductor device and method of fabricating the semiconductor device, in which the shared contact structure may include a gate electrode disposed on an active region of a substrate and including facing first and second sidewalls. The first sidewall may be covered with an insulating spacer. The source/drain regions may be formed within the active region adjacent the first sidewall, and provided on the opposite side of the second sidewall. A corner protection pattern may be formed adjacent the source/drain regions and the insulating spacer, and covered by an inter-layer dielectric. A shared contact plug may be formed through the inter-layer dielectric, to be in contact with the gate electrode, corner protection pattern and source/drain regions. | 11-18-2010 |
20100317170 | METHOD FOR IMPROVING THE THERMAL STABILITY OF SILICIDE - An embodiment of the invention is a method of making a transistor by performing an ion implant on a gate electrode layer | 12-16-2010 |
20110033999 | DOPING METHOD, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A doping method includes: a first step of depositing a material solution containing an antimony compound containing elements selected from the group consisting essentially of hydrogen, nitrogen, oxygen, and carbon together with antimony to a surface of a substrate; a second step of drying the material solution to form an antimony compound layer on the substrate; and a third step of performing heat treatment so that antimony in the antimony compound layer is diffused into the substrate. | 02-10-2011 |
20110034000 | SELECTIVE DEPOSITION OF GERMANIUM SPACERS ON NITRIDE - A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface. | 02-10-2011 |
20110039390 | Reducing Local Mismatch of Devices Using Cryo-Implantation - A method of forming an integrated circuit includes providing a semiconductor wafer, and forming a metal-oxide-semiconductor (MOS) device. The step of forming the MOS device includes forming a gate stack on the semiconductor wafer, and performing a cryo-implantation to form an implantation region adjacent the gate stack at a wafer temperature lower than 0° C. The step of performing the cryo-implantation is selected from the group consisting essentially of implanting the semiconductor wafer to form a pre-amorphized implantation (PAI) region; implanting the semiconductor wafer to form a lightly-doped source/drain region; implanting the semiconductor wafer to form a pocket/halo region; implanting the semiconductor wafer to form a deep source/drain region, and combinations thereof | 02-17-2011 |
20110065250 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Ni silicide is formed through simple steps. After forming a semiconductor film over a substrate, a Ni film is deposited over the semiconductor film while heating the substrate, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, a Ni film is deposited over the semiconductor film while heating the substrate up to 450° C. or higher, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, a Ni film is deposited with a thickness of 10 nm or more over the semiconductor film while heating the substrate to 450° C. or higher, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, and removing an oxide film on the semiconductor film, a Ni film is deposited over the semiconductor film while heating the substrate up to 450° C. or higher, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, and removing an oxide film on the semiconductor film, a Ni film is deposited with a thickness of 10 nm or more over the semiconductor film while heating the substrate up to 450° C. or higher, thereby forming Ni silicide on the semiconductor film. | 03-17-2011 |
20110104864 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed. | 05-05-2011 |
20110111571 | METHOD FOR OBTAINING QUALITY ULTRA-SHALLOW DOPED REGIONS AND DEVICE HAVING SAME - A method of forming ultra-shallow p-type lightly doped drain (LDD) regions of a PMOS transistor in a surface of a substrate includes the steps of providing a gaseous mixture of an inert gas, a boron-containing source, and an optional carbon-containing source, wherein the concentration of the gaseous mixture is at least 99.5% dilute with the inert gas and the optional carbon-containing source, if present, forming the gaseous mixture into a plasma, and forming the LDD regions, wherein the forming step includes plasma-doping the boron into the substrate using the plasma. N-type pocket regions are formed in the substrate underneath and adjacent to the LDD regions, wherein for a PMOS transistor having a threshold voltage of 100 mV, the n-type pocket regions include phosphorous impurities at a dopant concentration of less than 6.0×10 | 05-12-2011 |
20110124173 | Method of Manufacturing Semiconductor Device - Methods of manufacturing a semiconductor device include forming a gate electrode on a semiconductor substrate, forming spacers on side walls of the gate electrode, and doping impurities into the semiconductor substrate on both sides of the spacers to form highly doped impurity regions. The spacers are selectively etched to expose portions of the semiconductor substrate, and more lightly doped impurity regions are formed in the semiconductor substrate between the highly doped impurity regions and the gate electrode. | 05-26-2011 |
20110129979 | Method of Manufacturing a Semiconductor Device Having Improved Transistor Performance - In one aspect provides a method of manufacturing a semiconductor device having improved transistor performance. In one aspect, this improvement is achieved by conducting a pre-deposition spacer deposition process wherein a temperature of a bottom region of a furnace is higher than a temperature of in the top region and is maintained for a predetermined period. The pre-deposition temperature is changed to a deposition temperature, wherein a temperature of the bottom region is lower than a temperature of the top region. | 06-02-2011 |
20110129980 | CAP REMOVAL IN A HIGH-K METAL GATE ELECTRODE STRUCTURE BY USING A SACRIFICIAL FILL MATERIAL - Dielectric cap layers of sophisticated high-k metal gate electrode structures may be efficiently removed on the basis of a sacrificial fill material, thereby reliably preserving integrity of a protective sidewall spacer structure, which in turn may result in superior uniformity of the threshold voltage of the transistors. The sacrificial fill material may be provided in the form of an organic material that may be reduced in thickness on the basis of a wet developing process, thereby enabling a high degree of process controllability. | 06-02-2011 |
20110143512 | METHOD FOR DUAL ENERGY IMPLANTATION FOR ULTRA-SHALLOW JUNCTION FORMATION OF MOS DEVICES - A method for forming a lightly doped drain (LDD) region in a semiconductor substrate. The method includes generating an ion beam of a selected species, and accelerating the ion beam, wherein the accelerated ion beam includes a first accelerated portion and a second accelerated portion. The method further includes deflecting the accelerating ion beam, wherein the first and second accelerated portions are concurrently deflected into a first path trajectory having a first deflected angle and second path trajectory having a second deflected angle. In an embodiment, the first and second path trajectories travel in the same direction, which is perpendicular to the surface region of the semiconductor wafer, and the first deflected angle is greater than the second deflected angle. In an embodiment, the selected species may include an n-type ion comprising phosphorous (P), arsenic (As), or antimony (Sb). | 06-16-2011 |
20110159658 | METHOD FOR FABRICATING METAL-OXIDE SEMICONDUCTOR TRANSISTORS - A method for fabricating a metal-oxide semiconductor transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a first ion implantation process to implant a first molecular cluster having carbon, boron, and hydrogen into the semiconductor substrate at two sides of the gate structure for forming a doped region, wherein the molecular weight of the first molecular cluster is greater than 100. | 06-30-2011 |
20110195556 | POWER MOSFET WITH A GATE STRUCTURE OF DIFFERENT MATERIAL - A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage. | 08-11-2011 |
20110207282 | Methods for Producing a Tunnel Field-Effect Transistor - A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods. | 08-25-2011 |
20110223736 | LDD Epitaxy for FinFETs - A method of forming a semiconductor structure includes providing a substrate including a fin at a surface of the substrate, and forming a fin field-effect transistor (FinFET), which further includes forming a gate stack on the fin; forming a thin spacer on a sidewall of the gate stack; and epitaxially growing a epitaxy region starting from the fin. After the step of epitaxially growing the epitaxy region, a main spacer is formed on an outer edge of the thin spacer. After the step of forming the main spacer, a deep source/drain implantation is performed to form a deep source/drain region for the FinFET. | 09-15-2011 |
20110269286 | HEAVILY DOPED REGION IN DOUBLE-DIFFUSED SOURCE MOSFET (LDMOS) TRANSISTOR AND A METHOD OF FABRICATING THE SAME - A transistor includes a source, a drain and a gate. The source includes a p-doped p-body, a p+ region overlapping the p-body, an n+ region overlapping the p-body in proximity to the p+ region, and an n-doped source, heavily double-diffused (SHDD) region, only into the source region of the transistor, the SHDD region having a depth about equal to that of the first n+ region and overlapping the first n+ region. The drain includes a second n+ region and an n-doped shallow drain overlapping the second n+ region. The gate includes a gate oxide and a conductive material over the gate oxide. The SHDD region extends further laterally than the first n+ region beneath the gate oxide. The SHDD region is implanted using a dopant concentration greater than that of the n-doped shallow drain but less than that of the first n+ region. | 11-03-2011 |
20120003806 | METHOD OF FABRICATING AN INTEGRATED CIRCUIT DEVICE - A method for fabricating an integrated device is disclosed. A sacrificial gate stack is provided with a line width narrower than the target width of the final gate structure. After performing a tilt-angle implantation process, L-shape spacers are formed over the sidewalls of the sacrificial gate stack, and offset spacers are formed over the sidewalls of the L-shape spacers. An insulating layer is formed over the offset spacers and the substrate. Then, the sacrificial gate stack and the L-shape spacers are removed to form a trench in the insulating layer. A metal gate is then filled in the trench to form the final gate structure. | 01-05-2012 |
20120094461 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR - First gate electrodes of memory cell transistors are formed in series with each other on a semiconductor substrate. A second gate electrode of a first selection transistor is formed adjacent to one end of the first electrodes. A third gate electrode of a second selection transistor is formed adjacent to the second electrode. A fourth gate electrode of a peripheral transistor is formed on the substrate. First, second, and third sidewall films are formed on side surfaces of the second, third, and fourth gate electrodes, respectively. A film thickness of the third sidewall film is larger than that of the first and second sidewall films. A space between the first electrode and the second electrode is larger than a space between the first electrodes, and a space between the second electrode and the third electrode is larger than a space between the first electrode and the second electrode. | 04-19-2012 |
20120171834 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration. | 07-05-2012 |
20120190163 | METHOD FOR MAKING DUAL SILICIDE AND GERMANIDE SEMICONDUCTORS - A method for making a dual silicide or germanide semiconductor comprises steps of providing a semiconductor substrate, forming a gate, forming source/drain regions, forming a first silicide, reducing spacers thickness and forming a second silicide. Forming a gate comprises forming an insulating layer over the semiconductor substrate, and forming the gate over the insulating layer. Forming source/drain regions comprises forming lightly doped source/drain regions in the semiconductor substrate adjacent to the insulating layer, forming spacers adjacent to the gate and over part of the lightly doped source/drain regions, and forming heavily doped source/drain regions in the semiconductor substrate. The first silicide is formed on an exposed surface of lightly and heavily doped source/drain regions. The second silicide is formed on an exposed surface of lightly doped source/drain regions. A first germanide and second germanide may replace the first silicide and the second silicide. | 07-26-2012 |
20120196422 | Stress Memorization Technique Using Gate Encapsulation - Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein a stress memorization technique is used to enhance the performance of MOS transistor elements. One illustrative embodiment includes a method for forming a gate electrode above a channel region of a semiconductor device, wherein the channel region is formed in an active region of a semiconductor substrate. The method further includes forming a dielectric encapsulating layer in direct contact with the gate electrode, and performing a heat treatment process to induce a residual stress in the channel region. | 08-02-2012 |
20120214287 | SEMICONDUCTOR DEVICE - A semiconductor device includes a silicon substrate having a protrusion, a gate insulating film formed over an upper surface of the protrusion of the silicon substrate, a gate electrode formed over the gate insulating film, a source/drain region formed in the silicon substrate on the side of the gate electrode, a first side wall formed over the side surface of the protrusion of the silicon substrate, the first side wall containing an insulating material. a second side wall formed over the first side wall, the second side wall having a bottom portion formed below the upper surface of the protrusion of the silicon substrate, the second side wall containing a material having a Young's modulus greater than that of the silicon substrate, and a stress film formed over the gate electrode and the second side wall. | 08-23-2012 |
20130109145 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 05-02-2013 |
20130137236 | Tunnel Field-Effect Transistor with Narrow Band-Gap Channel and Strong Gate Coupling - A semiconductor device and the methods of forming the same are provided. The semiconductor device includes a low energy band-gap layer comprising a semiconductor material; a gate dielectric on the low energy band-gap layer; a gate electrode over the gate dielectric; a first source/drain region adjacent the gate dielectric, wherein the first source/drain region is of a first conductivity type; and a second source/drain region adjacent the gate dielectric. The second source/drain region is of a second conductivity type opposite the first conductivity type. The low energy band-gap layer is located between the first and the second source/drain regions. | 05-30-2013 |
20130230960 | STRUCTURE FABRICATION METHOD - A structure fabrication method. A provided structure includes a gate dielectric region on the substrate and a gate electrode region on the gate dielectric region. Atoms are implanted in a top portion of the gate electrode region, which expands the top portion of the gate electrode in a direction parallel to a top surface of the gate dielectric region. After the atom implantation, a conformal dielectric layer is formed on top and side walls of the gate electrode region. A dielectric spacer layer, formed on the conformal dielectric layer, is etched such that only spacer portions of the dielectric spacer layer which are under the conformal dielectric layer remain, wherein for any point of the remaining spacer portions, a straight line through that point and parallel to a reference direction intersects the conformal dielectric layer. The reference direction is perpendicular to the top surface of the gate dielectric region. | 09-05-2013 |
20130302964 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include a first insulating layer disposed on a substrate, a gate electrode disposed on the first insulating layer, and a second insulating layer disposed on the gate electrode and the first insulating layer. The second insulating layer includes a first discharge site. | 11-14-2013 |
20130323900 | Strained MOS Device and Methods for Forming the Same - A semiconductor structure includes a semiconductor substrate having a top surface; a gate stack on the semiconductor substrate; and a stressor in the semiconductor substrate and adjacent the gate stack. The stressor comprises at least a first portion with a first top surface lower than the top surface of the semiconductor substrate. | 12-05-2013 |
20140099767 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes. | 04-10-2014 |
20140170827 | Tunneling Field Effect Transistor (TFET) Formed By Asymmetric Ion Implantation and Method of Making Same - An embodiment integrated circuit device and a method of making the same. The embodiment method includes forming a first nitride layer over a gate stack supported by a substrate, implanting germanium ions in the first nitride layer in a direction forming an acute angle with a top surface of the substrate, etching away germanium-implanted portions of the first nitride layer to form a first asymmetric nitride spacer confined to a first side of the gate stack, the first asymmetric nitride spacer protecting a first source/drain region of the substrate from a first ion implantation, and implanting ions in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain. | 06-19-2014 |
20140170828 | PLASMA DOPING METHOD AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A doping method that forms a doped region at a desired location of a three-dimensional (3D) conductive structure, controls the doping depth and doping dose of the doped region relatively easily, has a shallow doping depth, and prevents a floating body effect. A semiconductor device is fabricated using the same doping method. The method includes, forming a conductive structure having a sidewall, exposing a portion of the sidewall of the conductive structure, and forming a doped region in the exposed portion of the sidewall by performing a plasma doping process. | 06-19-2014 |
20140187013 | Methods for Forming FinFETs Having Multiple Threshold Voltages - A method includes forming a first and a second gate stack to cover a first and a second middle portion of a first and a second semiconductor fin, respectively, and performing implantations to implant exposed portions of the first and the second semiconductor fins to form a first and a second n-type doped region, respectively. A portion of each of the first and the second middle portions is protected from the implantations. The first n-type doped region and the second n-type doped region have different gate proximities from edges of the first gate stack and the second stack, respectively. The first and the second n-type doped regions are etched using chlorine radicals to form a first and a second recess, respectively. An epitaxy is performed to re-grow a first semiconductor region and a second semiconductor region in the first recess and the second recess, respectively. | 07-03-2014 |
20140199818 | METHOD FOR FABRICATING AN ESD PROTECTION DEVICE - A method for fabricating an ESD protection device . Agate electrode of a core device is formed in a non I/O region and a gate electrode of an ESD protection device is formed in a I/O region. A first photoresist film masks the I/O region and reveals the non I/O region. The first photoresist film includes at least an opening adjacent to the gate electrode of the ESD protection device in the I/O region. A core pocket implantation process using the first photoresist film as an implant mask is performed to implant dopants of a second conductivity type into the I/O region through the opening and into the non I/O region, thereby forming a core pocket doping region in the I/O region and core pocket doping regions in the non I/O region. | 07-17-2014 |
20140370682 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Extension regions | 12-18-2014 |
20150017777 | METHOD OF FABRICATING MOS DEVICE - Provided is a method of fabricating a MOS device including the following steps. A gate structure is formed on a substrate and a first spacer is formed at a sidewall of the gate structure. A first implant process is performed to form source and drain extension regions in the substrate. A spacer material layer is formed on the gate structure, the first spacer and the substrate. A treatment process is performed so that stress form the spacer material layer is applied onto and memorized in a channel between two source and drain extension regions. An anisotropic process is performed to remove a portion of the spacer material so that a second spacer is formed. A second implant process is performed to form source and drain regions in the substrate. | 01-15-2015 |
20150087129 | Method for Producing Semiconductor Regions Including Impurities - A method for producing semiconductor regions including impurities includes forming a trench in a first surface of a semiconductor body. Impurity atoms are implanted into a bottom of the trench. The trench is extended deeper into the semiconductor body, thereby forming a deeper trench. Impurity atoms are implanted into a bottom of the deeper trench. | 03-26-2015 |
20150364570 | STRESS MEMORIZATION TECHNIQUES FOR TRANSISTOR DEVICES - One illustrative method disclosed herein includes, among other things, performing a source/drain extension ion implantation to form a doped extension implant region in the source/drain regions of the device, performing an ion implantation process on the source/drain regions with a Group VII material (e.g., fluorine), after performing the Group VII material ion implantation process, forming a capping material layer above the source/drain regions, and, with the capping material layer in position, performing an anneal process so as to form stacking faults in the source/drain regions. | 12-17-2015 |
20160133718 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is a semiconductor device. Two stack layers are disposed on a substrate of a first conductivity type. Each of stack layers includes a dielectric layer and a conductive layer. The dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. First doped region of a second conductivity type has a first dopant and is disposed in the substrate between the stack layers. A pre-amorphization implantation (PAI) region is disposed in the first doped region. A second doped region of the second conductivity type has a second dopant and is disposed in the PAI region. The first conductivity type is different from the second conductivity type. A diffusion rate of the second dopant is faster than a diffusion rate of the first dopant, and a thermal activation of the second dopant is higher than that of the first dopant. | 05-12-2016 |
20160380074 | METHOD OF FORMING FIELD EFFECT TRANSISTORS (FETS) WITH ABRUPT JUNCTIONS AND INTEGRATED CIRCUIT CHIPS WITH THE FETS - A method of forming field effect transistors (FETs) and on Integrated Circuit (IC) chips with the FETs. Channel placeholders at FET locations are undercut at each end of FET channels. Source/drain regions adjacent to each channel placeholder extend into and fill the undercut. The channel placeholder is opened to expose channel surface under each channel placeholder. Source/drain extensions are formed under each channel placeholder, adjacent to each source/drain region. After removing the channel placeholders metal gates are formed over each said FET channel. | 12-29-2016 |