Inventors list

Assignees list

Classification tree browser

Top 100 Inventors

Top 100 Assignees


Self-aligned

Subclass of:

438 - Semiconductor device manufacturing: process

438142000 - MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS

438197000 - Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.)

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
438301000 Source or drain doping 238
438300000 Having elevated source or drain (e.g., epitaxially formed source or drain, etc.) 55
Entries
DocumentTitleDate
20130078779METAL GATE DEVICE WITH LOW TEMPERATURE OXYGEN SCAVENGING - A semiconductor device with a metal gate is disclosed. The device includes a semiconductor substrate, source and drain features on the semiconductor substrate, and a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes an interfacial layer (IL) layer, a high-k (HK) dielectric layer formed over the semiconductor substrate, an oxygen scavenging metal formed on top of the HK dielectric layer, a scaling equivalent oxide thickness (EOT) formed by using a low temperature oxygen scavenging technique, and a stack of metals gate layers deposited over the oxygen scavenging metal layer.03-28-2013
20130040435METHOD FOR MANUFACTURING TRANSISTOR AND SEMICONDUCTOR DEVICE - A method for manufacturing a transistor and a semiconductor device is provided. The method for manufacturing a transistor may comprise: defining an active area on a semiconductor substrate, and forming on the active area a gate stack or a dummy gate stack, a source/drain extension region, a spacer and a source/drain region, wherein the source/drain extension region is embedded in the active area and self-aligned on both sides of the gate stack or dummy gate stack, the spacer surrounds the gate stack or dummy gate stack, and the source/drain region is embedded in the active area and self-aligned outside the spacer; removing at least a portion of the spacer to expose a portion of the active area; and forming an interlayer dielectric layer which covers the gate stack or dummy gate stack, the spacer and the exposed active area, wherein the dielectric constant of the material of the interlayer dielectric layer is smaller than that of the removed material of the spacer. It is beneficial for reducing the capacitance between the gate region and the source/drain region as well as between the gate region and the contact plug.02-14-2013
20130034943Tri-Gate Field-Effect Transistors Formed by Aspect Ration Trapping - Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach02-07-2013
20100105184METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device which includes forming a gate insulating film and a gate electrode over a semiconductor substrate, forming a first recess in the first semiconductor substrate on both sides of the gate electrode by dry etching, forming a second recess by removing a bottom and sidewalls of the first recess by wet etching, and forming a semiconductor layer in the second recess.04-29-2010
20130089962SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate is provided. A gate structure is formed on the substrate. A spacer is formed on the substrate beside the gate structure. The spacer includes a first spacer and a second spacer located on the external surface of the first spacer. A first etching process is performed to etch and form at least a recess in the substrate beside the spacer and entirely remove the second spacer. The etching rate of the first etching process to the first spacer is lower than the etching rate of the first etching process to the second spacer. An epitaxial layer is formed in the recess.04-11-2013
20130071977METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING GATE TO ACTIVE AND GATE TO GATE INTERCONNECTS - Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes processing the IC in a replacement gate technology including forming dummy gates, sidewall spacers on the dummy gates, and metal silicide contacts to active areas. A fill layer is deposited and planarized to expose the dummy gates and the dummy gates are removed. A mask is formed having an opening overlying a portion of the channel region from which the dummy gate was removed and a portion of an adjacent metal silicide contact. The fill layer and a portion of the sidewall spacers exposed through the mask opening are etched to expose a portion of the adjacent metal silicide contact. A gate electrode material is deposited overlying the channel region and exposed metal silicide contact and is planarized to form a gate electrode and a gate-to-metal silicide contact interconnect.03-21-2013
20100099231NOISE REDUCTION IN SEMICONDUCTOR DEVICE USING COUNTER-DOPING - One or more embodiments describe a method of fabricating a silicon based metal oxide semiconductor device, including introducing a first dopant into a first partial completion of the device, the first dopant including a first noise reducing species; and introducing a second dopant into a second partial completion of the device, the second dopant and the first dopant being opposite conductivity types.04-22-2010
20130164899SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A highly reliable semiconductor device in which a transistor including an oxide semiconductor film has stable electric characteristics is manufactured. In the semiconductor device which includes an inverted-staggered transistor having a bottom-gate structure and being provided over a substrate having an insulating surface, at least a first gate insulating film and a second gate insulating film are provided between a gate electrode layer and an oxide semiconductor film, and heat treatment is performed at a temperature of 450° C. or higher, preferably 650° C. or higher, and then the oxide semiconductor film is formed. By the heat treatment at a temperature of 450° C. or higher before the formation of the oxide semiconductor film, diffusion of hydrogen elements into the oxide semiconductor film, which causes degradation or variations in electric characteristics of the transistor, can be reduced, so that the transistor can have stable electric characteristics.06-27-2013
20130164900GATED CO-PLANAR POLY-SILICON THIN FILM DIODE - A diode has a first contact of a material having a first conductivity type, a second contact of a material having a second conductivity type arranged co-planarly with the first contact, a channel arranged co-planarly between the first and second contacts, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A diode has a layer of material arranged on a substrate, a first region of material doped to have a first conductivity type, a second region of material doped to have a second conductivity type, a channel between the first and second regions formed of an undoped region, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A method includes forming a layer of material on a substrate, forming a first region of a first conductivity in the material, forming a second region of a second conductivity in the material, arranged so as to provide a channel region between the first and second regions, the channel region remaining undoped, depositing a layer of gate dielectric on the layer of material, arranging a gate adjacent the channel region on the gate dielectric, and electrically connecting a voltage source to the gate.06-27-2013
20110059589METHOD FOR PRODUCING A FIELD EFFECT DEVICE HAVING SELF-ALIGNED ELECTRICAL CONNECTIONS WITH RESPECT TO THE GATE ELECTRODE - A gate dielectric, an insulating layer and and an etching mask are formed on a substrate. The etching mask delineates at least the gate electrode and the source and drain contacts and the source, drain and gate output lines of the first metal level of a field effect device. The gate electrode and the future source and drain contacts are formed simultaneously by etching of the insulating layer. A gate material is deposited to form the gate electrode. The source and drain contacts are formed at least in the insulating layer. The source, drain and gate output lines of the first metal level are formed in the etching mask.03-10-2011
20090269899Semiconductor integrated circuit device with reduced leakage current - The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.10-29-2009
20120115298METHOD OF FABRICATING GATE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer.05-10-2012
20120135577METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device, including the second sacrificial layer receiving a gate structure include a metal and a spacer on a sidewall of the gate structure therethrough being formed on a substrate. The second sacrificial layer is removed. A second etch stop layer and an insulating interlayer are sequentially formed on the gate structure, the spacer and the substrate. An opening passing through the insulating interlayer is formed to expose a portion of the gate structure, a portion of the spacer and a portion of the second etch stop layer on a portion of the substrate. The second etch stop layer being exposed through the opening is removed. The contact being electrically connected to the gate structure and the substrate and filling the opening is formed. The semiconductor device having the metal gate electrode and the shared contact has a desired leakage current characteristic and resistivity characteristics.05-31-2012
20110281413CONTACT HOLE, SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - The invention provides a method for forming a contact hole, comprising: forming a gate, a sidewall spacer, a sacrificial sidewall spacer, a source region and a drain region on a substrate, wherein the sidewall spacer is formed around the gate, the sacrificial sidewall spacer is formed over the sidewall spacer, and the source region and the drain region are formed within the substrate and on respective sides of the gate; forming an interlayer dielectric layer, with the gate, the sidewall spacer and the sacrificial sidewall spacer being exposed; removing the sacrificial sidewall spacer to form a contact space, a material that the sacrificial sidewall spacer is made of being different from any of materials that the gate, the sidewall spacer and the interlayer dielectric layer are made of; forming a conducting layer to fill the contact space; and cutting off the conducting layer, to form at least two conductors connected to the source region and the drain region respectively. The invention also provides a contact hole, the contact hole a gate and a sidewall spacer being formed on a substrate and within an interlayer dielectric layer, wherein the sides of the contact hole meet the sidewall spacer. The invention also provides a semiconductor device and a method for forming the same. With the technical solutions provided by the invention, the number of masks used can be reduced.11-17-2011
20110143510METHOD OF CONTROLLING GATE THICKNESS IN FORMING FINFET DEVICES - A method of forming a FinFET device is provided. In one embodiment, a fin is formed on a substrate. A gate structure is formed over the fin, the gate structure having a dielectric layer and a conformal first polysilicon layer formed above the dielectric layer. An etch stop layer is formed above the first polysilicon layer and thereafter a second polysilicon layer is formed above the etch stop layer. The second polysilicon layer and the etch stop layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed and source and drain regions are formed on opposite sides of the fin.06-16-2011
20120108024FIELD EFFECT TRANSISTOR HAVING NANOSTRUCTURE CHANNEL - A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure.05-03-2012
20120108025METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device which includes forming a gate insulating film and a gate electrode over a semiconductor substrate, forming a first recess in the first semiconductor substrate on both sides of the gate electrode by dry etching, forming a second recess by removing a bottom and sidewalls of the first recess by wet etching, and forming a semiconductor layer in the second recess.05-03-2012
20110287600Selective Etching in the Formation of Epitaxy Regions in MOS Devices - A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. After the step of performing the selective epitaxial growth, a selective etch-back is performed to the epitaxy region. The selective etch-back is performed using process gases comprising a first gas for growing the semiconductor material, and a second gas for etching the epitaxy region.11-24-2011
20110294274METHOD OF FORMING METAL GATE STRUCTURE AND METHOD OF FORMING METAL GATE TRANSISTOR - A method of forming metal gate transistor includes providing a substrate; forming a gate dielectric layer, a work function metal layer and a polysilicon layer stacked on the substrate; forming a hard mask and a patterned photoresist on the polysilicon layer; removing the patterned photoresist, and next utilizing the hard mask as an etching mask to remove parts of the polysilicon layer and parts of the work function metal layer. Thus, a gate stack is formed. Since the patterned photoresist is removed before forming the gate stack, the gate stack is protected from damages of the photoresist-removing process. The photoresist-removing process does not attack the sidewalls of the gate stack, so a bird's beak effect of the gate dielectric layer is prevent.12-01-2011
20100035399Method of forming self-aligned low resistance contact layer - Embodiments of the present invention describe a method of fabricating low resistance contact layers on a semiconductor device. The semiconductor device comprises a substrate having source and drain regions. The substrate is alternatingly exposed to a first precursor and a second precursor to selectively deposit an amorphous semiconductor layer onto each of the source and drain regions. A metal layer is then deposited over the amorphous semiconductor layer on each of the source and drain regions. An annealing process is then performed on the substrate to allow the metal layer to react with amorphous semiconductor layer to form a low resistance contact layer on each of the source and drain regions. The low resistance contact layer on each of the source and drain regions can be formed as either a silicide layer or germanide layer depending on the type of precursors used.02-11-2010
20120190162SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a gate electrode over a semiconductor substrate, a channel region provided in the semiconductor substrate below the gate electrode, and a strain generation layer configured to apply stress to the channel region, the strain generation layer being configured to apply greater stress in absolute value to the source edge of the channel region than to the drain edge of the channel region.07-26-2012
20100081245METHODS FOR FABRICATING MOS DEVICES HAVING HIGHLY STRESSED CHANNELS - Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, etching recesses into the substrate using the gate electrode as an etch mask, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.04-01-2010
20110171803INTEGRATED MEMORY DEVICE HAVING COLUMNS HAVING MULTIPLE BIT LINES - A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions.07-14-2011
20120289015METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH ENHANCED CHANNEL STRESS - A method for fabricating a semiconductor device with enhanced channel stress is provided. The method includes the following steps. Firstly, a substrate is provided. Then, at least one source/drain region and a channel are formed in the substrate. A dummy gate is formed over the channel. A contact structure is formed over the source/drain region. After the contact structure is formed, the dummy gate is removed to form a trench.11-15-2012
20120289016LOCALIZED COMPRESSIVE STRAINED SEMICONDUCTOR - One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline semiconductor bridge is formed over a substrate. The bridge has a first portion bonded to the substrate, a second portion bonded to the substrate, and a middle portion between the first and second portions separated from the substrate. The middle portion of the bridge is bonded to the substrate to provide a compressed crystalline semiconductor layer on the substrate. Other aspects are provided herein.11-15-2012
20080242037Semiconductor device having self-aligned epitaxial source and drain extensions - A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack, wherein the dopant increases the etch rate of the substrate and defines the location of the source and drain extensions, forming a pair of spacers on laterally opposite sides of the gate stack that are disposed atop the doped regions of the substrate, etching the doped regions of the substrate and portions of the substrate subjacent to the doped regions, wherein an etch rate of the doped regions is higher than an etch rate of the portions of the substrate subjacent to the doped regions, and depositing a silicon-based material in the etched portions of the substrate.10-02-2008
20120142158Self-Aligned Nanotube Field Effect Transistor and Method of Fabricating Same - A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.06-07-2012
20110223735Reducing Resistance in Source and Drain Regions of FinFETs - A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.09-15-2011
20130217198LOCALIZED IMPLANT INTO ACTIVE REGION FOR ENHANCED STRESS - Methods for enhancing strain in an integrated circuit are provided. Embodiments of the invention include using a localized implant into an active region prior to a gate etch. In another embodiment, source/drain regions adjacent to the gates are recessed to allow the strain to expand to full potential. New source/drain regions are allowed to grow back to maximize stress in the active region.08-22-2013
20100197099SCHOTTKY BARRIER FiNFET DEVICE AND FABRICATION METHOD THEREOF - A Schottky barrier FinFET device and a method of fabricating the same are provided. The device includes a lower fin body provided on a substrate. An upper fin body having first and second sidewalls which extend upwardly from a center of the lower fin body and face each other is provided. A gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls is provided. The Schottky barrier FinFET device includes a source and a drain which are formed on the sidewalls of the upper fin body adjacent to sidewalls of the gate structure and made of a metal material layer formed on an upper surface of the lower fin body positioned at both sides of the upper fin body, and the source and drain form a Schottky barrier to the lower and upper fin bodies.08-05-2010
20120196420Methods of Forming Silicide Regions and Resulting MOS Devises - A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.08-02-2012
20120142157Method of fabricating a semiconductor structure - The method of fabricating a semiconductor structure according to the present invention includes planarizing an inter-layer dielectric layer and further a hard mask to remove a portion of hard mask in a thickness direction. The remaining hard mask has a thickness less than the original thickness of the hard mask. The remaining hard mask and the dummy gate are removed to form a recess. After a gate material is filled into the recess, a gate with a relatively accurate height can be obtained.06-07-2012
20100221887Oxygen-Rich Layers Underlying BPSG - An integrated circuit structure and a method of forming the same are provided. The method includes providing a surface; performing an ionized oxygen treatment to the surface; forming an initial layer comprising silicon oxide using first process gases comprising a first oxygen-containing gas and tetraethoxysilane (TEOS); and forming a silicate glass over the initial layer. The method may further include forming a buffer layer using second process gases comprising a second oxygen-containing gas and TEOS, wherein the first and the second process gases have different oxygen-to-TEOS ratio.09-02-2010
20090148995Processes for manufacturing MOSFET devices with excessive round-hole shielded gate trench (SGT) - This invention discloses an improved method for manufacturing a trenched metal oxide semiconductor field effect transistor (MOSFET) device. The method includes a step of opening a trench in substrate and covering trench walls of the trench with a linen layer followed by removing a portion of the linen layer from a bottom portion of the trench. The method further includes a step of opening a round hole by applying an isotropic substrate etch on the bottom portion of the trench with the round hole extending laterally from the trench walls. The method further includes a step of filling the trench and the round hole at the bottom of the trench with a gate material followed by applying a time etch to removed the gate material from a top portion of the trench whereby the gate material only filling the round hole up to a lateral expansion point of the round hole.06-11-2009
20080268600MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS - A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide.10-30-2008
20100304542ENHANCED ETCH STOP CAPABILITY DURING PATTERNING OF SILICON NITRIDE INCLUDING LAYER STACKS BY PROVIDING A CHEMICALLY FORMED OXIDE LAYER DURING SEMICONDUCTOR PROCESSING - A gate electrode structure may be formed on the basis of a silicon nitride cap material in combination with a very thin yet uniform silicon oxide based etch stop material, which may be formed on the basis of a chemically driven oxidation process. Due to the reduced thickness, a pronounced material erosion, for instance, during a wet chemical cleaning process after gate patterning, may be avoided, thereby not unduly affecting the further processing, for instance with respect to forming an embedded strain-inducing semiconductor alloy, while nevertheless providing the desired etch stop capabilities during removing the silicon nitride cap material.12-02-2010
20100304543SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME - A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped with dopants and a metal germanosilicide layer disposed on the source/drain pattern. The metal germanosilicide layer is electrically connected to the source/drain pattern. Moreover, a proportion of germanium amount to the sum of the germanium amount and silicon amount in the metal germanosilicide layer is lower than that of germanium amount to the sum of the germanium amount and silicon amount in the source/drain pattern.12-02-2010
20090068809SEMICONDUCTOR MEMORY DEVICE HAVING LOCAL ETCH STOPPER AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.03-12-2009
20100197100Semiconductor Devices and Methods of Manufacturing Thereof - Semiconductor devices and methods of manufacturing thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a recess in the workpiece. The recess has a depth having a first dimension. A first semiconductive material is formed in the recess to partially fill the recess in a central region to a height having a second dimension. The second dimension is about one-half or greater of the first dimension. A second semiconductive material is formed over the first semiconductive material in the recess to completely fill the recess, the second semiconductive material being different than the first semiconductive material.08-05-2010
20120244674METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device includes providing a semiconductor substrate including a channel region, forming a gate electrode structure on the channel region of the semiconductor substrate, forming a first trench in the semiconductor substrate, and forming a second trench in the semiconductor device. The first trench may include a first tip that protrudes toward the channel. The second trench may be an enlargement of the first trench and may include a second tip that also protrudes toward the channel region. In some examples, the second tip may protrude further towards the channel region than the first tip.09-27-2012
20110076823METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for making a semiconductor MOS device is provided. A gate structure is formed on a substrate. A source and a drain are formed in the substrate on both sides of the gate structure. The substrate is then subjected to a pre-amorphization implant (PAI) process. A transitional stress layer is then formed on the substrate. Thereafter, a laser anneal with a first temperature is performed. After the laser anneal, a rapid thermal process is performed with a second temperature that is lower than the first temperature. Subsequently, the transitional stress layer is removed.03-31-2011
20080254586SOI SEMICONDUCTOR DEVICE WITH BODY CONTACT AND METHOD THEREOF - A method including providing a substrate and providing an insulating layer overlying the substrate is provided. The method further includes providing a body region comprising a body material overlying the insulating layer. The method further includes forming at least one transistor overlying the insulating layer, the at least one transistor having a source, a drain and a gate with a sidewall spacer, the sidewall spacer comprising a substantially uniform geometric shape around the gate, the gate overlying the body region. The method further includes forming a first silicide region within the source and a second silicide region within the drain, the first silicide region having a differing geometric shape than the second silicide region and being electrically conductive between the body region and the source.10-16-2008
20110053329Semiconductor device including a gate electrode of lower electrial resistance and method of manufacturing the same - A semiconductor device may include a gate insulating layer on a semiconductor substrate, a polysilicon layer doped with impurities on the gate insulating layer, an interface reaction preventing layer on the polysilicon layer, a barrier layer on the interface reaction preventing layer, and a conductive metal layer on the barrier layer. The interface reaction preventing layer may reduce or prevent the occurrence of a chemical interfacial reaction with the barrier layer, and the barrier layer may reduce or prevent the diffusion of impurities doped to the polysilicon layer. The interface reaction preventing layer may include a metal-rich metal silicide having a metal mole fraction greater than a silicon mole fraction, so that the interface reaction preventing layer may reduce or prevent the dissociation of the barrier layer at higher temperatures. Thus, a barrier characteristic of a poly-metal gate electrode may be improved and surface agglomerations may be reduced or prevented.03-03-2011
20110136314SYSTEMS AND METHODS FOR REDUCING CONTACT TO GATE SHORTS - A method for reducing contact to gate shorts in a semiconductor device and the resulting semiconductor device are described. In one embodiment, a gate is formed on a substrate, a contact is formed on the gate and the substrate, and an insulator is formed between the gate and the contact. The insulator may be formed by oxidizing the gate to form a dielectric between the contact and the gate after the contact is formed on the gate.06-09-2011
20110136313Methods of Forming CMOS Transistors with High Conductivity Gate Electrodes - Provided is a method for manufacturing a MOS transistor. The method comprises providing a substrate having a first active region and a second active region; forming a dummy gate stack on the first active region and the second active region, the dummy gate stack comprising a gate dielectric layer and a dummy gate electrode; forming source/drain regions in the first active region and the second active region disposed at both sides of the dummy gate stack; forming a mold insulating layer on the source/drain region; removing the dummy gate electrode on the first active region to form a first trench on the mold insulating layer; forming a first metal pattern to form a second trench at a lower portion of the first trench, and removing the dummy gate electrode on the second active region to from a third trench on the mold insulating layer; and forming a second metal layer in the second trench and the third trench to form a first gate electrode on the first active region and a second gate electrode on the second active region.06-09-2011
20090203181Semiconductor device manufacturing method, wiring and semiconductor device - In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.08-13-2009
20120309156METHOD FOR MANUFACTURING A SEMICONDUCTOR MEMORY DEVICE - A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.12-06-2012
20120309157SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.12-06-2012
20090104746CHANNEL STRAIN INDUCED BY STRAINED METAL IN FET SOURCE OR DRAIN - A process for forming a FET (e.g., an n-FET or a p-FET), in which during formation a metal which makes up a source or drain of the transistor is stressed so that stress is induced in a semiconductor channel of the transistor.04-23-2009
20120028430METHOD AND STRUCTURE TO IMPROVE FORMATION OF SILICIDE - A method begins with a structure having: a gate insulator on a silicon substrate between a gate conductor and a channel region within the substrate; insulating sidewall spacers on sidewalls of the gate conductor; and source and drain regions within the substrate adjacent the channel region. To silicide the gate and source and drain regions, the method deposits a metallic material over the substrate, the gate conductor, and the sidewalls, and performs a first heating process to change the metallic material into a metal-rich silicide at locations where the metallic material contacts silicon. The method removes the sidewall spacers, and performs a second heating process to change the metal-rich silicide into silicide having a lower metallic concentration than the metal-rich silicide. The silicide thus formed avoids being damaged by the spacer removal process.02-02-2012
20120164808METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening.06-28-2012
20120220096PLASMA DOPING METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A plasma doping method capable of introducing impurities into an object to be processed uniformly is supplied. Plasma of a diborane gas containing boron, which is a p-type impurity, and an argon gas, which is a rare gas, is generated, and no bias potential is applied to a silicon substrate. Thereby, the boron radicals in the plasma are deposited on the surface of the silicon substrate. After that, the supply of the diborane gas is stopped, and bias potential is applied to the silicon substrate. Thereby, the argon ions in the plasma are radiated onto the surface of the silicon substrate. The radiated argon ions collide with the boron radicals, and thereby boron radicals are introduced into the silicon substrate. The introduced boron radicals are activated by thermal processing, and thereby a p-type impurity diffusion layer is formed in the silicon substrate.08-30-2012
20120135576METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided are a semiconductor device and a method of fabricating a semiconductor device. The method includes providing a substrate having a channel region; forming a gate structure, which comprises a dummy gate pattern, on the substrate; forming first and second trenches by recessing the substrate on both sides of the gate structure, respectively; forming a first semiconductor pattern in the first and second trenches; removing the dummy gate pattern to expose a portion of the channel region; forming a recessed channel region by recessing the portion of the channel region; and forming a second semiconductor pattern in the recessed region.05-31-2012
20100173465SEMICONDUCTOR DEVICE HAVING SILICIDE TRANSISTORS AND NON-SILICIDE TRANSISTORS FORMED ON THE SAME SUBSTRATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first MIS transistor of a non-salicide structure and a second MIS transistor of a salicide structure which are both formed on a substrate of silicon. The first MIS transistor includes a first gate electrode of silicon, first sidewalls, a first source and drain, and plasma reaction films grown in a plasma atmosphere to cover the top surfaces of the first gate electrode and first source and drain, wherein the plasma reaction film prevents silicide formation on the first MIS transistor.07-08-2010
20120252180MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - There is a problem with a CMIS semiconductor integrated circuit using a High-k Gate insulation film that, in a device region having a short channel length and a narrow channel width, with an increase of the film thickness of an Interfacial Layer IL between the High-k Gate insulation film and a silicon-based substrate by activation annealing of source/drain regions, the absolute value of the threshold voltage increases.10-04-2012
20110124170PROCESS FOR FABRICATING A SELF-ALIGNED DEPOSITED SOURCE/DRAIN INSULATED GATE FIELD-EFFECT TRANSISTOR - Processes for forming self-aligned, deposited source/drain, insulated gate, transistors and, in particular, FETs. By depositing a source/drain in a recess such that it remains only in the recess, the source/drain can be formed self-aligned to a gate and/or a channel of such a device. For example, in one such process a gate structure of a transistor may be formed and, in a material surrounding the gate structure, a recess created so as to be aligned to an edge of the gate structure. Subsequently, a source/drain conducting material may be deposited in the recess. Such a source/drain conducting material may be deposited, in some cases, as layers, with one or more such layers being planarized following its deposition. In this way, the conducting material is kept within the boundaries of the recess.05-26-2011
20110124169METHODS OF SELECTIVELY DEPOSITING AN EPITAXIAL LAYER - Methods for selectively depositing an epitaxial layer are provided herein. In some embodiments, providing a substrate having a monocrystalline first surface and a non-monocrystalline second surface; exposing the substrate to a deposition gas to deposit a layer on the first and second surfaces, the layer comprising a first portion deposited on the first surfaces and a second portion deposited on the second surfaces; and exposing the substrate to an etching gas comprising a first gas comprising hydrogen and a halogen and a second gas comprising at least one of a Group III, IV, or V element to selectively etch the first portion of the layer at a slower rate than the second portion of the layer. In some embodiments, the etching gas comprises hydrogen chloride (HCl) and germane (GeH05-26-2011
20120231600SEMICONDUCTOR PROCESS HAVING DIELECTRIC LAYER INCLUDING METAL OXIDE AND MOS TRANSISTOR PROCESS - A semiconductor process having a dielectric layer including metal oxide is provided. The semiconductor process includes: A substrate is provided. A dielectric layer including metal oxide is formed on the substrate, wherein the dielectric layer has a plurality of oxygen-related vacancies. A first oxygen-importing process is performed to fill the oxygen-related vacancies with oxygen. Otherwise, three MOS transistor processes are also provided, each of which has a gate dielectric layer including a high dielectric constant, and a first oxygen-importing process is performed to fill the oxygen-related vacancies with oxygen.09-13-2012
20080299733METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING AN IMPLANTATION OF IONS IN A MATERIAL LAYER TO BE ETCHED - A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature having a side surface and a top surface is formed over the substrate. A material layer is formed over the substrate. The material layer covers at least the side surface of the feature. An ion implantation process is performed to create an ion-implanted portion in the material layer. An etch process adapted to remove the ion-implanted portion at a greater etch rate than other portions of the material layer is performed.12-04-2008
20120094459Semiconductor Devices Including Compressive Stress Patterns and Methods of Fabricating the Same - Provided is a method of fabricating a semiconductor device. Gate patterns are formed on a substrate including an NMOS transistor region and a PMOS transistor region. A spacer structure is formed on sidewalls of the gate patterns. The substrate in the PMOS transistor region is etched using the gate patterns and the spacer structure as etching masks, and thereby a recessed region is formed. A compressive stress pattern is formed in the recessed region, and a sidewall of the compressive stress pattern protrudes upwardly from an upper surface of the substrate. A mask oxide layer is formed on a sidewall of the spacer structure. The mask oxide layer is formed to cover a portion of the sidewall of the compressive stress pattern that protrudes upwardly from the upper surface of the substrate.04-19-2012
20120100685LOCALIZED IMPLANT INTO ACTIVE REGION FOR ENHANCED STRESS - Methods for enhancing strain in an integrated circuit are provided. Embodiments of the invention include using a localized implant into an active region prior to a gate etch. In another embodiment, source/drain regions adjacent to the gates are recessed to allow the strain to expand to full potential. New source/drain regions are allowed to grow back to maximize stress in the active region.04-26-2012
20100167485Contact Barrier Structure and Manufacturing Methods - A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.07-01-2010
20130017660SELF-ALIGNED SOURCE AND DRAIN STRUCTURES AND METHOD OF MANUFACTURING SAMEAANM Fang; ZiweiAACI Baoshan TownshipAACO TWAAGP Fang; Ziwei Baoshan Township TWAANM Zhang; YingAACI Hsinchu CityAACO TWAAGP Zhang; Ying Hsinchu City TWAANM Xu; Jeff J.AACI Jhubei CityAACO TWAAGP Xu; Jeff J. Jhubei City TW - An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. In an example, the method includes forming a gate structure over a substrate; forming a doped region in the substrate; performing a first etching process to remove the doped region and form a trench in the substrate; and performing a second etching process that modifies the trench by removing portions of the substrate.01-17-2013
20080233701Methods of Forming Integrated Circuit Devices Including a Depletion Barrier Layer at Source/Drain Regions - Integrated circuit devices include an integrated circuit substrate having a channel region therein. A gate pattern is disposed on a top surface of the channel region. A depletion barrier layer covers a surface of the integrated circuit substrate adjacent opposite sides of the gate pattern and extending along a portion of a lateral face of the channel region. A source/drain layer is disposed on the depletion barrier layer and electrically contacting the lateral face of the channel region in a region not covered by the depletion barrier layer. The channel region may protrude from a surface of the substrate. The depletion barrier layer may be an L-shaped depletion barrier layer and the device may further include a device isolation layer disposed at a predetermined portion of the substrate through the source/drain layer and the depletion barrier layer. The depletion barrier layer and the device isolation layer may be formed of the same material.09-25-2008
20130178033SELF-ALIGNED CONTACTS - A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.07-11-2013
20130095628MASK ROM FABRICATION METHOD - A mask ROM fabrication method which comprises steps: sequentially forming a gate dielectric layer and a first photoresist layer on a substrate; letting a light having a wavelength of 365 nm pass through a first phase shift mask to photolithographically form on the first photoresist layer a plurality of first trenches having a width of 243-365 nm; doping the substrate to form a plurality of embedded bit lines having a width of 243-365 nm; removing the first photoresist layer; sequentially forming a polysilicon layer and a second photoresist layer on the gate dielectric layer; and letting the light pass through a second phase shift mask to photolithographically form a plurality of polysilicon word lines on the polysilicon layer. Thereby is reduced the line width of mask ROM to 243-365 nm and decreased the area of mask ROM.04-18-2013
20130130460SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device comprises steps as follows: A first dummy gate having a first high-k gate insulator layer, a first composite sacrificial layer, and a first dummy gate electrode sequentially stacked on a substrate is firstly provided. The first dummy gate electrode is subsequently removed to expose the first composite sacrificial layer. The first composite sacrificial layer is then removed. Thereafter, a first work function layer is formed on the first high-k gate insulator layer, and a first metal gate electrode is formed on the first work function layer.05-23-2013
20130157431STRUCTURE AND METHOD FOR THERMAL TREATMENT WITH EPITAXIAL SICP THERMAL STABILITY IMPROVEMENT - The present disclosure provides a method for making an integrated circuit in one embodiment. The method includes providing a semiconductor substrate having an active region and a first gate stack disposed on the semiconductor substrate in the active region; forming in-situ phosphorous-doped silicon carbide (SiCP) features on the semiconductor substrate and disposed on sides of the first gate stack; replacing the first gate stack with a second gate stack having a high k dielectric material layer; and thereafter performing a millisecond annealing (MSA) process with a thermal profile having a first thermal wavelet and a second thermal wavelet.06-20-2013
20130157432ENHANCING INTEGRITY OF A HIGH-K GATE STACK BY PROTECTING A LINER AT THE GATE BOTTOM DURING GATE HEAD EXPOSURE - Sophisticated gate stacks including a high-k dielectric material and a metal-containing electrode material may be covered by a protection liner, such as a silicon nitride liner, which may be maintained throughout the entire manufacturing sequence at the bottom of the gate stacks. For this purpose, a mask material may be applied prior to removing cap materials and spacer layers that may be used for encapsulating the gate stacks during the selective epitaxial growth of a strain-inducing semiconductor alloy. Consequently, enhanced integrity may be maintained throughout the entire manufacturing sequence, while at the same time one or more lithography processes may be avoided.06-20-2013
20120021582METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: forming a lower electrode layer in contact with a surface of a nitride semiconductor layer; forming an Al layer on the lower electrode layer; performing a heat treatment after the formation of the Al layer; removing the Al layer after the heat treatment is performed; and forming an upper electrode layer on the lower electrode layer after the removal of the Al layer.01-26-2012
20120295412METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises: providing a substrate having an active area and a gate structure on the active area and formed with a first interlayer dielectric layer thereon, wherein the first interlayer dielectric layer has a first open to expose a portion of a surface of the active area, and an upper surface of the first interlayer dielectric layer is substantially flush with an upper surface of the gate; filling the first open with a first conductive material to form a first portion of contact; forming a second interlayer dielectric layer over the first interlayer dielectric layer, the second interlayer dielectric layer having a second open to substantially expose an upper part of the first portion of the contact in the first open; and filling the second open with a second conductive material to form a second portion of the contact.11-22-2012
20130203231SELECTIVE ETCH CHEMISTRY FOR GATE ELECTRODE MATERIALS - A chemical solution including an aqueous solution, an oxidizing agent, and a pH stabilizer selected from quaternary ammonium salts and quaternary ammonium alkali can be employed to remove metallic materials in cavities for forming a semiconductor device. For example, metallic materials in gate cavities for forming a replacement gate structure can be removed by the chemical solution of the present disclosure with, or without, selectivity among multiple metallic materials such as work function materials. The chemical solution of the present disclosure provides different selectivity among metallic materials than known etchants in the art.08-08-2013
20120077321METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Reliability of a semiconductor element and its product yield are improved by reducing variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)03-29-2012
20130095629Finfet Parasitic Capacitance Reduction Using Air Gap - Methods are disclosed to fabricate a transistor, for example a FinFET, by forming over a substrate at least one electrically conductive channel between a source region and a drain region; forming a gate structure to be disposed over a portion of the channel, the gate structure having a width and a length and a height defining two opposing sidewalls of the gate structure and being formed such that the channel said passes through the sidewalls; forming spacers on the sidewalls; forming a layer of epitaxial silicon over the channel; removing the spacers; and forming a dielectric layer to be disposed over the gate structure and portions of the channel that are external to the gate structure such that a capacitance-reducing air gap underlies the dielectric layer and is disposed adjacent to the sidewalls of said gate structure in a region formerly occupied by the spacers.04-18-2013
20120094460METHOD FOR FABRICATING MOS TRANSISTORS - A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate. Next, the spacer is thinned, and epitaxial layer is grown in each of the two recesses. By thinning the spacer before the epitaxial layer is formed, the present invention could stop the epitaxial layer to grow against the sidewall of the spacer, thereby preventing problem such as Ion degradation.04-19-2012

Patent applications in class Self-aligned

Patent applications in all subclasses Self-aligned