Class / Patent application number | Description | Number of patent applications / Date published |
438297000 | Recessed oxide formed by localized oxidation (i.e., LOCOS) | 7 |
20080242036 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device, includes: a) forming a first semiconductor layer on a semiconductor substrate; b) forming a second semiconductor layer on the first semiconductor layer; c) sequentially etching a part of the second semiconductor layer and a part of the first semiconductor layer so as to form a first groove exposing the first semiconductor layer; d) forming a cavity between the semiconductor substrate and the second semiconductor layer by etching the first semiconductor layer through the first groove under an etching condition in which the first semiconductor layer is more easily etched than the second semiconductor layer; e) forming an embedded oxide film in the cavity; f) etching the embedded oxide film from a lateral surface side thereof so as to form a gap between a peripheral part of the second semiconductor layer and the semiconductor substrate; and g) forming an insulating etching stopper layer in the gap. | 10-02-2008 |
20080293206 | UNIQUE LDMOS PROCESS INTEGRATION - Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 90 or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors. | 11-27-2008 |
20110201169 | Thermal Treatment Equipment and Method for Heat-Treating - The invention provides a method for activating impurity element added to a semiconductor and performing gettering process in shirt time, and a thermal treatment equipment enabling to perform such the heat-treating. The thermal treatment equipment comprises treatment rooms of n pieces (n>2) performing heat-treating, a preparatory heating room, and a cooling room, and heating a substrate using gas heated by heating units of n pieces as a heating source, wherein a gas-supplying unit is connected to a gas charge port of the cooling room, a discharge port of the cooling room is connected to a first gas-heating unit through a heat exchanger, a charge port of an m-th (1≦m≦(n−1)) treatment room is connected to a discharge port of an m-th gas-heating unit, a charge port of an n-th treatment room is connected to a discharge port of an n-th gas-heating unit, a discharge port of the n-th treatment room is connected to the heat exchanger, and discharge port of the heat exchanger is connected to gas charge port of the preparatory heating room. | 08-18-2011 |
20120302027 | Method for Fabricating Silicon Nanowire Field Effect Transistor Based on Wet Etching - Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching. The method includes defining an active region; depositing a silicon oxide film as a hard mask, forming a pattern of a source and a drain and a fine bar connecting the source and the drain; transferring the pattern on the hard mask to a silicon substrate by performing etching process for the silicon substrate; performing ion implanting; etching the silicon substrate by wet etching, so that the silicon fine bar connecting the source and the drain is suspended; reducing the silicon fine bar to a nano size to form a silicon nanowire; depositing a polysilicon film; forming a polysilicon gate line acrossing the silicon nanowire by electron beam lithography and forming a structure of nanowire-all-around; forming a silicon oxide sidewall at both sides of the polysilicon gate line, by depositing a silicon oxide film and subsequently etching the silicon oxide film; forming the source and the drain by using ion implantation and high temperature annealing, so that the silicon nanowire field effect transistor is finally fabricated. The method is compatible with a conventional integrated circuit fabrication technology. The fabrication process is simple and convenient, and has a short cycle. | 11-29-2012 |
20150044843 | SEMICONDUCTOR FIN ON LOCAL OXIDE - A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins. The first semiconductor material can be selected from materials more easily oxidized relative to the second semiconductor material to provide a uniform height for the semiconductor fins after formation of the localized oxide layer. | 02-12-2015 |
20150140767 | PROCESS FOR MANUFACTURING DEVICES FOR POWER APPLICATIONS IN INTEGRATED CIRCUITS - A MOS transistor for power applications is formed in a substrate of semiconductor material by a method integrated in a process for manufacturing integrated circuits which uses an STI technique for forming insulating regions. The method includes the phases of forming an insulating element on a top surface of the substrate and forming a control electrode on a free surface of the insulating element. The insulating element insulates the control electrode from the substrate. The insulating element includes a first portion and a second portion. The extension of the first portion along a first direction perpendicular to the top surface is lower than the extension of the second portion along such first direction. The phase of forming the insulating element includes generating the second portion by locally oxidizing the top surface. | 05-21-2015 |
20160141389 | Radiation Hardened MOS Devices and Methods of Fabrication - Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a Bird's Beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the Bird's Beak region and terminating at the inner edge of the Bird's Beak region, a gate included in the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the Bird's Beak and guard regions. A variation of minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density. | 05-19-2016 |