Class / Patent application number | Description | Number of patent applications / Date published |
438289000 | Doping of semiconductive channel region beneath gate insulator (e.g., adjusting threshold voltage, etc.) | 69 |
20080299732 | METHOD FOR REDUCING OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS - A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations along the width of the gate conductor. | 12-04-2008 |
20080311716 | METHODS FOR FORMING FIELD EFFECT TRANSISTORS AND EPI-SUBSTRATE - A semiconductor method includes thermally treating at least a portion of a substrate so as to generate a plurality of vacancies in a region at a depth substantially near to a surface of the substrate. The substrate is then quenched so as to substantially maintain the vacancies in the region substantially near to the surface of the substrate. | 12-18-2008 |
20090081842 | PROCESS FOR ATOMIC LAYER DEPOSITION - The present invention relates to a process of making thin film electronic components and devices, such as thin film transistors, environmental barrier layers, capacitors, insulators and bus lines, where most or all of the layers are made by an atmospheric atomic layer deposition process. | 03-26-2009 |
20090170269 | HIGH VOLTAGE MOSFET DEVICES CONTAINING TIP COMPENSATION IMPLANT - Semiconductor devices and methods for making semiconductor devices are described in this application. The semiconductor devices comprise a MOSFET device in a semiconductor substrate, with the MOSFET device containing source and drain regions with a tip implant region near the surface of the substrate. The tip implant region contains a tip compensation implant region located under the gate of the MOSFET device that overlaps with the source and drain. The tip compensation implant region reduces the dopant concentration in this gate-drain overlap region, while maintaining a graded drain-well junction profile, thereby reducing the band to band tunneling and increasing the drain breakdown voltage. Other embodiments are described. | 07-02-2009 |
20100120215 | Nitrogen Based Implants for Defect Reduction in Strained Silicon - A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer. | 05-13-2010 |
20100151647 | MOS DEVICE RESISTANT TO IONIZING RADIATION - An embodiment of a MOS device resistant to ionizing-radiation, has: a surface semiconductor layer with a first type of conductivity; a gate structure formed above the surface semiconductor layer, and constituted by a dielectric gate region and a gate-electrode region overlying the dielectric gate region; and body regions having a second type of conductivity, formed within the surface semiconductor layer, laterally and partially underneath the gate structure. In particular, the dielectric gate region is formed by a central region having a first thickness, and by side regions having a second thickness, smaller than the first thickness; the central region overlying an intercell region of the surface semiconductor layer, set between the body regions. | 06-17-2010 |
20100167483 | METHOD FOR FABRICATING PMOS TRANSISTOR - A method for fabricating a PMOS transistor is disclosed herein. In one embodiment, the method can include forming a gate insulation layer and a polysilicon layer over a semiconductor substrate; asymmetrically etching the polysilicon layer; doping the asymmetrically etched polysilicon layer with a P-type dopant; diffusing the dopant in the asymmetrically etched polysilicon layer towards the semiconductor substrate; planarizing the asymmetrically etched polysilicon layer; forming a gate metal layer over the planarized polysilicon layer; forming a hard mask, which delimits a region to be formed with a gate of the PMOS transistor, over the gate metal layer; forming a gate stack by patterning the gate metal layer, the planarized polysilicon layer, and the gate insulation layer; and forming a source/drain in the semiconductor substrate at both sides of the gate stack. | 07-01-2010 |
20100297822 | Methods of forming capacitor structures, methods of forming threshold voltage implant regions, and methods of implanting dopant into channel regions - The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location. | 11-25-2010 |
20110020995 | Nonvolatile semiconductor memory and method of manufacturing the same - A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer. | 01-27-2011 |
20110039387 | Fully Isolated High-Voltage MOS Device - A semiconductor structure includes a semiconductor substrate; an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate; a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate; and a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub. | 02-17-2011 |
20110065249 | Method of manufacturing a semiconductor device in which an increase in area of the semiconductor device is suppressed - A method of manufacturing a semiconductor device includes: performing, in a case of manufacturing a first semiconductor device which operates by a first power supply voltage, at least one step from among channel ion implantation, gate oxide film formation, and gate electrode patterning according to a process of forming an element which operates with the first power supply voltage; performing, in a case of manufacturing a second semiconductor device which operates by a second power supply voltage, at least one step from among the channel ion implantation, the gate oxide film formation, and the gate electrode patterning according to a process of forming an element which operates with the second power supply voltage; and commonly performing at least diffusion region formation in the case of manufacturing the first semiconductor device and in the case of manufacturing the second semiconductor device. | 03-17-2011 |
20110076822 | LATERAL METAL OXIDE SEMICONDUCTOR DRAIN EXTENSION DESIGN - A semiconductor device | 03-31-2011 |
20110129977 | PLASMA DOPING METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A plasma doping method capable of introducing impurities into an object to be processed uniformly is supplied. Plasma of a diborane gas containing boron, which is a p-type impurity, and an argon gas, which is a rare gas, is generated, and no bias potential is applied to a silicon substrate. Thereby, the boron radicals in the plasma are deposited on the surface of the silicon substrate. After that, the supply of the diborane gas is stopped, and bias potential is applied to the silicon substrate. Thereby, the argon ions in the plasma are radiated onto the surface of the silicon substrate. The radiated argon ions collide with the boron radicals, and thereby boron radicals are introduced into the silicon substrate. The introduced boron radicals are activated by thermal processing, and thereby a p-type impurity diffusion layer is formed in the silicon substrate. | 06-02-2011 |
20110195553 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. The method comprises: forming a first layer; forming a P-well on the first layer; forming an isolation region in the P-well; performing an extra implantation on a surface between the P-well and the first layer; and forming a source/drain region. The method of the present invention can solve the punch through problem of the conventional iso-NMOS transistor without increasing cost. | 08-11-2011 |
20110269284 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHODS FOR THEM - The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film. On this account, on fabricating the semiconductor device having a high-performance integration system by forming the non-singlecrystalline Si semiconductor element and the singlecrystalline Si semiconductor element on the large insulating substrate, the process for making the singlecrystalline Si is simplified. Further, the foregoing arrangement provides a semiconductor substrate and a fabrication method thereof, which ensures device isolation of the minute singlecrystalline Si semiconductor element without highly-accurate photolithography, when the singlecrystalline Si semiconductor element is transferred onto the large insulating substrate. | 11-03-2011 |
20120009751 | REDUCING CONTAMINATION IN A PROCESS FLOW OF FORMING A CHANNEL SEMICONDUCTOR ALLOY IN A SEMICONDUCTOR DEVICE - In sophisticated approaches for forming high-k metal gate electrode structures in an early manufacturing stage, a threshold adjusting semiconductor alloy may be deposited on the basis of a selective epitaxial growth process without affecting the back side of the substrates. Consequently, any negative effects, such as contamination of substrates and process tools, reduced surface quality of the back side and the like, may be suppressed or reduced by providing a mask material and preserving the material at least during the selective epitaxial growth process. | 01-12-2012 |
20120034745 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICES WITH REDUCED JUNCTION DIFFUSION - A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling. | 02-09-2012 |
20120083087 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A protection film is formed on a semiconductor substrate. Impurity ions are implanted into the semiconductor substrate through the protection film. The impurity is activated to form an impurity layer. The protection film is removed after forming the impurity layer. The semiconductor substrate of a surface portion of the impurity layer is removed after removing the protection film. A semiconductor layer is epitaxially grown above the semiconductor substrate after removing the semiconductor substrate of the surface portion of the impurity layer. | 04-05-2012 |
20120135575 | METHODS OF FORMING INTEGRATED CIRCUITS - A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A dopant-rich layer having first type dopants is formed on a sidewall and a bottom of each of the recesses. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has second type dopants. The second type dopants are opposite to the first type dopants. | 05-31-2012 |
20120149162 | METHOD FOR MANUFACTURING SUSPENDED FIN AND GATE-ALL-AROUND FIELD EFFECT TRANSISTOR - The present application discloses a method for manufacturing a gate-all-around field effect transistor, comprising the steps of forming a suspended fin in a semiconductor substrate; forming a gate stack around the fin; and forming source/drain regions in the fin on both sides of the gate stack, wherein an isolation dielectric layer is formed in a portion of the semiconductor substrate which is adjacent to bottom of both the fin and the gate stack. The present invention relates to a method for manufacturing a gate-all-around device on a bulk silicon substrate, which suppress a self-heating effect and a floating-body effect of the SOI substrate, and lower a manufacture cost. The inventive method is a conventional top-down process with respect to a reference plane, which can be implemented as a simple manufacture process, and is easy to be integrated into and compatible with a planar CMOS process. The inventive method suppresses a short channel effect and promotes miniaturization of MOSFETs. | 06-14-2012 |
20120231599 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing semiconductor devices includes forming a plurality of patterns spaced apart from each other on a semiconductor substrate, forming a filling layer, not removed in a subsequent process of forming a mask pattern and where the filling layer formed to have a lower height than the plurality of patterns, between the plurality of patterns, forming a mask layer on the entire structure where the filling layer is formed, and forming the mask pattern by removing some of the mask layer so that some of the plurality of patterns is removed. | 09-13-2012 |
20120264268 | METHODS OF FORMING ELECTRICAL ISOLATION REGIONS BETWEEN GATE ELECTRODES - Methods of forming nonvolatile memory devices include forming first and second floating gate electrodes of first and second nonvolatile memory cells, respectively, at side-by-side locations on a substrate. The substrate is selectively etched to define a trench therein extending between the first and second floating gate electrodes. The trench is at least partially filled with a first electrical insulation pattern. An inorganic polysilazane-type spin-on-glass (SOG) layer is conformally deposited on the first and second floating gate electrodes and on the first electrical insulation pattern and then partially removed. | 10-18-2012 |
20120276704 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device includes a substrate where an active region is defined by an isolation layer, a gate electrode simultaneously crossing both the isolation layer and the active region, and a junction region formed in the active region at both sides of the gate electrode and separated from the isolation layer by a certain distance in a direction where the gate electrode is extended. The electrostatic discharge protection device is able to prevent the increase of a leakage current while securing an electrostatic discharge protection property that a semiconductor device requires. | 11-01-2012 |
20130040433 | Semiconductor Structures Employing Strained Material Layers with Defined Impurity Gradients and Methods for Fabricating Same - Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced. | 02-14-2013 |
20130130458 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided. The method includes forming a gate pattern on a semiconductor substrate, performing a C ion implantation process for suppressing diffusion of dopants in the semiconductor substrate, and performing a halo ion implantation process including P ions. Therefore, a hot carrier effect due to change of a dopant profile and degradation caused by GIDL can be improved. | 05-23-2013 |
20130137234 | METHODS FOR FORMING SEMICONDUCTOR DEVICES - Methods are provided for forming semiconductor devices. One method includes etching trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. Dummy gate structures are formed, which includes a first dummy gate structure, that overlie and are transverse to the fins. A back fill material is filled between the dummy gate structures. The first dummy gate structure and an upper portion of the insulating material are removed to expose an active fins portion of the fins. The active fins portion is dimensionally modified to form an altered active fins portion. A high-k dielectric material and a work function determining gate electrode material are deposited overlying the altered active fins portion. | 05-30-2013 |
20130164898 | CARRIER MOBILITY IN SURFACE-CHANNEL TRANSISTORS, APPARATUS MADE THEREWITH, AND SYSTEM CONTAINING SAME - A surface channel transistor is provided in a semiconductive device. The surface channel transistor is either a PMOS or an NMOS device. Epitaxial layers are disposed above the surface channel transistor to cause an increased bandgap phenomenon nearer the surface of the device. A process of forming the surface channel transistor includes grading the epitaxial layers. | 06-27-2013 |
20130178032 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a first gate electrode on a semiconductor substrate in a first transistor region; forming a channel dose region; and forming a first source extension region, wherein the channel dose region is formed by using a first mask as a mask and by ion-implanting a first dopant of the first conductivity type, and the first mask covering a drain side of the first gate electrode and covering a drain region, and the first source extension region is formed by using a second mask and the gate electrode as masks and by ion-implanting a second dopant of a second conductivity type that is a conductivity type opposite to the first conductivity type, the second mask covering the drain side of the first gate electrode and covering the drain region. | 07-11-2013 |
20130224926 | PENETRATING IMPLANT FOR FORMING A SEMICONDUCTOR DEVICE - A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack. | 08-29-2013 |
20130309831 | Method of Manufacturing a Semiconductor Device - A method of manufacturing a semiconductor device, which comprises: providing a semiconductor substrate; forming a dummy gate structure and a spacer surrounding the dummy gate structure on the semiconductor substrate; forming source/drain regions on both sides of the gate structure within the semiconductor substrate using the dummy gate structure and the spacer as a mask; forming an interlayer dielectric layer on the upper surface of the semiconductor substrate, the upper surface of the interlayer dielectric layer being flush with the upper surface of the dummy gate structure; removing at least a part of the dummy gate structure so as to form a trench surrounded by the spacer; performing tilt angle ion implantation into the semiconductor substrate using the interlayer dielectric layer and spacer as a mask so as to form an asymmetric Halo implantation region; sequentially forming a gate dielectric layer and a metal gate in the trench. The present invention prevents the Halo implanted ions from entering into the source/drain regions, thus reducing the source/drain junction capacitance; and the asymmetric Halo implantation region can reduce the static power dissipation of the semiconductor device. | 11-21-2013 |
20130316509 | Semiconductor Device Manufacturing Method - The present invention provides a manufacturing method for a semiconductor device having epitaxial source/drain regions, in which a diffusion barrier layer of the source/drain regions made of epitaxial silicon-carbon or germanium silicon-carbon are added on the basis of epitaxially growing germanium-silicon of the source/drain regions in the prior art process, and the introduction of the diffusion barrier layer of the source/drain regions prevents diffusion of the dopant in the source/drain regions, thus mitigating the SCE and DIBL effect. The use of the diffusion barrier layer for the source/drain regions can also reduce the dosage of HALO implantation in the subsequent step, thus if HALO is performed before epitaxial growth of the source/drain regions, impact on the surfaces of the source/drain regions can be alleviated; if HALO is performed after epitaxial growth of the source/drain regions, the stress release effect of the epitaxial layer of the source drain/regions caused by the implantation can be reduced as much as possible. | 11-28-2013 |
20140187008 | HIGH TILT ANGLE PLUS TWIST DRAIN EXTENSION IMPLANT FOR CHC LIFETIME IMPROVEMENT - An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor. | 07-03-2014 |
20140220755 | Semiconductor Structures Employing Strained Material Layers with Defined Impurity Gradients and Methods for Fabricating Same - Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced. | 08-07-2014 |
20140242769 | METHOD OF MANUFACTURING A SUPER-JUNCITON SEMICONDUCTOR DEVICE - A method of manufacturing a super-junction semiconductor device is disclosed that allows forming a high concentration layer with high precision and improves the trade-off relationship between the Eoff and the dV/dt using a trench embedding method. The method comprises a step of forming a parallel pn layer using a trench embedding method and a step of forming a proton irradiated layer in the upper region of the pn layer. Then, heat treatment is conducted on the proton irradiated layer for transforming the protons into donors to form a high concentration n type semiconductor layer. Forming the high concentration n type semiconductor layer by means of proton irradiation allows forming a high concentration n type semiconductor layer with an impurity concentration and thickness with high precision as compared with forming the layer by means of an epitaxial growth process. | 08-28-2014 |
20140302656 | Method of Forming Ultra Shallow Junction - The present invention discloses a method of forming ultra shallow junction, wherein the method includes the following steps: (1) providing a grid side wall etched semiconductor structure; (2) after the implantation of the nitrogen source ion into the said semiconductor structures, implanting the boron ions into the said structure of semiconductor by lightly doped drain (LDD) process; (3) forming an ultra shallow junction on the semiconductor structure by continuous processes of the heavily doped ions implantation and the anneal. The new source of N28 was introduced into this invention. N28 can reduce the diffusion of boron atom in the silicon substrate, and it can not interact with silicon atom to form the covalent bond. Hence, it overcomes problem of the aggravation of polysilicon gate depletion layer when carbon assisted ion implantation. Meanwhile, an ultra shallow junction is formed by simple process. | 10-09-2014 |
20140322882 | METHODS OF FORMING FIELD EFFECT TRANSISTORS, INCLUDING FORMING SOURCE AND DRAIN REGIONS IN RECESSES OF SEMICONDUCTOR FINS - Methods of forming a fin-shaped Field Effect Transistor (FinFET) are provided. The methods may include selectively incorporating source/drain extension-region dopants into source and drain regions of a semiconductor fin, using a mask to block incorporation of the source/drain extension-region dopants into at least portions of the semiconductor fin. The methods may include removing portions of the source and drain regions of the semiconductor fin to define recesses therein. The methods may include epitaxially growing source and drain regions from the recesses in the semiconductor fin. | 10-30-2014 |
20140377926 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A fin type active pattern is formed on a substrate. The fin type active pattern projects from the substrate. A diffusion film is formed on the fin type active pattern. The diffusion film includes an impurity. The impurity is diffused into a lower portion of the fin type active pattern to form a punch-through stopper diffusion layer. | 12-25-2014 |
20150111358 | CARRIER MOBILITY IN SURFACE-CHANNEL TRANSISTORS, APPARATUS MADE THEREWITH, AND SYSTEMS CONTAINING SAME - A surface channel transistor is provided in a semiconductive device. The surface channel transistor is either a PMOS or an NMOS device. Epitaxial layers are disposed above the surface channel transistor to cause an increased bandgap phenomenon nearer the surface of the device. A process of forming the surface channel transistor includes grading the epitaxial layers. | 04-23-2015 |
20150325684 | MANUFACTURING METHOD OF N-TYPE MOSFET - A method for manufacturing an NMOSFET may comprise: defining an active region for the NMOSFET on a semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interfacial oxide layer; forming a metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the metal gate layer; forming a Poly-Si layer on the metal gate layer; patterning the Poly-Si layer, the metal gate layer, the high-K gate dielectric layer and the interfacial oxide layer to form a gate stack; forming a gate spacer surrounding the gate stack; and forming source and drain regions. During annealing for the S/D activation to form the S/D regions, the dopant ions implanted in the metal gate layer may accumulate at both interfaces of the upper interface and the bottom interface of High K dielectric, and electric dipoles with appropriate polarities are generated by interface reaction at the bottom interface, so that the metal gate of the NMOSFET may have its effective work function adjusted. | 11-12-2015 |
20150340460 | ADVANCED TRANSISTORS WITH THRESHOLD VOLTAGE SET DOPANT STRUCTURES - An advanced transistor with threshold voltage set dopant structure includes a gate with length Lg and a well doped to have a first concentration of a dopant. A screening region is positioned between the well and the gate and has a second concentration of dopant greater than 5×10 | 11-26-2015 |
20150357233 | METHOD AND APPARATUS FOR FABRICATING A MEMORY DEVICE WITH A DIELECTRIC ETCH STOP LAYER - The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as DRAM or SRAM, various layers are deposited to form structures, such as PMOS gates, NMOS gates, memory cells, P+ active areas, and N+ active areas. These structures are fabricated through the use of multiple masking processes, which may cause shorts when a buried digit layer is deposited if the masking processes are misaligned. Accordingly, a dielectric etch stop layer, such as aluminum oxide Al | 12-10-2015 |
20160027647 | HIGH TILT ANGLE PLUS TWIST DRAIN EXTENSION IMPLANT FOR CHC LIFETIME IMPROVEMENT - An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor. | 01-28-2016 |
20160079389 | PREPARATION METHOD OF SEMICONDUCTOR DEVICE - The invention presents a preparation method of semiconductor device, form an amorphous region in the semiconductor substrate, then form the source/drain region of the semiconductor device in the semiconductor substrate, the amorphous region can restrain the generation of end-of-range defects of the source/drain region, then can lower well the current leakage between the semiconductor device source/drain region and the semiconductor substrate; besides, after the dummy gate structure is eliminated, form a short channel inhibition region in the channel region; it can restrain the short-channel effect of the semiconductor device and satisfy the requirement of keeping narrowing the feature size of the device. | 03-17-2016 |
20160087082 | POWER LDMOS SEMICONDUCTOR DEVICE WITH REDUCED ON-RESISTANCE AND MANUFACTURING METHOD THEREOF - An electronic semiconductor device including a semiconductor body having a first structural region and a second structural region, which extends on the first structural region and houses a drain region; a body region, which extends into the second structural region; a source region, which extends into the body region; and a gate electrode, which extends over the semiconductor body for generating a conductive channel between the source region and the drain region. The device includes a first conductive trench extending through, and electrically insulated from, the second structural region on one side of the gate electrode; and a second conductive trench extending through the source region, the body region, and right through the second structural region on an opposite side of the gate electrode, electrically insulated from the second structural region and electrically coupled to the body region and to the source region. | 03-24-2016 |
20160118475 | COUNTERDOPED SEMICONDUCTOR DEVICE - A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a third type region including a third conductivity type that is opposite the first conductivity type, the third type region covering the first type region. The semiconductor device includes a fourth type region including a fourth conductivity type that is opposite the second conductivity type, the fourth type region covering the second type region. The semiconductor device includes a channel region extending between the third type region and the fourth type region. | 04-28-2016 |
20160380057 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a base dielectric layer, a semiconductor substrate layer disposed on the base dielectric layer, and a transistor disposed in the semiconductor substrate layer. The transistor includes a gate dielectric layer disposed on the semiconductor substrate layer, a gate electrode disposed on the gate dielectric layer, source and drain electrodes disposed within the semiconductor substrate layer on opposite sides of the gate electrode, an undoped channel region, a base dopant region, and a threshold voltage setting region. The undoped channel region, base dopant region, and threshold voltage setting region are disposed within the semiconductor substrate layer. The undoped channel region is disposed between the source electrode and the drain electrode, and the base dopant region and the threshold voltage setting region extend beneath the source electrode and the drain electrode. The threshold voltage setting region is disposed between the undoped channel region and the base dopant region. | 12-29-2016 |
438290000 | After formation of source or drain regions and gate electrode | 16 |
20080206946 | Memory and method of fabricating the same - A memory capable of reducing the memory cell size is provided. This memory includes a first conductive type first impurity region formed on a memory cell array region of the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a plurality of second conductive type second impurity regions, formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode. | 08-28-2008 |
20080311717 | Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications - An insulated-gate field-effect transistor ( | 12-18-2008 |
20090004803 | MULTI-STAGE IMPLANT TO IMPROVE DEVICE CHARACTERISTICS - One aspect of the inventors' concept relates to a method of forming a semiconductor device. In this method, a gate structure is formed over a semiconductor body. A source/drain mask is patterned over the semiconductor body implanted source and drain regions are formed that are associated with the gate structure. After forming the implanted source and drain regions, a multi-stage implant is performed on the source and drain regions that comprises at least two implants where the dose and energy of the first implant varies from the dose and energy of the second implant. Other methods and devices are also disclosed. | 01-01-2009 |
20090004804 | METHOD OF FABRICATING SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device may include forming a well in a semiconductor substrate, and then forming a gate oxide on and/or over the semiconductor substrate, and then forming a gate on and/or over the gate oxide, and then forming a pocket under the gate, and then performing a first spike anneal on the semiconductor substrate, and then performing a deep source/drain implant process on the semiconductor substrate, and then performing a second spike anneal on the semiconductor substrate. | 01-01-2009 |
20090035910 | Method of Forming The NDMOS Device Body With The Reduced Number of Masks - This disclosure describes an improved process and resulting structure that allows a single masking step to be used to define both the body and the threshold adjustment layer of the body. The method consists of forming a first mask on a surface of a substrate with an opening exposing a first region of the substrate; implanting through the opening a first impurity of a first conductivity type and having a first diffusion coefficient; and implanting through the opening a second impurity of the first conductivity type and having a second diffusion coefficient lower than the first diffusion coefficient. The first and second impurities are then co-diffused to form a body region of a field effect transistor. The remainder of the device is formed. | 02-05-2009 |
20090191682 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE - A fabrication method of a semiconductor device includes: forming a gate insulating film and a gate electrode on an N type well; forming first source/drain regions by implanting a first element in regions of the N type well on both sides of the gate electrode, the first element being larger than silicon and exhibiting P type conductivity; forming second source/drain regions by implanting a second element in the regions of the N type well on the both sides of the gate electrode, the second element being smaller than silicon and exhibiting P type conductivity; and forming a metal silicide layer on the source/drain regions. | 07-30-2009 |
20110014768 | METHOD AND SYSTEM FOR IMPROVED NICKEL SILICIDE - According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate. | 01-20-2011 |
20110256683 | METHOD OF MANUFACTURING A HIGH-PERFORMANCE SEMICONDUCTOR DEVICE - The present invention relates to a method of manufacturing a semiconductor device, wherein the method comprises: providing a substrate; forming a source region, a drain region, a dummy gate structure, and a gate dielectric layer on the substrate, wherein the dummy gate structure is between the source region and the drain region on the substrate, and the gate dielectric layer is between the substrate and the dummy gate structure; annealing the source region and the drain region; removing the dummy gate structure to form an opening; implanting dopants into the substrate from the opening to form a steep retrograded well; annealing to activate the dopants; and forming a metal gate on the gate dielectric layer by deposition. | 10-20-2011 |
20120214286 | METHOD FOR FABRICATING AN NMOS TRANSISTOR - A method for fabricating an NMOS transistor includes providing a substrate; forming a gate dielectric layer structure on the substrate and forming a gate electrode on the gate dielectric layer structure. The method further includes performing a fluorine ion implantation below the gate dielectric layer and an annealing process in an atmosphere comprising hydrogen or hydrogen plasma. The method also includes forming a source region and a drain region on both sides of the gate electrode before or after the fluorine ion implantation. | 08-23-2012 |
20120302026 | METHOD FOR FORMING A TRANSISTOR - A method for forming a transistor includes providing a substrate, forming a well region in the substrate, and forming a gate structure on a surface of the well region. The gate structure includes a gate oxide layer on the surface of the well region and a gate on the gate oxide layer. The method further includes forming source/drain regions in the substrate at opposite sides of the gate structure and performing an ion doping to the substrate to adjust a threshold voltage. The ion doping is performed after the source/drain regions are formed to reduce the impact to the diffusion of the ions caused by heat treatments performed before the ion doping. The method further includes heating the substrate after the ion doping at a temperature from about 400° C. to about 500° C. | 11-29-2012 |
20130011986 | Method for Manufacturing Full Silicide Metal Gate Bulk Silicon Multi-Gate Fin Field Effect Transistors - The present application discloses a method for manufacturing a full silicide metal gate bulk silicon multi-gate fin field effect transistor, which comprises the steps of: forming at least one fin on the semiconductor substrate; forming a gate stack structure on top and side surfaces of the fin; forming a source/drain extension area in the fin on both sides of the gate stack structure; forming a source/drain area on both sides of the source/drain extension area; forming silicide on the source/drain area; forming a full silicide metal gate electrode; and forming contact and implementing metalization. The present invention eliminates the self-heating effect and the floating body effect of SOI devices, then has a much lower cost, overcomes such defects as the polysilicon gate depletion effect, Boron penetration effect, and large series resistance of polysilicon gate electrodes, and has good compatibility with the planar COMS technology, thus it can be easily integrated. | 01-10-2013 |
20140038378 | APPARATUS AND METHOD FOR A METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH SOURCE SIDE PUNCH-THROUGH PROTECTION IMPLANT - A metal oxide semiconductor field effect transistor (MOSFET) with source side punch-through protection implant. Specifically, the MOSFET comprises a semiconductor substrate, a gate stack formed above the semiconductor substrate, source and drain regions, and a protection implant. The semiconductor substrate comprises a first p-type doping concentration. The source and drain regions comprise an n-type doping concentration, and are formed on opposing sides of the gate stack in the semiconductor substrate. The protection implant comprises a second p-type doping concentration, and is formed in the semiconductor substrate under the source region and surrounds the source region in order to protect the source region from the depletion region corresponding to the drain region. | 02-06-2014 |
20140141586 | Guard Rings on Fin Structures - A device includes a semiconductor substrate, isolation regions extending into the semiconductor substrate, a plurality of semiconductor fins higher than top surfaces of the isolation regions, and a plurality of gate stacks. Each of the gate stacks includes a gate dielectric on a top surface and sidewalls of one of the plurality of semiconductor fin, and a gate electrode over the gate dielectric. The device further includes a plurality of semiconductor regions, each disposed between and contacting two neighboring ones of the plurality of semiconductor fins. The device further includes a plurality of contact plugs, each overlying and electrically coupled to one of the plurality of semiconductor regions. An electrical connection electrically interconnects the plurality of semiconductor regions and the gate electrodes of the plurality of gate stacks. | 05-22-2014 |
20140154853 | METHOD FOR MANUFACTURING N-TYPE MOSFET - The present disclosure discloses a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer. | 06-05-2014 |
20140370679 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according an aspect of the present disclosure may include an isolation layer formed within a substrate and formed to define an active region, a junction formed in the active region, well regions formed under the isolation layer, and a plug embedded within the substrate between the junction and the well regions and formed extend to a greater depth than the well regions. | 12-18-2014 |
20160172444 | Method for Fabricating a Transistor Device With a Tuned Dopant Profile | 06-16-2016 |
438291000 | Using channel conductivity dopant of opposite type as that of source and drain | 7 |
20080293204 | Shallow junction formation and high dopant activation rate of MOS devices - A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; implanting carbon into the semiconductor substrate; and implanting an n-type impurity into the semiconductor substrate to form a lightly doped source/drain (LDD) region, wherein the n-type impurity comprises more than one phosphorous atom. The n-type impurity may include phosphorous dimer or phosphorous tetramer. | 11-27-2008 |
20090233410 | Self-Aligned Halo/Pocket Implantation for Reducing Leakage and Source/Drain Resistance in MOS Devices - A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation. | 09-17-2009 |
20110059588 | MOS TRANSISTOR FOR REDUCING SHORT-CHANNEL EFFECTS AND ITS PRODUCTION - The invention is related to a MOS transistor and its fabrication method to reduce short-channel effects. Existing process has the problem of high complexity and high cost to reduce short-channel effects by using epitaxial technique to produce an elevated source and drain structure. In the invention, the MOS transistor, fabricated on a silicon substrate after an isolation module is finished, includes a gate stack, a gate sidewall spacer, and source and drain areas. The silicon substrate has a groove and the gate stack is formed in the groove. And the process for the MOS transistor includes the following steps: forming the groove; carrying out well implantation, anti-punchthrough implantation and threshold-voltage adjustment implantation; forming the gate stack in the groove which comprising patterning the gate electrode; carrying lightly doped drain implantation and halo implantation; forming the gate sidewall spacer; carrying source and drain implantation to get the source and drain areas; forming a metal silicide layer on the source and drain areas. | 03-10-2011 |
20110207281 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A method of producing a semiconductor device includes the steps of forming a trench in a semiconductor substrate of a first conductive type so that an active region having a first portion and a second region is formed; implanting a first impurity of the first conductive type at an implantation angle between 30 degrees and 45 degrees relative to a normal line in an implantation direction rotating relative to the normal line so that a first channel diffusion region and a channel stopper region of the first conductive type are formed; filling the trench with an insulation layer; implanting a second impurity of a second conductive type so that a second channel diffusion region of the second conductive type is formed; forming a gate insulation film on the first portion and the second portion; and forming a gate electrode on the gate insulation film. | 08-25-2011 |
20120208336 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a first gate electrode on a semiconductor substrate in a first transistor region; forming a channel dose region; and forming a first source extension region, wherein the channel dose region is formed by using a first mask as a mask and by ion-implanting a first dopant of the first conductivity type, and the first mask covering a drain side of the first gate electrode and covering a drain region, and the first source extension region is formed by using a second mask and the gate electrode as masks and by ion-implanting a second dopant of a second conductivity type that is a conductivity type opposite to the first conductivity type, the second mask covering the drain side of the first gate electrode and covering the drain region. | 08-16-2012 |
20130078777 | METHOD FOR FABRICATING JUNCTIONLESS TRANSISTOR - A method is provided for fabricating a transistor. According to the method, a doped material layer is formed on a semiconductor layer, and dopant is diffused from the doped material layer into the semiconductor layer to form a graded dopant region in the semiconductor layer. The graded dopant region has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer, with a gradual decrease in the doping concentration. The doped material layer is removed, and then a gate stack is formed on the semiconductor layer. Source and drain regions are formed adjacent to an active area that is in the semiconductor layer underneath the gate stack. The active area comprises at least a portion of the graded dopant region, and the source and drain regions and the active area have the same conductivity type. | 03-28-2013 |
20160163550 | Gate Electrodes with Notches and Methods for Forming the Same - A device includes a semiconductor substrate, and a Device Isolation (DI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the DI region. A gate electrode is disposed over the gate dielectric, wherein a notch of the gate electrode overlaps a portion of the DI region. | 06-09-2016 |