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Gate insulator structure constructed of diverse dielectrics (e.g., MNOS, etc.) or of nonsilicon compound

Subclass of:

438 - Semiconductor device manufacturing: process

438142000 - MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS

438197000 - Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.)

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DocumentTitleDate
20090221120METHOD OF FORMING A GATE DIELECTRIC - A method of forming a semiconductor device includes providing a substrate for the semiconductor device. A base oxide layer is formed overlying the substrate by applying a rapid thermal oxidation (RTO) of the substrate in the presence of oxygen. A nitrogen-rich region is formed within and at a surface of the base oxide layer. The nitrogen-rich region overlies an oxide region in the base oxide layer. Afterwards, the semiconductor device is annealed in a dilute oxygen and hydrogen-free ambient of below 1 Torr partial pressure of the oxygen. The annealing heals bond damage in both the oxide region and the nitrogen-rich region in the base oxide layer. After annealing the semiconductor device in the dilute oxygen ambient, in-situ steam generation (ISSG) is used to grow and density the oxide region in the base oxide layer at an interface between the substrate and base oxide layer.09-03-2009
20080261368WORK FUNCTION ADJUSTMENT WITH THE IMPLANT OF LANTHANIDES - Semiconductor devices and fabrication methods are provided, in which fully silicided transistor gates are provided for MOS transistors. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.10-23-2008
20120244673METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include selectively implanting an impurity into a underlying layer containing silicon using a mask to form a boron-added region and an etched region. The boron-added region contains boron, and a boron concentration of the etched region is lower than a boron concentration in the boron added region. The method can include forming a pair of holes reaching the etched region in the stacked body including a plurality of layers of electrode layers. The method can include forming a depression part connected to a lower end of each of the pair of holes in the underlying layer by removing the etched region through the holes using an etching solution.09-27-2012
20090155970ENHANCED MULTI-BIT NON-VOLATILE MEMORY DEVICE WITH RESONANT TUNNEL BARRIER - A non-volatile memory cell uses a resonant tunnel barrier that has an amorphous silicon and/or amorphous germanium layer between two layers of either HfSiON or LaAlO06-18-2009
20090325354SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a semiconductor device that includes a semiconductor substrate (12-31-2009
20090042350MANUFACTURING METHOD OF NONVOLATILE MEMORY - A manufacturing method for a non-volatile memory includes first providing a substrate with a gate structure formed thereon. The gate structure includes a first gate and a gate dielectric layer located between the first gate and the substrate. A first doping and a second doping region are formed on the substrate at two sides of the gate, respectively. A first insulating layer is formed on the substrate, and a portion of the first insulating layer and a portion of the substrate are removed to form a trench, which divides the second doping region into a third doping region and a fourth doping region. Finally, a tunneling dielectric layer, a charge-trapping layer and a top dielectric layer are formed inside the trench, and a second gate which fills the trench is formed on the substrate.02-12-2009
20130071976NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - Nonvolatile memory devices and methods of forming the same are provided, the nonvolatile memory devices may include first regions and second regions which extend in a first direction and are alternately disposed in a semiconductor substrate along a second direction crossing the first direction. Buried doped lines are formed at the first regions respectively and extend in the first direction. The buried doped lines may be doped with a dopant of a first conductivity type. Bulk regions doped with a dopant of a second conductivity type and device isolation patterns are disposed along the second direction. The bulk regions and the device isolation patterns may be formed in the second regions. Word lines crossing the buried doped lines and the bulk regions are formed parallel to one another. Contact structures are connected to the buried doped lines and disposed between the device isolation patterns.03-21-2013
20130065370Method for Fabricating Field Effect Transistor Devices with High-Aspect Ratio Mask - A method for forming feature on a substrate includes forming at least one layer of a feature material on a substrate, patterning a photolithographic resist material on the at least one layer of the feature material, removing portions of the feature material to define a feature, depositing a masking material layer over the resist material and exposed regions of the substrate, modifying a portion of the substrate, and removing the masking material layer and the resist material.03-14-2013
20130164897TRANSISTORS HAVING ARGON GATE IMPLANTS AND METHODS OF FORMING THE SAME - Transistors are provided including first and second source/drain regions, a channel region and a gate stack having a first gate dielectric over a substrate, the first gate dielectric having a dielectric constant higher than a dielectric constant of silicon dioxide, and a metal material in contact with the first gate dielectric, the metal material being doped with an inert element. Integrated circuits including the transistors and methods of forming the transistors are also provided.06-27-2013
20090011564Method of forming a gate oxide layer - A nitrogen implantation to a substrate on the edges of an active area is added before filling an insulating layer in a trench during a shallow trench isolation process to reduce the thickness of a gate oxide formed later on the edges of the active area.01-08-2009
20110281412PRODUCTION OF A TRANSISTOR GATE ON A MULTIBRANCH CHANNEL STRUCTURE AND MEANS FOR ISOLATING THIS GATE FROM THE SOURCE AND DRAIN REGIONS - A method for fabricating a microelectronic device comprising: a support, an etched stack of thin layers comprising: at least one first block and at least one second block resting on the support, in which at least one drain region and at least one source region, respectively, are capable of being formed, several semiconductor bars connecting a first zone of the first block and another zone of the second block, and able to form a multi-branch transistor channel, or several transistor channels, the device also comprising: a gate surrounding said bars and located between said first block and said second block, the gate being in contact with a first and a second insulating spacer in contact with at least one sidewall of the first block and with at least one sidewall of the second block, respectively, and at least partially separated from the first block and the second block, via said insulating spacers.11-17-2011
20110300682CHARGE TRAPPING DEVICES WITH FIELD DISTRIBUTION LAYER OVER TUNNELING BARRIER - A memory cell comprising: a semiconductor substrate with a surface with a source region and a drain region disposed below the surface of the substrate and separated by a channel region; a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed above the channel region; a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region; a charge trapping structure disposed above the conductive layer and above the channel region; a top dielectric structure disposed above the charge trapping structure and above the channel region; and a top conductive layer disposed above the top dielectric structure and above the channel region are described along with devices thereof and methods for manufacturing.12-08-2011
20100112772Method of fabricating semiconductor device - A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.05-06-2010
20090263950SEMICONDUCTOR DEVICE - A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1010-22-2009
20090275182METHOD FOR FABRICATING A METAL HIGH DIELECTRIC CONSTANT TRANSISTOR WITH REVERSE-T GATE - A method is provided for fabricating a transistor. A silicon layer is provided, and a first layer comprising a high dielectric constant material is formed on the silicon layer. A second layer including a metal or metal alloy is formed on the first layer, and a third layer including silicon or polysilicon is formed on the second layer. The first, second, and third layers are etched so as to form a gate stack, and ions are implanted to form source and drain regions in the silicon layer. Source and drain silicide contact areas are formed in the source and drain regions, and a gate silicide contact area is formed in the third layer. After forming these silicide contact areas, the third layer is etched without etching the first and second layers, so as to substantially reduce the width of the third layer.11-05-2009
20090142899INTERFACIAL LAYER FOR HAFNIUM-BASED HIGH-K/METAL GATE TRANSISTORS - A method of forming an interfacial layer for hafnium-based high-k/metal gate transistors comprises depositing a hafnium-based high-k dielectric layer on a semiconductor substrate and then annealing the high-k dielectric layer and the semiconductor substrate in a nitric oxide atmosphere for a time duration and at a temperature sufficient to drive at least a portion of the nitric oxide through the dielectric layer to an interface between the dielectric layer and the substrate. At this interface, the nitric oxide reacts with the substrate to form a silicon oxynitride interfacial layer.06-04-2009
20090275183METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A thermal oxidation method capable of obtaining a high oxidation rate by generating a sufficient enhanced-rate oxidation phenomenon even in a low temperature region is provided. In addition, a thermal oxidation method capable of forming a silicon oxide film having a high reliability even when formed at a low temperature region. A basic concept herein is to form a silicon oxide film by thermal reaction by generating a large amount of oxygen radicals (O*) having a large reactivity without using plasma. More specifically, ozone (O11-05-2009
20120289014METHOD FOR FABRICATING TRANSISTOR WITH HIGH-K DIELECTRIC SIDEWALL SPACER - A method is provided for fabricating a transistor. The transistor includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.11-15-2012
20080242034METHOD OF MAKING THREE DIMENSIONAL NAND MEMORY - A method of making a monolithic, three dimensional NAND string, includes forming a semiconductor active region of a first memory cell over a semiconductor active region of a second memory cell. The semiconductor active region of the first memory cell is a first pillar having a square or rectangular cross section when viewed from above, the first pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. The semiconductor active region of the second memory cell is a second pillar having a square or rectangular cross section when viewed from above, the second pillar located under the first pillar, the second pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. One second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar.10-02-2008
20080305597SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF - The object of the present invention is to provide a method of manufacturing high permittivity gate dielectrics for a device such as an MOSFET. A HfSiO film 12-11-2008
20110207280SCAVANGING METAL STACK FOR A HIGH-K GATE DIELECTRIC - A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y M08-25-2011
20090053870METHOD FOR PREPARING FLASH MEMORY STRUCTURES - A method for preparing a flash memory structure comprises the steps of forming a plurality of dielectric blocks having block sidewalls on a substrate, forming a plurality of first spacers on the block sidewalls of the dielectric blocks, removing a portion of the substrate not covered by the dielectric blocks and the first spacers to form a plurality of trenches in the substrate, performing a deposition process to form an isolation dielectric layer filling the trenches, removing the dielectric blocks to expose spacer sidewalls of the first spacers, forming a plurality of second spacers on the spacer sidewalls of the first spacers, and removing a portion of the substrate not covered by the first spacers, the second spacers and the isolation dielectric layer to form a plurality of second trenches in the substrate.02-26-2009
20090162984METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed are methods for manufacturing a semiconductor device. One method includes the steps of forming a gate electrode on a semiconductor substrate, sequentially forming a first oxide layer, a nitride layer and a second oxide layer on the semiconductor substrate including the gate electrode, dry-etching the second oxide layer, wet-etching the nitride layer, and forming source and drain regions at sides of the gate electrode by implanting ions into the semiconductor substrate on which the first oxide layer is formed. According to the method, in the process of forming a gate spacer in the semiconductor device, an oxide layer of the gate spacer remains on the source and drain regions, and then an ion implantation process is performed, so that plasma damage and current leakage can be inhibited from occurring in the source and drain regions. Thus, device characteristics of a CMOS image sensor can be improved.06-25-2009
20090004801Method of forming lutetium and lanthanum dielectric structures - Methods of forming dielectric structures are shown. Methods of forming dielectric structures are shown that include lutetium oxide and lanthanum aluminum oxide crystals embedded within the lutetium oxide. Specific methods shown include monolayer deposition which yields process improvements such as chemistry control, step coverage, crystallinity/microstructure control.01-01-2009
20090004802METHOD OF FABRICATING NON-VOLATILE MEMORY DEVICE HAVING CHARGE TRAPPING LAYER - A method of fabricating a non-volatile memory device having a charge trapping layer includes forming a tunneling layer, a charge trapping layer, a blocking layer and a control gate electrode layer over a substrate, forming a mask layer pattern on the control gate electrode layer, performing an etching process using the mask layer pattern as an etching mask to remove an exposed portion of the control gate electrode layer, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness, forming an insulating layer for blocking charges from moving on the control gate electrode layer and the mask layer pattern, performing anisotropic etching on the insulating layer to form an insulating layer pattern on a sidewall of the control gate electrode layer and a partial upper sidewall of the blocking layer, and performing an etching process on the blocking layer exposed by the anisotropic etching, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness.01-01-2009
20090017590METHOD FOR FABRICATING SONOS A MEMORY - A method for fabricating a SONOS memory is disclosed. First, a semiconductor substrate is provided and a SONOS memory cell is formed on said semiconductor substrate. A passivation layer is deposited on the SONOS memory cell and a contact pad is formed on the passivation layer. Subsequently, an ultraviolet treatment is performed and an annealing process is conducted thereafter.01-15-2009
20090081840Method of Forming Field Effect Transistors Using Diluted Hydrofluoric Acid to Remove Sacrificial Nitride Spacers - Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, sacrificial nitride spacers on opposing sidewalls of the gate electrode and source/drain regions, which are self-aligned to the sacrificial nitride spacers, on a semiconductor substrate. The sacrificial nitride spacers are selectively removed using a diluted hydrofluoric acid solution having a nitride-to-oxide etching selectivity in excess of one. In order to increase charge carrier mobility within a channel of the field effect transistor, a stress-inducing electrically insulating layer is formed on opposing sidewalls of the gate electrode. This insulating layer is configured to induce a net tensile stress (NMOS) or compressive stress (PMOS) in the channel.03-26-2009
20130217197INTEGRATION TECHNIQUE USING THERMAL OXIDE SELECT GATE DIELECTRIC FOR SELECT GATE AND REPLACEMENT GATE FOR LOGIC - A control gate overlying a charge storage layer is formed. A thermally-grown oxygen-containing layer is formed over the control gate. A polysilicon layer is formed over the oxygen-containing layer and planarized. A first masking layer is formed defining a select gate location laterally adjacent the control gate and a second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening in the dielectric. A high-k gate dielectric and logic gate are formed in the opening.08-22-2013
20100248439Method of fabricating non-volatile memory device having vertical structure - A method of fabricating a non-volatile memory device according to an example embodiment may include etching a plurality of sacrificial films and insulation films to form a plurality of first openings that expose a plurality of first portions of a semiconductor substrate. A plurality of channel layers may be formed in the plurality of first openings so as to coat the plurality of first portions of the semiconductor substrate and side surfaces of the plurality of first openings. A plurality of insulation pillars may be formed on the plurality of channel layers so as to fill the plurality of first openings. The plurality of sacrificial films and insulation films may be further etched to form a plurality of second openings that expose a plurality of second portions of the semiconductor substrate. A plurality of side openings may be formed by removing the plurality of sacrificial films. A plurality of gate dielectric films may be formed on surfaces of the plurality of side openings. A plurality of gate electrodes may be formed on the plurality of gate dielectric films so as to fill the plurality of side openings.09-30-2010
20090081841Non-Volatile Memory Device and Manufacturing Method Thereof - A non-volatile memory device having a Polysilicon Oxide Nitride Oxide Semiconductor (SONOS) structure in which a charge trap layer is separated physically in a horizontal direction, and a method of manufacturing the same. The charge trap layer that traps electric charges toward the source and the drain is physically divided. It can fundamentally prevent the charges at both sides from being moved mutually. It is therefore possible to prevent interference between charges at both sides although the cell size is reduced.03-26-2009
20090191681NOR-TYPE FLASH MEMORY DEVICE WITH TWIN BIT CELL STRUCTURE AND METHOD OF FABRICATING THE SAME - A NOR-type flash memory device comprises a plurality twin-bit memory cells arranged so that pairs of adjacent memory cells share a source/drain region and groups of four adjacent memory cells are electrically connected to each other by a single bitline contact.07-30-2009
20090053871METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device and method of fabricating a semiconductor memory device, wherein a tunnel insulating layer, a first charge trap layer and an isolation mask layer are sequentially stacked over a semiconductor substrate in which a cell region and a peri region are defined. The isolation mask layer, the first charge trap layer, the tunnel insulating layer and the semiconductor substrate are etched to thereby form trenches. An isolation layer is formed within each trench. The first charge trap layer is exposed by removing the isolation mask layer formed in the cell region. A second charge trap layer is formed on the exposed first charge trap layer and the isolation layer. A blocking layer and a control gate are formed over the semiconductor substrate in which the second charge trap layer is formed.02-26-2009
20090203178Memory device and method of manufacturing the same - A example embodiment may provide a memory device that may include an active pattern on a semiconductor substrate, a first charge trapping layer pattern on the active pattern, a first gate electrode on the first charge trapping layer pattern, a second charge trapping layer pattern on a sidewall of the active pattern in a first direction, a second gate electrode on the second charge trapping layer pattern in the first direction, and/or a source/drain region in the active pattern. The memory device may have improved integration by forming a plurality of charge trapping layer patterns on the same active pattern.08-13-2009
20090209076METHOD FOR MANUFACTURING SONOS FLASH MEMORY - A method for manufacturing a semiconductor device which includes steps of forming a dummy layer on a semiconductor substrate, forming a groove 12 in the semiconductor substrate while using the dummy layer as a mask, forming a tunnel insulating film and a trap layer to cover an inner surface of the groove and the dummy layer, eliminating the trap layer formed above the upper surface and at the sides of the dummy layer, and forming a top insulating film to cover a remaining trap layer and the exposed tunnel insulating film.08-20-2009
20090246925NITRIDE READ ONLY MEMORY DEVICE WITH BURIED DIFFUSION SPACERS AND METHOD FOR MAKING THE SAME - A method for making a nitride read only memory device with buried diffusion spacers is disclosed. An oxide-nitride-oxide (ONO) layer is formed on top of a silicon substrate, and a polysilicon gate is formed over the ONO layer. The polysilicon gate is formed less than a length of the ONO layer. Two buried diffusion spacers are formed beside two sidewalls of the polysilicon gate and over the ONO layer. Two buried diffusion regions are implanted on the silicon substrate next to the two buried diffusion spacers. The two buried diffusion regions are then annealed such that the approximate interfaces of the buried diffusion regions are under the sidewalls of the polysilicon gate. The structure of a nitride read only memory device with buried diffusion spacers is also described.10-01-2009
20100159660METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A method of manufacturing a flash memory device includes preparing a semiconductor substrate comprising a cell area and a peripheral area, forming a first well and an oxide-nitride-oxide (ONO) layer in the cell area, forming a second well in the peripheral area of the semiconductor substrate comprising the first well and forming a first oxide layer in the peripheral area, forming a first polysilicon layer over the ONO layer and the first oxide layer and performing a first etch process to form a memory gate comprising an ONO layer pattern and a first polysilicon pattern in the cell area, forming a second oxide layer pattern and a second polysilicon pattern over either sidewall of the memory gate and forming a gate in the peripheral area, performing a third etch process so that the second oxide layer pattern and the second polysilicon pattern remain over only the one sidewall of the memory gate to form a select gate, and forming a first impurity area in the semiconductor substrate between the memory gates adjacent to each other.06-24-2010
20080213963Charge trapping memory device with two separated non-conductive charge trapping inserts and method for making the same - A charge trapping memory device with two separated non-conductive charge trapping inserts is disclosed. The charge trapping memory device has a silicon substrate with two junctions. A gate oxide (GOX) is formed on top of the silicon substrate and between the two junctions. A polysilicon gate is defined over the GOX. A layer of bottom oxide (BOX) is grown on top of the silicon substrate and a conformal layer of top oxide (TOX) is grown along the bottom and the sidewalls of the polysilicon gate. Two charge trapping inserts are located beside the GOX and between the BOX and the TOX. The polysilicon gate needs to be at least partially over each of the two charge trapping inserts. The charge trapping inserts are made from a non-conductive charge trapping material. A method for fabricating such a device is also described.09-04-2008
20100159661NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - An object of the present invention is to provide a nonvolatile semiconductor storage device with a superior charge holding characteristic in which highly-efficient writing is possible at low voltage, and to provide a manufacturing method thereof.06-24-2010
20100221885METHOD OF MANUFACTURING DIELECTRIC FILM - The present invention provides a method of manufacturing a dielectric film having a high permittivity. An embodiment of the present invention is a method of manufacturing, on a substrate, a dielectric film including a metallic oxynitride containing an element A made of Hf or a mixture of Hf and Zr, an element B made of Al, and N and O. The manufacturing method includes: a step of forming a metallic oxynitride whose mole fractions of the element A, the element B, and N expressed as B/(A+B+N) has a range of 0.015≦(B/A+B+N))≦0.095 and N/(A+B+N) has a range of 0.045≦(N/(A+B+N)) and a mole fraction O/A of the element A and O has a range expressed as 1.0<(O/A)<2.0, and having a noncrystalline structure; and a step of performing an annealing treatment at 700° C. or higher on the metallic oxynitride having a noncrystalline structure to form a metallic oxynitride including a crystalline phase with a cubical crystal incorporation percentage of 80% or higher.09-02-2010
20120196419SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In an MIS-type GaN-FET, a base layer made of a conductive nitride including no oxygen, here, TaN, is provided on a surface layer as a nitride semiconductor layer to cover at least an area of a lower face of a gate insulation film made of Ta08-02-2012
20100221886Methods of Forming Charge-Trap Type Non-Volatile Memory Devices - Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate.09-02-2010
20110129976LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE - A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.06-02-2011
20100304541SYSTEMS AND METHODS FOR MEMORY STRUCTURE COMPRISING A PPROM AND AN EMBEDDED FLASH MEMORY - A memory structure that combines embedded flash memory and PPROM. The PPROM can be used as a memory structure. The flash memory can be used, e.g., as air replacement cells or back up memory, or additional memory cells. The PPROM cells are stacked on top of the flash memory cells and the PPROM density can be increased by implementing three-dimensional PPROM structures.12-02-2010
20130137233HYDROGEN BARRIER LINER FOR FERRO-ELECTRIC RANDOM ACCESS MEMORY (FRAM) CHIP - A method for forming a hydrogen barrier liner for a ferro-electric random access memory chip including forming a first dielectric layer over a substrate; forming a gate over the first dielectric layer; forming a first aluminum oxide layer over the gate and the first dielectric layer; forming a second dielectric layer over the first aluminum oxide layer; etching a trench through the second dielectric layer and the first aluminum oxide layer to the gate; forming a hydrogen barrier liner over the second dielectric layer, the hydrogen barrier liner lining the trench and contacting the gate; forming a silicon dioxide layer over the first aluminum dioxide layer, the silicon dioxide layer substantially filling the trench; and substantially removing the silicon dioxide layer leaving a silicon dioxide plug in the trench.05-30-2013
20100311217Non-Volatile Memory Device Having A Nitride-Oxide Dielectric Layer - A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.12-09-2010
20100317169METHODS OF FABRICATING NON-VOLATILE MEMORY DEVICES USING INCLINED ION IMPLANTATION - Provided is a method of manufacturing a non-volatile memory device by performing ion implantation at an angle such that active regions of memory cell transistors in a cell region and peripheral transistors in a peripheral region each have different doping concentrations. The method includes forming a plurality of memory cell transistor gates on a cell region of a substrate surface and a plurality of peripheral transistor gates on a peripheral region of the substrate surface, where a distance between adjacent ones of the peripheral transistor gates is greater than a distance between adjacent ones of the memory cell transistor gates, and performing an ion implantation process at an implantation angle that is selected based on a height of the memory cell transistor gates and the distance between the adjacent ones thereof to implant ions into portions of the peripheral region between the peripheral transistor gates without implanting the ions into portions of the cell region between the memory cell transistor gates.12-16-2010
20090068808Method of manufacturing a nonvolatile semiconductor memory device having a gate stack - A nonvolatile semiconductor memory device includes a semiconductor substrate having a source region and a drain region, and a gate stack formed on the semiconductor substrate between and in contact with the source and drain regions. The gate stack includes, in sequential order from the substrate: a tunneling film; a first trapping material film doped with a first predetermined impurity, the first trapping material film having a higher dielectric constant than the nitride film (Si03-12-2009
20110039386LATERAL POCKET IMPLANT CHARGE TRAPPING DEVICES - A charge trapping memory cell is described, having pocket implants along the sides of the channel and having the same conductivity type as the channel, and which implants have a concentration of dopants higher than in the central region of the channel. This effectively disables the channel in the region of non-uniform charge trapping caused by a bird's beak or other anomaly in the charge trapping structure on the side of the channel. The pocket implant can be formed using a process compatible with standard shallow trench isolation processes.02-17-2011
20110039385SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.02-17-2011
20110014767LOW-TEMPERATURE GROWN HIGH QUALITY ULTRA-THIN CoTiO3 GATE DIELECTRICS - A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO01-20-2011
20100178744MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE WHOSE GATE INSULATING FILM CONTAINS Hf AND O - An insulating film having Hf and O is formed over a semiconductor substrate. A cap film having oxygen and titanium as constituent elements is formed over the insulating film. The insulating film and cap film are thermally treated in a nitrogen gas or noble gas to diffuse titanium in the cap film into the insulating film to form a gate insulating film. A gate electrode film is formed over the gate insulating film.07-15-2010
20100178745Flash Memory Device and Fabrication Method Thereof - The present invention relates to a flash memory device and a fabrication method thereof. A trench may be formed within a junction region between word lines by etching a semiconductor substrate between not only a word line and a select line, but also between adjacent word lines. Accordingly, the occurrence of a program disturbance phenomenon can be prevented as the injection of hot carriers into a program-inhibited cell is minimized in a program operation.07-15-2010
20110033996METHOD FOR PRODUCING A CONDUCTIVE NANOPARTICLE MEMORY DEVICE - A method for producing a memory device with nanoparticles, comprising the steps of: 02-10-2011
20110117712SEMICONDUCTOR DEVICE WITH HIGH K DIELECTRIC CONTROL TERMINAL SPACER STRUCTURE - A semiconductor device including a control terminal sidewall spacer structure made of a high-K dielectric material. The semiconductor device includes a control terminal where the spacer structure is a sidewall spacer structure for the control terminal. The semiconductor device includes current terminal regions located in a substrate. In some examples, the spacer structure has a height that is less than the height of the control terminal. In some examples, the spacer structure includes portions located over the regions of the substrate between the first current terminal region and the second current terminal region.05-19-2011
20110117713METHOD OF MAKING FLASH MEMORY CELLS AND PERIPHERAL CIRCUITS HAVING STI, AND FLASH MEMORY DEVICES AND COMPUTER SYSTEMS HAVING THE SAME - An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased.05-19-2011
20100197098METHOD OF FABRICATING A HIGH PERFORMANCE POWER MOS - A method of fabricating a semiconductor device includes forming in the substrate a well region comprising a first type of dopant; forming in the well region a base region comprising a second type of dopant different from the first type of dopant; and forming in the substrate source and drain regions comprising the first type of dopant. The method further includes forming on the substrate a gate electrode interposed laterally between the source and drain regions; and forming on the substrate a gate spacer disposed laterally between the source region and the gate electrode adjacent a side of the gate electrode and having a conductive feature embedded therein. The well region surrounds the drain region and the base region, and the base region is disposed partially underlying the gate electrode surrounding the source region defining a channel under the gate electrode of having a length substantially less than half the length of the gate electrode.08-05-2010
20100015773SONOS MEMORY DEVICE HAVING CURVED SURFACE AND METHOD FOR FABRICATING THE SAME - A new SONOS memory device is provided, in which a conventional planar surface of multi-dielectric layers (ONO layers) is instead formed with a curved surface such as a cylindrical shape, and included is a method for fabricating the same.01-21-2010
20090311840METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming, over a substrate, a gate insulating film containing a high-k insulating film which is composed of a material having a dielectric constant larger than that of silicon dioxide film; forming a gate electrode containing a metal over the gate insulating film; forming extension regions by implanting an dopant into the substrate using the gate electrode as a mask; and annealing the substrate, having the dopant implanted therein, by flash lamp annealing or laser annealing; wherein the annealing further includes: a first step irradiating a substrate with a light pulse having a predetermined peak intensity; and a second step irradiating a substrate with light pulses having peak intensities lower than that of the light pulse used in the first step.12-17-2009
20110097866NON-VOLATILE MEMORY CELL AND METHOD OF FABRICATING THE SAME - A method of fabricating a non-volatile memory cell is disclosed. The method includes the steps of: forming two separate charge trapping structures on a semiconductor substrate; forming first spacers on sidewalls of the two charge trapping structures; forming a gate dielectric layer on the substrate; forming a gate on the two charge trapping structures and the gate dielectric layer between the two charge trapping structures; and forming two doped regions in the substrate besdie the gate.04-28-2011
20100261326ISOLATED-NITRIDE-REGION NON-VOLATILE MEMORY CELL AND FABRICATION METHOD - An isolated-nitride-region non-volatile memory cell is formed in a semiconductor substrate. Spaced-apart source and drain regions are disposed in the semiconductor substrate forming a channel therebetween. An insulating region is disposed over the semiconductor substrate. A gate is disposed over the insulating region and is horizontally aligned with the channel. A plurality of isolated nitride regions are disposed in the insulating region and are not in contact with either the channel or the gate.10-14-2010
20120171831ASYMMETRIC FET INCLUDING SLOPED THRESHOLD VOLTAGE ADJUSTING MATERIAL LAYER AND METHOD OF FABRICATING SAME - A method of forming a semiconductor structure is provided. The method includes providing a structure including at least one dummy gate region located on a surface of a semiconductor substrate and a dielectric material layer located on sidewalls of the at least one dummy gate region. Next, a portion of the dummy gate region is removed exposing an underlying high k gate dielectric. A sloped threshold voltage adjusting material layer is then formed on an upper surface of the high k gate dielectric, and thereafter a gate conductor is formed atop the sloped threshold voltage adjusting material layer.07-05-2012
20110177664MEHTOD FOR FABRICATING A SONOS MEMORY - A method for fabricating SONOS memory is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer on the surface of the semiconductor substrate; forming a hard mask on the second silicon oxide layer; patterning the hard mask, the second silicon oxide layer, the silicon nitride layer, and the first silicon oxide layer to form a patterned hard mask and a stacked structure; forming a gate oxide layer on surface of the patterned hard mask; removing the gate oxide layer and the patterned hard mask; forming a patterned polysilicon layer on surface of the stacked structure; and forming a source/drain region in the semiconductor substrate adjacent to two sides of the polysilicon layer.07-21-2011
20110256682Multiple Deposition, Multiple Treatment Dielectric Layer For A Semiconductor Device - A method is provided for fabricating a semiconductor device. A semiconductor substrate is provided. A first high-k dielectric layer is formed on the semiconductor substrate. A first treatment is performed on the high-k dielectric layer. In an embodiment, the treatment includes a UV radiation in the presence of O10-20-2011
20080254585Method for fabricating semiconductor memory - A method for fabricating a semiconductor memory, the method including: forming an element isolation region in a concave portion of the semiconductor substrate; forming a layer of a gate electrode material so as to cover the concave portion and the element isolation region; forming a gate electrode by forming a mask on a surface of the layer of a gate electrode material so that a height from an upper surface of the convex portion to the surface of the mask is higher than a height from the surface of the element isolation region to the upper surface of the convex portion and by patterning the layer of the gate electrode material; forming a charge storing layer at least one of side surfaces of the gate electrode in contact with the convex portion; and forming a sidewall on a part of the charge storing layer.10-16-2008
20120202329CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - There is provided a charge trap type non-volatile memory device and a method for fabricating the same, the charge trap type non-volatile memory device including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; a charge barrier layer formed over the charge trap layer; a gate electrode formed over the charge barrier layer; and an oxide-based spacer formed over sidewalls of the charge trap layer and provided to isolate the charge trap layer.08-09-2012
20110020994MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is described. First, a substrate is provided. Thereafter, a gate structure including, from bottom to top, a high-k layer, a work function metal layer, a wetting layer, a polysilicon layer and a mask layer is formed on the substrate. Afterwards, a spacer is formed on the sidewall of the gate structure. Source/drain regions are then formed in the substrate beside the gate structure. Further, an interlayer dielectric layer is formed over the substrate. Thereafter, a portion of the interlayer dielectric layer is removed to expose the surface of the mask layer. Afterwards, the mask layer and the polysilicon layer are sequentially removed to expose the surface of the wetting layer. A selective chemical vapor deposition process is then performed, so as to bottom-up deposit a metal layer from the surface of the wetting layer.01-27-2011
20120122284METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a plurality of gate structures including a metal on a substrate having an isolation layer, forming first insulating interlayer patterns covering sidewalls of the gate structures, forming first capping layer patterns and a second capping layer pattern on the gate structures and the first insulating interlayer patterns, the first capping layer patterns covering upper faces of the gate structures, and the second capping layer pattern overlapping the isolation layer, partially removing the first insulating interlayer patterns using the first and the second capping layer patterns as etching masks to form first openings that expose portions of the substrate, forming metal silicide patterns on the portions of the substrate exposed in the forming of the first openings, and forming conductive structures on the metal silicide patterns.05-17-2012
20120122283METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method includes forming a plurality of dummy gate structures on a substrate, each dummy gate structure including a dummy gate electrode and a dummy gate mask, forming a first insulation layer on the substrate and the dummy gate structures to fill a first space between the dummy gate structures, planarizing upper portions of the first insulation layer and the dummy gate structures, removing the remaining first insulation layer to expose a portion of the substrate, forming an etch stop layer on the remaining dummy gate structures and the exposed portion of the substrate, forming a second insulation layer on the etch stop layer to fill a second space between the dummy gate structures, planarizing upper portions of the second insulation layer and the etch stop layer to expose the dummy gate electrodes, removing the exposed dummy gate electrodes to form trenches, and forming metal gate electrodes in the trenches.05-17-2012
20110263091MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device using an oxide semiconductor, with stable electric characteristics and high reliability. In a process for manufacturing a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation is performed by heat treatment and oxygen doping treatment is performed. The transistor including a gate insulating film subjected to the oxygen doping treatment and the oxide semiconductor film subjected to the dehydration or dehydrogenation by the heat treatment is a transistor having high reliability in which the amount of change in threshold voltage of the transistor by the bias-temperature stress (BT) test can be reduced.10-27-2011
20110136312SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD - The disclosure pertains to a semiconductor device and its manufacture method, the semiconductor device including non-volatile memory cells and a peripheral circuit including field effect transistors having an insulated gate. A semiconductor device and its manufacture method are to be provided, the semiconductor device having memory cells with a high retention ability and field effect transistors having an insulated gate with large drive current. The semiconductor device has a semiconductor substrate (06-09-2011
20100330762METHOD FOR FORMING BIT LINES FOR SEMICONDUCTOR DEVICES - A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity,12-30-2010
20100330761SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Exposed are a semiconductor device and method of fabricating the same. The device includes an insulation film that is disposed between an active pattern and a substrate, which provides various improvements. This structure enhances the efficiency of high integration and offers an advanced structure for semiconductor devices.12-30-2010
20110086485METHOD FOR MANUFACTURING A MOS SEMICONDUCTOR MEMORY DEVICE, AND PLASMA CVD DEVICE - To manufacture a MOS semiconductor memory device having an insulating film laminate in which adjacent insulating films have band-gaps of different sizes, a plasma processing device which transmits microwaves to a chamber by means of a planar antenna having a plurality of holes is used to perform plasma CVD under pressure conditions that differ from at least pressure conditions used when forming the adjacent insulating films, and the insulating films are sequentially formed by altering the band-gaps of the adjacent insulating films that constitute the insulating film laminate.04-14-2011
20100022060BI-AXIAL TEXTURING OF HIGH-K DIELECTRIC FILMS TO REDUCE LEAKAGE CURRENTS - The present invention is directed to methods of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a high-K dielectric material assisted with an ion beam to enable the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric films have a high degree of crystallographic alignment at grain boundaries. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The result is a dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.01-28-2010
20120302025Method for Manufacturing a Semiconductor Structure - The present application provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate; forming a gate dielectric layer on the substrate; forming a dummy gate structure on the gate dielectric layer, wherein the dummy gate is formed from a polymer material; implanting dopants into portions of the substrates on opposite sides of the dummy gate structure to form source/drain regions; removing the dummy gate; annealing the source/drain regions to activate the dopants; and forming a metal gate. According to the present invention, it is proposed to manufacture a dummy gate structure with a polymer material, which significantly simplifies the subsequent etching process for removing the dummy gate structure and alleviates the etching difficulty accordingly.11-29-2012
20120045880METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer, a polysilicon layer, and a hard mask; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; and forming a conductive layer in the opening for forming a gate.02-23-2012
20110165750METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING STRUCTURES - In methods of manufacturing a semiconductor device, a plurality of gate structures spaced apart from each other and oxide layer patterns. A sputtering process using the oxide layer patterns as a sputtering target to connect the oxide layer patterns on the adjacent gate structures to each other is performed, so that a gap is formed between the gate structures. A volume of the gap is formed uniformly to have desired volume by controlling a thickness of the oxide layer patterns.07-07-2011
20110165749METHOD OF MAKING A SEMICONDUCTOR STRUCTURE USEFUL IN MAKING A SPLIT GATE NON-VOLATILE MEMORY CELL - A method of making a semiconductor device on a semiconductor layer is provided. The method includes: forming a select gate dielectric layer over the semiconductor layer; forming a select gate layer over the select gate dielectric layer; and forming a sidewall of the select gate layer by removing at least a portion of the select gate layer. The method further includes growing a sacrificial layer on at least a portion of the sidewall of the select gate layer and under at least a portion of the select gate layer and removing the sacrificial layer to expose a surface of the at least portion of the sidewall of the select gate layer and a surface of the semiconductor layer under the select gate layer. The method further includes forming a control gate dielectric layer, a charge storage layer, and a control gate layer.07-07-2011
20120058618Nonvolatile semiconductor storage device with charge storage layer and its manufacturing method - A method of manufacturing a nonvolatile semiconductor storage device includes sequentially forming a charge storage film, a conductive film, and a mask film on a semiconductor substrate, sequentially removing the mask film, the conductive film, and the charge storage film at a given portion to form a groove, forming a word gate electrode to fill in the groove whose inside is covered with an insulating film, after said forming the word gate electrode, removing the mask film, after said removing the mask film, forming a spacer film to cover the conductive film and the word gate electrode, etching back the spacer film to form a spacer layer on both sides of the word gate electrode through the insulating film, removing the conductive film and the charge storage film to form a control gate electrode, and forming a source drain diffusion layer.03-08-2012
20120028429METHOD OF FORMING A NON-VOLATILE ELECTRON STORAGE MEMORY AND THE RESULTING DEVICE - The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure.02-02-2012
20120156848METHOD OF MANUFACTURING NON-VOLATILE MEMORY DEVICE AND CONTACT PLUGS OF SEMICONDUCTOR DEVICE - A method of manufacturing a non-volatile memory device includes alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate, forming first openings exposing the substrate, forming sidewall insulating layers on sidewalls of the first openings, and forming channel regions on the sidewall insulating layers. The first openings penetrate the interlayer sacrificial layers and the interlayer insulating layers. The sidewall insulating layers have different thicknesses according to distances from the substrate.06-21-2012
20120156847LAYER FORMATION WITH REDUCED CHANNEL LOSS - Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.06-21-2012
20120070951SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - There is provided a semiconductor device including bit lines (03-22-2012
20100120214Method of manufacturing nonvolatile memory device and nonvolatile memory device manufactured by the method - A method of manufacturing a nonvolatile memory device having a three-dimensional memory device includes alternately stacking a plurality of first and second material layers having a different etching selectivity on a semiconductor substrate; forming an opening penetrating the plurality of first and second material layers; removing the first material layers exposed by the opening to form extended portions extending in a direction perpendicular to the semiconductor substrate from the opening; conformally forming a charge storage layer along a surface of the opening and the extended portions; and removing the charge storage layer formed on sidewalls of the second material layers to locally form the charge storage layer patterns in the extended portions.05-13-2010
20110092040SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor.04-21-2011
20110065248SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF PRODUCING THE SAME - A semiconductor integrated circuit device includes a substrate, a nonvolatile memory device formed in a memory cell region of the substrate, and a semiconductor device formed in a device region of the substrate. The nonvolatile memory device has a multilayer gate electrode structure including a tunnel insulating film and a floating gate electrode formed thereon. The floating gate electrode has sidewall surfaces covered with a protection insulating film. The semiconductor device has a gate insulating film and a gate electrode formed thereon. A bird's beak structure is formed of a thermal oxide film at an interface of the tunnel insulating film and the floating gate electrode, the bird's beak structure penetrating into the floating gate electrode along the interface from the sidewall faces of the floating gate electrode, and the gate insulating film is interposed between the substrate and the gate electrode to have a substantially uniform thickness.03-17-2011
20120122285MEMORY DEVICE HAVING TRAPEZOIDAL BITLINES AND METHOD FO FABRICATING SAME - A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.05-17-2012
20120129310METHODS OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A HIGH-K GATE DIELECTRIC LAYER AND SEMICONDUCTOR DEVICES FABRICATED THEREBY - A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.05-24-2012
20100210085METHOD FOR FABRICATING NON-VOLATILE MEMORY - A method for fabricating a non-volatile memory of the invention includes providing a substrate, and a tunnel layer is formed on the substrate. A charge-trapping layer is formed on the tunnel layer using silane (SiH08-19-2010
20100173464Non-volatile memory structure and method of fabrication - A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.07-08-2010
20100291745METHOD FOR MANUFACTURING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Bit line diffusion layers are formed in an upper part of a semiconductor substrate with a bit line contact region being interposed between the bit line diffusion layers. A conductive film is formed over the semiconductor substrate, the bit line diffusion layers, and first gate insulating films. Then, control gate electrodes are formed from the conductive film. Thereafter, at least the first gate insulating film in the bit line contact region is removed, and a connection diffusion layer is formed in the bit line contact region so as to connect the bit line diffusion layers located on both sides of the bit line contact region. When forming the control gate electrodes, the conductive film is left so as to extend over the bit line contact region and over the bit line diffusion layers located on both sides of the bit line contact region.11-18-2010
20120083086SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - There is provided a semiconductor device including a semiconductor substrate (04-05-2012
20080299730METAL OXYNITRIDE AS A pFET MATERIAL - A compound metal comprising MO12-04-2008
20080299731ERASEABLE NONVOLATILE MEMORY WITH SIDEWALL STORAGE - A nonvolatile storage cell, integrated circuit (IC) including the cells and method of manufacturing the cells. A layered spacer (ONO) is formed at least at one sidewall of cell gates. Source/drain diffusions at each layered spacer underlap the adjacent gate. Charge may be stored at a layer (an imbedded nitride layer) in the layered spacer.12-04-2008
20110003452HIGH-k CAPPED BLOCKING DIELECTRIC BANDGAP ENGINEERED SONOS AND MONOS - A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-κ material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used.01-06-2011
20110008943SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - The present invention provides a technology capable of reducing an area occupied by a nonvolatile memory while improving the reliability of the nonvolatile memory. In a semiconductor device, the structure of a code flash memory cell is differentiated from that of a data flash memory cell. More specifically, in the code flash memory cell, a memory gate electrode is formed only over the side surface on one side of a control gate electrode to improve a reading speed. In the data flash memory cell, on the other hand, a memory gate electrode is formed over the side surfaces on both sides of a control gate electrode. By using a multivalued memory cell instead of a binary memory cell, the resulting data flash memory cell can have improved reliability while preventing deterioration of retention properties and reduce its area.01-13-2011
20110045647METHODS OF FORMING NON-VOLATILE MEMORY DEVICES - A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced.02-24-2011
20100233863METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a technique capable of suppressing the diffusion of copper atoms adhering to the back face of a semiconductor substrate from the back face into the inside of the semiconductor substrate, and capable of suppressing performance degradation of semiconductor elements such as a MISFET formed at the main face of the semiconductor substrate, in semiconductor devices using copper wiring for a wiring layer. A copper diffusion prevention film formed at the main face of the semiconductor substrate is denoted by a first copper diffusion prevention film, and a copper diffusion prevention film formed at the back face of the semiconductor substrate is denoted by a second copper diffusion prevention film. The characteristic of the embodiment lies in that the second copper diffusion prevention film is formed at the back face of the semiconductor substrate. Thus, by the formation of the second copper diffusion prevention film at the back face of the semiconductor substrate prior to the formation of the copper wiring, the diffusion of copper atoms (including copper compounds) from the back face of the semiconductor substrate can be prevented.09-16-2010
20090280611NON-VOLATILE MEMORY SEMICONDUCTOR DEVICE HAVING AN OXIDE-NITRIDE-OXIDE (ONO) TOP DIELECTRIC LAYER - A non-volatile memory (NVM) cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate, a drain region in a portion of the silicon substrate, and a well region disposed in a portion of the silicon substrate between the source and drain regions. The cell includes a bottom oxide layer formed on the main surface of the substrate. The bottom oxide layer is disposed on a portion of the main surface proximate the well region. The cell includes a charge storage layer disposed above the bottom oxide layer, a dielectric tunneling layer disposed above the charge storage layer and a control gate formed above the dielectric tunneling layer. The dielectric tunneling layer includes a first oxide layer, a nitride layer and a second oxide layer. Erasing the NVM cell includes applying a positive gate voltage to inject holes from the gate.11-12-2009
20120329230FABRICATION OF SILICON OXIDE AND OXYNITRIDE HAVING SUB-NANOMETER THICKNESS - A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000° C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000° C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0.5 Å to 10 Å.12-27-2012
20120100684METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes sequentially forming a first gate insulating layer and a second gate insulating layer on a substrate, implanting impurity ions into the substrate and performing a first thermal process for activating the impurity ions to form a source and drain region, and forming a third gate insulating layer on the substrate after the first thermal process has been completed.04-26-2012
20130023100METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device, the method including forming on a substrate a transistor that includes a gate electrode and a source and drain region, forming an interlayer insulating film on the transistor, forming a contact hole in the interlayer insulating film to expose a top surface of the source and drain region, and a thin film is formed at an interface between the contact hole and the exposed top surface of the source and drain region. The method further including selectively removing at least a portion of the thin film by performing an etching process in a non-plasma atmosphere, forming an ohmic contact film on the source and drain region where at least a portion of the thin film was selectively removed, and forming a contact plug by filling the contact hole with a conductive material.01-24-2013
20110159656METHOD FOR MANUFACTURING A MOSFET WITH A SURROUNDING GATE OF BULK SI - A method for manufacturing a bulk Si nanometer surrounding-gate MOSFET based on a quasi-planar process, including: local oxidation isolation or shallow trench isolation; depositing buffer SiO06-30-2011
20130023099METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In one embodiment, a method of manufacturing a nonvolatile semiconductor memory includes forming a plurality of memory cell transistors and a plurality of selection transistors on a substrate. The method further includes burying first and second insulators successively between memory cell transistors and between a memory cell transistor and a selection transistor, and forming the first and second insulators successively on side surfaces of selection transistors, the side surfaces facing a space between the selection transistors. The method further includes burying third to fifth insulators successively between the selection transistors via the first and second insulators. The method further includes removing the second and fourth insulators by a first etching so that the second and fourth insulators partially remain between the selection transistors. The method further includes removing the second and fourth insulators remaining between the selection transistors by a second etching performed after the first etching.01-24-2013
20130023098MANUFACTURING METHOD FOR METAL GATE - A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.01-24-2013
20130178030METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOW - An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.07-11-2013
20130178031INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES - An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunneling layer; and forming a MOS device over a second region of the substrate.07-11-2013
20110230028MANUFACTURING METHOD OF STRAIGHT WORD LINE NOR TYPE FLASH MEMORY ARRAY - In a manufacturing method of a straight word line NOR flash memory array, a source line is implanted after the formation of a word line in the NOR type flash memory array is completed, and a discrete implant region is formed in the NOR type flash memory array and parallel to a component isolation structure, and each discrete implant region constitutes an electric connection with a low impedance between a source line and source contacts on the source line. With such discrete distribution, adjacent memory cells will not be short-circuited or failed even if a deviation of a mash occurs during the manufacturing process.09-22-2011
20120282748Method for manufacturing stack structure of PMOS device and adjusting gate work function - The present disclosure provides a method for manufacturing a gate stack structure and adjusting a gate work function for a PMOS device, comprising: growing an ultra-thin interface oxide layer or oxynitride layer on a semiconductor substrate by rapid thermal oxidation or chemical method after conventional LOCOS or STI dielectric isolation is completed; depositing high-K gate dielectric and performing rapid thermal annealing; depositing a composite metal gate; depositing a barrier metal layer; depositing a polysilicon film and a hard mask and then performing photolithography and etching the hard mask; removing photoresist and etching the polysilicon film, the barrier metal layer, the metal gate, the high-K gate dielectric, and the interface oxide layer in sequence to form a gate stack structure of polysilicon film/barrier metal layer/metal gate/high-K gate dielectric; forming spacers, source/drain implantation in a conventional manner and performing rapid thermal annealing, whereby while source/drain dopants are activated, adjusting of metal gate effective work function of the PMOS device is achieved.11-08-2012
20130203230SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate is provided. An ozone saturated deionized water process is performed to form an oxide layer on the substrate. A dielectric layer is formed on the oxide layer. A post dielectric annealing (PDA) process is performed on the dielectric layer and the oxide layer.08-08-2013
20130210209METHOD OF INTEGRATING A CHARGE-TRAPPING GATE STACK INTO A CMOS FLOW - Embodiments of a method of integration of a non-volatile memory device into a MOS flow are described. Generally, the method includes: forming a dielectric stack on a surface of a substrate, the dielectric stack including a tunneling dielectric overlying the surface of the substrate and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack; patterning the cap layer and the dielectric stack to form a gate stack of a memory device in a first region of the substrate and to remove the cap layer and the charge-trapping layer from a second region of the substrate; and performing an oxidation process to form a gate oxide of a MOS device overlying the surface of the substrate in the second region while simultaneously oxidizing the cap layer to form a blocking oxide overlying the charge-trapping layer. Other embodiments are also disclosed.08-15-2013

Patent applications in class Gate insulator structure constructed of diverse dielectrics (e.g., MNOS, etc.) or of nonsilicon compound