Entries |
Document | Title | Date |
20080199997 | Methods of Forming Inter-poly Dielectric (IPD) Layers in Power Semiconductor Devices - A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities. | 08-21-2008 |
20080227255 | Methods of Forming Vertical Transistors - A vertical transistor forming method includes forming a first pillar above a first source/drain and between second and third pillars, providing a first recess between the first and second pillars and a wider second recess between the first and third pillars, forming a gate insulator over the first pillar, forming a front gate and back gate over opposing sidewalls of the first pillar by depositing a gate conductor material within the first and second recesses and etching the gate conductor material to substantially fill the first recess, forming the back gate, and only partially fill the second recess, forming the front gate, forming a second source/drain elevationally above the first source/drain, and providing a transistor channel in the first pillar. The channel is operationally associated with the first and second sources/drains and with the front and back gates to form a vertical transistor configured to exhibit a floating body effect. | 09-18-2008 |
20080242028 | METHOD OF MAKING THREE DIMENSIONAL NAND MEMORY - A method of making a monolithic, three dimensional NAND string including a first memory cell located over a second memory cell, includes growing a semiconductor active region of second memory cell, and epitaxially growing a semiconductor active region of the first memory cell on the semiconductor active region of the second memory cell in a different growth step from the step of growing the semiconductor active region of second memory cell. | 10-02-2008 |
20080242029 | METHOD AND STRUCTURE FOR MAKING A TOP-SIDE CONTACT TO A SUBSTRATE - A method for forming a semiconductor structure includes the following steps. A starting semiconductor substrate having a top-side surface and a back-side surface is provided. A recess is formed in the starting semiconductor substrate through the top-side of the starting semiconductor substrate. A semiconductor material is formed in the recess. A vertically conducting device is formed in and over the semiconductor material, where the starting semiconductor substrate serves as a terminal of the vertically conducting device. A non-recessed portion of the starting semiconductor substrate allows a top-side contact to be made to portions of the starting semiconductor substrate extending beneath the semiconductor material. | 10-02-2008 |
20080274599 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A TRENCH SURROUNDING PLURAL UNIT CELLS - A semiconductor device comprises a plurality of unit cells, each comprising a vertical metal oxide semiconductor field effect transistor (MOSFET). The unit cell includes a first source region formed in a first base region, a second source region formed in the first base region and separated from the first source region, and a second base region formed in the first base region and disposed between the first and second source regions. The semiconductor device further comprises a trench gate formed in a vicinity of each of the plurality of unit cells. The second base region of an unit cell is separated from the second base region of an adjacent unit cell, and the first or second source region of an unit cell is separated from the first or second source region of an adjacent unit cell. | 11-06-2008 |
20080293202 | Method for manufacturing semiconductor device - A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode. | 11-27-2008 |
20080299725 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing semiconductor devices comprises forming an semiconductor layer of the first conduction type on a substrate of the first conduction type; forming an anti-oxidizing layer on the surface of the semiconductor layer of the first conduction type, the anti-oxidizing layer having an aperture only through a region for use in formation of a guard ring layer of the second conduction type; forming the guard ring layer of the second conduction type in the surface of the semiconductor layer of the first conduction type through implantation of ions into a surface where said anti-oxidizing layer is formed; forming an oxide layer at least in the aperture; forming a base layer of the second conduction type adjacent to the guard ring layer of the second conduction type in the surface of the semiconductor layer of the first conduction type; and forming a diffused layer of the first conduction type through implantation of ions into the base layer of the second conduction type. | 12-04-2008 |
20080299726 | SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS - A semiconductor apparatus with a superjunction structure includes a gate electrode which fills a trench that is formed in an epitaxial layer, and a column region which is surrounded by the gate electrode in a plane view. A photomask for forming the column region is elaborated. The photomask has a compensation pattern that compensates a deformation of a photo resist pattern caused by photo interference and a deformation of the ion implantation region diffused by heat treatment. Therefore extending direction of the gate electrode and the outer edge of the column region are substantially parallel. | 12-04-2008 |
20080299727 | Vertical trench gate transistor semiconductor device and method for fabricating the same - A first region functioning as a transistor includes a drain region, a body region formed over the drain region, a source region formed over the body region and a trench formed through the body region and having a gate electrode buried therein. A source region is formed over the body region extending in a second region. The source region forming an upper edge of the trench is rounded. | 12-04-2008 |
20080318383 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, including: preparing a semiconductor substrate having an element-isolating film filled in the first trench and an active region; forming a mask-forming film over the semiconductor substrate; forming a first mask having an opening traversing the active region; performing anisotropic etching using the first mask to form a second mask made of the mask-forming film and a second trench having opposite exposed surfaces of the element-isolating film, being shallower than the first trench and being formed in the active region; implanting oxygen ions obliquely using the second mask such that oxygen ions are radiated at a region including a boundary between a surface of the semiconductor substrate inside the second trench and one of the opposite exposed surfaces of the element-isolating film; oxidizing the oxygen ion-implanted region inside the second trench to form an oxidized region; and removing the oxidized region. | 12-25-2008 |
20090004797 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a plurality of pillars which are arranged on a substrate in a first direction and a second direction that intersects the first direction, thereby forming a resulting structure, forming a capping layer on the resulting structure including the pillars, removing the capping layer formed on the substrate between the pillars to expose the substrate between the pillars, thereby forming a resulting structure, forming a metal layer on the resulting structure, forming a silicide layer on the exposed substrate between the pillars by applying a first heat treatment to the metal layer, removing a non-reacted silicide layer, and forming an isolation trench in the substrate which is between rows of the pillars arranged in the first direction and is under the silicide layer to define bit lines which surround the pillars and are extended to the first direction. | 01-01-2009 |
20090004798 | Recessed Gate Structure With Stepped Profile - Disclosed herein are a recess-gate structure in which junctions have a thickness significantly smaller than the thickness of a device isolation layer to thereby prevent shorting of the junctions located at opposite lateral sides of the device isolation layer close thereto, resulting in an improvement in the operational reliability of a resultant device, and a method for forming the same. The recess-gate structure comprises a silicon substrate in which an active region and a device isolation region are defined, a plurality of gates formed on the substrate, gate spacers formed at the side wall of the respective gates, and junctions formed in the substrate at opposite lateral sides of the gates and defining an asymmetrical structure relative to each other. A gate recess is defined in the active region of the substrate to have a stepped profile consisting of a bottom plane, top plane, and vertical plane. The bottom plane of the stepped gate recess exists in only the active region except for the device isolation region. | 01-01-2009 |
20090023261 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, includes the steps of forming a dummy gate insulating film and a dummy gate electrode, forming source and drain regions, forming a first insulating film, forming a second insulating film, removing the second insulating film, simultaneously removing the first insulating film and the second insulating film that remains, while planarizing the first insulating film and the second insulating film that remains, forming a gate electrode trench by removing the dummy gate electrode and the dummy gate insulating film, forming a gate insulating film, and forming a gate electrode, wherein a field effect transistor is formed by the method. | 01-22-2009 |
20090035908 | PROCESS FOR FABRICATING A NANOWIRE-BASED VERTICAL TRANSISTOR STRUCTURE - The invention relates to a process for fabricating a vertical transistor structure. On a substrate ( | 02-05-2009 |
20090053869 | METHOD FOR PRODUCING AN INTEGRATED CIRCUIT INCLUDING A TRENCH TRANSISTOR AND INTEGRATED CIRCUIT - A method for producing an integrated circuit including a trench transistor and an integrated circuit is disclosed. | 02-26-2009 |
20090061584 | Semiconductor Process for Trench Power MOSFET - The present invention provides a semiconductor process for a trench power MOSFET. The semiconductor process includes providing a substrate, forming an EPI wafer on the surface, performing trench dry etching, performing HTP hard mask oxide deposition and channel self- align implant, performing boron (B) implant and completing the P-body region through a thermal process, performing arsenic (As) implant and completing the n+ source region through a thermal process, and depositing BPSG ILD, front side metal Al, and backside metal Ti/Ni/Ag. | 03-05-2009 |
20090061585 | High-voltage vertical transistor with a multi-gradient drain doping profile - A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 03-05-2009 |
20090068806 | FIELD EFFECT TRANSISTOR - A field effect transistor is provided. The field effect transistor includes a channel region, electrically conductive channel connection regions, and a control region. The electrically conductive channel connection regions adjoin the channel region along with a transistor dielectric. The control region is separated from the channel region by the transistor dielectric. In addition, the control region may comprise a monocrystalline material. | 03-12-2009 |
20090075444 | Method of forming semiconductor device having three-dimensional channel structure - A method of forming a semiconductor device is provided. A hollowed portion is formed over an active region of a semiconductor substrate. The bottom of the hollowed portion is lowered in level than the surface of an isolation region of the substrate. A first mask is formed in the hollowed portion, except on a side region that is adjacent to the boundary between the active region and the isolation region. A trench is formed in the side region of the active region by using the first mask and the isolation region as a mask. | 03-19-2009 |
20090098701 | Method of manufacturing an integrated circuit - The present invention provides a method of manufacturing an integrated circuit comprising the steps of: providing a semiconductor substrate, etching at least one trench into a surface of said semiconductor substrate, performing an ion implantation step, wherein a direction of said ion implantation step is parallel to a vertical centre line of said trench, and performing a single oxidation step to form a first oxide layer with a first layer thickness covering a bottom of said at least one trench and a second oxide layer with a second layer thickness covering the sidewalls of said at least one trench, wherein said first layer thickness differs from said second layer thickness. | 04-16-2009 |
20090104744 | VERTICAL GATED ACCESS TRANSISTOR - According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The plurality of shallow trenches and the plurality of deep trenches are parallel to each other. The method further comprises depositing a layer of conductive material over the first region and a second region of the substrate. The method further comprises etching the layer of conductive material to define a plurality of lines separated by a plurality of gaps over the first region of the substrate, and a plurality of active device elements over the second region of the substrate. The method further comprises masking the second region of the substrate. The method further comprises removing the plurality of lines from the first region of the substrate, thereby creating a plurality of exposed areas from which the plurality of lines were removed. The method further comprises etching a plurality of elongate trenches in the plurality of exposed areas while the second region of the substrate is masked. | 04-23-2009 |
20090111230 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 04-30-2009 |
20090111231 | Method for Forming Shielded Gate Field Effect Transistor Using Spacers - A trench is formed in a semiconductor region. A dielectric layer lining sidewalls and bottom surface of the trench is formed. The dielectric layer is thicker along lower sidewalls and the bottom surface than along upper sidewalls of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. Dielectric spacers are formed along the upper trench sidewalls. After forming the dielectric spacers, an inter-electrode dielectric (IED) is formed in the trench over the shield electrode. After forming the IED, the dielectric spacers are removed. | 04-30-2009 |
20090117699 | METHOD FOR PREPARING A RECESSED TRANSISTOR STRUCTURE - A method for preparing a recessed transistor structure comprises the steps of performing an implanting process to form a doped layer in a substrate, forming a plurality of gate-isolation blocks on the substrate, forming a plurality of first spacers on sidewalls of the gate-isolation blocks, removing a portion of the substrate not covered by the first spacers and the gate-isolation blocks to form a plurality of depressions in the substrate between the first spacers, forming a gate oxide layer on inner sidewalls of the depressions, and forming a gate structure on the gate oxide layer to complete the recessed transistor structure. | 05-07-2009 |
20090117700 | Method for Manufacturing a Trench Power Transistor - A method for manufacturing a trench power transistor includes providing a substrate, forming an epitaxy layer on the substrate, performing a dry etching process on the epitaxy layer for generating a first trench, forming a gate oxide layer in the first trench and depositing poly-Si on the gate oxide layer in the first trench, performing a boron implant process on regions outside the first trench and inside the epitaxy layer, performing an arsenic implant process on regions beside the first trench and inside the epitaxy layer, depositing a first dielectric material on the surface of the epitaxy layer, performing a dry etching process on the epitaxy layer for generating a second trench, depositing a conductive material in the second trench for forming a p-well junction on sidewalls of the second trench, and performing a wet immersion process for forming a contact hole, and depositing frontside and backside metal. | 05-07-2009 |
20090130811 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH UNIFORM CONCENTRATION ION DOPING IN RECESS GATE CHANNEL REGION - A semiconductor device is manufactured by defining a groove in a semiconductor substrate, where the groove includes an upper portion and a lower portion, among other steps. A sacrificial layer is then formed to selectively fill the lower portion of the groove. Impurity ions are implanted into the semiconductor substrate while the lower portion of the groove is filled with the sacrificial layer. The sacrificial layer is then removed, and a gate is formed on the groove. In the method for manufacturing the semiconductor device, impurities can be doped at a uniform concentration in the channel area of the semiconductor device. | 05-21-2009 |
20090148993 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING A RECESS CHANNEL STRUCTURE THEREIN - A method of fabricating a semiconductor device having a recess channel structure is provided. A first recess is formed in a substrate. A liner and a filling layer are formed in the first recess. A portion of the substrate adjacent to the first recess and a portion of the liner and the filling layer are removed to form trenches. An insulation layer fills the trenches to form isolation structures. The filling layer is removed, using the liner as an etching stop layer, to expose the insulation layer. A portion of the exposed insulation layer is removed to form a second recess having divots adjacent to the sidewalls of the substrate. The liner is removed. A dielectric layer and a gate are formed over the substrate covering the second recess. Source and drain regions are formed in the substrate adjacent to the second recess. | 06-11-2009 |
20090148994 | Method of manufacturing semiconductor device with recess gate transistor - A method of manufacturing a semiconductor device includes forming a plurality of recesses in a semiconductor substrate, forming a gate insulating film in the plurality of recesses, and a plurality of gate electrodes on the gate insulating film in the plurality of recesses, forming an insulating layer on the semiconductor substrate and the plurality of gate electrodes, forming a plurality of contact holes in the insulating layer, the contact holes being formed between adjacent ones of the plurality of gate electrodes, implanting a first impurity into the semiconductor substrate through the plurality of contact holes to form each of source and drain regions in contact with the gate insulating film. | 06-11-2009 |
20090170265 | Method of Fabricating a Recess Gate Type Transistor - A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween. | 07-02-2009 |
20090176342 | Method of fabricating semiconductor device having deifferential gate dielectric layer and related device - A semiconductor device and method of fabricating a semiconductor device are provided. The method includes forming a gate trench in a semiconductor substrate to define source/drain regions. The source/drain regions are separated from each other by the gate trench, and the semiconductor substrate is exposed through the gate trench. The semiconductor substrate has impurities of a first conductivity type. The source/drain regions have impurities of a second conductivity type different from the first conductivity type. The concentration of the second conductivity type impurities increases as the impurities approach the surfaces of the source/drain regions. A differential gate dielectric layer is formed along the surfaces of the source/drain regions and the semiconductor substrate exposed through the gate trench. A gate electrode filling the gate trench is formed. The differential gate dielectric layer has a first thickness between the gate electrode and the semiconductor substrate and has a second thickness greater than the first thickness between the gate electrode: and the source/drain regions. | 07-09-2009 |
20090191678 | Method of Forming a Shielded Gate Field Effect Transistor - A semiconductor region with an epitaxial layer extending over the semiconductor region is provided. A first silicon etch is performed to form an upper trench portion extending into and terminating within the epitaxial layer. A protective material is formed extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion. A second silicon etch is performed to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the semiconductor region, such that the lower trench portion is narrower than the upper trench portion. A two-pass angled implant of dopants of the first conductivity type is carried out to form a silicon region of first conductivity type along sidewalls of the lower trench portion, while the protective material blocks the implant dopants from entering the sidewalls of the upper trench portion and the mesa region adjacent the upper trench portion. | 07-30-2009 |
20090197380 | METHOD FOR MANUFACTURING A RECESSED GATE TRANSISTOR - A method of manufacturing a recessed gate transistor includes forming a hard mask pattern over a substrate; and then forming a trench in the substrate by performing an etching process using the hard mask pattern as an etch mask; and then performing a pullback-etching process on the hard mask pattern to expose a source region in the substrate; and then forming a gate silicon layer in the trench and over the substrate including the hard mask pattern after performing the pullback-etching process; and then performing an etch-back process on the gate silicon layer to expose the hard mask pattern such that the uppermost surface of the gate silicon layer is below the uppermost surface of the hard mask pattern; and then removing the hard mask pattern; and then simultaneously etching the gate silicon layer and the exposed portion of the substrate. | 08-06-2009 |
20090209073 | Gate Structure in a Trench Region of a Semiconductor Device and Method for Manufacturing the Same - Disclosed are a gate structure in a trench region of a semiconductor device and a method for manufacturing the same. The semiconductor device includes a pair of drift regions formed in a semiconductor substrate; a trench region formed between the pair of drift regions; an oxide layer spacer on sidewalls of the trench region; a gate formed in the trench region; and a source and a drain formed in the pair of the drift regions, respectively. | 08-20-2009 |
20090215237 | Method of forming lateral trench MOSFET with direct trench polysilicon contact - A lateral trench MOSFET includes a trench containing a device segment and a gate bus segment. The gate bus segment of the trench is contacted by a conductive plug formed in a dielectric layer overlying the substrate, thereby avoiding the need for the conventional surface polysilicon bridge layer. The conductive plug is formed in a substantially vertical hole in the dielectric layer. The gate bus segment may be wider than the device segment of the trench. A method includes forming a shallow trench isolation (STI) while the conductive material in the trench is etched. | 08-27-2009 |
20090215238 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH ENLARGED RECESSED GATE ELECTRODES - A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed. | 08-27-2009 |
20090215239 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A trench gate type power transistor of high performance is provided. A trench gate as a gate electrode is formed in a super junction structure comprising a drain layer and an epitaxial layer. In this case, the gate electrode is formed in such a manner that an upper surface of the epitaxial layer becomes higher than that of a channel layer formed over the drain layer. Then, an insulating film is formed over each of the channel layer and the epitaxial layer and thereafter a part of the insulating film is removed to form side wall spacers over side walls of the epitaxial layer. Subsequently, with the side wall spacers as masks, a part of the channel layer and that of the drain layer are removed to form a trench for a trench gate. | 08-27-2009 |
20090233408 | Semiconductor device manufacturing method - A method of manufacturing a semiconductor device having a polycrystalline silicon layer ( | 09-17-2009 |
20090233409 | METHOD FOR PRODUCTION OF SEMICONDUCTOR DEVICE - A method for producing a semiconductor device, the method includes the steps of: forming a hard mask layer with a mask opening on a semiconductor substrate in which is formed a source region; forming a side wall mask on the side wall of the mask opening; forming a trench by using the side wall mask and the hard mask layer as a mask in such a way that the trench reaches the source region; removing the side wall mask; forming a gate electrode inside the mask opening and the trench, with a gate insulating film interposed thereunder; forming a side wall on the side wall of the gate electrode; and forming a drain region on the surface of the semiconductor substrate which is adjacent to the gate electrode. | 09-17-2009 |
20090239346 | SEMICONDUCTOR DEVICE WITH FINFET AND METHOD OF FABRICATING THE SAME - A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of a central trench formed in a central portion of the active region. Upper surfaces and side surfaces of the first projection and the second projection comprise a channel region. A channel ion implantation layer is provided at a bottom of the central trench and at a lower portion of the fin. A gate oxide layer is provided on the fin. A gate electrode is provided on the gate oxide layer. A source region and a drain region are provided in the active region at sides of the gate electrode. A method of forming such a device is also provided. | 09-24-2009 |
20090246923 | Method of Forming Shielded Gate FET with Self-aligned Features - A method for forming a shielded gate field effect transistor includes the following steps. Trenches are formed in a semiconductor region of a first conductivity type. A shield electrode is formed in a bottom portion of each trench, the shield electrode being insulated from the semiconductor region by a shield dielectric. A gate electrode recessed in each trench is formed over the shield electrode, the gate electrode being insulated from the shield electrode. Using a first mask, a body region of a second conductivity type is formed in the semiconductor region by implanting dopants. Using the first mask, source regions of the first conductivity type are formed in the body region by implanting dopants. | 10-01-2009 |
20090253237 | Scalable Power Field Effect Transistor with Improved Heavy Body Structure and Method of Manufacture - A method for forming a field effect transistor (FET) includes the following steps. A well region of a first conductivity type is formed in a semiconductor region of a second conductivity type. A gate electrode is formed adjacent to but insulated from the well region. A source region of the second conductivity type is formed in the well region. A heavy body recess is formed extending into and terminating within the well region adjacent the source region. The heavy body recess is at least partially filled with a heavy body material having a lower energy gap than the well region. | 10-08-2009 |
20090258467 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a vertical transistor in a semiconductor device improves integration of the semiconductor device according to a design rule. After a semiconductor substrate is etched to form a buried bit line, a gate electrode pattern that surrounds a cylindrical channel region pattern of the vertical transistor is formed, thereby preventing damage to the gate electrode pattern due to an etching process. The gate electrode pattern surrounds the channel region pattern where a width is narrower than second source and drain regions. The second source and drain regions are then deposited over the channel region pattern and the gate electrode pattern. As a result, a neck-shaped channel region does not collapse due to the weight of the second source and drain regions. | 10-15-2009 |
20090269895 | Method of Manufacturing Non-Volatile Memory Device - Non-volatile memory devices and a method of manufacturing the same, wherein data storage of two bits per cell is enabled and the devices can pass the limit in terms of layout, whereby channel length can be controlled. The non-volatile memory device includes gate lines formed in one direction on a semiconductor substrate in which trenches are formed, wherein the gate lines gap-fill the trenches, a dielectric layer formed between the semiconductor substrate and the gate lines, bit separation insulating layers formed between the semiconductor substrate and the dielectric layer under the trenches, and isolation structures formed by etching the trenches, and the dielectric layer and the semiconductor substrate between the trenches in a line form vertical to the gate lines and gap-filling an insulating layer. | 10-29-2009 |
20090280609 | Method of making silicon carbide semiconductor device - In a method of making a silicon carbide semiconductor device having a MOSFET, after a mask is placed on a surface of a first conductivity type drift layer of silicon carbide, ion implantation is performed by using the mask to form a lower layer of a deep layer extending in one direction. A first conductivity type current scattering layer having a higher concentration than the drift layer is formed on the surface of the drift layer. After another mask is placed on a surface of the current scattering layer, ion implantation is performed by using the other mask to form an upper layer of the deep layer at a position corresponding to the lower layer in such a manner that the lower layer and the upper layer are connected together. | 11-12-2009 |
20090280610 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including a buried insulating film formed in a bottom part of a trench and a buried-type gate electrode formed in the trench, the method including selectively forming an insulating film in the bottom part of the trench, forming a resist having an opening in a part that corresponds to a region where a device isolation insulating film is formed on a surface of a semiconductor substrate after forming the insulating film, and oxidizing the surface of the semiconductor substrate in the opening to form the device isolation insulating film. | 11-12-2009 |
20090286371 | Formation of a MOSFET Using an Angled Implant - A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n | 11-19-2009 |
20090286372 | SUPERJUNCTION TRENCH DEVICE FORMATION METHODS - Methods for forming semiconductor structures are provided for a semiconductor device employing a superjunction structure and overlying trench with embedded control gate. An embodiment comprises forming interleaved first and second spaced-apart regions of first and second semiconductor materials of different conductivity type and different mobilities so that the second semiconductor material has a higher mobility for the same carrier type than the first semiconductor material, and providing an overlying third semiconductor material in which a trench is formed with sidewalls having thereon a fourth semiconductor material that has a higher mobility than the third material, adapted to carry current between source regions, through the fourth semiconductor material in the trench and the second semiconductor material in the device drift space to the drain. In a further embodiment, the first and third semiconductor materials are relaxed materials and the second and fourth semiconductor materials are strained semiconductor materials. | 11-19-2009 |
20090291541 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES WITH LOCAL RECESS CHANNEL TRANSISTORS - A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a V | 11-26-2009 |
20090311839 | Method for manufacturing silicon carbide semicondutor device having trench gate structure - A manufacturing method of a SiC device includes: forming a drift layer on a substrate having an orientation tilted from a predetermined orientation with an offset angle; obliquely implanting a second type impurity with a mask on the drift layer so that a deep layer is formed in the drift layer, wherein the impurity is implanted to cancel the offset angle; forming a base region on the deep layer and the drift layer; implanting a first type impurity on the base region so that a high impurity source region is formed; forming a trench having a bottom shallower than the deep layer on the source region to reach the drift layer; forming a gate electrode in the trench via a gate insulation film; forming a source electrode on the source region and the base region; and forming a drain electrode on the substrate. | 12-17-2009 |
20100015769 | Power Device With Trenches Having Wider Upper Portion Than Lower Portion - A method of forming a semiconductor device includes the following. A masking layer with opening is formed over a silicon layer. The silicon layer is isotropically etched through the masking layer openings so as to remove bowl-shaped portions of the silicon layer, each of which includes a middle portion and outer portions extending directly underneath the masking layer. The outer portions form outer sections of corresponding trenches. Additional portions of the silicon layer are removed through the masking layer openings so as to form a middle section of the trenches which extends deeper into the silicon layer than the outer sections of the trenches. A first doped region of a first conductivity type is formed in an upper portion of the silicon layer. An insulating layer is formed within each trench, and extends directly over a portion of the first doped region adjacent each trench sidewall. Silicon is removed from adjacent each trench until, of the first doped region, only the portions adjacent the trench sidewalls remain. The remaining portions of the first doped region adjacent the trench sidewalls form source regions which are self-aligned to the trenches. | 01-21-2010 |
20100015770 | Double gate manufactured with locos techniques - This invention discloses a method for manufacturing a trenched semiconductor power device that includes step of opening a trench in a semiconductor substrate. The method further includes a step of opening a top portion of the trench first then depositing a SiN on sidewalls of the top portion followed by etching a bottom surface of the top portion of the trench then silicon etching to open a bottom portion of the trench with a slightly smaller width than the top portion of the trench. The method further includes a step of growing a thick oxide layer along sidewalls of the bottom portion of the trench thus forming a bird-beak shaped layer at an interface point between the top portion and bottom portion of the trench. | 01-21-2010 |
20100041196 | Method for Fabricating a Transistor having a Recess Gate Structure - A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate. | 02-18-2010 |
20100041197 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING RECESSED-CHANNEL-ARRAY MOSFET HAVING A HIGHER OPERATIONAL SPEED - A semiconductor device includes a recessed-channel-array MOSFET including a gate electrode having a portion received in a recess. The gate insulting film has a first portion made of silicon oxide in contact with the sidewall of the recess and a second portion made of silicon oxynitride in contact with the bottom of the recess. The first portion has an equivalent oxide thickness larger than the equivalent oxide thickness of the second portion to reduce the parasitic capacitance of the gate electrode. | 02-18-2010 |
20100055857 | METHOD OF FORMING A POWER DEVICE - A method of forming a power device includes providing a substrate, a semiconductor layer having at least a trench and being disposed on the substrate, a gate insulating layer covering the semiconductor layer, and a conductive material disposed in the trench, performing an ion implantation process to from a body layer, performing a tilted ion implantation process to from a heavy doped region, forming a first dielectric layer overall, performing a chemical mechanical polishing process until the body layer disposed under the heavy doped region is exposed to form source regions on the opposite sides of the trench, and forming a source trace directly covering the source regions disposed on the opposite sides of the trench. | 03-04-2010 |
20100087039 | Methods for manufacturing trench MOSFET with implanted drift region - A method to manufacture a trenched semiconductor power device including a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The method for manufacturing the trenched semiconductor power device includes a step of carrying out a tilt-angle implantation through sidewalls of trenches to form drift regions surrounding the trenches at a lower portion of the body regions with higher doping concentration than the epi layer for Rds reduction, and preventing a degraded breakdown voltage due to a thick oxide in lower portion of trench sidewall and bottom. In an exemplary embodiment, the step of carrying out the tilt-angle implantation through the sidewalls of the trenches further includes a step of carrying out a tilt angle implantation with a tilt-angle ranging between 4 to 30 degrees. | 04-08-2010 |
20100093144 | SEMICONDUCTOR DEVICE UTILIZING A METAL GATE MATERIAL SUCH AS TUNGSTEN AND METHOD OF MANUFACTURING THE SAME - Known drawbacks associated with use of tungsten as a gate material in a semiconductor device are prevented. A gate oxide layer, a polysilicon layer, and a nitride layer are sequentially formed on a semiconductor substrate having a isolation layer for defining the active region. A groove is formed by etching the nitride layer. A metal nitride layer is formed to an U shape in the groove, and then a metal layer is formed to bury the groove. A hard mask layer is formed for defining a gate forming region on the nitride layer, the metal nitride layer, and the metal layer. A metal gate is formed by etching the nitride layer, the polysilicon layer, and the gate oxide layer using the hard mask layer as an etch barrier. | 04-15-2010 |
20100099230 | Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer - This invention discloses a method of manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide. | 04-22-2010 |
20100105181 | METHODS OF FABRICATING VERTICAL TWIN-CHANNEL TRANSISTORS - A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions. | 04-29-2010 |
20100105182 | Shallow source MOSFET - Fabricating a semiconductor device includes forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate having a gate top surface that extends substantially above the top substrate surface at least in center region of the trench opening, the gate having a vertical edge that includes an extended portion, the extended portion extending above the trench opening and being substantially aligned with the trench wall. It further includes implanting a body, implanting a plurality of source regions embedded in the body, forming a plurality of spacers that insulate the source regions from the gate, the plurality of spacers being situated immediately adjacent to the gate and immediately adjacent to respective ones of the plurality of source regions, wherein the plurality of spacers do not substantially extend into the trench and do not substantially extend over the trench, disposing a dielectric layer over the source, the spacers, the gate, and at least a portion of the body, forming a contact opening, and disposing metal to form a contact with the body at the contact opening. | 04-29-2010 |
20100151642 | FABRICATION METHOD OF TRENCHED METAL-OXIDE-SEMICONDUCTOR DEVICE - A fabrication method of a trenched metal-oxide-semiconductor device is provided. Firstly, an epitaxial layer is formed on a substrate. Then, a plurality of gate trenches is formed in the epitaxial layer. Afterward, a spacer is formed on the sidewall of the trench gates. The spacer is utilized as a mask to selectively implant oxygen ion into the bottom of the gate trenches so as to form a bottom oxide layer on the bottom of the gate trenches to reduce capacitance between gate and drain. | 06-17-2010 |
20100151643 | METHOD FOR PRODUCING AN INTEGRATED CIRCUIT INCLUDING A TRENCH TRANSISTOR AND INTEGRATED CIRCUIT - A method for producing an integrated circuit including a trench transistor and an integrated circuit is disclosed. | 06-17-2010 |
20100151644 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A type semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a plurality of gate electrodes which are formed in gate trenches via gate insulating films, the gate trenches being formed through the second semiconductor layer and the third semiconductor layer; a plurality of impurity regions of the second conductivity type which are formed at regions below bottoms of contact trenches, the contact trenches being formed at the third semiconductor layer in a thickness direction thereof between corresponding ones of the gate trenches and longitudinal cross sections of the contact trenches being shaped in ellipse, respectively; first electrodes which are formed so as to embed the contact trenches and contacted with the impurity regions, respectively; and a second electrode formed on a rear surface of the semiconductor substrate. | 06-17-2010 |
20100173461 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region. | 07-08-2010 |
20100184264 | MANUFACTURING METHOD OF SEMICONDUCTOR POWER DEVICES - Disclosed is a power semiconductor device, in particular, a trench type power semiconductor device for use in power electronic devices. A method of manufacturing the same is provided. The method of manufacturing the power semiconductor device adopts a trench MOSFET to decrease the size of the device, in place of a vertical type DMOSFET, under a situation in which the cost must be lowered owing to excessive cost competition. As the manufacturing process is simplified and the characteristics are improved, the cost is reduced, resulting in mass production and the creation of profit. | 07-22-2010 |
20100190307 | HIGH DENSITY TRENCH MOSFET WITH SINGLE MASK PRE-DEFINED GATE AND CONTACT TRENCHES - Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches that are wider than those trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact. | 07-29-2010 |
20100203695 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A semiconductor device includes an insulation layer disposed on a substrate having a first area and a second area, a first wiring disposed on the insulation layer in the first area, a first active structure disposed on the first wiring, a first gate insulation layer enclosing the first upper portion, a first gate electrode disposed on the first gate insulation layer, a first impurity region disposed at the first lower portion, and a second impurity region disposed at the first upper portion. The first wiring may extend in a first direction. The first active structure includes a first lower portion extending in the first direction and a first upper portion protruding from the first lower portion. The first gate electrode may extend in a second direction. The first impurity region may be electrically connected to the first wiring. | 08-12-2010 |
20100203696 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device suitable for preventing a threshold voltage of a recess gate from decreasing due to a voltage of an adjacent storage node comprises a semiconductor substrate having an active region which includes a gate area and a storage node contact area and is recess in the gate area; a device isolation structure formed in the semiconductor substrate to define the active region and having a shield layer therein; a recess gate formed in the gate area of the semiconductor substrate; and a storage node formed to be connected with the storage node contact area of the active region. | 08-12-2010 |
20100216290 | Method for forming semiconductor device - A method for forming semiconductor device, which simultaneously forms a trench MOS transistor device, and an embedded schottky barrier diode (SBD) device in a semiconductor substrate. The embedded SBD device has lower forward voltage drop, which reduces power dissipation. In addition, the voltage bearing ability may be modified easily by virtue of altering the dopant concentration or the width of the voltage bearing dopant region, or the thickness of epitaxial silicon layer. Furthermore, extra cost of purchasing SBD diode may be saved. | 08-26-2010 |
20100216291 | Methods of fabricating semiconductor devices and semiconductor devices including threshold voltage control regions - A semiconductor device includes a semiconductor substrate including isolation regions defining first and second active regions having a first and second conductivity type, respectively, first threshold voltage control regions in predetermined regions of the first active region, wherein the first threshold voltage control regions have the first conductivity type and a different impurity concentration from the first active region, a first gate trench extending across the first active region, wherein portions of side bottom portions of the first gate trench adjacent to the respective isolation region are disposed at a higher level than a central bottom portion of the first gate trench, and the first threshold voltage control regions remain in the first active region under the side bottom portions of the first gate trench adjacent to the respective isolation region, and a first gate pattern. Methods of manufacturing such semiconductor devices are also provided. | 08-26-2010 |
20100216292 | SEMICONDUCTOR DEVICE FOR REDUCING INTERFERENCE BETWEEN ADJOINING GATES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate having an active region having a plurality of recessed channel areas extending across the active region and a plurality of junction areas also extending across the active region. Gates are formed in and over the recessed channel areas of the active region. A device isolation structure is formed in the semiconductor substrate to delimit the active region, and the device isolation structure has recessed portions, each of which is formed near a junction area of the active region. Landing plugs are formed over each junction area in the active region and extend to fill the recessed portion of the device isolation structure outside the active region. The semiconductor device suppresses interference caused by an adjoining gate leading to a decrease in leakage current from a cell transistor. | 08-26-2010 |
20100240183 | METHOD OF MANUFACTURING POWER SEMICONDUCTOR DEVICE - A mask layer having a plurality of openings is formed on the first layer. A second layer having a second conductivity type different from the first conductivity type is formed on the first layer by introducing impurities using the mask layer. A third layer having the first conductivity type is formed on the second layer by introducing impurities using the mask layer. A trench extending through the second layer and the third layer to the first layer is formed by carrying out etching using an etching mask including at least the mask layer. A gate insulation film covering a sidewall of the trench is formed. A trench gate filling the trench is formed on the gate insulation film. | 09-23-2010 |
20100240184 | METHOD OF FORMING BURIED GATE ELECTRODE - A method of forming a buried gate electrode prevents voids from being formed in a silicide layer of the gate electrode. The method begins by forming a trench in a semiconductor substrate, forming a conformal gate oxide layer on the semiconductor in which the trench has been formed, forming a first gate electrode layer on the gate oxide layer, forming a silicon layer on the first gate electrode layer to fill the trench. Then, a portion of the first gate electrode layer is removed to form a recess which exposed a portion of a lateral surface of the silicon layer. A metal layer is then formed on the semiconductor substrate including on the silicon layer. Next, the semiconductor substrate is annealed while the lateral surface of the silicon layer is exposed to form a metal silicide layer on the silicon layer. | 09-23-2010 |
20100240185 | Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device includes: forming a trench for forming buried type wires by etching a substrate; forming first and second oxidation layers on a bottom of the trench and a wall of the trench, respectively; removing a part of the first oxidation layer and the entire second oxidation layer; and forming the buried type wires on the wall of the trench by performing a silicide process on the wall of the trench from which the second oxidation layer is removed. As a result, the buried type wires are insulated from each other. | 09-23-2010 |
20100248437 | Methods of forming recessed gate structures including blocking members, and methods of forming semiconductor devices having the recessed gate structures - A recessed gate structure in a semiconductor device includes a gate electrode partially buried in a substrate, a blocking member formed in the buried portion of the gate electrode, and a gate insulation layer formed between the gate electrode and the substrate. The blocking member may effectively prevent a void or a seam in the buried portion of the gate electrode from contacting the gate insulation layer adjacent to a channel region in subsequent manufacturing processes. Thus, the semiconductor device may have a regular threshold voltage and a leakage current passing through the void or the seam may efficiently decrease. | 09-30-2010 |
20100267211 | Method of manufacturing semiconductor apparatus - A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance. | 10-21-2010 |
20100273304 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device according to the present invention includes forming a first trench and a second trench by etching the first trench further, in an epitaxial layer formed over a substrate, extending a width of the second trench, forming an oxidize film by oxidizing the extended second trench, and filling an electrode material in the first trench and the second trench including the oxidized film formed therein. The method of fabricating a semiconductor device according to the present invention enables to fabricate a semiconductor device that improves the withstand voltage between a drain and a source and reduce the on-resistance. | 10-28-2010 |
20100279478 | TRENCH MOSFET HAVING TRENCH CONTACTS INTEGRATED WITH TRENCH SCHOTTKY RECTIFIERS HAVING PLANAR CONTACTS - An integrated configuration comprising trench MOSFET having trench contacts and trench Schottky rectifier having planar contacts is disclosed. The trench contacts for trench MOSFET provide a lower specific on-resistance. Besides, for trench gate connection, planar gate contact is employed in the present invention to avoid shortage issue between gate and drain in shallow trench gate. Besides, W plugs filled into both trench contacts and planar contacts enhance the metal step coverage capability. | 11-04-2010 |
20100285646 | Method of fabricating power semiconductor device - Wider and narrower trenches are formed in a substrate. A first gate material layer is deposited but not fully fills the wider trench. The first gate material layer in the wider trench and above the substrate original surface is removed by isotropic or anisotropic etching back. A first dopant layer is formed in the surface layer of the substrate at the original surface and the sidewall and bottom of the wider trench by tilt ion implantation. A second gate material layer is deposited to fully fill the trenches. The gate material layer above the original surface is removed by anisotropic etching back. A second dopant layer is formed in the surface layer of the substrate at the original surface by ion implantation. The dopants are driven-in to form a base in the substrate and a bottom-lightly-doped layer surrounding the bottom of the wider trench and adjacent to the base. | 11-11-2010 |
20100285647 | INSULATED GATE SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An insulated gate silicon carbide semiconductor device is provided having small on-resistance in a structure obtained by combining the SIT and MOSFET structures having normally-off operation. The device includes an n | 11-11-2010 |
20100285648 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a transistor having a recessed gate, contact plugs formed in a region of a plurality of trenches, which are formed by recessing a semiconductor substrate. Further, a metal line and a source/drain region can be connected through the contact plug, so that on-current can be increased as much as an increased channel area. | 11-11-2010 |
20100291744 | HIGH DENSITY TRENCH MOSFET WITH SINGLE MASK PRE-DEFINED GATE AND CONTACT TRENCHES - Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact. | 11-18-2010 |
20100311215 | SEMICONDUCTOR DEVICE HAVING A BURIED GATE THAT CAN REALIZE A REDUCTION IN GATE-INDUCED DRAIN LEAKAGE (GIDL) AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a buried gate that can realize a reduction in gate-induced drain leakage is presented. The semiconductor device includes a semiconductor substrate, a buried gate, and a barrier layer. The semiconductor substrate has a groove. The buried gate is formed in a lower portion of the groove and has a lower portion wider than an upper portion. The barrier layer is formed on sidewalls of the upper portion of the buried gate. | 12-09-2010 |
20100311216 | Method for Forming Active and Gate Runner Trenches - A method for forming a trench-gated field effect transistor (FET) includes the following steps. Using a first mask, defining and simultaneously forming a plurality of active gate trenches and at least one gate runner trench extending to a first depth within a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench; and using the first mask and a second mask for protecting the at least one gate runner trench, further extending only the plurality of active gate trenches to a second and final depth within the silicon region. | 12-09-2010 |
20100330760 | Fabrication method of trenched metal-oxide-semiconductor device - A fabrication method of trenched metal-oxide-semiconductor device is provided. A pattern layer with a plurality of openings is formed on a semiconductor base, and then a spacer is formed on the sidewall of the opening to define the gate trench. After the gate electrode formed in the gate trench, a dielectric structure is formed on the gate electrode by filling dielectric material into the opening. Then, the pattern layer and the spacer are removed and a dielectric layer is formed on the dielectric structure. The portion of the dielectric layer on the sidewall of the dielectric structure defines the source regions. After the source regions are formed in the well, another dielectric layer is formed on the dielectric layer to define the heavily doped regions adjacent to the source regions. | 12-30-2010 |
20110003447 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH VERTICAL TRANSISTOR - A method for fabricating a semiconductor device includes forming a plurality of first active pillars by etching a substrate using a hard mask layer as an etching barrier, forming a gate conductive layer surrounding sidewalls of the first active pillars and the hard mask layer, forming a word line conductive layer filling gaps defined by the gate conductive layer, forming word lines and vertical gates by simultaneously removing portions of the word line conductive layer and the gate conductive layer on the sidewalls of the hard mask layer, forming an inter-layer dielectric layer filling gaps formed by removing the word line conductive layer and the gate conductive layer, exposing surfaces of the first active pillars by removing the hard mask layer, and growing second active pillars over the first active pillars. | 01-06-2011 |
20110003448 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING VERTICAL-TYPE CHANNEL - A method for fabricating a semiconductor device includes the following steps. A device isolation layer with a trench type is etched in a predetermined portion of a substrate to define an active region. Predetermined portions where gate lines traverse in the device isolation layer are etched to a certain depth to form a plurality of first recesses. A pair of gate lines filling the first recesses and traversing over the active region is formed. Portions of the active region which storage nodes contact on one sides of the gate lines are etched to form a plurality of second recesses. An ion-implantation process is performed to form a plurality of first junction regions beneath the second recesses and to form a second junction region in a portion of the active region between the gate lines such that the second junction region contacts bit lines. | 01-06-2011 |
20110003449 | Power Device With Trenches Having Wider Upper Portion Than Lower Portion - A method of forming a semiconductor device includes the following. Removing portions of a silicon layer such that a trench having sidewalls which fan out near the top of the trench to extend directly over a portion of the silicon layer is formed in the silicon layer; and forming source regions in the silicon layer adjacent the trench sidewall such that the source regions extend into the portions of the silicon layer directly over which the trench sidewalls extend. | 01-06-2011 |
20110008939 | Method of making a trench MOSFET having improved avalanche capability using three masks process - A method of forming trench MOSFET structure having improved avalanche capability is disclosed. In a preferred embodiment according to the present invention, only three masks are needed in the fabricating process, wherein the source region is formed by performing source Ion Implantation through contact open region of a thick contact interlayer for saving source mask. Furthermore, said source region has a doping concentration along channel region lower than along contact trench region, and source junction depth along channel region shallower than along contact trench, and source doping profile along surface of epitaxial layer has Guassian-distribution from trenched source-body contact to channel region. | 01-13-2011 |
20110008940 | SELF-ALIGNED V-CHANNEL MOSFET - Forming a high-κ/metal gate field effect transistor using a gate last process in which the channel region has a curved profile thus increasing the effective channel length improves the short channel effect. During the high-κ/metal gate process, after the sacrificial materials between the sidewall spacers are removed, the exposed semiconductor substrate surface at the bottom of the gate trench cavity is etched to form a curved recess. Subsequent deposition of high-κ gate dielectric layer and gate electrode metal into the gate trench cavity completes the high-κ/metal gate field effect transistor having a curved channel region that has a longer effective channel length. | 01-13-2011 |
20110008941 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, including (a) etching a semiconductor substrate to form a first trench defining an active region; (b) forming a first spacer on sidewalls of the first trench; (c) etching a bottom of the first trench to form a second trench; (d) etching a sidewall of the second trench to form a third trench including an undercut space; (e) forming a device isolation structure that fills the first, second and third trenches; (f) etching the semiconductor substrate of a gate region to form a recess; and (g) forming a gate that fills the recess. | 01-13-2011 |
20110008942 | SEMICONDUCTOR DEVICE HAVING ASYMMETRIC BULB-TYPE RECESS GATE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a silicon substrate; a device isolation structure formed in the silicon substrate to delimit an active region which has a pair of gate forming areas, a drain forming area between the gate forming areas, and source forming areas outside the gate forming areas; an asymmetric bulb-type recess gate formed in each gate forming area of the active region and having the shape of a bulb on the lower end portion of the sidewall thereof facing the source forming area; and source and drain areas respectively formed on the surface of the substrate on both sides of the asymmetric bulb-type recess gate. | 01-13-2011 |
20110014761 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The characteristics of a semiconductor device including a trench-gate power MISFET are improved. The semiconductor device includes a substrate having an active region where the power MISFET is provided and an outer circumferential region which is located circumferentially outside the active region and where a breakdown resistant structure is provided, a pattern formed of a conductive film provided over the substrate in the outer circumferential region with an insulating film interposed therebetween, another pattern isolated from the pattern, and a gate electrode terminal electrically coupled to the gate electrodes of the power MISFET and provided in a layer over the conductive film. The conductive film of the pattern is electrically coupled to the gate electrode terminal, while the conductive film of another pattern is electrically decoupled from the gate electrode terminal. | 01-20-2011 |
20110014762 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in and over the grooves; gate spacers formed on both sidewalls of the gates over portions of the recessed active region which are positioned on both sides of the gates; an LDD region formed in the active region under the gate spacers; junction areas formed in the active region on both sides of the gates including the gate spacers; and landing plugs formed on the junction areas. | 01-20-2011 |
20110014763 | Method of Forming Low Resistance Gate for Power MOSFET Applications - A trench gate field effect transistor includes the following steps. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench. A recessed polysilicon layer is formed in the trench. A highly conductive cap layer is formed over and in contact with the recessed polysilicon layer. Rapid thermal processing is performed to cause the recessed polysilicon layer and the highly conductive cap layer to react. | 01-20-2011 |
20110014764 | METHOD OF FORMING A DUAL-TRENCH FIELD EFFECT TRANSISTOR - A method of forming a field effect transistor includes forming a well region in a semiconductor region of a first conductivity type. The well region may be of a second conductivity type and have an upper surface and a lower surface. The method also includes forming a plurality of gate trenches extending into the semiconductor region to a depth below the lower surface of the well region, and forming a plurality of stripe trenches extending through the well region and into the semiconductor region to a depth below the plurality of gate trenches. The plurality of stripe trenches may be laterally spaced from the plurality of gate trenches. The method also includes at least partially filling the plurality of stripe trenches with a semiconductor material of the second conductivity type. The semiconductor material of the second conductivity type may form a PN junction with a portion of the semiconductor region. | 01-20-2011 |
20110039383 | Shielded gate trench MOSFET device and fabrication - A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask. | 02-17-2011 |
20110039384 | Power MOSFET With Recessed Field Plate - A trench MOSFET contains a recessed field plate (RFP) trench adjacent the gate trench. The RFP trench contains an RFP electrode insulated from the die by a dielectric layer along the walls of the RFP trench. The gate trench has a thick bottom oxide layer, and the gate and RFP trenches are preferably formed in the same processing step and are of substantially the same depth. When the MOSFET operates in the third quadrant (with the source/body-to-drain junction forward-biased), the combined effect of the RFP and gate electrodes significantly reduces in the minority carrier diffusion current and reverse-recovery charge. The RFP electrode also functions as a recessed field plates to reduce the electric field in the channel regions when the MOSFET source/body to-drain junction reverse-biased. | 02-17-2011 |
20110053326 | SUPER JUNCTION TRENCH POWER MOSFET DEVICE FABRICATION - Methods of fabricating a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device are described. A column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant. | 03-03-2011 |
20110053327 | METHOD OF FORMING RECESS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING THE SAME - Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer. | 03-03-2011 |
20110059586 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the second conductivity type provided in an interior portion of the second semiconductor layer corresponding to a part under the contact groove. An uppermost portion of the fifth semiconductor layer contacts the third semiconductor layer, a lowermost portion of the fifth semiconductor layer has a higher impurity concentration than that of the other portion in the fifth semiconductor layer and is located in the second semiconductor layer and not contacting the first semiconductor layer, and the fifth semiconductor layer is narrower from the uppermost portion to the lower most portion. | 03-10-2011 |
20110065247 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a method for manufacturing a semiconductor device. A well region formed on a semiconductor substrate includes a plurality of trench regions, and a source electrode is connected to a source region formed on a substrate surface between the trench regions. Adjacently to the source region, a high concentration region is formed, which is brought into butting contact with the source electrode together with the source region, whereby a substrate potential is fixed. A drain region is formed at a bottom portion of the trench region, whose potential is taken to the substrate surface by a drain electrode buried inside the trench region. An arbitrary voltage is applied to a gate electrode, and the drain electrode, whereby carriers flow from the source region to the drain region and the semiconductor device is in an on-state. | 03-17-2011 |
20110070708 | Method for making trench MOSFET with shallow trench structures - A method for making trench MOSFET with shallow trench structures with thick trench bottom is disclosed. The improved method resolves the problem of deterioration of breakdown voltage resulted by LOCOS having a bird's beak shape introduced in prior art, and at the same time, the inventive device has a lower Qgd and lower Rds. | 03-24-2011 |
20110076817 | INTEGRATED CIRCUIT DEVICE WITH A SEMICONDUCTOR BODY AND METHOD FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT DEVICE - An integrated circuit device with a semiconductor body and a method for the production of a semiconductor device a provided. The semiconductor body comprises a cell field with a drift zone of a first conduction type. In addition, the semiconductor device comprises an edge region surrounding the cell field. Field plates with a trench gate structure are arranged in the cell field, and an edge trench surrounding the cell field is provided in the edge region. The front side of the semiconductor body is in the edge region provided with an edge zone of a conduction type complementing the first conduction type with doping materials of body zones of the cell field. The edge zone of the complementary conduction type extends both within and outside the edge trench. | 03-31-2011 |
20110081756 | Semiconductor device having vertical mosfet and method of manufacturing the same - A method of manufacturing a semiconductor device, includes forming a first trench and a second trench in a semiconductor region of a first conductivity type simultaneously, forming a gate insulating film and a gate electrode in the first trench, forming a channel region of a second conductivity type in the semiconductor region, forming a source region of the first conductivity type in the channel region, forming a diffusion region of the first conductivity type which has a higher concentration than that of the semiconductor region in a part of the semiconductor region located immediately under the second trench by implanting impurity ions of the first conductivity type through the second trench, and forming a drain electrode in a part of the second trench. | 04-07-2011 |
20110081757 | MEMORY HAVING A VERTICAL ACCESS DEVICE - Semiconductor memory devices having vertical access devices are disclosed. In some embodiments, a method of forming the device includes providing a recess in a semiconductor substrate that includes a pair of opposed side walls and a floor extending between the opposed side walls. A dielectric layer may be deposited on the side walls and the floor of the recess. A conductive film may be formed on the dielectric layer and processed to selectively remove the film from the floor of the recess and to remove at least a portion of the conductive film from the opposed sidewalls. | 04-07-2011 |
20110092039 | Fin field effect transistor and method for forming the same - Example embodiments are directed to a method of forming a field effect transistor (FET) and a field effect transistor (FET) including a source/drain pair that is elevated with respect to the corresponding gate structure. | 04-21-2011 |
20110104862 | METHOD OF FORMING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes the following processes. A first semiconductor structure is formed, which extends upwardly in a direction perpendicular to a main surface from a surface of a semiconductor substrate. A first insulating film is formed which extends on a surface of the first semiconductor structure. A gate electrode is formed which extends on the first insulating film. The gate electrode has a top surface which is lower than a top surface of the first semiconductor structure. A liner film is formed, which may include, but is not limited to, first and second liner portions. The first liner portion covers the gate electrode. The second liner portion extends upwardly from the top surface of the gate electrode. The liner film includes nitrogen and oxygen. | 05-05-2011 |
20110111569 | MOS TRANSISTOR WITH GATE TRENCH ADJACENT TO DRAIN EXTENSION FIELD INSULATION - An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer. | 05-12-2011 |
20110124167 | Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions - A novel integration scheme for forming power MOSFET, particularly forming salicides for both gate and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicides. | 05-26-2011 |
20110124168 | Methods of Forming Field Effect Transistors, Methods of Forming Field Effect Transistor Gates, Methods of Forming Integrated Circuitry Comprising a Transistor Gate Array and Circuitry Peripheral to the Gate Array, and Methods of Forming Integrated Circuitry Comprising a Transistor Gate Array Including First Gates and Second Grounded Isolation Gates - The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated. | 05-26-2011 |
20110129975 | METHOD FOR FABRICATING SIDE CONTACT IN SEMICONDUCTOR DEVICE USING DOUBLE TRENCH PROCESS - A method for fabricating a semiconductor device is provided, the method includes forming a double trench including a first trench and a second trench formed below the first trench and having surfaces covered with insulation layers, and removing portions of the insulation layers to form a side contact exposing one sidewall of the second trench. | 06-02-2011 |
20110136309 | METHOD OF FORMING AN INSULATED GATE FIELD EFFECT TRANSISTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE - In one embodiment, a method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming disposable dielectric stack overlying a substrate. The method also includes forming the trench regions adjacent to the disposable dielectric stack. After the insulated gate electrodes are formed, the method includes removing the disposable dielectric stack, and then forming spacers adjacent the insulated gate electrodes. The method further includes using the spacers to form recessed regions in the insulated gate electrodes and the substrate, and then forming enhancement regions in the first and second recessed regions. | 06-09-2011 |
20110136310 | METHOD OF FORMING AN INSULATED GATE FIELD EFFECT TRANSISTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE - A method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming dielectric stack overlying a substrate. The dielectric stack includes a first layer of one material overlying the substrate and a second layer of a different material overlying the first layer. Trench regions are formed adjacent to the dielectric stack. After the insulated shield electrodes are formed, the method includes removing the second layer and then forming the insulated gate electrodes. Portions of gate electrode material are removed to form first recessed regions, and dielectric plugs are formed in the first recessed regions using the first layer as a stop layer. The first layer is then removed, and spacers are formed adjacent the dielectric plugs. Second recessed regions are formed in the substrate self-aligned to the spacers. | 06-09-2011 |
20110143508 | METHOD OF FABRICATING VERTICAL CHANNEL TRANSISTOR - A method of fabricating a vertical channel transistor includes: forming a line type active pattern on a substrate so as to extend in a first horizontal direction; forming a vertical channel isolating the active pattern in a second horizontal direction intersecting the first horizontal direction and extending vertically on the substrate; | 06-16-2011 |
20110143509 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes the following processes. A groove is formed in a semiconductor substrate. A gate insulating film is formed on an inside wall of the groove. A buried gate electrode is formed on the gate insulating film and on a bottom portion of the groove. A cap insulating film covering the buried gate electrode is formed in an upper portion of the groove. The cap insulating film has a top surface which is different in level from a top surface of the semiconductor substrate. A first inter-layer insulating film is formed on the top surface of the semiconductor substrate and on the top surface of the cap insulating film. The first inter-layer insulating film with a flat top surface fills a gap in level between the top surface of the semiconductor substrate and the top surface of the cap insulating film. | 06-16-2011 |
20110151633 | METHODS OF FORMING A CONDUCTIVE LAYER STRUCTURE AND METHODS OF MANUFACTURING A RECESSED CHANNEL TRANSISTOR INCLUDING THE SAME - In a method of forming a conductive layer structure and a method of manufacturing a recess channel transistor, a first insulating layer and a first conductive layer are sequentially formed on a substrate having a first region a second region and the substrate is exposed in a recess-forming area in the first region. A recess is formed in the recess-forming-area by etching the exposed region of the substrate. A second insulating layer is conformally formed on a sidewall and a bottom of the recess. A second conductive layer pattern is formed on the second insulating layer to fill up a portion of the recess. A spacer is formed on the second conductive layer pattern and on the second insulating layer on the sidewall of the recess. A third conductive layer pattern is formed on the second conductive layer pattern and the spacer to fill up the recess. | 06-23-2011 |
20110151634 | LATERAL DRAIN-EXTENDED MOSFET HAVING CHANNEL ALONG SIDEWALL OF DRAIN EXTENSION DIELECTRIC - An integrated circuit ( | 06-23-2011 |
20110159651 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The invention provides a method of manufacturing a semiconductor device at low cost in which the gate insulation film having a trench structure is not damaged by arsenic ions when the emitter layer or the like is formed and the insulation breakdown voltage is enhanced. A gate electrode made of polysilicon formed in a trench is thermally oxidized in a high temperature furnace or the like to form a thick polysilicon thermal oxide film on the gate electrode. Impurity ions are then ion-implanted to form an N type semiconductor layer that is to be an emitter layer or the like. At this time, the polysilicon thermal oxide film is formed thicker than the projected range Rp of impurity ions in the silicon oxide film for forming the N type semiconductor layer as the emitter layer or the like by ion implantation. This prevents a gate insulation film between the gate electrode and the N type semiconductor layer from being damaged by the impurity ions. | 06-30-2011 |
20110159652 | FABRICATING METHOD OF VERTICAL TRANSISTOR - A substrate is provided. A pillar protruding out of a surface of the substrate is already formed on the substrate, and a patterned layer is already formed on the pillar. The pillar includes a lower part, a channel region, and an upper part from bottom to top, and the lower part has a first doped region. A gate dielectric layer is formed on a sidewall at one side of the pillar. A surrounding gate is formed on the gate dielectric layer located on the channel region, and a base line electrically connected to the channel region is formed on a sidewall at the other side of the pillar. A second doped region is formed in the upper part of the pillar. | 06-30-2011 |
20110165747 | SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF - A method for manufacturing a semiconductor apparatus includes forming a contact pad layer over a substrate in an active region; patterning the contact pad layer and the substrate to form a first trench, the first trench defining a contact pad pattern; etching the substrate to form a second trench that extends vertically from the first trench; forming a gate insulating pattern over the substrate in the second trench; and forming a buried gate in the second trench. | 07-07-2011 |
20110171799 | METHOD OF FORMING POWER MOSFET - A method of forming a power MOSFET is described. An epitaxial layer of first conductivity type is formed on a substrate of first conductivity type. A body layer of second conductivity type is formed in the epitaxial layer. A plurality of mask patterns are formed on the substrate. A plurality of trenches are formed in the body layer and the epitaxial layer between the mask patterns. An oxide layer is formed on surfaces of the trenches. A conductive layer is formed in the trenches. A trimming process is performed to the mask patterns to reduce the line width of each mask pattern. Two source regions of first conductivity type are formed in the body layer beside each trench by using the trimmed mask patterns as a mask. A plurality of dielectric patterns are formed on the conductive layer and between the trimmed mask patterns. The trimmed mask patterns are removed. | 07-14-2011 |
20110177662 | Method of Forming Trench-Gate Field Effect Transistors - A method of forming a field effect transistor includes: forming a trench in a semiconductor region; forming a shield electrode in the trench; performing an angled sidewall implant of impurities of the first conductivity type to form a channel enhancement region adjacent the trench; forming a body region of a second conductivity type in the semiconductor region; and forming a source region of the first conductivity type in the body region, the source region and an interface between the body region and the semiconductor region defining a channel region therebetween, the channel region extending along the trench sidewall. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region. | 07-21-2011 |
20110183482 | TRANSISTORS WITH LATERALLY EXTENDED ACTIVE REGIONS AND METHODS OF FABRICATING SAME - A transistor and method of fabricating the transistor are disclosed. The transistor is disposed in an active region of a substrate defined by an isolation region and includes a gate electrode and associated source/drain regions. The isolation region includes an upper isolation region and an lower isolation region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive profile. | 07-28-2011 |
20110183483 | Semiconductor device and method of manufacturing the semiconductor device - In a semiconductor device, the semiconductor device may include a first active structure, a first gate insulation layer, a first gate electrode, a first impurity region, a second impurity region and a contact structure. The first active structure may include a first lower pattern in a first region of a substrate and a first upper pattern on the first lower pattern. The first gate insulation layer may be formed on a sidewall of the first upper pattern. The first gate electrode may be formed on the first gate insulation layer. The first impurity region may be formed in the first lower pattern. The second impurity region may be formed in the first upper pattern. The contact structure may surround an upper surface and an upper sidewall of the first upper pattern including the second impurity region. Accordingly, the contact resistance between the contact structure and the second impurity region may be decreased and structural stability of the contact structure may be improved. | 07-28-2011 |
20110183484 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device comprises a plurality of semiconductor pillars laid out in matrix in a first and a second directions parallel with a main surface of a semiconductor substrate, and extending to a direction substantially perpendicular to the main surface; gate insulating films covering each surface of the plurality of semiconductor pillars, respectively; upper diffusion layers formed in each upper part of the plurality of semiconductor pillars, respectively; lower diffusion layers formed in each lower part of the plurality of semiconductor pillars, respectively; gate electrodes encircling at least each channel region between each upper diffusion layer and each lower diffusion layer, respectively; and a plurality of lower electrodes short-circuiting the lower diffusion layers adjacent in the first direction. | 07-28-2011 |
20110189830 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A semiconductor substrate is prepared. The semiconductor substrate has a first region and a second region other than the first region. A first mask is formed over the first region. The first mask has a first line-and-space pattern extending in a first direction. A first removing process is performed. The first removing process selectively removes the first region with the first mask to form a first groove extending in the first direction. The first removing process removes an upper part of the second region while a remaining part of the second region having a first surface facing upward. The bottom level of the first groove is higher than the level of the first surface. | 08-04-2011 |
20110201168 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING A RECESSED-CHANNEL - A method according to example embodiments includes forming isolation regions in a substrate, the isolation regions defining active regions. Desired regions of the active regions and the isolation regions are removed, thereby forming recess channel trenches to a desired depth. The recess channel trenches are fog to have a first region in contact with the active regions and a second region in contact with the isolation regions. A width of a bottom surface of the recess channel trenches is less than that of a top surface thereof. The active regions and the isolation regions are annealed to uplift the bottom surface of the recess channel trenches. An area of the bottom surface of the first region is increased. A depth of the bottom surface of the first region is reduced. | 08-18-2011 |
20110207276 | POWER MOS DEVICE FABRICATION - Fabricating a semiconductor device includes forming a hard mask on the substrate having a top substrate surface; forming a gate trench in the substrate, through the hard mask; depositing gate material in the gate trench; removing the hard mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; and disposing an anti-punch through implant along at least a section of the trench wall but not along the trench bottom. | 08-25-2011 |
20110207277 | METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING VERTICAL CHARGE-COMPENSATED STRUCTURE AND SUB-SURFACE CONNECTING LAYER - In one embodiment, a semiconductor device is formed having vertical localized charge-compensated trenches, trench control regions, and sub-surface doped layers. The vertical localized charge-compensated trenches include at least a pair of opposite conductivity type semiconductor layers. The trench control regions are configured to provide a generally vertical channel region electrically coupling source regions to the sub-surface doped layers. The sub-surface doped layers are further configured to electrically connect the drain-end of the channel to the vertical localized charge compensation trenches. Body regions are configured to isolate the sub-surface doped layers from the surface of the device. | 08-25-2011 |
20110212586 | Method for Forming Shielded Gate Field Effect Transistors - A method for forming a field effect transistor includes forming a trench in a semiconductor region and forming a dielectric layer lining lower sidewalls and bottom surface of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. An inter-electrode dielectric (IED) is formed in the trench over the shield electrode by carrying out a steam ambient oxidation and carrying out a dry ambient oxidation. A gate electrode is formed in an upper portion of the trench. The gate electrode may be insulated from the shield electrode by the IED. | 09-01-2011 |
20110217820 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device using a recess channel array is disclosed. A substrate is provided having a first region and a second region, including a first transistor in the first region including a first gate electrode partially filling a trench, and source and drain regions that are formed at both sides of the trench, and covered by a first insulating layer. A first conductive layer is formed on the substrate. A contact hole through which the drain region is exposed is formed by patterning the first conductive layer and the first insulating layer. A contact plug is formed that fills the contact hole. A bit line is formed that is electrically connected to the drain region through the contact plug, and simultaneously a second gate electrode is formed in the second region by patterning the first conductive layer. | 09-08-2011 |
20110223731 | Vertical Channel Transistors And Methods For Fabricating Vertical Channel Transistors - Provided are a vertical channel transistor and a method for fabricating a vertical channel transistor. The method includes forming an active layer on a substrate, forming a plurality of vertical channels on the active layer, forming a plurality of isolated gate electrodes to surround sidewalls of the plurality of vertical channels, forming a buried bitline to extend along the active layer between the plurality of vertical channels, forming a plug-in between the plurality of vertical channels to connect the plurality of isolated gate electrodes and forming a wordline on a location where the plug-in and the plurality of isolated gate electrodes are connected. | 09-15-2011 |
20110230024 | METHOD FOR MANUFACTURING NON-VOLATILE MEMORY - A method for manufacturing a non-volatile memory is provided. The method comprises steps of providing a substrate. Thereafter, a plurality of first doped regions are formed in the substrate and then a plurality of trenches are formed in a portion of the first doped regions. A plurality of second doped regions are formed in a portion of the substrate under the bottoms of the trenches respectively. Then, a charge storage layer is formed conformal to a surface of the substrate and a conductive layer is formed over the substrate, wherein the conductive layer covers the charge storage layer and fills in the trenches. | 09-22-2011 |
20110230025 | FABRICATION METHOD OF TRENCHED METAL-OXIDE-SEMICONDUCTOR DEVICE - A fabrication method of a trenched metal-oxide-semiconductor device is provided. Firstly, an epitaxial layer is formed on a substrate. Then, a plurality of gate trenches is formed in the epitaxial layer. Afterward, a spacer is formed on the sidewall of the trench gates. The spacer is utilized as a mask to selectively implant oxygen ion into the bottom of the gate trenches so as to form a bottom oxide layer on the bottom of the gate trenches to reduce capacitance between gate and drain. | 09-22-2011 |
20110237037 | Methods of Forming Recessed Channel Array Transistors and Methods of Manufacturing Semiconductor Devices - In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure. | 09-29-2011 |
20110244641 | Shielded Gate Trench FET with an Inter-electrode Dielectric Having a Low-k Dielectric Therein - A method for forming a shielded gate trench field effect transistor (FET) includes forming trenches in a semiconductor region, forming a shield electrode in a bottom portion of each trench, and forming an inter-electrode dielectric (IED) extending over the shield electrode. The IED may comprise a low-k dielectric. The method also includes forming a gate electrode in an upper portion of each trench over the IED. | 10-06-2011 |
20110263089 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device is fabricated by forming a first gate conductive layer in a peripheral circuit region of a semiconductor substrate including a cell region and the peripheral circuit region; forming a buried-type gate in the cell region; and forming a bit line contact and a bit line conductive layer in the cell region and a second gate conductive layer in the peripheral circuit region. This minimizes a process for opening the cell region and the peripheral circuit region, thereby minimizing defects that can be generated from a boundary between the cell region and the peripheral circuit region. As a result, the manufacturing cost of devices may be reduced. | 10-27-2011 |
20110263090 | SEMICONDUCTOR DEVICE AHVING VERTICAL PILLAR TRANSISTORS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a single surface of lower portions of the silicon pillars, and drain areas of the vertical pillar transistors are connected with one another. | 10-27-2011 |
20110269279 | METHOD FOR FORMING JUNCTIONS OF VERTICAL CELLS IN SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a plurality of active regions that are separated from each other by a plurality of trenches, respectively, wherein the trenches are formed by etching a substrate, forming an insulation layer having openings that each expose a portion of a first sidewall of each active region, forming a filling layer which fills the openings, forming a diffusion control layer over a substrate structure including the filling layer, and forming a junction on a portion of the first sidewall of each active region. | 11-03-2011 |
20110269280 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device, including: a first group of transistors formed on a semiconductor substrate; and a second group of transistors formed on the semiconductor substrate, each of which is lower in operating voltage than each of the transistors in the first group; wherein each of the transistors in the first group includes a first gate electrode formed on the semiconductor substrate through a first gate insulating film, and a silicide layer formed on the first gate electrode; each of the transistors in the second group includes a second gate electrode formed in a trench for gate formation, formed in an insulating film above the semiconductor substrate, through a second gate insulating film; and a protective film is formed so as to cover the silicide layer on each of the first gate electrodes of the first group of transistors. | 11-03-2011 |
20110275187 | METHOD FOR FORMING A VERTICAL MOS TRANSISTOR - A method is used to form a vertical MOS transistor. The method utilizes a semiconductor layer. An opening is etched in the semiconductor layer. A gate dielectric is formed in the opening that has a vertical portion that extends to a top surface of the first semiconductor layer. A gate is formed in the opening having a major portion laterally adjacent to the vertical portion of the gate dielectric and an overhang portion that extends laterally over the vertical portion of the gate dielectric. An implant is performed to form a source region at the top surface of the semiconductor layer while the overhang portion is present. | 11-10-2011 |
20110275188 | SEMICONDUCTOR DEVICE HAVING A BURIED GATE THAT CAN REALIZE A REDUCTION IN GATE-INDUCED DRAIN LEAKAGE (GIDL) AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a buried gate that can realize a reduction in gate-induced drain leakage is presented. The semiconductor device includes a semiconductor substrate, a buried gate, and a barrier layer. The semiconductor substrate has a groove. The buried gate is formed in a lower portion of the groove and has a lower portion wider than an upper portion. The barrier layer is formed on sidewalls of the upper portion of the buried gate. | 11-10-2011 |
20110287598 | METHOD OF MANUFACTURING SUPER-JUNCTION SEMICONDUCTOR DEVICE - A method of manufacturing a super-junction semiconductor device prevents mutual positional deviation between the region of the first conductivity type in the alternating conductivity type layer and the second trench for forming a trench gate from resulting. The method includes growing an alternating conductivity type layer epitaxially on a heavily doped n-type semiconductor substrate, the alternating conductivity type layer including n-type and p-type semiconductor regions arranged alternately and repeated such that n-type and p-type regions are adjoining each other, and arranged to extend perpendicular to the substrate's major surface. The method includes forming a first trench having a predetermined depth in the surface portion of n-type semiconductor region; forming an n-type thin layer on the inner surface of the first trench; and burying gate electrode in the space surrounded by the n-type thin layer with a gate insulator film interposed between a gate electrode and the n-type thin layer | 11-24-2011 |
20110287599 | Method of Fabricating a Transistor - A method of fabricating a saddle-fin transistor may include: forming a buffer oxide film and a hard mask oxide film over a semiconductor substrate; etching the buffer oxide film, the hard mask oxide film and the semiconductor substrate corresponding to a mask pattern to form a trench corresponding to a gate electrode and a fin region; oxidizing the exposed semiconductor substrate in the trench to form a gate oxide film; depositing a gate lower electrode in the trench; and depositing a gate upper electrode over the gate lower electrode to fill the trench. | 11-24-2011 |
20110306172 | LATERAL TRENCH MOSFET HAVING A FIELD PLATE - One embodiment relates to an integrated circuit that includes a lateral trench MOSFET disposed in a semiconductor body. The lateral trench MOSFET includes source and drain regions having a body region therebetween. A gate electrode region is disposed in a trench that extends beneath the surface of the semiconductor body at least partially between the source and drain. A gate dielectric separates the gate electrode region from the semiconductor body. In addition, a field plate region in the trench is coupled to the gate electrode region, and a field plate dielectric separates the field plate region from the semiconductor body. Other integrated circuits and methods are also disclosed. | 12-15-2011 |
20110312138 | Methods of Manufacturing Power Semiconductor Devices with Trenched Shielded Split Gate Transistor - Methods of manufacturing power semiconductor devices include forming trenches in a substrate, depositing a shield oxide layer that conforms to the trenches, depositing a gate polysilicon layer into the trenches, etching the gate polysilicon layer so that the gate polysilicon layer is recessed in the trench, etching the shield oxide layer so that the shield oxide layer is recessed in the trench and lower than the gate polysilicon layer, depositing a layer of gate oxide across the top of the substrate, sidewalls of the trenches and troughs inside the trenches leaving a recess, depositing shield polysilicon in the recess, etching the shield polysilicon layer so that the shield polysilicon layer is recessed in the trench and higher than the gate polysilicon layer, forming a well region, and forming a source region. The well region can be formed with a −p-well implant. The source region can be performed with an n+ source implant. | 12-22-2011 |
20110312139 | SEMICONDUCTOR DEVICE WITH A GATE HAVING A BULBOUS AREA AND A FLATTENED AREA UNDERNEATH THE BULBOUS AREA AND METHOD FOR MANUFACTURING THE SAME | 12-22-2011 |
20110318894 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a first semiconductor region of a second conductivity type on a semiconductor layer of a first conductivity type, forming a mask selectively opening a surface of the first semiconductor region, and forming a trench penetrating through the first semiconductor region to reach the semiconductor layer. The method can include exposing further a part of the surface of the first semiconductor region from the mask. The method can include forming a control electrode in the trench, and forming selectively a second semiconductor region of the first conductivity type on the surface of the first semiconductor region. The method can include removing the mask having the opening. The method can include forming selectively a third conductor region of the second conductivity type on the surface of the first semiconductor region. | 12-29-2011 |
20110318895 | FABRICATION METHOD OF TRENCHED POWER MOSFET - A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench. | 12-29-2011 |
20120009748 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH SIDE JUNCTION - A method for fabricating a semiconductor device, including etching a substrate to form a trench, forming a junction region in the substrate under the trench, etching the bottom of the trench to a certain depth to form a side junction, and forming a bit line coupled to the side junction. | 01-12-2012 |
20120015491 | Method of fabricating a high-voltage transistor with an extended drain structure - A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls; then partially filling each of the trenches with a dielectric material that covers the first and second sidewalls. The remaining portions of the trenches are then filled with a conductive material to form first and second field plates. Source and body regions are formed in an upper portion of the mesa, with the body region separating the source from a lower portion of the mesa. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b). | 01-19-2012 |
20120015492 | INSULATED GATE TYPE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer. | 01-19-2012 |
20120021577 | GATE TRENCH CONDUCTOR FILL - Semiconductor devices and methods for making such devices are described. The semiconductor devices contain a substrate with a trench in an upper portion thereof, a gate insulating layer on a sidewall and bottom of the trench, and a conductive gate of an amorphous silicon or polysilicon material on the gate oxide layer. The amorphous silicon or polysilicon layer can be doped with nitrogen, as well as B and/or P dopants, which have been activated by microwaves. The devices can be made by providing a trench in the upper surface of a semiconductor substrate, forming a gate insulating layer on the trench sidewall and bottom, and depositing a doped amorphous silicon or polysilicon layer on the gate insulating layer, and then activating the deposited amorphous silicon or polysilicon layer at low temperatures using microwaves. The resulting polysilicon or amorphous silicon layer contains fewer voids resulting from Si grain movement. Other embodiments are described. | 01-26-2012 |
20120021578 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A trench gate type power transistor of high performance is provided. A trench gate as a gate electrode is formed in a super junction structure comprising a drain layer and an epitaxial layer. In this case, the gate electrode is formed in such a manner that an upper surface of the epitaxial layer becomes higher than that of a channel layer formed over the drain layer. Then, an insulating film is formed over each of the channel layer and the epitaxial layer and thereafter a part of the insulating film is removed to form side wall spacers over side walls of the epitaxial layer. Subsequently, with the side wall spacers as masks, a part of the channel layer and that of the drain layer are removed to form a trench for a trench gate. | 01-26-2012 |
20120021579 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An aspect of the present invention provides a semiconductor device that includes a first conductivity type semiconductor body, a source region in contact with the semiconductor body, whose bandgap is different from that of the semiconductor body, and which formed heterojunction with the semiconductor body, a gate insulating film in contact with a portion of junction between the source region and the semiconductor body, a gate electrode in contact with the gate insulating film, a source electrode, a low resistance region in contact with the source electrode and the source region, and connected ohmically with the source electrode, and a drain electrode connected ohmically with the semiconductor body. | 01-26-2012 |
20120021580 | METHOD OF MANUFACTURING TRENCH MOSFET STRUCTURES USING THREE MASKS PROCESS - In according with the present invention, a semiconductor device is formed as follows. A contact insulation layer is deposited on the top surface of said silicon layer. A contact mask is applied and following with a dry oxide etching to remove the contact insulation layer from contact open areas. The silicon layer is implanted with a source dopant through the contact open areas and the source dopant is diffused to form source regions, thereby a source mask is saved. A dry silicon etch is carried out to form trenched source-body contacts in the contact open areas, penetrating through the source regions and extending into the body regions. | 01-26-2012 |
20120028425 | METHODS FOR FABRICATING TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS - A trench metal oxide semiconductor field effect transistor (MOSFET) can be fabricated in an upward direction. A trench bottom doping (TBD) process and/or a trench bottom oxide (TBO) process can be performed after formation of a substrate and a first epitaxial (epi) layer. Poly seal can be performed after the formation of TBO layers and before a merged epitaxial lateral overgrowth (MELO) step to improve quality and purity of a second epi layer formed in the MELO step. Plasma dry etching with an end point mode can be performed according to the locations of TBO layers to improve the uniformity of trench depth. | 02-02-2012 |
20120028426 | Inverted-trench grounded-source FET structure using conductive substrates, with highly doped substrates - This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination. | 02-02-2012 |
20120028427 | Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET - This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate. | 02-02-2012 |
20120028428 | Vertical type semiconductor device and method of manufacturing a vertical type semiconductor device - A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns. | 02-02-2012 |
20120040505 | METHOD AND DEVICE INCLUDING TRANSISTOR COMPONENT HAVING A FIELD ELECTRODE - A transistor component and method of forming a transistor component. One embodiment provides a semiconductor arrangement including a semiconductor body having a at least one first trench, a first field electrode arranged in the lower trench section of the at least one first trench and being insulated from the semiconductor body by a field electrode dielectric. A dielectric layer is formed on the first field electrode in the at least one first trench, including depositing a dielectric material on a first side of the semiconductor body and on the field plate at a higher deposition rate than on sidewalls of the at least one first trench. | 02-16-2012 |
20120045877 | FABRICATION METHOD OF POWER SEMICONDUCTOR STRUCTURE WITH REDUCED GATE IMPEDANCE - A fabrication method of a power semiconductor structure with reduced gate impedance is provided. Firstly, a polysilicon gate is formed in a substrate. Then, dopants are implanted into the substrate with the substrate being partially shielded by the polysilicon gate. Afterward, an isolation layer is formed to cover the polysilicon gate. Thereafter, a thermal drive-in process is carried out to form at least a body surrounding the polysilicon gate. Then, the isolation layer is removed to expose the polysilicon gate. Afterward, a metal layer is deposited on the dielectric layer and the polysilicon gate, and a self-aligned silicide layer is formed on the polysilicon gate by using a thermal process. | 02-23-2012 |
20120058615 | Method of Forming Shielded Gate Power Transistor Utilizing Chemical Mechanical Planarization - A method of forming a shielded gate field effect transistor includes: forming a plurality of active gate trenches in a silicon region; lining lower sidewalls and bottom of the active gate trenches with a shield dielectric; using a CMP process, filling a bottom portion of the active gate trenches with a shield electrode comprising polysilicon; forming an interpoly dielectric (IPD) over the shield electrode in the active gate trenches; lining upper sidewalls of the active gate trenches with a gate dielectric; and forming a gate electrode over the IPD in an upper portion of the active gate trenches. | 03-08-2012 |
20120064684 | METHOD FOR MANUFACTURING A SUPER-JUNCTION TRENCH MOSFET WITH RESURF STEPPED OXIDES AND TRENCHED CONTACTS - A method of manufacturing a super junction semiconductor device having resurf stepped oxide structure is disclosed by providing semiconductor silicon layer having trenches and mesas. A plurality of first doped column regions of a second conductivity type in parallel surrounded with second doped column regions of a first conductivity type adjacent to sidewalls of the trenches are formed by angle ion implantations into a plurality of mesas through opening regions in a block layer covering both the mesas and a termination area. | 03-15-2012 |
20120064685 | Methods of making random access memory devices, transistors, and memory cells - A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel. | 03-15-2012 |
20120083081 | METHOD FOR PRODUCING A GATE ELECTRODE STRUCTURE - A transistor with a gate electrode structure is produced by providing a semiconductor body with a first surface, and with a first sacrificial layer extending in a vertical direction of the semiconductor body from the first surface. A first trench extending from the first surface into the semiconductor body is formed by removing the sacrificial layer in a section adjacent the first surface. A second trench is formed by isotropically etching the semiconductor body in the first trench. A third trench is formed below the second trench by removing at least a part of the first sacrificial layer below the second trench. A dielectric layer is formed which at least covers sidewalls of the third trench and which only covers sidewalls of the second trench. A gate electrode is formed on the dielectric layer in the second trench. The gate electrode and dielectric layer in the second trench form the gate electrode structure. | 04-05-2012 |
20120083082 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing the semiconductor device includes forming a trench to be an alignment mark in a semiconductor substrate, forming a mask film exposing a region to be a device isolation region and covering a region to be a device region by aligning with the alignment mark above the semiconductor substrate with the trench formed in, anisotropically etching the semiconductor substrate with the mask film as a mask to form a device isolation trench in the region to be the device isolation region of the semiconductor substrate, and burying the device isolation trench by an insulating film to form a device isolation insulating film. In forming the trench, the trench is formed in a depth which is smaller than a depth equivalent to a thickness of the mask film. | 04-05-2012 |
20120083083 | Trench metal oxide semiconductor field effect transistor (MOSFET) with low gate to drain coupled charges (Qgd) structures - A trenched semiconductor power device includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The trenched semiconductor power device further comprises tilt-angle implanted body dopant regions surrounding a lower portion of trench sidewalls for reducing a gate-to-drain coupling charges Qgd between the trenched gates and a drain disposed at a bottom of the semiconductor substrate. The trenched semiconductor power device further includes a source dopant region disposed below a bottom surface of the trenched gates for functioning as a current path between the drain to the source for preventing a resistance increase caused by the body dopant regions surrounding the lower portions of the trench sidewalls. | 04-05-2012 |
20120083084 | Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier source - A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source and that may include a PtSi, ErSi layer and may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer. | 04-05-2012 |
20120083085 | METHOD FOR PRODUCING AN ELECTRODE STRUCTURE - A method for producing a semiconductor device with an electrode structure includes providing a semiconductor body with a first surface, and with a first sacrificial layer extending in a vertical direction of the semiconductor body from the first surface, and forming a first trench extending from the first surface into the semiconductor body. The first trench is formed at least by removing the sacrificial layer in a section adjacent to the first surface. The method further includes forming a second trench by isotropically etching the semiconductor body in the first trench, forming a dielectric layer which covers sidewalls of the second trench, and forming an electrode on the dielectric layer in the second trench, the electrode and the dielectric layer in the second trench forming the electrode structure. | 04-05-2012 |
20120094454 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING VERTICAL CHANNEL TRANSISTOR - A method of fabricating a semiconductor device including a vertical channel transistor. The method may include: forming a plurality of first device isolation layers in a substrate as a pattern of lines having a first depth from an upper surface of a substrate, to define a plurality of active regions, forming a plurality of trenches having a second depth smaller than the first depth, etching portions of the substrate that are under some of the plurality of trenches that are selected at a predetermined interval, to form a plurality of device isolation trenches having a third depth that is greater than the second depth, forming second device isolation layers that include an insulating material, in lower portions of the plurality of device isolation trenches, and forming buried bit lines in lower portions of the plurality of trenches and the plurality of device isolation trenches. | 04-19-2012 |
20120094455 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and method of manufacturing the same. The method includes: defining a first active area and a second active area on a substrate, the first and second active areas being in a line form, forming a first main trench and a second main trench on the substrate, forming a first sub-trench and a second sub-trench in bottoms of the first and second main trenches, respectively, forming a buried insulation layer filling the first and second sub-trenches, partially exposing the substrate at an area where the first active area crosses with the first sub-trench and an area where the second active area crosses with the second sub-trench and forming the first buried bit line and the second buried bit line on the buried insulation layer, and the first and second buried bit lines being extended in parallel to each other. | 04-19-2012 |
20120100682 | Manufactruing method of semiconductor device having vertical type transistor - A manufacturing method of a semiconductor device includes the steps of: forming an insulating pillar on the main surface of a silicon substrate; forming a protective film on the side surface of the insulating pillar; forming a silicon pillar on the main surface of the silicon substrate; forming a gate insulating film on the side surface of the silicon pillar; and forming first and second gate electrodes so as to contact each other and so as to cover the side surfaces of the silicon pillar and insulating pillar, respectively. According to the present manufacturing method, the protective film is formed on the side surface of the insulating pillar as a dummy pillar, thus preventing the dummy pillar from being eroded when the silicon pillar for channel is processed into a transistor. Therefore, it is possible to reduce a probability of occurrence of gate electrode disconnection. | 04-26-2012 |
20120100683 | TRENCH-TYPED POWER MOS TRANSISTOR AND METHOD FOR MAKING THE SAME - A trench-typed power MOS transistor comprises a trench-typed gate area, which includes a gate conductor and an isolation layer. A thin sidewall region of the isolation layer is formed between the gate conductor and a well region. A thick sidewall region of the isolation layer is formed between the gate conductor and a double diffusion region. A thick bottom region of the isolation layer is formed between the gate conductor and a deep well region. | 04-26-2012 |
20120129306 | CONFIGURATION AND METHOD TO FORM MOSFET DEVICES WITH LOW RESISTANCE SILICIDE GATE AND MESA CONTACT REGIONS - A novel integration scheme for forming power MOSFET, particularly forming salicided layers for both gate contact regions and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicided layers. | 05-24-2012 |
20120129307 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The present invention provides a technique capable of attaining an improvement in current detection accuracy in a trench gate type power MISFET equipped with a current detection circuit. Inactive cells are disposed so as to surround the periphery of a sense cell. That is, the inactive cell is provided between the sense cell and an active cell. All of the sense cell, active cell and inactive cells are respectively formed of a trench gate type power MISFET equipped with a dummy gate electrode. At this time, the depth of each trench extends through a channel forming region and is formed up to the deep inside (the neighborhood of a boundary with a semiconductor substrate) of an n-type epitaxial layer. Further, a p-type semiconductor region is provided at a lower portion of each trench. The p-type semiconductor region is formed so as to contact the semiconductor substrate. | 05-24-2012 |
20120135573 | METHOD FOR MANUFACTURING VERTICAL TRANSISTOR HAVING ONE SIDE CONTACT - A method for manufacturing a vertical transistor having a one side contact includes: forming separate active regions using trenches, on a semiconductor substrate, the active regions having first and second side surfaces facing the trenches; forming a first liner on the first and second side surfaces; forming a second liner which exposes a lower portion of the first liner on the first side surface; forming a third liner covering the portion of the first layer exposed by the second liner; forming a sacrifice layer on the third liner to fill the trench; forming an etch barrier to selectively expose upper end portions of the first to third liners positioned adjacent to the first side surface; selectively removing the third liner not covered by the etch barrier to expose a portion of the first liner not covered by the second liner; selectively removing the exposed portion of the first liner to expose a lower portion of the first side surface; and forming a buried bit line contacted with the exposed portion of the first side surface. | 05-31-2012 |
20120142155 | HIGH ASPECT RATIO TRENCH STRUCTURES WITH VOID-FREE FILL MATERIAL - A field effect transistor (FET) includes a trench extending into a semiconductor region. A conductive electrode is disposed in the trench, and the conductive electrode is insulated from the semiconductor region by a dielectric layer. The conductive electrode includes a conductive liner lining the dielectric layer along opposite sidewalls of the trench. The conductive liner has tapered edges such that a thickness of the conductive liner gradually increases from a top surface of the conductive electrode to a point in lower half of the conductive electrode. The conductive electrode further includes a conductive fill material sandwiched by the conductive liner. The FET further includes a drift region of a first conductivity type in the semiconductor region, and a body region of a second conductivity type extending over the drift region. Source regions of the first conductivity type extend in the body region adjacent the trench. | 06-07-2012 |
20120142156 | INSULATED GATE TYPE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer. | 06-07-2012 |
20120149161 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is disclosed. A resist pattern is formed on a surface of a semiconductor layer in which a first layer and a second layer are sequentially formed on a substrate. A gate recess is formed by removing a part or the entire second layer in an opening area of the resist pattern. The resist pattern is removed. A dry etching residue attached to a bottom surface and lateral surfaces of the gate recess is removed after the resist pattern is removed. An insulating film is formed on the bottom surface, the lateral surfaces, and the semiconductor layer after the dry etching residue is removed. A gate electrode is formed via the insulating film on an area where the gate recess is formed. A source electrode and a drain electrode are formed on the semiconductor layer. | 06-14-2012 |
20120156844 | SEMICONDUCTOR DEVICES INCLUDING VERTICAL CHANNEL TRANSISTORS AND METHODS OF FABRICATING THE SAME - Methods of fabricating semiconductor devices may include forming first trenches in a substrate to define fin patterns and forming buried dielectric patterns filling lower regions of the first trenches. The first trenches extend in parallel. A gate dielectric layer is formed on upper inner sidewalls of the first trenches, and a gate conductive layer filling the first trenches is formed on the substrate including the gate dielectric layer. The gate conductive layer, the gate dielectric layer and the fin patterns are patterned to form second trenches crossing the first trenches and defining active pillars. Semiconductor devices may also be provided. | 06-21-2012 |
20120156845 | METHOD OF FORMING A FIELD EFFECT TRANSISTOR AND SCHOTTKY DIODE - A method for forming a field effect transistor and Schottky diode includes forming a well region in a first portion of a silicon region where the field effect transistor is to be formed but not in a second portion of the silicon region where the Schottky diode is to be formed. Gate trenches are formed extending into the silicon region. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. Exposed surfaces of the well region are recessed to form a recess between every two adjacent trenches. Without masking any portion of the active area, a zero-degree blanket implant is performed to form a heavy body region of the second conductivity type in the well region between every two adjacent trenches. | 06-21-2012 |
20120171828 | Method of Forming a FET Having Ultra-low On-resistance and Low Gate Charge - In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor. | 07-05-2012 |
20120178230 | METHOD FOR FABRICATING TRENCH DMOS TRANSISTOR - A method for fabricating trench DMOS transistor includes: forming an oxide layer and a barrier layer with photolithography layout sequentially on a semiconductor substrate; etching the oxide layer and the semiconductor substrate with the barrier layer as a mask to form a trench; forming a gate oxide layer on the inner wall of the trench; forming a polysilicon layer on the barrier layer, filling up the trench; etching back the polysilicon layer with the barrier layer mask to remove the polysilicon layer on the barrier layer to form a trench gate; removing the barrier layer and the oxide layer; implanting ions into the semiconductor substrate on both sides of the trench gate to form a diffusion layer; coating a photoresist layer on the diffusion layer and defining a source/drain layout thereon; implanting ions into the diffusion layer based on the source/drain layout with the photoresist layer mask to form the source/drain; forming sidewalls on both the sides of the trench gate after removing the photoresist layer; and forming a metal silicide layer on the diffusion layer and the trench gate. Effective result of the present invention is achieved with lower cost and improved efficiency of fabrication. | 07-12-2012 |
20120196416 | TRENCH MOSFET WITH ULTRA HIGH CELL DENSITY AND MANUFACTURE THEREOF - A trench MOSFET structure with ultra high cell density is disclosed, wherein the source regions and the body regions are located in different regions to save the mesa area between every two adjacent gate trenches in the active area. Furthermore, the inventive trench MOSFET is composed of stripe cells to further increase cell packing density and decrease on resistance Rds between the drain region and the source region. | 08-02-2012 |
20120202327 | Compressive Polycrystalline Silicon Film and Method of Manufacture Thereof - In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C. | 08-09-2012 |
20120214285 | Methods Of Forming A Vertical Transistor And At Least A Conductive Line Electrically Coupled Therewith, Methods Of Forming Memory Cells, And Methods Of Forming Arrays Of Memory Cells - Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed. | 08-23-2012 |
20120220089 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A gate electrode is formed so as to embed an electrode material in a recess for an electrode, which has been formed in a structure of stacked compound semiconductors, through a gate insulation film, and also a field plate electrode that comes in Schottky contact with the structure of the stacked compound semiconductors is formed by embedding an electrode material in a recess for an electrode, which has been formed in the structure of the stacked compound semiconductors so that the field plate electrode directly comes in contact with the structure of the stacked compound semiconductors at least on the bottom face of the recess for the electrode. | 08-30-2012 |
20120220090 | METHOD FOR MANUFACTURING AN INTEGRATED POWER DEVICE ON A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICE - An embodiment of a method for manufacturing a power device being integrated on a semiconductor substrate comprising at least the steps of making, in the semiconductor substrate, at least a trench having sidewalls and a bottom, covering the sidewalls and the bottom of said at least one trench with a first insulating coating layer and making, inside said at least one trench, a conductive gate structure. An embodiment of the method provides the formation of the conductive gate structure comprising the steps of covering at least the sidewalls with a second conductive coating layer of a first conductive material; making a conductive central region of a second conductive material having a different resistivity than the first conductive material; and making a plurality of conductive bridges between said second conductive coating layer and said conductive central region. | 08-30-2012 |
20120220091 | METHODS OF MAKING POWER SEMICONDUCTOR DEVICES WITH THICK BOTTOM OXIDE LAYER - A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench. | 08-30-2012 |
20120220092 | METHOD OF FORMING A HYBRID SPLIT GATE SIMICONDUCTOR - Method of forming a Hybrid Split Gate Semiconductor. In accordance with a method embodiment of the present invention, a plurality of first trenches is formed in a semiconductor substrate to a first depth. A plurality of second trenches is formed in the semiconductor substrate to a second depth. The first plurality of trenches are parallel with the second plurality of trenches. The trenches of the plurality of first trenches alternate with and are adjacent to trenches of the plurality of second trenches. | 08-30-2012 |
20120231595 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure is provided. A second area is between first and third areas. An epitaxial layer is formed on a substrate. A first gate is formed in the epitaxial layer and partially in first and second areas. A second gate is formed in the epitaxial layer and partially in second and third areas. A body layer is formed in the epitaxial layer in first and second areas. A doped region is formed in the body layer in the first area. All of the doped region, the epitaxial layer and the second gate are partially removed to form a first opening in the doped region and in the body layer in the first area, and form a second opening in the epitaxial layer in the third area and in a portion of the second gate. A first metal layer is filled in first and second openings. | 09-13-2012 |
20120244672 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can form a plurality of grooves extending in a first direction on a semiconductor substrate. The method can form an insulating layer on the inner face of the groove and on the top face of the semiconductor substrate. The method can deposit a first conductive layer on the insulating layer so as to fill in the groove. The method can deposit a second conductive layer on the first conductive layer. The method can form a hard mask in a region including part of a region immediately above the groove on the second conductive layer. The method can form a columnar body including the hard mask and the second conductive layer by etching the second conductive layer using the hard mask as a mask. | 09-27-2012 |
20120258578 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an epitaxial layer having a first conduction type, a base layer formed adjacent and on the epitaxial layer and having an opposite second conduction type to the first conduction type, a source layer formed selectively on the base layer and having the first conduction type, a trench which passes through the base layer and the source layer and which reaches the epitaxial layer, an insulation film formed along an interior wall of the trench, a control electrode formed within the trench via the insulation film, and a semiconductor region formed along the bottom part of the trench at the epitaxial layer and having the first conduction type. | 10-11-2012 |
20120264266 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a step-type recess pattern formed in a substrate, a gate electrode buried in the recess pattern and having a gap disposed between the gate electrode and upper sidewalls of the recess pattern, an insulation layer filling the gap, and a source and drain region formed in a portion of the substrate at two sides of the recess pattern. The semiconductor device is able to secure a required data retention time by suppressing the increase of leakage current caused by the reduction of a design rule. | 10-18-2012 |
20120270375 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a semiconductor device which prevents defects and achieves miniaturization. A projecting portion or a trench (a groove portion) is formed in an insulating layer and a channel formation region of a semiconductor layer is provided in contact with the projecting portion or the trench, so that the channel formation region is extended in a direction perpendicular to a substrate. Thus, miniaturization of the transistor can be achieved and an effective channel length can be extended. In addition, before formation of the semiconductor layer, an upper-end corner portion of the projecting portion or the trench with which the semiconductor layer is in contact is subjected to round chamfering, so that a thin semiconductor layer can be formed with good coverage. | 10-25-2012 |
20120276701 | Superjunction Structures for Power Devices and Methods of Manufacture - A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type. | 11-01-2012 |
20120276702 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a channel region, forming a buffer layer on the channel region, and heat-treating the channel region by using a gas containing halogen atoms. | 11-01-2012 |
20120276703 | METHOD OF FORMING AN INSULATED GATE FIELD EFFECT TRANSISTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE - A method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming dielectric stack overlying a substrate. The dielectric stack includes a first layer of one material overlying the substrate and a second layer of a different material overlying the first layer. Trench regions are formed adjacent to the dielectric stack. | 11-01-2012 |
20120282745 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device according to the present invention includes forming a first trench and a second trench by etching the first trench further, in an epitaxial layer formed over a substrate, extending a width of the second trench, forming an oxidize film by oxidizing the extended second trench, and filling an electrode material in the first trench and the second trench including the oxidized film formed therein. The method of fabricating a semiconductor device according to the present invention enables to fabricate a semiconductor device that improves the withstand voltage between a drain and a source and reduce the on-resistance. | 11-08-2012 |
20120282746 | INVERTED-TRENCH GROUNDED-SOURCE FET STRUCTURE USING CONDUCTIVE SUBSTRATES, WITH HIGHLY DOPED SUBSTRATES - This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination. | 11-08-2012 |
20120289012 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, disposed on a surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; a trench that penetrates the second semiconductor region to reach the first semiconductor region; a first electrode disposed inside the trench via an insulating film; a first recess portion disposed deeper than an upper end of the first electrode, in a surface layer of the second semiconductor region, so as to be in contact with the trench; and a second electrode embedded in the first recess portion. | 11-15-2012 |
20120289013 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset. | 11-15-2012 |
20120295410 | METHOD FOR FABRICATING SUPER-JUNCTION POWER DEVICE WITH REDUCED MILLER CAPACITANCE - A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer. | 11-22-2012 |
20120295411 | CLOSED CELL TRENCH POWER MOSFET STRUCTURE AND METHOD TO FABRICATE THE SAME - A closed cell trench MOSFET structure having a drain region of a first conductivity type, a body of a second conductivity type, a trenched gate, and a plurality of source regions of the first conductivity type is provided. The body is located on the drain region. The trenched gate is located in the body and has at least two stripe portions and a cross portion. A bottom of the stripe portions is located in the drain region and a bottom of the cross portion is in the body. The source regions are located in the body and at least adjacent to the stripe region of the trenched gate. | 11-22-2012 |
20120302021 | FABRICATION OF MOS DEVICE WITH VARYING TRENCH DEPTH - Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; disposing gate material in the gate trench; forming a body in the epitaxial layer; forming a source in the body; forming an active region contact trench that has a varying trench depth; and disposing a contact electrode within the active region contact trench. Forming the active region contact trench includes performing a first etch to form a first contact trench depth associated with a first region, and performing a second etch to form a second contact trench depth associated with a second region. The first contact trench depth is substantially different from the second contact trench depth. | 11-29-2012 |
20120309147 | Semiconductor Component and Method for Producing a Semiconductor Component - A semiconductor component is produced by forming a trench in a semiconductor region. The trench has an upper trench region and a lower trench region. The upper trench region is wider than the lower trench region such that a step is formed in the semiconductor region. A dopant is introduced into the step to form a locally delimited dopant region in the semiconductor region. | 12-06-2012 |
20120309148 | METHOD FOR MANUFACTURING A POWER SEMICONDUCTOR DEVICE - A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures. | 12-06-2012 |
20120322217 | FABRICATION METHOD OF TRENCHED POWER SEMICONDUCTOR DEVICE WITH SOURCE TRENCH - A fabrication method of a trenched power semiconductor device with source trench is provided. Firstly, at least two gate trenches are formed in a base. Then, a dielectric layer and a polysilicon structure are sequentially formed in the gate trench. Afterward, at least a source trench is formed between the neighboring gate trenches. Next, the dielectric layer and a second polysilicon structure are sequentially formed in the source trench. The second polysilicon structure is located in a lower portion of the source trench. Then, the exposed portion of the dielectric layer in the source trench is removed to expose a source region and a body region. Finally, a conductive structure is filled into the source trench to electrically connect the second polysilicon structure, the body region, and the source region. | 12-20-2012 |
20120329225 | POWER MOS DEVICE FABRICATION - Fabricating a semiconductor device includes forming a mask on a substrate having a top substrate surface; forming a gate trench in the substrate, through the mask; depositing gate material in the gate trench; removing the mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; forming a plug in the source body contact trench, wherein the plug extends below a bottom of the body region; and disposing conductive material in the source body contact trench, on top of the plug. | 12-27-2012 |
20120329226 | LOW POWER MEMORY DEVICE WITH JFET DEVICE STRUCTURES - There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory cells having a memory element and a JFET access device electrically coupled to the memory element. The memory cells may be isolated using diffusion based isolation. | 12-27-2012 |
20120329227 | Formation of Field Effect Transistor Devices - A method includes defining active regions on a substrate, forming a dummy gate stack material over exposed portions of the active regions of the substrate and non-active regions of the substrate, removing portions of the dummy gate stack material to expose portions of the active regions and non-active regions of the substrate and define dummy gate stacks, forming a gap-fill dielectric material over the exposed portions of the substrate and the source and drain regions, removing portions of the gap-fill dielectric material to expose the dummy gate stacks, removing the dummy gate stacks to form dummy gate trenches, forming dividers within the dummy gate trenches, depositing gate stack material inside the dummy gate trenches, over the dividers, and the gap-fill dielectric material, and removing portions of the gate stack material to define gate stacks. | 12-27-2012 |
20130005101 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE INCLUDING A DIELECTRIC LAYER - A method for producing a semiconductor device with a dielectric layer includes: providing a semiconductor body with a first trench extending into the semiconductor body, the first trench having a bottom and a sidewall; forming a first dielectric layer on the sidewall in a lower portion of the first trench; forming a first plug in the lower portion of the first trench so as to cover the first dielectric layer, the first plug leaving an upper portion of the sidewall uncovered; forming a sacrificial layer on the sidewall in the upper portion of the first trench; forming a second plug in the upper portion of the first trench; removing the sacrificial layer, so as to form a second trench having sidewalls and a bottom; and forming a second dielectric layer in the second trench and extending to the first dielectric layer. | 01-03-2013 |
20130005102 | Data Cells with Drivers and Methods of Making and Operating the Same - Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate, and a third gate extending between the first semiconductor fin and the second semiconductor fin. In some embodiments, the third gate may not be electrically connected to the first gate or the second gate. | 01-03-2013 |
20130023096 | SINGLE CRYSTAL U-MOS GATES USING MICROWAVE CRYSTAL REGROWTH - Semiconductor devices and methods for making such devices are described. The UMOS semiconductor devices contain single-crystal gates that have been re-grown or formed at low temperature using microwaves. The devices can be formed by providing a semiconductor substrate, forming a trench in the substrate, forming an insulating layer in the trench, depositing a pre-gate layer on the insulating layer, the pre-gate layer comprising a conductive and/or semiconductive material (Si or SiGe) with a non-single crystal structure, contacting the pre-gate layer with a seed layer with a single-crystal structure, and heating the pre-gate layer using microwaves at low temperatures to recrystallize the non-single crystal structure into a single-crystal structure. These processes can improve the resistance and mobility of the gate either as a single crystal structure, optionally with a silicide contact above the source-well junction, enabling a higher switching speed UMOS device. Other embodiments are described. | 01-24-2013 |
20130023097 | U-MOS TRENCH PROFILE OPTIMIZATION AND ETCH DAMAGE REMOVAL USING MICROWAVES - Semiconductor devices and methods for making such devices are described. The UMOS (U-shaped MOSFET) semiconductor devices can be formed by providing a semiconductor substrate, forming a trench in the substrate using a wet or dry etching process, and then radiating the trench structure using microwaves (MW) at low temperatures. The MW radiation process improves the profile of the trench and repairs the damage to the trench structure caused by the dry etching process. The microwave radiation can help re-align the Si or SiGe atoms in the semiconductor substrate and anneal out the defects present after the dry etching process. As well, the microwave radiation can getter atoms or ions used in the dry etching process that are left in the lattice of the trench structure. Other embodiments are described. | 01-24-2013 |
20130029465 | MANUFACTURING METHOD OF MEMORY STRUCTURE - The instant disclosure relates to a manufacturing method of memory structure for dynamic random-access memory (DRAM). The method includes the steps of: (a) providing a substrate having a plurality of parallel trenches formed on a planar surface thereof each defining a buried gate, where a first insulating layer is formed on the planar surface of the substrate; (b) forming a gate oxide layer on the surface of each trench that defines the buried gate; (c) disposing a metal filler on the gate oxide layer to fill each of the trenches; (d) removing the metal filler in the upper region of each trench to selectively expose the gate oxide layer; (e) implanting ions at an oblique angle toward the exposed portions of the gate oxide layer in each trench to respectively form a drain electrode and a source electrode in the substrate abreast the gate oxide layer. | 01-31-2013 |
20130029466 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor device, including: a first semiconductor region of a first conductivity type; a second semiconductor region having pairs of first pillar regions of the first conductivity type, and second pillar regions of a second conductivity type alternately provided; a third semiconductor region of the second conductivity type; a fourth semiconductor region of the first conductivity type; and control electrodes each provided within a trench through an insulating film, a sidewall of the trench being formed so as to contact each of the third semiconductor region and the fourth semiconductor region. | 01-31-2013 |
20130052780 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - In a method of fabricating a semiconductor device, isolation structures are formed in a substrate to define active regions. Conductive structures are formed on the substrate to cross over at least two of the active regions and the isolation structures, the conductive structures extending in a first direction. An interfacial layer is conformally formed on the substrate in contact with the conductive structures. A first insulation layer is provided on the interfacial layer, wherein the first insulation layer is formed using a flowable chemical vapor deposition (CVD) process, and wherein the interfacial layer reduces a tensile stress generated at an interface between the conductive structures and the first insulation layer while the first insulation layer is formed. | 02-28-2013 |
20130059423 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device, including: forming an active region surrounded by an element isolation region in a substrate; forming a pair of gate trenches in the active region; forming a pair of gate electrodes by embedding a conductor in the gate trenches; forming an implanted layer by implanting ions into a substrate surface between the gate electrodes; and thermally diffusing impurities of the implanted layer at least to a depth of bottom portions of the gate trenches by a transient enhanced diffusion method to form a diffusion layer region between the gate electrodes at least to a depth of bottom portions of the gate electrodes. | 03-07-2013 |
20130059424 | Buried Gate Transistor - An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess. | 03-07-2013 |
20130095626 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device, includes: and forming, on an upper face of a silicon substrate, a plurality of concave portions extending in a first direction, performing, in a gas that contains fluorine or a fluoride, plasma processing on the silicon substrate in which the concave portions are formed. The method further includes performing, in a gas that contains hydrogen, thermal processing on the silicon substrate after completion of performing the plasma processing; forming an insulating film on an inner face of the concave portions after completion of performing the thermal processing; and forming a conductive film on the insulating film. | 04-18-2013 |
20130102118 | SEMICONDUCTOR DEVICE WITH ONE-SIDE-CONTACT AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench. | 04-25-2013 |
20130109143 | Vertical Gate LDMOS Device | 05-02-2013 |
20130115744 | Vertical Gate LDMOS Device - A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material. | 05-09-2013 |
20130115745 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING DEVICE ISOLATION TRENCHES SELF-ALIGNED TO GATE TRENCHES - Methods of manufacturing a semiconductor device can be provided by forming a structure including a plurality of gate trenches that extend in a first direction and a mold layer having openings and that extend in the first direction on a substrate. Filling layers can be formed to fill the openings and the mold layer can be removed so that the filling layers remain on the substrate. A spacer layer can be formed which fills a space between the filling layers directly adjacent to each other at one side of each of the filling layers and forms a spacer at the sidewall of each of the filling layers at the other side of each of the filling layers. Device isolation trenches can be formed that extend in parallel to the plurality of gate trenches by etching the substrate exposed by the spacer layer. | 05-09-2013 |
20130115746 | Method for Fabricating a Vertical LDMOS Device - A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprises a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one embodiment, a method for fabricating a vertically arranged LDMOS device comprises forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. The method further comprises diffusing impurities from the diffusion agent layer through the dielectric material to form a lightly doped drain region extending laterally around the sidewalls into the semiconductor body. | 05-09-2013 |
20130115747 | TRENCH GATE SEMICONDUCTOR DEVICE AND THE METHOD OF MANUFACTURING THE SAME - A trench gate semiconductor device is disclosed which has a trench gate structure including an insulator in the upper portion of a first trench, the insulator being on a gate electrode; a source region having a lower end surface positioned lower than the upper surface of the gate electrode; a second trench in the surface portion of a semiconductor substrate between the first trenches, the second trench having a slanted inner surface providing the second trench with the widest trench width at its opening and a bottom plane positioned lower than the lower end surface of the source region, the slanted inner surface being in contact with the source region; and a p-type body-contact region in contact with the slanted inner surface of the second trench. The trench gate semiconductor device and its manufacturing method facilitate increasing the channel density and lowering the body resistance of the parasitic BJT. | 05-09-2013 |
20130130455 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to a method of manufacturing a semiconductor device including a buried gate, after a recess is formed by etching a semiconductor substrate, since an etching back process is not performed on a gate electrode material buried within the recess, variability in the depth of the gate electrode material can be reduced. In addition, GIDL can be improved by a selective oxidation process and control of a thickness of a spacer and data retention time can be increased. | 05-23-2013 |
20130137230 | Semiconductor Device with Field Electrode - A method of producing a semiconductor device includes providing a semiconductor body having a first surface and a dielectric layer arranged on the first surface and forming at least one first trench in the dielectric layer. The at least one first trench extends to the semiconductor body and defines a dielectric mesa region in the dielectric layer. The method further includes forming a second trench in the dielectric mesa region distant to the at least one first trench, forming a semiconductor layer on uncovered regions of the semiconductor body in the at least one first trench and forming a field electrode in the second trench. | 05-30-2013 |
20130149824 | METHOD FOR MANUFACTURING A TUNNELING FIELD EFFECT TRANSISTOR WITH A U-SHAPED CHANNEL - The present invention belongs to the technical field of semiconductor device manufacturing and specifically relates to a method for manufacturing a tunneling field effect transistor with a U-shaped channel. The U-shaped channel can effectively extend the transistor channel length, restrain the generation of leakage current in the transistor, and decrease the chip power consumption. The method for manufacturing a tunneling field effect transistor with a U-shaped channel put forward in the present invention is capable of realizing an extremely narrow U-shaped channel, overcoming the alignment deviation introduced by photoetching, and improving the chip integration degree. | 06-13-2013 |
20130149825 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device which combines reliability and the guarantee of electrical characteristics is provided. A power MOSFET and a protection circuit formed over the same semiconductor substrate are provided. The power MOSFET is a trench gate vertical type P-channel MOSFET and the conduction type of the gate electrode is assumed to be P-type. The protection circuit includes a planar gate horizontal type offset P-channel MOSFET and the conduction type of the gate electrode is assumed to be N-type. These gate electrode and gate electrode are formed in separate steps. | 06-13-2013 |
20130149826 | FinFETs with Multiple Fin Heights - An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces. | 06-13-2013 |
20130157428 | Methods of Manufacturing Semiconductor Devices Including Transistors - A method of manufacturing a semiconductor device includes forming a gate insulation layer pattern on a substrate, forming a sacrificial layer including impurities on the gate insulation layer pattern, annealing the sacrificial layer so that the impurities in the sacrificial layer diffuse into the gate insulation layer pattern, removing the sacrificial layer, and forming a gate electrode on the gate insulation layer pattern. | 06-20-2013 |
20130164895 | Trench-Gated Power Devices with Two Types of Trenches and Reliable Polycidation - Methods and systems for power semiconductor devices and structures with silicide cladding on both gates and field plates. Sidewall spacers, e.g. of silicon nitride, avoid lateral shorts or leakage between the gate silicide and the source region. A source metallization makes lateral contact to the shallow n++ source, and also makes contact to the field plate silicide and the p+ body contact region. | 06-27-2013 |
20130189819 | METHOD OF MANUFACTURING VERTICAL PLANAR POWER MOSFET AND METHOD OF MANUFACTURING TRENCH-GATE POWER MOSFET - In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth. | 07-25-2013 |
20130196477 | METHODS OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING FINE PATTERNS - Methods of fabricating a semiconductor device are provided. The method includes forming active lines in a semiconductor substrate, forming contact lines generally crossing over the active lines, forming line-shaped etch mask patterns generally crossing over the active lines and the contact lines, etching the contact lines exposed by the line-shaped etch mask patterns to form contact separation grooves and to form contact patterns generally remaining at intersections between the line-shaped etch mask patterns and the active lines, etching the active lines exposed by the contact separation grooves to form active separation grooves that generally divide each of the active lines into a plurality of active patterns, forming gates that substantially intersect the active patterns, and forming bit lines electrically connected to the contact patterns. | 08-01-2013 |
20130210204 | METHOD FOR ETCHING POLYCRYSTALLINE SILICON, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND ETCHING PROGRAM - According to an embodiment, a method for etching polycrystalline silicon includes a step of holding the polycrystalline silicon at a temperature higher than or equal to T | 08-15-2013 |
20130224919 | METHOD FOR MAKING GATE-OXIDE WITH STEP-GRADED THICKNESS IN TRENCHED DMOS DEVICE FOR REDUCED GATE-TO-DRAIN CAPACITANCE - A method for making gate-oxide with step-graded thickness (S-G GOX) in a trenched DMOS device is proposed. First, a substrate is provided and a silicon oxide-silicon nitride-silicon oxide (ONO) protective composite layer is formed atop. Second, an upper interim trench (UIT), an upper trench protection wall (UTPW) and a lower interim trench (LIT) are created into the substrate. Third, the substrate material surrounding the LIT is shaped and oxidized into a desired thick-oxide-layer of thickness T | 08-29-2013 |
20130224920 | SEMICONDUCTOR DEVICE INCLUDING METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTORS AND METHODS OF FABRICATING THE SAME - A method of fabricating a semiconductor device may include patterning a substrate to form trenches, forming a sacrificial layer to cover inner surfaces of the trenches, the sacrificial layer having a single-layered structure, forming sacrificial patterns by isotropically etching the sacrificial layer such that the sacrificial layer remains on bottom surfaces of the trenches, forming lightly doped regions in sidewalls of the trenches using the sacrificial patterns as an ion mask, removing the sacrificial patterns, and sequentially forming a gate insulating layer and a gate electrode layer in the trenches. | 08-29-2013 |
20130224921 | LATERAL TRENCH TRANSISTOR, AS WELL AS A METHOD FOR ITS PRODUCTION - A method for production of doped semiconductor regions in a semiconductor body of a lateral trench transistor includes forming a trench in the semiconductor body and introducing dopants into at least one area of the semiconductor body that is adjacent to the trench, by carrying out a process in which dopants enter the at least one area through inner walls of the trench. | 08-29-2013 |
20130224922 | UMOS Semiconductor Devices Formed by Low Temperature Processing - UMOS (U-shaped trench MOSFET) semiconductor devices that have been formed using low temperature processes are described. The source region of the UMOS structure can be formed before the etch processes that are used to create the trench, allowing low-temperature materials to be incorporated into the semiconductor device from the creation of the gate oxide layer oxidation forward. Thus, the source drive-in and activation processing that are typically performed after the trench etch can be eliminated. The resulting UMOS structures contain a trench structure with both a gate insulting layer comprising a low temperature dielectric material and a gate conductor comprising a low temperature conductive material. Forming the source region before the trench etch can reduce the problems resulting from high temperature processes, and can reduce auto doping, improve threshold voltage control, reduce void creation, and enable incorporation of materials such as silicides that cannot survive high temperature processing. Other embodiments are described. | 08-29-2013 |
20130230955 | METHOD FOR FABRICATING A VERTICAL TRANSISTOR - A method for fabricating a vertical transistor comprises steps: forming a plurality of first trenches in a substrate; sequentially epitaxially growing a first polarity layer and a channel layer inside the first trenches, and forming a first retard layer on the channel layer; etching the first retard layer and the channel layer along the direction vertical to the first trenches to form a plurality of pillars; respectively forming a gate on a first sidewall and a second sidewall of each pillar; removing the first retard layer on the pillar; and epitaxially growing a second polarity layer on the pillar. The present invention is characterized by using an epitaxial method to form the first polarity layer, the channel layer and the second polarity layer and has the advantage of uniform ion concentration distribution. Therefore, the present invention can fabricate a high-quality vertical transistor. | 09-05-2013 |
20130230956 | Trench Electrode Arrangement - A method includes forming a trench extending from a first surface of a semiconductor body into the semiconductor body such that a first trench section and at least one second trench section adjoin the first trench section, wherein the first trench section is wider than the second trench section. A first electrode is formed, in the at least one second trench section, and dielectrically insulated from semiconductor regions of the semiconductor body by a first dielectric layer. An inter-electrode dielectric layer is formed, in the at least one second trench section, on the first electrode. A second electrode is formed, in the at least one second trench section on the inter-electrode dielectric layer, and in the first trench section, such that the second electrode at least in the first trench section is dielectrically insulated from the semiconductor body by a second dielectric layer. | 09-05-2013 |
20130230957 | Methods of Forming Field Effect Transistors on Substrates - The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field effect transistor comprises a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region. Such implementation includes conducting a dopant activation anneal of the pair of source/drain regions prior to depositing material from which a conductive portion of the transistor gate is made. Other aspects and implementations are contemplated. | 09-05-2013 |
20130244385 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a trench MOSFET through use of a simple process having good controllability, which is capable of forming the trench MOSFET on the same substrate as a CMOS transistor and capable of reducing the element area. The method of manufacturing a trench MOSFET includes a formation of a three-dimensional body contact region. Thus, the trench MOSFET can have a structure which can ensure a contact similar to that in a conventional case even in a smaller area. | 09-19-2013 |
20130244386 | SELF-ALIGNED CARBON ELECTRONICS WITH EMBEDDED GATE ELECTRODE - A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack that includes a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions. | 09-19-2013 |
20130260523 | METHOD FOR FABRICATING SUPER-JUNCTION POWER DEVICE WITH REDUCED MILLER CAPACITANCE - A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer. | 10-03-2013 |
20130273704 | METHODS OF FORMING A POLYSILICON LAYER AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of forming a polysilicon layer includes providing a silicon precursor onto an object loaded in a process chamber to form a seed layer. The silicon precursor includes a nitrogen containing silicon precursor and a chlorine containing silicon precursor. The method further includes providing a silicon source on the seed layer. | 10-17-2013 |
20130288442 | METHOD FOR FORMING IMPURITY REGION OF VERTICAL TRANSISTOR AND METHOD FOR FABRICATING VERTICAL TRANSISTOR USING THE SAME - A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region. | 10-31-2013 |
20130295736 | FABRICATION METHOD OF TRENCH POWER SEMICONDUCTOR STRUCTURE - A fabrication method of a trench power semiconductor structure is provided. First, a substrate with a first epitaxial layer is provided. Then, a dielectric layer is formed on the first epitaxial layer. A shielding layer is formed on the dielectric layer. Next, a portion of the shielding and the dielectric layers are removed to form a shielding structure and a dielectric structure on the first epitaxial layer, wherein the shielding structure is stacked on the dielectric structure. A selective epitaxial growth technique is utilized to form a second epitaxial layer surrounding the dielectric and the shielding structures on the exposed surface of the first epitaxial layer and the second epitaxial layer. Afterward, the shielding structure is removed to form a trench on the dielectric structure. A gate oxide layer is further formed on the inner surface of the trench. Lastly, a conducting structure is formed in the trench. | 11-07-2013 |
20130295737 | Semiconductor Cells, Arrays, Devices and Systems Having a Buried Conductive Line and Methods for Forming the Same - Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device. | 11-07-2013 |
20130302958 | METHOD OF MAKING AN INSULATED GATE SEMICONDUCTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE - In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer. | 11-14-2013 |
20130302959 | Semiconductor Device With Vertical Channel Transistor And Method Of Fabricating The Same - A semiconductor device with vertical channel transistors and a method of fabricating the same are provided. A method of fabricating the semiconductor device includes patterning a substrate to form a trench that defines an active region, forming a sacrificial pattern in a lower region of the trench, forming a spacer on an upper sidewall of the trench, recessing a top surface of the sacrificial pattern to form a window exposing a sidewall of the active region between the spacer and the sacrificial pattern, doping a sidewall of the trench through the window to form a doped region in the active region, and forming a wiring in the trench to be connected to the doped region. | 11-14-2013 |
20130309827 | Method for Manufacturing a Transistor for Preventing or Reducing Short Channel Effect - A transistor for preventing or reducing short channel effect includes a substrate; a gate stack disposed over the substrate; a first junction region disposed on the substrate at a first side surface of the gate stack, said first junction layer being formed of an epitaxial layer; a trench formed within the substrate at a second side surface of the gate stack; and a second junction region disposed below the trench, said second junction layer being lower than the first junction region. | 11-21-2013 |
20130309828 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a semiconductor device manufacturing method, comprising forming a first sacrificial layer that contacts at least a portion of a first semiconductor layer and has a higher solid solubility for impurities included in the first semiconductor layer than the first semiconductor layer; annealing the first sacrificial layer and the first semiconductor layer; removing the first sacrificial layer through a wet process; after removing the first sacrificial layer, performing at least one of forming an insulating layer that covers at least a portion of the first semiconductor layer and etching a portion of the first semiconductor layer; and forming an electrode layer that is electrically connected to the first semiconductor layer. | 11-21-2013 |
20130323897 | SEMICONDUCTOR DEVICE WITH IMPROVED ON-RESISTANCE - A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone. | 12-05-2013 |
20130330895 | METHOD OF MANUFACTURING THE TRENCH POWER SEMICONDUCTOR STRUCTURE - A method of manufacturing a trench power semiconductor structure is provided. The method comprising the steps of: providing a base, forming a dielectric pattern layer on the base to define an active region and a terminal region, wherein a portion of the base in the active region and the terminal region is covered by the dielectric pattern layer; selectively forming a first epitaxial layer on the base without being covered by the dielectric pattern layer; removing the dielectric pattern layer in the active region to form a gate trench on the base, and forming a gate dielectric layer on the first epitaxial layer and on the inner surface of the gate trench; forming the gate structure in the gate trench; utilizing the dielectric pattern layer to forming a body on or in the first epitaxial layer; and forming a source on the upper portion of the body. | 12-12-2013 |
20130330896 | MANUFACTURING METHOD OF SILICON CARBIDE SEMICONDUCTOR DEVICE - A manufacturing method of a silicon carbide semiconductor device includes: forming a drift layer on a silicon carbide substrate; forming a base layer on or in a surface portion of the drift layer; forming a source region in a surface portion of the base layer; forming a trench to penetrate the base layer and to reach the drift layer; forming a gate electrode on a gate insulation film in the trench; forming a source electrode electrically connected to the source region and the base layer; and forming a drain electrode on a back surface of the substrate. The forming of the trench includes: flattening a substrate surface; and etching to form the trench after flattening. | 12-12-2013 |
20130337623 | QUANTUM-WELL-BASED SEMICONDUCTOR DEVICES - Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer. | 12-19-2013 |
20130344667 | Trench FET with Source Recess Etch - A high voltage vertical field effect transistor device ( | 12-26-2013 |
20140004671 | SUPER-SELF-ALIGNED TRENCH-DMOS STRUCTURE AND METHOD | 01-02-2014 |
20140017864 | METHOD OF FORMING TRENCH GATE MOSFET - A method of forming a trench gate MOSFET is provided. An epitaxial layer is formed on a substrate. A trench is formed in the epitaxial layer. A first insulating layer is conformally formed on surfaces of the epitaxial layer and the trench. A first conductive layer is formed at the bottom of the trench. A portion of the first insulating layer is removed to form a second insulating layer exposing an upper portion of the first conductive layer. An oxidation process is performed to oxidize the first conductive layer to a third insulating layer, wherein a fourth insulating layer is simultaneously formed on the surface of the epitaxial layer and on the sidewall of the trench. A second conductive layer is formed in the trench. Two body layers are formed in the epitaxial layer beside the trench. Two doped regions are formed in the body layers respectively beside the trench. | 01-16-2014 |
20140017865 | Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings. | 01-16-2014 |
20140038375 | SEMICONDUCTOR DEVICE HAVING VERTICAL MOS TRANSISTOR AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device including a vertical MOS transistor, includes forming a trench for shallow trench isolation in a semiconductor substrate, and burying an element isolation insulating film in the trench, forming an insulating film to be a mask for forming a semiconductor pillar, in a region subjected to shallow trench isolation, etching the semiconductor substrate in the region subjected to the shallow trench isolation with the insulating film as a mask, and forming a semiconductor pillar for the vertical MOS transistor, implanting an impurity onto the semiconductor substrate, and forming a lower diffusion layer in the portion shallower than the depth of the shallow trench isolation, and forming a gate insulating film on the semiconductor substrate and the side surface of the semiconductor pillar for the vertical MOS transistor. | 02-06-2014 |
20140051220 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH REDUCED MILLER CAPACITANCE - A method for fabricating a semiconductor transistor device. An epitaxial layer is grown on a semiconductor substrate. A gate trench is formed in the epitaxial layer. A spacer is formed on a sidewall of the gate trench. A recess is formed at the bottom of the gate trench. A thermal oxidation process is performed to form an oxide layer in the recess. The oxide layer completely fills the recess. The spacer is then removed. A gate oxide layer is formed on the exposed sidewall of the gate trench. A gate is then formed into the gate trench. | 02-20-2014 |
20140073101 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A trench having a side wall and a bottom portion is formed in a silicon carbide substrate. A trench insulating film is formed to cover the bottom portion and the side wall. A silicon film is formed to fill the trench with the trench insulating film being interposed therebetween. The silicon film is etched so as to leave a portion of the silicon film that is disposed on the bottom portion with the trench insulating film being interposed therebetween. The trench insulating film is removed from the side wall. By oxidizing the silicon film, a bottom insulating film is formed. A side wall insulating film is formed on the side wall. | 03-13-2014 |
20140073102 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method of forming a device in each of vertical trench gate MOSFET region and control lateral planar gate MOSFET region of a semiconductor substrate is disclosed. A trench is formed in the substrate in the vertical trench gate MOSFET region, a first gate oxide film is formed along the internal wall of the trench, and the trench is filled with a polysilicon film. A LOCOS oxide film is formed in a region isolating the devices. A second gate oxide film is formed on the substrate in the lateral planar gate MOSFET region. Advantages are that number of steps is suppressed, the gate threshold voltage of an output stage MOSFET is higher than the gate threshold voltage of a control MOSFET, the thickness of the LOCOS oxide film does not decrease, and no foreign object residue remains inside the trench. | 03-13-2014 |
20140087534 | METHODS OF MANUFACTURING VERTICAL STRUCTURE NONVOLATILE MEMORY DEVICES - A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends. | 03-27-2014 |
20140094013 | FABRICATING METHOD OF TRENCH-GATE METAL OXIDE SEMICONDUCTOR DEVICE - A fabricating method of a trench-gate metal oxide semiconductor device is provided. The fabricating method includes the steps of defining a first zone and a second zone in a substrate, forming at least one first trench in the second zone, forming a dielectric layer on the first zone and the second zone, filling the dielectric layer in the first trench, performing an etching process to form at least one second trench in the first zone by using the dielectric layer as an etching mask, forming a first gate dielectric layer on a sidewall of the second trench, and filling a conducting material layer into the second trench, thereby forming a first gate electrode. | 04-03-2014 |
20140099762 | MANUFACTURING METHOD OF TRENCH TYPE POWER TRANSISTOR DEVICE WITH SUPER JUNCTION - The present invention provides a manufacturing method of a trench type power transistor device with a super junction. First, a substrate of a first conductivity type is provided, and then an epitaxial layer of a second conductive type is formed on the substrate. Next, a through hole is formed in the epitaxial layer, and the through hole penetrates through the epitaxial layer. Two doped drain regions of the first conductivity type are then formed in the epitaxial layer respectively at two sides of the through hole, and the doped drain regions extend from a top surface of the epitaxial layer to be in contact with the substrate. | 04-10-2014 |
20140106527 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A method of producing a semiconductor device, includes: forming a semiconductor layer on a substrate; forming an a recess in the semiconductor layer by dry etching with a gas containing fluorine components, the recess having an opening portion on the surface of the semiconductor layer; forming a fluorine-containing region by heating the semiconductor layer and thus diffusing, into the semiconductor layer, the fluorine components attached to side surfaces and a bottom surface of the recess; forming an insulating film on an inner surface of the recess and on the semiconductor layer; and forming an electrode on the insulating film in a region in which the recess is formed. | 04-17-2014 |
20140120670 | TRENCHED POWER MOSFET WITH ENHANCED BREAKDOWN VOLTAGE AND FABRICATION METHOD THEREOF - A trenched power semiconductor device with enhanced breakdown voltage is provided. The trenched power semiconductor device has a first trench penetrating the body region located between two neighboring gate trenches. A polysilicon structure with a conductivity type identical to that of the body region is located in a lower portion of the first trench and spaced from the body region with a predetermined distance. A dielectric structure is located on the polysilicon structure and at least extended to the body region. Source regions are located in an upper portion of the body region. A heavily doped region located in the body region is extended to the bottom of the body region. A conductive structure is electrically connected to the heavily doped region and the source region. | 05-01-2014 |
20140120671 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to the present invention includes a semiconductor layer provided with a gate trench, a first conductivity type source region formed to be exposed on a surface side of the semiconductor layer, a second conductivity type channel region formed on a side of the source region closer to a back surface of the semiconductor layer to be in contact with the source region, a first conductivity type drain region formed on a side of the channel region closer to the back surface of the semiconductor layer to be in contact with the channel region, a gate insulating film formed on an inner surface of the gate trench, and a gate electrode embedded inside the gate insulating film in the gate trench, while the channel region includes a channel portion formed along the side surface of the gate trench so that a channel is formed in operation and a projection projecting from an end portion of the channel portion closer to the back surface of the semiconductor layer toward the back surface. | 05-01-2014 |
20140120672 | TRENCH MOSFET HAVING A TOP SIDE DRAIN - This invention discloses a trench MOSFET comprising a top side drain region in a wide trench in a termination area besides a BV sustaining area, wherein said top side drain comprises a top drain metal connected to an epitaxial layer and a substrate through a plurality of trenched drain contacts, wherein the wide trench is formed simultaneously when a plurality of gate trenches are formed in an active area, and the trenched drain contacts are formed simultaneously when a trenched source-body contact is formed in the active area. | 05-01-2014 |
20140134812 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a trench in a substrate, forming a pre-gate insulating film along side surfaces and a bottom surface of the trench, and oxidizing the pre-gate insulating film through a densification process. | 05-15-2014 |
20140134813 | FABRICATION OF SHIELDED GATE TRENCH MOSFET WITH INCREASED SOURCE-METAL CONTACT - Fabricating a semiconductor device includes: forming a gate trench on a semiconductor substrate; forming a spacer inside the gate trench; forming one or more gate electrodes within the gate trench; implanting a body region; implanting a source region; forming a contact trench; disposing dielectric material within the gate trench; removing at least a portion of the dielectric material such that at least a portion of the source region extends above the dielectric material; and depositing a metal layer over at least a portion of a gate trench opening, at least a portion of the source region, and at least a portion of the contact trench. | 05-15-2014 |
20140141585 | TRENCH GATE TYPE SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A method of producing a trench gate type MOSFET is provided in which each intersection trench is formed as a two-stage trench structure. A gate trench is backfilled with a mask material and the mask material is then patterned to form a mask used for forming each intersection trench. The intersection trench intersecting the gate trench is provided so as to be deeper than the gate trench. A Schottky electrode is provided in the bottom of each intersection trench | 05-22-2014 |
20140147979 | Vertical Gate LDMOS Device - A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material. | 05-29-2014 |
20140154851 | NON-VOLATILE GRAPHENE NANOMECHANICAL SWITCH - Methods for making non-volatile switches include depositing gate material in a recess of a substrate; depositing drain metal in a recess of the gate material; planarizing the gate material, drain metal, and substrate; forming sidewalls by depositing material on the substrate around the gate material; forming a flexible conductive element between the sidewalls to establish a gap between the flexible conductive element and the gate material, such that the gap separating the flexible conductive element and the gate material is sized to create a negative threshold voltage at the gate material for opening a circuit; and forming a source terminal in electrical contact with the flexible conductive element. | 06-05-2014 |
20140162420 | METHOD OF FABRICATING SEMICONDUCTOR DEVICES HAVING VERTICAL CELLS - According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower preliminary stack structures by alternately stacking a plurality of interlayer insulating and sacrificial layers on a cell, first pad area, sacrificial area and second pad area of a substrate; removing an entire portion of the upper preliminary stack structure on the second pad area; forming a first mask defining openings over parts of the first and second pad areas; etching an etch depth corresponding to ones of the plurality of interlayer insulating and sacrificial layers through a remaining part of the preliminary stack structure exposed by the first mask; and repetitively performing a first staircase forming process that includes shrinking sides of the first mask and etching the etch depth through remaining parts of the plurality of interlayer insulating and sacrificial layers exposed by the shrunken first mask. | 06-12-2014 |
20140162421 | SEMICONDUCTOR DEVICES WITH FIELD PLATES - A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer. | 06-12-2014 |
20140162422 | Apparatus and Method for Power MOS Transistor - A MOS transistor comprises a substrate, a first region formed over the substrate, a second region grown from the first region, a third region of formed in the second region, a first drain/source region formed in the third region, a first gate electrode formed in a first trench, a second drain/source region formed in the second region and on an opposite side of the first trench from the first drain/source region and a second trench coupled between the second drain/source region and the second region, wherein the second trench is of a same depth as the first trench. | 06-12-2014 |
20140170823 | METHOD FOR FABRICATING TRENCH TYPE TRANSISTOR - A method for fabricating a trench type transistor. An epitaxial layer is provided on a semiconductor substrate. A hard mask with an opening is formed on the epitaxial layer. A gate trench is etched into the substrate through the opening. A gate oxide layer and a trench gate are formed within the gate trench. After forming a cap layer atop the trench gate, the hard mask is removed. An ion well and a source doping region are formed in the epitaxial layer. A spacer is then formed on a sidewall of the trench gate and the cap layer. Using the cap layer and the spacer as an etching hard mask, the epitaxial layer is etched in a self-aligned manner, thereby forming a contact hole. | 06-19-2014 |
20140170824 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: sequentially forming an n− type epitaxial layer, a p type epitaxial layer, and a first n+ region on a first surface of an n+ type silicon carbide substrate; forming a trench by penetrating the first n+ region and the p type epitaxial layer, and etching part of the n− type epitaxial layer; forming a buffer layer in the trench and on the first n+ region; etching the buffer layer to form a buffer layer pattern on both sidewalls defined by the trench; forming a first silicon film on the first n+ region, the buffer layer pattern, and a surface of the n− type epitaxial layer exposed by the trench; oxidizing the first silicon film to form a first silicon oxide film; removing the buffer layer pattern by an ashing process to form a first silicon oxide film pattern; forming a second silicon film on the first silicon oxide film pattern and in the trench; oxidizing the second silicon film to form a second silicon oxide film; and etching the second silicon oxide film to form a gate insulating film within the trench, wherein the first silicon oxide film pattern is positioned on the first n+ region and at the bottom of the trench on the surface of the n− type epitaxial layer. | 06-19-2014 |
20140179074 | METHOD OF MAKING MOSFET INTEGRATED WITH SCHOTTKY DIODE WITH SIMPLIFIED ONE-TIME TOP-CONTACT TRENCH ETCHING - Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)06-26-2014 | |
20140179075 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode. | 06-26-2014 |
20140187004 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Disclosed is a method for fabricating a semiconductor device including: sequentially forming a first insulating film and a first barrier layer on a first surface of a substrate; etching the first barrier layer to form a first barrier layer pattern; etching the first insulating film to form a first insulating film pattern; removing the first barrier layer pattern and forming a first type epitaxial layer on an exposed first portion of the substrate; forming a second insulating film and a second barrier layer on the first type epitaxial layer and the first insulating film pattern; etching the second barrier layer to form a second barrier layer pattern; etching the second insulating film to form a second insulating film pattern, and etching the first insulating film pattern; and forming a second type epitaxial layer on an exposed second portion of the first surface of the n substrate. | 07-03-2014 |
20140187005 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, ELECTRONIC DEVICE AND VEHICLE - A method for manufacturing a semiconductor device includes forming a recess over a surface of an n-type semiconductor substrate, forming a gate insulation film over an inner wall and a bottom face of the recess, embedding a gate electrode into the recess, forming a p-type base layer in the surface layer of the substrate so as to be shallower than the recess; and forming an n-type source layer in the p-type base layer so as to be shallower than the p-type base layer. The impurity profile of the p-type base layer in a thickness direction includes a second peak being located closer to a bottom face side of the substrate than the first peak and being higher than the first peak, and a third peak located between the first peak and the second peak by implanting impurity ions three times or more at ion implantation energies different from each other. | 07-03-2014 |
20140199814 | METHOD OF MANUFACTURE FOR A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes providing a semiconductor layer of a first conductivity type and forming a semiconductor layer of a second conductivity type thereon. The method also includes forming an insulator layer on the semiconductor layer of the second conductivity type, etching a trench into at least the semiconductor layer of the second conductivity type, and forming a thermal oxide layer in the trench and on the semiconductor layer of the second conductivity type. The method further includes implanting ions into the thermal oxide layer, forming a second insulator layer, removing the second insulator layer from a portion of the trench, and forming an oxide layer in the trench and on the epitaxial layer. Moreover, the method includes forming a material in the trench, forming a second gate oxide layer over the material, and patterning the second gate oxide layer. | 07-17-2014 |
20140199815 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer. | 07-17-2014 |
20140199816 | METHOD OF FABRICATING A SUPER JUNCTION TRANSISTOR - A method of fabricating a super junction transistor is provided. A drain substrate is provided. An epitaxial layer is formed on the drain substrate. A plurality of trenches is formed in the epitaxial layer. A buffer layer is formed and is in direct contact with the interior surface of the trenches. A dopant source layer is filled into the trenches. An etching process is performed to form a plurality of recessed structures above the respective trenches. A gate oxide layer is formed on the surface of each recessed trench and the dopants inside the dopant source layer are diffused into the epitaxial layer through the buffer layer to thereby form at least a body diffusion layer of the first conductivity type. A gate conductor is filled into the recessed structures to form a plurality of gate structure units. A doped source region having the first conductivity type is formed. | 07-17-2014 |
20140206164 | Chemical Mechanical Polish in the Growth of Semiconductor Regions - A method includes performing a first planarization step to remove portions of a semiconductor region over isolation regions. The first planarization step has a first selectivity, with the first selectivity being a ratio of a first removal rate of the semiconductor region to a second removal rate of the isolation regions. After the isolation regions are exposed, a second planarization step is performed on the isolation regions and a portion of the semiconductor region between the isolation regions. The second planarization step has a second selectivity lower than the first selectivity, with the second selectivity being a ratio of a third removal rate of the portion of semiconductor region to a fourth removal rate of the isolation regions. | 07-24-2014 |
20140206165 | Self-Aligned Trench MOSFET and Method of Manufacture - A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region. The MOSFET also includes a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions, a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, a source/body contact disposed above the source/body contact spacers, and a plurality of source/body contact, plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions. | 07-24-2014 |
20140213026 | TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH EMBEDDED SCHOTTKY RECTIFIER USING REDUCED MASKS PROCESS - A trench MOSFET with embedded schottky rectifier having at least one anti-punch through implant region using reduced masks process is disclosed for avalanche capability enhancement and cost reduction. The source regions have a higher doping concentration and a greater junction depth along sidewalls of the trenched source-body contacts than along adjacent channel regions near the gate trenches. | 07-31-2014 |
20140256103 | METHOD FOR FABRICATING ELECTRONIC DEVICES HAVING SEMICONDUCTOR MEMORY UNIT - Devices and methods based on disclosed technology include, among others, an electronic device including silicide layers capable of effectively reducing contact resistance in the electronic device including buried gates and a method for fabricating the electronic device. Specifically, an electronic device in one implementation includes a plurality of buried gates formed in a substrate and silicide layers formed over the substrate between the buried gates and protruding upwardly from the buried gates. | 09-11-2014 |
20140256104 | MANUFACTURING METHOD OF VERTICAL CHANNEL TRANSISTOR ARRAY - A manufacturing method of a vertical channel transistor array is provided. The method includes following steps. A plurality of embedded word lines are formed at bottoms of trenches, and each of the embedded word lines is located at a first side wall of one of the trenches and connected to first sides of the semiconductor pillars in the same row. Each of the embedded word lines is not connected to second sides of the semiconductor pillars in the same row, and the first sides are opposite to the second sides. Only one embedded word line is correspondingly connected to the semiconductor pillars arranged in one row. An isolation structure is formed between a second side wall of each of the trenches and each of the embedded word lines. The first side wall is opposite to the second side wall. | 09-11-2014 |
20140273373 | METHOD OF MAKING A VERTICAL NAND DEVICE USING SEQUENTIAL ETCHING OF MULTILAYER STACKS - A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening. | 09-18-2014 |
20140287563 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An aspect of the present embodiment, there is provided a method of manufacturing a semiconductor device, including adsorbing a photolytic group on a hydrophilic surface of a substrate on which a concave portion is provided, irradiating a first area of the substrate with light to transform the photolytic group to a hydrophobic group to modify a surface of the first area, selectively coating a resist on a second area which is a portion of the substrate other than the first area modified by hydrophobic group. | 09-25-2014 |
20140295632 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING GROOVED SOURCE CONTACT REGION - In a method of fabricating a semiconductor device, a channel layer is formed on a substrate, and trench patterns are formed in the channel layer. Impurity bodies are formed in the channel layer between the trench patterns, and grooves are formed between the trench patterns in the impurity bodies formed in the channel layer. Source isolation regions are formed in the impurity bodies at bottom portions of the grooves, and source regions are formed in the impurity bodies at sidewall portions of the grooves. | 10-02-2014 |
20140295633 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes: a semiconductor substrate including a drain, a drift making contact with a front face of the drain, a body contacting with a front face of the drift, a source provided in part of a front face of the body, and a floating surrounded by the drift; and a gate including an insulator formed on an inner wall of a trench and a electrode disposed inside the insulator and which has a bottom portion contacting with the floating, the manufacturing method includes: forming the trench in a semiconductor wafer so as to have a bottom portion in which an end portion in a short direction perpendicular to a longitudinal direction thereof is deeper than a central portion; injecting an impurity ions into the bottom portion of the trench; and forming the central portion of the trench in the short direction to be deepened. | 10-02-2014 |
20140315364 | Methods Of Forming A Vertical Transistor - Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed. | 10-23-2014 |
20140322877 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A trench gate type MISFET and a diode are formed in a semiconductor substrate. First and second trenches are formed in the semiconductor substrate. A gate electrode is formed in the first trench through a gate insulating film. A dummy gate electrode is formed in the second trench through a dummy gate insulating film. A cathode n | 10-30-2014 |
20140335672 | PROCESS FOR MANUFACTURING SEMICONDUCTOR TRANSISTOR DEVICE - A process for manufacturing a semiconductor transistor device is provided. The process comprises steps of providing a substrate; forming a patterned hard mask on the substrate; forming a spacer on a sidewall of the patterned hard mask; forming a trench by removing a portion of the substrate not being covered by the patterned hard mask and the spacer; and filling a conductive material into the trench. | 11-13-2014 |
20140342517 | METHOD FOR FABRICATING TRENCH TYPE POWER SEMICONDUCTOR DEVICE - A method of forming a trench type semiconductor power device is disclosed. An epitaxial layer is formed on a substrate. A gate trench is formed in the epitaxial layer. A gate oxide layer and a trench gate are formed in the gate trench. A source region is then formed in the epitaxial layer. A dielectric layer is then deposited in a blanket manner. A contact hole is then formed in the dielectric layer and the epitaxial layer. A base ion implantation is then carried out to form at least one doping region in the epitaxial layer through the contact hole. A contact hole implantation process is then performed to form a contact doping region at the bottom of the contact hole. | 11-20-2014 |
20140342518 | POWER MOSFET STRUCTURE AND METHOD - A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth. | 11-20-2014 |
20140342519 | THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF MANUFACTURING THE SAME - A three-dimensional (3-D) non-volatile memory device includes channel structures each including channel layers stacked over a substrate and extending in a first direction, wherein the channel layers include well regions, respectively, vertical gates located and spaced from each other between the channel structures, and a well pick-up line contacting on the well regions of the channel layers and extending in a second direction crossing the channel structures. | 11-20-2014 |
20140349456 | TRENCH POWER MOSFET STRUCTURE FABRICATION METHOD - A trench power MOSFET structure and fabrication method thereof is provided. The fabrication method comprises following process. First, form an isolating trench. Then, form at least two doped regions around the isolating trench. The doped regions are adjacent and the doping concentrations of two doped regions are different. Form an isolating structure in the isolating trench. Wherein, the junction profiles of the two doped regions are made by on implantation method for moderate the electric field distribution and decreasing the conduction loss. | 11-27-2014 |
20140357033 | METHOD FOR FABRICATING A METAL HIGH-K GATE STACK FOR A BURIED RECESSED ACCESS DEVICE - A method for fabricated a buried recessed access device comprising etching a plurality of gate trenches in a substrate, implanting and activating a source/drain region in the substrate, depositing a dummy gate in each of the plurality of gate trenches, filling the plurality of gate trenches with an oxide layer, removing each dummy gate and depositing a high-K dielectric in the plurality of gate trenches, depositing a metal gate on the high-K dielectric in each of the plurality of gate trenches, depositing a second oxide layer on the metal gate and forming a contact on the source/drain. | 12-04-2014 |
20140363939 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A semiconductor device includes an active region, a gate conductor and a source electrode. The active region includes a drain region, a channel region stacked on the drain region, and a source region stacked on the channel region. The active region is formed of a silicon semiconductor layer. The gate conductor is embedded within a trench, which is formed from the source region to the drain region penetrating through the channel region. The source electrode is formed to come in contact with the source region and includes an adhesion layer. The source electrode is formed of a metal layer having a film thickness of 150 â„« or smaller. The interface between the source electrode and the source region is silicidized. | 12-11-2014 |
20150011065 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a drain region of a first conductivity type formed on a semiconductor substrate; an element forming region that is provided on the drain region and that has a concave portion reaching the drain region; a gate electrode disposed in the concave portion; a superjunction structure portion that is disposed in the element forming region and that is formed by alternately arranging a drift layer of the first conductivity type penetrated by the concave portion and a resurf layer of a second conductivity type being in contact with the drift layer on the semiconductor substrate; and a base region of the second conductivity type that is disposed on the superjunction structure portion so as to be in contact with the drift layer in the element forming region, that is penetrated by the concave portion, and that faces the gate electrode with the gate insulating film therebetween. | 01-08-2015 |
20150011066 | SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND METHOD OF MANUFACTURING THE SAME - A gate electrode is formed in a trench reaching a drain region so as to leave a concave portion on the top of the trench. A first insulating film is formed, which fills the concave portion and of which the thickness increases as the distance from an end of the trench increases on the substrate surface on both sides of the trench. First and second source regions are formed in a self-alignment manner by introduction of impurities through the first insulating film. | 01-08-2015 |
20150017773 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In the semiconductor device, a line-type buried gate is formed by burying a non-operating gate (isolation gate) with a polysilicon material to reduce a work function and a Gate Induced Drain Leakage (GIDL) caused by the non-operating gate, resulting in improvement of refresh characteristics of the semiconductor device. Operating gates including a metal conductive material may be formed in a separate step. | 01-15-2015 |
20150024563 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - The upper end of a gate electrode is situated below the surface of a semiconductor substrate. An insulating layer is formed over the gate electrode and over the semiconductor substrate situated at the periphery thereof. The insulating layer has a first insulating film and a low oxygen permeable insulating film. The first insulating film is, for example, an NSG film and the low oxygen permeable insulating film is, for example, an SiN film. Further, a second insulating film is formed over the low oxygen permeable insulating film. The second insulating film is, for example, a BPSG film. The TDDB resistance of a vertical MOS transistor is improved by processing with an oxidative atmosphere after forming the insulating layer. Further since the insulating layer has the low oxygen permeable insulating film, fluctuation of the threshold voltage of the vertical MOS transistor can be suppressed. | 01-22-2015 |
20150037952 | RECESSED CHANNEL INSULATED-GATE FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED GATE AND INCREASED CHANNEL LENGTH - A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor. | 02-05-2015 |
20150037953 | METHOD FOR FABRICATING TRENCH TYPE TRANSISTOR - An epitaxial layer is formed on the semiconductor substrate. A nitride doping region is then formed at a surface of the epitaxial layer. A hard mask layer is formed on the epitaxial layer. The hard mask layer comprises at least an opening. Through the opening, agate trench is etched into the epitaxial layer. A gate is formed within the gate trench. The hard mask layer is removed such that the gate protrudes from the surface of the epitaxial layer. An ion well is formed within the epitaxial layer. A source doping region is formed within the ion well. An upper portion of the gate that protrudes from the surface of the epitaxial layer is selectively oxidized to thereby form an oxide capping layer. Using the oxide capping layer as an etching hard mask, the epitaxial layer is self-aligned etched to thereby form a contact hole. | 02-05-2015 |
20150037954 | SUPER-JUNCTION TRENCH MOSFETS WITH SHORT TERMINATIONS - A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough. | 02-05-2015 |
20150044837 | Trench Power MOSFET - A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. | 02-12-2015 |
20150050791 | METHOD FOR MANUFACTURING RECTIFIER WITH VERTICAL MOS STRUCTURE - A method for manufacturing a rectifier with a vertical MOS structure is provided. A first multi-trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second multi-trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second multi-trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second multi-trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first multi-trench structure. | 02-19-2015 |
20150056772 | SEMICONDUCTOR DEVICE COMPRISING BURIED GATE AND METHOD FOR FABRICATING THE SAME - The present invention provides a semiconductor device including a buried gate and a method for fabricating the same, in which the width of a contact plug may not exceed a predetermined width. The method including forming a plurality of trenches over a substrate using the mask pattern, forming a gate insulating film in each of the plurality of trenches, forming a plurality of gate electrodes filling portions of the plurality of trenches, removing an exposed gate insulating film formed over each of the plurality of gate electrodes in each of the plurality of the trenches, forming a plurality of sealing films filling remaining portions of the plurality of trenches, and forming a plurality of contact plugs over the substrate between the trenches. | 02-26-2015 |
20150064868 | Apparatus and Method for Power MOS Transistor - A method comprises forming a first trench and a second trench, depositing a dielectric material in a lower portion of the first trench, depositing a gate electrode material in the second trench and an upper portion of the first trench, forming a first N+ region and a second N+ region through an ion implantation process, wherein the first N+ region and the second N+ region are on opposite sides of the first trench and forming an accumulation layer along a sidewall of the second trench. | 03-05-2015 |
20150072493 | METHOD OF FORMING TRENCH GATE MOSFET - A method of forming a trench gate MOSFET is provided. An epitaxial layer is formed on a substrate. A trench is formed in the epitaxial layer. A first insulating layer is conformally formed on surfaces of the epitaxial layer and the trench. A first conductive layer is formed at the bottom of the trench. A portion of the first insulating layer is removed to form a second insulating layer exposing an upper portion of the first conductive layer. An oxidation process is performed to oxidize the first conductive layer to a third insulating layer, wherein a fourth insulating layer is simultaneously formed on the surface of the epitaxial layer and on the sidewall of the trench. A second conductive layer is formed in the trench. Two body layers are formed in the epitaxial layer beside the trench. Two doped regions are formed in the body layers respectively beside the trench. | 03-12-2015 |
20150079747 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device including sequentially forming an n-type epitaxial layer, a p type epitaxial layer, and an n+ region on a first surface of an n+ type silicon carbide substrate; forming a buffer layer on the n+ region; forming a photosensitive film pattern on a part of the buffer layer; etching the buffer layer using the photosensitive film pattern as a mask to form a buffer layer pattern; sequentially forming a first metal layer and a second metal layer which include a first portion and a second portion; removing one or more components to expose a part of the n+ region; and etching the exposed part of the n+ region using the first portion of the first metal layer and the first portion of the second metal layer as masks to form a trench. | 03-19-2015 |
20150079748 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower part buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers. In accordance with this technology, a lower part of the pipe connection gate electrode is buried in the substrate. Accordingly, electric resistance may be reduced because the pipe connection gate electrode may have an increased volume without a substantial increase of the height. | 03-19-2015 |
20150079749 | TERMINATION ARRANGEMENT FOR VERTICAL MOSFET - Representative implementations of devices and techniques provide a termination arrangement for a transistor structure. The periphery of a transistor structure may include a recessed area having features arranged to improve performance of the transistor at or near breakdown. | 03-19-2015 |
20150087124 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth semiconductor region, a control electrode, and an insulating film. The first region contains silicon carbide. The second region is provided on the first region and contains silicon carbide. The third region is provided on the second region and contains silicon carbide. The fourth region is provided on the third region and contains silicon carbide. The control electrode is provided in a trench. The trench is formed in the fourth, the third, and the second semiconductor region. The insulating film is provided between a side surface of the trench and the control electrode. The insulating film contains a high-dielectric constant region. The high-dielectric constant region contacts with at least the third semiconductor region. The high-dielectric constant region has a higher dielectric constant than a dielectric constant of silicon oxide. | 03-26-2015 |
20150104917 | Power MOSFET and Methods for Forming the Same - A device includes a trench extending into a semiconductor region and having a first conductivity type, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer and having an edge portion overlapping the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion contacting the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. A MOS-containing device is at a surface of the semiconductor region. | 04-16-2015 |
20150111353 | SEMICONDUCTOR DEVICE AND THE METHOD OF MANUFACTURING THE SAME - A semiconductor device according to the invention includes p-type well region | 04-23-2015 |
20150111354 | SUPERJUNCTION DEVICES HAVING NARROW SURFACE LAYOUT OF TERMINAL STRUCTURES, BURIED CONTACT REGIONS AND TRENCH GATES, AND METHODS OF MANUFACTURING THE DEVICES - Superjunction semiconductor devices having narrow surface layout of terminal structures and methods of manufacturing the devices are provided. The narrow surface layout of terminal structures is achieved, in part, by connecting a source electrode to a body contact region within a semiconductor substrate at a body contact interface comprising at least a first side of the body contact region other than a portion of a first main surface of the semiconductor substrate. | 04-23-2015 |
20150118810 | BURIED FIELD RING FIELD EFFECT TRANSISTOR (BUF-FET) INTEGRATED WITH CELLS IMPLANTED WITH HOLE SUPPLY PATH - This invention discloses a semiconductor power device formed in a semiconductor substrate comprises a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region. The semiconductor power device further comprises a body region, a source region and a gate disposed near the top surface of the semiconductor substrate and a drain disposed at a bottom surface of the semiconductor substrate. Source trenches are opened into the highly doped region filled with a conductive trench filling material in electrical contact with the source region near the top surface. A buried field ring regions is disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. In an alternate embodiment, there are doped regions doped with a dopant of a same conductivity type of the buried field ring regions surrounding the sidewalls of the source trenches to function as a charge supply path. | 04-30-2015 |
20150118811 | METHOD OF MAKING A VERTICAL NAND DEVICE USING SEQUENTIAL ETCHING OF MULTILAYER STACKS - A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening. | 04-30-2015 |
20150294899 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A device isolation layer of the memory device includes a first insulation layer in a lower portion of a device isolation trench, a second insulation layer in an upper portion of the device isolation trench and a separation layer between the first insulation layer and the second insulation layer. First and second conductive fillers are in the first and second insulation layers and are separated by the separation layer. | 10-15-2015 |
20150294981 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: vertical channel layers; a pipe channel layer configured to connect lower ends of the vertical channel layers; and a pipe gate surrounding the pipe channel layer and including a first region, which is in contact with the pipe channel layer and includes a first-type impurity, and remaining second regions including a second-type impurity different from the first type impurity. | 10-15-2015 |
20150311317 | Method of Manufacturing a Semiconductor Device - A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is formed by forming a source region, forming a drain region, forming a channel region, forming a drift zone, and forming a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. Forming the semiconductor device further includes forming a conductive layer, a portion of the conductive layer being disposed beneath the gate electrode and insulated from the gate electrode. | 10-29-2015 |
20150318361 | Method for Forming a Transistor Device having a Field Electrode - A method for forming a transistor device includes forming a field electrode arrangement by forming a trench in a first surface of a semiconductor body, forming a protection layer on sidewalls of the trench in an upper trench section, forming a dielectric layer on a bottom of the trench and on sidewall sections uncovered by the protection layer, and forming a field electrode at least on the dielectric layer. The method further includes forming a gate electrode and a gate electrode dielectric horizontally spaced apart from the field electrode arrangement with respect to the first surface, forming a body region adjacent the gate electrode and dielectrically insulated from the gate electrode by the gate dielectric, and forming a source region in the body region. | 11-05-2015 |
20150318379 | SUPER-JUNCTION STRUCTURES HAVING IMPLANTED REGIONS SURROUNDING AN N EPITAXIAL LAYER IN DEEP TRENCH - A super junction structure having implanted column regions surrounding an N epitaxial layer in a deep trench is disclosed to overcome charge imbalance problem and to further reduce Rds. The inventive super junction can be used for MOSFET and Schottky rectifier. | 11-05-2015 |
20150325638 | VERTICAL TRENCH MOSFET DEVICE IN INTEGRATED POWER TECHNOLOGIES - A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region bounded on at least two opposite sides by the deep trench structures. The deep trench structures include dielectric liners. The deep trench structures are spaced so as to form RESURF regions for the drift region. Vertical gates are formed in vertically oriented gate trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions. A body implant mask for implanting dopants for the transistor body is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners. | 11-12-2015 |
20150333070 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The present invention provides a semiconductor device manufacturing method that reduces contact resistances in a memory cell region. This semiconductor device manufacturing method includes: a step wherein a gate insulating film and gate electrodes are formed in a second region; a step wherein a first liner film is formed so as to cover wires and the first gate electrodes in a first region and the second region; a step wherein first gate sidewalls are formed by etching back the first liner film in the second region; a step wherein a second liner film is formed so as to cover the first liner film in the first region while covering the gate electrodes in the second region; a step wherein second gate sidewalls adjoining the first gate sidewalls are formed by etching back the second liner film in the second region; a step wherein an impurity diffusion region is formed by injecting impurities into a semiconductor substrate in the second region; a step wherein the impurity diffusion region is activated by means of a thermal treatment; and a step wherein the second liner film is removed from the first region after the thermal treatment. | 11-19-2015 |
20150333151 | METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDING PROTRUSION TYPE ISOLATION LAYER - A semiconductor device may include a semiconductor layer having a convex portion and a concave portion surrounding the convex portion. The semiconductor device may further include a protrusion type isolation layer filling the concave portion and extending upward so that an uppermost surface of the isolation layer is a at level higher that an uppermost surface of the convex portion. | 11-19-2015 |
20150333153 | SEMICONDUCTOR DEVICE HAVING VERTICAL MOSFET WITH SUPER JUNCTION STRUCTURE, AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes: preparing a semiconductor substrate, in which a first semiconductor layer is formed on a substrate; forming a first concave portion in the first semiconductor layer; forming trenches on the first semiconductor layer in the first concave portion; epitaxially growing a second semiconductor layer for embedding in each trench and the first concave portion; forming a SJ structure having PN columns including the second semiconductor layer in each trench and the first semiconductor layer between the trenches; and forming the vertical MOSFET by: forming a channel layer and a source region contacting the channel layer on the SJ structure; forming a gate electrode over the channel layer through a gate insulating film; forming a source electrode connected to the source region; and forming a drain electrode on a rear of the substrate. | 11-19-2015 |
20150349091 | SEMICONDUCTOR POWER DEVICES MANUFACTURED WITH SELF-ALIGNED PROCESSES AND MORE RELIABLE ELECTRICAL CONTACTS - This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate. | 12-03-2015 |
20150357437 | MOS-Transistor with Separated Electrodes Arranged in a Trench - A MOS transistor is produced by forming a first trench in a semiconductor body, forming a first isolation layer on inner surfaces of the first trench, and filling the first trench with conductive material to form a first electrode within the first trench. A portion of the first electrode is removed along one side wall of the first trench to form a cavity located within the first trench. A second isolation layer is formed on inner surfaces of the cavity, and the cavity is at least partially filled with conductive material to form a second electrode within the cavity. A structured third isolation layer is formed on a top surface of the semiconductor body, and a metallization layer is formed on the structured third isolation layer. The first or the second electrode is electrically and thermally connected to the metallization layer via openings in the structured third isolation layer. | 12-10-2015 |
20150380318 | Integrated Circuit Having a Vertical Power MOS Transistor - A method includes forming a buried layer in a substrate, growing an epitaxial layer over the substrate, etching the epitaxial layer and the buried layer to form a first trench and a second trench, wherein the first trench and the second trench are of a same depth and a width of the second trench is greater than a width of the first trench, forming a dielectric layer in a bottom portion of the first trench, forming a first gate electrode in an upper portion of the first trench and filling the second trench with a gate electrode material, forming gate electrodes for a plurality of lateral transistors formed in the substrate, forming a body region, forming a first drain/source region over the body region and forming a second drain/source region over the epitaxial layer. | 12-31-2015 |
20160013283 | METHOD FOR MANUFACTURING GATE STACK STRUCTURE IN INSTA-METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT-TRANSISTOR | 01-14-2016 |
20160027900 | Trench Power MOSFET - A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. | 01-28-2016 |
20160049407 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a device isolation pattern on a substrate to define active patterns, a gate electrode crossing the active patterns, first and second impurity regions in each of the active patterns and on both sides of the gate electrode, a bit line crossing the gate electrode, a first contact electrically connecting the first impurity region to the bit line, and a second contact electrically connected to the second impurity region. The second contact includes a vertically-extended portion covering an upper side surface of the second impurity region. | 02-18-2016 |
20160071923 | TRENCH GATE TRENCH FIELD PLATE VERTICAL MOSFET - A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions. | 03-10-2016 |
20160071955 | SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS AND METHOD OF MANUFACTURING THE SAME - A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a semiconductor substrate having an active island, a gate buried in a predetermined portion of the active island, a source and a drain formed at both sides of the gate, and a current blocking layer formed in the active island corresponding to a lower portion of the drain. When current flows in from the drain, the current blocking layer is configured to discharge the current into the inside of the semiconductor substrate through a lower portion of the source. | 03-10-2016 |
20160079352 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To realize a semiconductor device having a power MOSFET satisfying both a low conduction resistance and a high junction breakdown voltage by a simple and easy manufacturing method. Over an n-type substrate, a p-type epitaxial layer of a low concentration is formed, and, in an active part, a plurality of active regions is defined by a plurality of trenches that is formed in the epitaxial layer and extends in a first direction with first intervals in a second direction orthogonal to the first direction. In the epitaxial layer between the adjacent trenches, an n-type diffusion region that functions as a drain offset layer is formed, and, in the epitaxial layer between a side wall of the trench and the n-type diffusion region, a p-type diffusion region connected with a channel region (the p-type diffusion region) is formed, to constitute a super junction structure. Further, by forming an n-type diffusion region in the epitaxial layer, having a prescribed width from a side wall of a trench lying in the end part of the active part toward an outer periphery part, to achieve the improvement of a drain breakdown voltage. | 03-17-2016 |
20160079356 | ELECTRONIC DEVICE OF VERTICAL MOS TYPE WITH TERMINATION TRENCHES HAVING VARIABLE DEPTH - An electronic device is integrated on a chip of semiconductor material having a main surface and a substrate region with a first type of conductivity. The electronic device has a vertical MOS transistor, formed in an active area having a body region with a second conductivity type. A set of one or more cells each one having a source region of the first conductivity, a gate region of electrically conductive material in a gate trench extending from the main surface in the body region and in the substrate region, and an insulating gate layer, and a termination structure with a plurality of termination rings surrounding at least part of the active area on the main surface, each termination ring having a floating element of electrically insulating material in the termination trench extending from the main surface in the chip and at least one bottom region of said semiconductor material of the second conductivity type extending from at least one deepest portion of a surface of the termination trench in the chip; the termination trenches have a depth from the main surface decreasing moving away from the active area. | 03-17-2016 |
20160079390 | SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS AND METHOD OF MANUFACTURING THE SAME - A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a semiconductor substrate having an active island, a gate buried in a predetermined portion of the active island, a source and a drain formed at both sides of the gate, and a current blocking layer formed in the active island corresponding to a lower portion of the drain. When current flows in from the drain, the current blocking layer is configured to discharge the current into the inside of the semiconductor substrate through a lower portion of the source. | 03-17-2016 |
20160086804 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - First, a first resist mask for forming an n | 03-24-2016 |
20160087033 | SEMICONDUCTOR DEVICE HAVING LOCALIZED CHARGE BALANCE STRUCTURE AND METHOD - In one embodiment, a semiconductor device has a superjunction structure formed adjoining a low-doped n-type region. A low-doped p-type region is formed adjoining the superjunction structure above the low-doped n-type region and is configured to improve Eas characteristics. A body region is formed adjacent the low-doped p-type region and a control electrode structure is formed adjacent the body region for controlling a channel region within the body region. | 03-24-2016 |
20160093529 | Method of Manufacturing a Semiconductor Device Having a Cell Field Portion and a Contact Area - A semiconductor device is manufactured at least partially in a semiconductor substrate. The substrate has first and second opposing main surfaces. The method includes forming a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion, and forming the cell field portion by at least forming a transistor. The method further includes insulating a part of the semiconductor substrate from other substrate portions to form a connection substrate portion, forming an electrode adjacent to the second main surface so as to be in contact with the connection substrate portion, forming an insulating layer over the first main surface, forming a metal layer over the insulating layer, forming a trench in the first main surface, and filling the trench with a conductive material, and electrically coupling the connection substrate portion to the metal layer via the trench. | 03-31-2016 |
20160093717 | DUAL WORK FUNCTION BURIED GATE TYPE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A transistor includes a substrate having an active region defined by an isolation layer; a first trench defined in the active region and a second trench defined in the isolation layer; a fin region formed under the first trench; and a buried gate electrode covering sidewalls of the fin region and filling the first and second trenches. The buried gate electrode includes a first work function layer formed on the sidewalls of the fin region; a second work function layer formed on sidewalls of the first trench and the second trench; a third work function layer positioned over the fin region and contacting the second work function layer; and a low resistance layer contacting the third work function layer and partially filling the first and second trenches. | 03-31-2016 |
20160111435 | THREE-DIMENSIONAL MEMORY STRUCTURE HAVING SELF-ALIGNED DRAIN REGIONS AND METHODS OF MAKING THEREOF - A memory stack structure can be formed through a stack of an alternating plurality of first material layers and second material layers and through an overlying temporary material layer having a different composition than the first and second material layers. The memory stack structure can include a memory film and a semiconductor channel layer. The overlying temporary material layer is removed selective to the stack to form a lateral recess. Portions of the memory film are removed around the lateral recess, and dopants are laterally introduced into an upper portion of the semiconductor channel to form a self-aligned drain region. | 04-21-2016 |
20160126348 | INSULATED GATE SEMICONDUCTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE AND METHOD - A semiconductor device includes a semiconductor region with a charge balance region on a junction blocking region, which has a lower doping concentration. A trench structure having an insulated shield electrode and an insulated gate electrode is provided in the semiconductor region. The semiconductor device further includes one or more features configured to improve operating performance. The features include terminating the trench structure in the junction blocking region, providing a localized doped region adjoining a lower surface of a body region and spaced apart from the trench structure, disposing a notch proximate to the lower surface of the body region, and/or configuring the insulated shield electrode to have a wide portion adjoining a narrow portion. | 05-05-2016 |
20160148844 | MOS Transistor Structure and Method - A method comprises depositing a first dielectric layer on a top surface of a substrate, implanting ions of a first conductivity type into the substrate, forming a first trench and a second trench in the substrate, forming a first gate in the first trench and a second gate in the second trench and forming a first drain/source region, a second drain/source region and a third drain/source region with the first conductivity type, wherein the first drain/source region and the second drain/source region are formed on opposing sides of the first gate and the third drain/source region and the second drain/source region are formed on opposing sides of the second gate. | 05-26-2016 |
20160155821 | Methods for Producing a Vertical Semiconductor and a Trench Gate Field Effect Semiconductor Device | 06-02-2016 |
20160163818 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - In a method for producing an SiC semiconductor device, a p type layer is formed in a trench by epitaxially growing, and is then left only on a bottom portion and ends of the trench by hydrogen etching, thereby to form a p type SiC layer. Thus, the p type SiC layer can be formed without depending on diagonal ion implantation. Since it is not necessary to separately perform the diagonal ion implantation, it is less likely that a production process will be complicated due to transferring into an ion implantation apparatus, and thus manufacturing costs reduce. Since there is no damage due to a defect caused by the ion implantation, it is possible to reduce a drain leakage and to reliably restrict the p type SiC layer from remaining on the side surface of the trench. | 06-09-2016 |
20160172461 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | 06-16-2016 |
20160172468 | METHOD OF FORMING A SILICON-CARBIDE DEVICE WITH A SHIELDED GATE | 06-16-2016 |
20160181391 | DIODE STRUCTURES WITH CONTROLLED INJECTION EFFICIENCY FOR FAST SWITCHING | 06-23-2016 |
20160190283 | FABRICATION OF MOSFET DEVICE WITH REDUCED BREAKDOWN VOLTAGE - Fabricating a semiconductor device comprises: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer; forming a source embedded in the body; forming a contact trench that extends through the source and at least part of the body; disposing an implant at least along a contact trench wall; and disposing an epitaxial enhancement portion below the contact trench and in contact with the implant. | 06-30-2016 |
20160197084 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 07-07-2016 |
20160254354 | METHOD FOR MANUFACTURING ISOLATION STRUCTURE INTEGRATED WITH SEMICONDUCTOR DEVICE | 09-01-2016 |
20160380079 | METHOD OF FORMING A TRANSISTOR AND STRUCTURE THEREFOR - In one embodiment, a semiconductor device is formed to include a gate structure extending into a semiconductor material that is underlying a first region of semiconductor material. The gate structure includes a conductor and also a gate insulator that has a first portion positioned between the gate conductor and a first portion of the semiconductor material that underlies the gate conductor. The first portion of the semiconductor material is configured to form a channel region of the transistor which underlies the gate conductor. The gate structure may also include a shield conductor overlying the gate conductor and having a shield insulator between the shield conductor and the gate conductor. The shield insulator may also have a second portion positioned between the shield conductor and a second portion of the gate insulator and a third portion overlying the shield conductor. | 12-29-2016 |
20170236910 | Methods of Manufacturing a Power MOSFET | 08-17-2017 |
20180025918 | METHOD FOR MANUFACTURING TRANSISTOR AND DISPLAY DEVICE | 01-25-2018 |
20220140113 | METHOD FOR ADJUSTING GROOVE DEPTH AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The method for adjusting a groove depth includes: preparing masks having different thicknesses on respective top surfaces of a plurality of substrates made of silicon carbide; forming a first opening having a predetermined width and a second opening having a width wider than the first opening in each of the masks; simultaneously forming a first groove and a second groove in each of the substrates by selectively etching via the first opening and the second opening; measuring a depth ratio of the first groove to the second groove in each of the substrates; and acquiring a thickness of a mask such that the depth ratio is an intended value, from a relationship between each thickness of the masks and each depth ratio in the substrate. | 05-05-2022 |