Class / Patent application number | Description | Number of patent applications / Date published |
438266000 | Having additional, nonmemory control electrode or channel portion (e.g., for accessing field effect transistor structure, etc.) | 20 |
20090035907 | METHOD OF FORMING STACKED GATE STRUCTURE FOR SEMICONDUCTOR MEMORY - A method of manufacturing a nonvolatile semiconductor memory comprising: forming a gate insulating film formed on a surface of a semiconductor substrate; forming a source region and a drain region in the semiconductor substrate; forming a floating gate electrode on the gate insulating film; forming a inter-gate insulating film on the floating gate electrode; forming a control gate electrode on the inter-gate insulating film; forming a source contact region wherein the source contact region is electrically contact to said source region, and top part of said source contact region is lower than bottom part of said control gate electrode. | 02-05-2009 |
20090061582 | MANUFACTURING METHOD OF NON-VOLATILE MEMORY - A manufacturing method of a non-volatile memory includes first providing a substrate for defining multiple pairs of active regions; forming a control gate in one of each pair of the active regions of the substrate; sequentially forming a gate oxide layer, a conductor layer, and a patterned mask layer on the substrate, wherein the patterned mask layer exposes a portion of the conductor layer; forming a first dielectric layer on the exposed portion of the conductor layer; removing the patterned mask layer; removing the conductor layer without covering the first dielectric layer, and using the remained conductor layer as the floating gate; forming a second dielectric layer on sidewalls of the floating gate; forming an erase gate above the floating gate and correspondingly above the control gate, and forming a source region and a drain region in the other one of each pair of the active regions | 03-05-2009 |
20090148990 | Semiconductor devices and methods of forming the same - A method of forming a semiconductor device includes forming line patterns on a substrate, the line patterns defining narrow and wide gap regions, forming spacer patterns in the narrow and wide gap regions on sidewalls of the line patterns, spacer patterns in the wide gap regions exposing an upper surface of the substrate, and spacer patterns in the narrow gap regions contacting each other to fill the narrow gap regions, forming an insulating interlayer to cover the spacer patterns and the line patterns, forming at least one opening through the insulating interlayer, the opening including at least one contact hole selectively exposing the upper surface of the substrate in the wide gap region, the contact hole being formed by using the spacer patterns in the narrow gap region as an etching mask, and forming a conductive pattern to fill the opening. | 06-11-2009 |
20090286370 | Multi-State Non-Volatile Integrated Circuit Memory Systems that Employ Dielectric Storage Elements - Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate. | 11-19-2009 |
20100003795 | Method for Fabricating Flash Memory Device Having Vertical Floating Gate - A method for fabricating a flash memory device includes forming a control gate having a hollow donut shape over an insulation layer formed over a substrate. The method also includes forming an inter-poly dielectric of a spacer shape on an inner wall of the control gate, filling a conductive layer for a floating gate between the spacer shaped inter-poly dielectrics, and forming an interlayer insulation layer over a resulting product formed with the conductive layer for a floating gate. The method further includes removing a center portion of the conductive layer for a floating gate to form an opening, forming a tunnel insulation layer on an inner face of the opening, and filling with a semiconductor layer the opening formed with the tunnel insulation layer to form an active region. | 01-07-2010 |
20100041194 | SEMICONDUCTOR DEVICE WITH SPLIT GATE MEMORY CELL AND FABRICATION METHOD THEREOF - A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell. | 02-18-2010 |
20100159655 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICES - A semiconductor memory device has a floating gate formed on a semiconductor substrate at certain intervals along a plane with a first insulator interposed therebetween, and a control gate formed on the layer of floating gates with a second insulator interposed therebetween. The device includes a semiconductor layer formed by selectively epitaxially growing the semiconductor substrate between the floating gates on the semiconductor substrate with a third insulator interposed therebetween. | 06-24-2010 |
20110070707 | METHOD OF MANUFACTURING NOR FLASH MEMORY - In a method of manufacturing a NOR flash memory, two times of tilt ion implantation process are conducted to form a tilt-implanted source region, so as to improve the distribution of the source region in a semiconductor substrate and reduce the probability of short channel effect (SCE) between the drain regions and the source region in the NOR flash memory. | 03-24-2011 |
20110189829 | METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES HAVING STACKED STRUCTURES - A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure. | 08-04-2011 |
20110263087 | Semiconductor Device and Manufacturing Method Thereof - A semiconductor device which is formed in a self-aligned manner without causing a problem of misalignment in forming a control gate electrode and in which a leak between the control gate electrode and a floating gate electrode is not generated, and a manufacturing method of the semiconductor device are provided. A semiconductor device includes a semiconductor film, a first gate insulating film over the semiconductor film, a floating gate electrode over the first gate insulating film, a second gate insulating film which covers the floating gate electrode, and a control gate electrode over the second gate insulating film. The control gate electrode is formed so as to cover the floating gate electrode with the second gate insulating film interposed therebetween, the control gate electrode is provided with a sidewall, and the sidewall is formed on a stepped portion of the control gate electrode, generated due to the floating gate electrode. | 10-27-2011 |
20120231594 | FLASH CELL WITH FLOATING GATE TRANSISTORS FORMED USING SPACER TECHNOLOGY - Methods for forming split gate flash cell structures provide for symmetrical cells that are immune to misalignment of the photoresist pattern when forming the control gates. Spacers are utilized to form the floating gates in the floating gate transistors used in the flash cells. The spacers may be oxide spacers used to mask a polysilicon layer that will form the floating gates or the spacers may be polysilicon spacers that will themselves form the floating gates. The inter-gate oxide of the floating gate transistors may be formed using HTO or may be deposited. Hard mask spacers are used in conjunction with the control gate photoresist patterning operation to control the size and configuration of the control gate and the channel length. | 09-13-2012 |
20120264264 | METHOD OF FABRICATING NON-VOLATILE MEMORY DEVICE - A method of fabricating a non-volatile memory device is provided. A substrate including a first region and a second region is provided. Then, an uneven surface is formed on the substrate in the second region. Thereafter, a doped layer is formed in the substrate in the second region, and the doped layer is served as a control gate. Afterward, a dielectric layer is formed on the substrate in the first region and on the uneven surface of the substrate in the second region. Next, a floating gate is formed on the dielectric layer, and the floating gate is extended from the first region to the second region. Source and drain regions are formed in the substrate at opposite sides of the floating gate in the first region. | 10-18-2012 |
20120329223 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SAME - In a semiconductor storage device a select gate electrode is arranged into a ring shape so as to surround the second impurity regions, and is electrically connected to a word line. A first control gate electrode is arranged into a ring shape on the outer peripheral side of the select gate electrode, and a second control gate electrode is arranged into a ring shape on the inner peripheral side of the select gate electrode. A pair of first and second bit lines corresponding to every row are placed on the memory cells of the device, a first bit line is electrically connected to one of first impurity regions that are adjacent along the row direction, and a second bit line is electrically connected to the other of the first impurity regions that are adjacent along the row direction. | 12-27-2012 |
20130171786 | NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION - A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over an NVM work function setting metal, the NVM work function setting metal is on a high-k dielectric, and a metal logic gate of a logic transistor is similarly formed over work function setting and high-k dielectric materials. The logic transistor is formed while portions of the metal select gate of the NVM cell are formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate. | 07-04-2013 |
20150044833 | DENSE ARRAYS AND CHARGE STORAGE DEVICES - There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing. | 02-12-2015 |
20150056768 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is disclosed. The method includes the steps of: sequentially forming agate dielectric layer and a first gate layer on a semiconductor substrate, wherein the gate dielectric layer is between the first gate layer and the semiconductor substrate; forming at least an opening in the first gate layer; forming a first dielectric layer conformally on the semiconductor substrate wherein the first dielectric layer covers the first gate layer; and forming a second gate layer filling the opening and overlapping the first gate layer. | 02-26-2015 |
20150340375 | SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE - A method for manufacturing a semiconductor device may include the following steps: preparing a stacked structure; processing the stacked structure to form a first gate structure and a preliminary structure; forming a dielectric material layer that covers at least the first gate structure; forming a dielectric layer using the dielectric material layer, such that a portion of the dielectric layer is positioned between the first gate structure and the preliminary structure; performing an annealing process on at least one of the dielectric material layer and the dielectric layer; processing the preliminary structure to form a second gate structure; and after the annealing process has been performed, forming a first metal silicide member on the second gate structure and/or forming a second metal silicide member on an active region associated with the second gate structure. | 11-26-2015 |
20190148529 | Method Of Forming Pairs Of Three-Gate Non-volatile Flash Memory Cells Using Two Polysilicon Deposition Steps | 05-16-2019 |
438267000 | Including forming gate electrode as conductive sidewall spacer to another electrode | 2 |
20080293201 | NONVOLATILE SEMICONDUCTOR MEMORY AND A FABRICATION METHOD THEREOF - A nonvolatile semiconductor memory includes: a device region and a device isolating region, which have a pattern with a striped form that extends in a first direction, and are alternately and sequentially disposed at a first pitch in a second direction that is perpendicular to the first direction; and a contact made of a first conductive material, which is connected to the device region and disposed at the first pitch in the second direction. On a cross section of the second direction, the bottom width of the contact is longer than the top width of the contact, and the bottom width is longer than the width of the device region. | 11-27-2008 |
20150072489 | NON-VOLATILE MEMORY (NVM) CELL AND HIGH-K AND METAL GATE TRANSISTOR INTEGRATION - A method of making a semiconductor device includes depositing a layer of polysilicon in a non-volatile memory (NVM) region and a logic region of a substrate. The layer of polysilicon is patterned into a gate in the NVM region while the layer of polysilicon remains in the logic region. A memory cell is formed including the gate in the NVM region while the layer of polysilicon remains in the logic region. The layer of polysilicon in the logic region is removed and the substrate is implanted to form a well region in the logic region after the memory cell is formed. A layer of gate material is deposited in the logic region. The layer of gate material is patterned into a logic gate in the logic region. | 03-12-2015 |