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Having additional gate electrode surrounded by dielectric (i.e., floating gate)

Subclass of:

438 - Semiconductor device manufacturing: process

438142000 - MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS

438197000 - Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.)

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
438261000 Multiple interelectrode dielectrics or nonsilicon compound gate insulator 53
438264000 Tunneling insulator 41
438258000 Including additional field effect transistor (e.g., sense or access transistor, etc.) 24
438259000 Including forming gate electrode in trench or recess in substrate 19
438266000 Having additional, nonmemory control electrode or channel portion (e.g., for accessing field effect transistor structure, etc.) 15
438262000 Including elongated source or drain region disposed under thick oxide regions (e.g., buried or diffused bitline, etc.) 6
438265000 Oxidizing sidewall of gate electrode 5
20080206945PROCESS FOR FORMING DIFFERENTIAL SPACES IN ELECTRONICS DEVICE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE - A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the whole electronic device; forming a first mask to cover the first transistor; removing the first conformal insulating layer not covered by the first mask; removing the first mask; forming a second conformal insulating layer of a second thickness on the whole device; and removing the insulating layers until the protective layer is exposed to form first spacers of a first width on the side walls of the gate electrodes of the first transistor and second spacers of a second width on the side walls of the gate electrodes of the second transistor.08-28-2008
20090124055Transistor structure and method for making same - A gate structure in a transistor and method for fabricating the structure are disclosed. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.05-14-2009
20090142894METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE - A method for fabricating a semiconductor structure. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. A semiconductor layer and a gate stack on the semiconductor layer are provided. The semiconductor layer includes (i) a channel region directly beneath the gate stack, and (ii) first and second semiconductor regions essentially not covered by the gate stack, and wherein the channel region is disposed between the first and second semiconductor regions. The first and second semiconductor regions are removed. Regions directly beneath the removed first and second semiconductor regions are removed so as to form first and second source/drain regions, respectively, such that top surfaces of the first and second source/drain regions are below a top surface of the channel region.06-04-2009
20080220579STRESS ENHANCED MOS TRANSISTOR AND METHODS FOR ITS FABRICATION - According to a method for fabricating a stress enhanced MOS device having a channel region at a surface of a semiconductor substrate, first and second trenches are etched into the semiconductor substrate, the first trench having a first side surface, and the second trench having a second side surface. The first and second side surfaces are formed astride the channel region. The first and second side surfaces are then oxidized in a controlled oxidizing environment to thereby grow an oxide region. The oxide region is then removed, thereby repositioning the first and second side surfaces closer to the channel region. With the first and second side surfaces repositioned, the first and second trenches are filled with SiGe.09-11-2008
20080199996METHOD FOR FORMING A SPLIT GATE MEMORY DEVICE - A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.08-21-2008
Entries
DocumentTitleDate
20080261366NON-VOLATILE MEMORY DEVICE HAVING IMPROVED ERASE EFFICIENCY AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device having an improved erase efficiency and a method of manufacturing the same are provided. The method includes: forming a stack structure of a tunnel dielectric layer, a charge trapping layer, a charge blocking layer and a gate on a semiconductor substrate; and performing a post treatment of the gate using an oxygen or CF10-23-2008
20080261365NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A technology realizing decreases of capacitance between the adjoining floating gates and of the threshold voltage shift caused by interference between the adjoining memory cells in a nonvolatile semiconductor memory device with the advances of miniaturization in the period following the 90 nm generation. By having the floating gate 10-23-2008
20100009503METHOD OF FORMING DIELECTRIC LAYER ABOVE FLOATING GATE FOR REDUCING LEAKAGE CURRENT - A method of fabricating a memory system is disclosed that includes a set of non-volatile storage elements. The method includes forming a floating gate having a top and at least two sides. A dielectric cap is formed at the top of the floating gate. An inter-gate dielectric layer is formed around the at least two sides of the floating gate and over the top of the dielectric cap. A control gate is formed over the top of the floating gate, the inter-gate dielectric layer separates the control gate from the floating gate. In one aspect, forming the dielectric cap includes implanting oxygen in the top of the floating gate and heating the floating gate to form the dielectric cap from the implanted oxygen and silicon from which the floating gate was formed.01-14-2010
20130084684MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention improves the production yield of a semiconductor device having nonvolatile memory cells of a split gate structure. The level difference of a lower layer resist film with which an end of a memory mat is covered is gentled, the uniformity of the thickness of a resist intermediate layer formed over the lower layer resist film is improved, and local thickness reduction or disappearance is prevented by, after forming a silicon oxide film and a silicon nitride film over each of selective gate electrodes formed in a memory cell region of a semiconductor substrate, removing the silicon oxide film and the silicon nitride film over the selective gate electrode located on the outermost side (a dummy cell region) of the memory mat in the gate length direction.04-04-2013
20130065368NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING EMBEDDED NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH SIDEWALL GATE - A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.03-14-2013
20090233405METHODS OF FORMING NAND-TYPE NONVOLATILE MEMORY DEVICES - Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line pattern continuously penetrating the second insulating layer, the semiconductor pattern and the first insulating layer, the source line pattern being connected with the first and second common sources, wherein a grain boundary of the semiconductor layer is positioned at a center between the one pair of seed contact structures adjacent to each other, and is positioned over the first common drain or the first common source.09-17-2009
20090047763SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR WITH COMPOSITE GATE STRUCTURE AND TRANSISTOR WITH SINGLE GATE STRUCTURE, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having a single gate structure containing a lamination of a third polycrystalline silicon film and a fourth polycrystalline silicon film, wherein the first polycrystalline silicon film and the third polycrystalline silicon film have substantially the same thickness; the first polycrystalline silicon film and the third polycrystalline silicon film have different impurity concentrations controlled independently of each other; the second polycrystalline silicon film and the fourth polycrystalline silicon film have substantially the same thickness, and the second polycrystalline silicon film, the fourth polycrystalline silicon film, and the third polycrystalline silicon film have substantially the same impurity concentration. Also, a method for manufacturing the above-described semiconductor device is described.02-19-2009
20090047762APPARATUS AND METHOD FOR A MEMORY ARRAY WITH SHALLOW TRENCH ISOLATION REGIONS BETWEEN BIT LINES FOR INCREASED PROCESS MARGINS - The present invention provides an apparatus and method for a non-volatile memory comprising at least one array of memory cells with shallow trench isolation (STI) regions between bit lines for increased process margins. Specifically, in one embodiment, each of the memory cells in the array of memory cells includes a source, a control gate, and a drain, and is capable of storing at least one bit. The array of memory cells further includes word lines that are coupled to control gates of memory cells. The word lines are arranged in rows in the array. In addition, the array comprises bit lines coupled to source and drains of memory cells. The bit lines are arranged in columns in the array. Also, the array comprises at least one row of bit line contacts for providing electrical conductivity to the bit lines. Further, the array comprises shallow trench isolation (STI) regions separating each of the bit lines along the row of bit line contacts.02-19-2009
20090011560MULTIPLE SELECT GATE ARCHITECTURE WITH SELECT GATES OF DIFFERENT LENGTHS - The invention provides methods and apparatus. A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in series with one non-volatile memory cell of the string of two or more non-volatile memory cells, and a second select gate coupled in series with the first select gate. A length of the second select gate is greater than a length of the first select gate.01-08-2009
20090011559NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING A NON-VOLATILE SEMICONDUCTOR MEMORY - An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diffusion of impurities from the first semiconductor layer to regions above the second semiconductor layer; and a third semiconductor layer provided on the second semiconductor layer, including a first source region having a second conductivity type, a first drain regions having the second conductivity type and a first channel region having the second conductivity type for each of the memory cell transistors.01-08-2009
20090011558METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A method of manufacturing a NAND nonvolatile semiconductor memory which involves forming a bit line contact between adjacent select transistors of the NAND nonvolatile semiconductor memory, the method has patterning memory cells and said select transistors of said NAND nonvolatile semiconductor memory; forming a first insulating film between adjacent two of said memory cells, between said memory cells and said select transistors, and between adjacent two of said select transistors; selectively etching the first insulating film between said select transistors to form a side wall spacer on each of said select transistors; forming a second insulating film on said memory cells, said first insulating film between said memory cells, said select transistors and said side wall spacers; forming a resist pattern on said second insulating film; and simultaneously forming an opening in an insulating film and a control gate on a floating gate of each of said select transistors using said resist pattern and an opening between said adjacent select transistors using said resist pattern.01-08-2009
20090011557METHOD FOR MANUFACTURING A FLASH MEMORY - A method for manufacturing a flash memory includes providing a substrate with a sacrificial oxide layer, a sacrificial poly-Si layer, a hard mask layer and a trench exposing part of the substrate and filled with an oxide layer, later depositing a oxide layer conformally on the sacrificial oxide layer and the oxide layer, and afterwards removing the oxide layer on the sacrificial oxide layer and on the top of the oxide layer and the sacrificial oxide layer to form a spacer as a STI oxide spacer.01-08-2009
20110287596SYSTEM AND METHOD FOR PROVIDING LOW VOLTAGE HIGH DENSITY MULTI-BIT STORAGE FLASH MEMORY - A system and method is disclosed for providing a low voltage high density multi-bit storage flash memory. A dual bit memory cell of the invention comprises a substrate having a common source, a first drain and first channel, and a second drain and a second channel. A common control gate is located above the source. A first floating gate and a second floating gate are located on opposite sides of the control gate. Each floating gate is formed with a sharp tip adjacent to the control gate and an upper curved surface that follows a contour of the surface of the control gate. The sharp tips of the floating gates efficiently discharge electrons into the control gate when the memory cell is erased. The curved surfaces increase capacitor coupling between the control gate and the floating gates.11-24-2011
20080280411METHOD FOR MANUFACTURING PHASE CHANGE MEMORY DEVICE USING A PATTERNING PROCESS - A phase change memory device is made by processes including forming a first interlayer dielectric on a semiconductor substrate that has junction regions. Then etching the first interlayer dielectric and thereby defining contact holes that expose the junction regions. A conductive layer is formed on the first interlayer dielectric to fill the contact holes. Forming a hard mask layer on the conductive layer and etching the hard mask layer and the conductive layer to form contact plugs in the contact holes. Finally, forming a conductive layer pattern that is located on the contact plug and portions of the first interlayer dielectric adjacent to the contact plug and having a hard mask thereon.11-13-2008
20090124054METHOD OF MAKING INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING - A programmable non-volatile device is made with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.05-14-2009
20080280409Memory Arrays, Semiconductor Constructions And Electronic Systems; And Methods Of Forming Memory Arrays, Semiconductor Constructions And Electronic Systems - Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.11-13-2008
20080318379METHOD FOR FABRICATING NON-VOLATILE STORAGE WITH INDIVIDUALLY CONTROLLABLE SHIELD PLATES BETWEEN STORAGE ELEMENTS - A method for fabricating non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped polysilicon between storage elements and their associated word lines, and providing contacts for the shield plates. The shield plates reduce electromagnetic coupling between floating gates of the storage elements, and can be used to optimize programming, read and erase operations. In one approach, the shield plates provide a field induced conductivity between storage elements in a NAND string during a sense operation so that source/drain implants are not needed in the substrate. In some control schemes, alternating high and low voltages are applied to the shield plates. In other control schemes, a common voltage is applied to the shield plates.12-25-2008
20110171797NAND FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.07-14-2011
20080280410SELF ALIGNED NARROW STORAGE ELEMENTS FOR ADVANCED MEMORY DEVICE - A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing the exposed portion of the second layer while leaving a portion of the second layer that is protected by the spacer, the method can make a sub-lithographic charge storage element from the remaining portion of the second layer on the semiconductor substrate.11-13-2008
20080286922METHOD OF FABRICATING SEMICONDUCTOR DEVICE - In one example embodiment, a method of fabricating a semiconductor device includes various steps. First, an isolation film is formed on a semiconductor substrate to define a field region and an active region. Then, a stack gate structure is formed. Next, a first photoresist and a second photoresist are sequentially formed on the stack gate structure. Then, a patterning process is performed to remove the second photoresist in a source line region. Next, a patterning process is performed to remove the first photoresist in the source line region, to thereby expose the isolation film. Then, the exposed isolation film is removed to expose the semiconductor substrate in the source line region. Finally, a cell source ion implantation process is performed using the patterned second photoresist as an ion injection mask to form a source line having impurity ions implanted thereto in the semiconductor substrate of the source line region.11-20-2008
20080286924SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate insulation film; a second gate insulation film provided on the floating gate electrode; a control gate electrode provided on the second gate insulation film; a source layer and a drain layer that are provided in the semiconductor substrate, the source layer and the drain layer respectively being provided either side of a channel region which is below the floating gate electrode; a source electrode that is electrically connected to the source layer; a buffer film provided on the drain layer; and a memory cell including a drain electrode electrically connected to the drain layer through the buffer film, wherein when viewing the surface of the semiconductor substrate from above, an overlapped area between the floating gate electrode and the drain layer is smaller than an overlapped area between the floating gate electrode and the source layer.11-20-2008
20080286923METHOD FOR FABRICATING FLASH MEMORY - A method for fabricating a flash memory device is disclosed that can improve the reliability of the device by counteracting against the generation of charge traps induced by interfacial damage of an oxide film during the formation of spacers. The method may comprise forming spacers comprised of an oxide film and a nitride film, nitriding an interface of the oxide film after removal of the nitride film; and forming a salicide film after formation of an insulating film on a sidewall of the nitrided oxide film.11-20-2008
20090004794USE OF DILUTE STEAM AMBIENT FOR IMPROVEMENT OF FLASH DEVICES - The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide-nitride-oxide or ONO) is enhanced in the dilute steam oxidation. Thermal budget can be radically conserved by growing thin oxide layers on either side of a nitride layer prior to etching, and enhancing the oxide layers by dilute steam oxidation through the exposed sidewall after etching. The thin oxide layers, like the initial tunnel oxide, serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.01-01-2009
20090061581METHOD FOR MANUFACTURING TRENCH ISOLATION STRUCTURE AND NON-VOLATILE MEMORY - A method for manufacturing a non-volatile memory is provided. An isolation structure is formed in a trench formed in a substrate. A portion of the isolation structure is removed to form a recess. A first dielectric layer and a first conductive layer are formed sequentially on the substrate. Bar-shaped cap layers are formed on the substrate. The first conductive layer not covered by the bar-shaped cap layers is removed to form first gate structures. A second dielectric layer is formed on the sidewalls of the first gate structures. A third dielectric layer is formed on the substrate between the first gate structures. A second conductive layer is formed on the third dielectric layer. The bar-shaped cap layers and a portion of the first conductive layer are removed to form second gate structures. A doped region is formed in the substrate at two sides of each of the second gate structures.03-05-2009
20080293197METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a semiconductor memory device includes forming a device separation film on a semiconductor substrate using a mask pattern for defining an entire source line region as an active region to separate a device separation region from an active region; forming a stack gate structure on the semiconductor substrate; forming a common source line by implanting impurity ions into the semiconductor substrate in the source line region; and performing an impurity ion implantation process on the semiconductor substrate to form a drain region.11-27-2008
20090239345Methods of Fabricating Nonvolatile Semiconductor Memory Devices - A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines on the opposing sidewalls of one of the plurality of pillars and crossing beneath the bit line, and a pair of memory layers interposed between respective ones of the pair of word lines and the one of the plurality of pillars. Methods of fabricating a nonvolatile semiconductor memory device include selectively etching a semiconductor substrate to form pluralities of stripes having opposing sidewalls and being arranged along a direction, forming memory layers and word lines along the sidewalls of the stripes selectively etching the stripes to form a plurality of pillars, and forming a bit line connecting the pillars and crossing above the word lines.09-24-2009
20100047980PROCESS FOR FORMING DIFFERENTIAL SPACES IN ELECTRONICS DEVICE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE - A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the whole electronic device; forming a first mask to cover the first transistor; removing the first conformal insulating layer not covered by the first mask; removing the first mask; forming a second conformal insulating layer of a second thickness on the whole device; and removing the insulating layers until the protective layer is exposed to form first spacers of a first width on the side walls of the gate electrodes of the first transistor and second spacers of a second width on the side walls of the gate electrodes of the second transistor.02-25-2010
20100184263METHODS OF FABRICATING FLASH MEMORY DEVICES HAVING SHARED SUB ACTIVE REGIONS - Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.07-22-2010
20110059585NONVOLATILE MEMORY DEVICE AND FABRICATION METHOD - Provided is a nonvolatile memory device and a fabrication method. The nonvolatile memory device includes an active region defined in a semiconductor substrate, a gate insulating layer formed on the active region and a plurality of gate patterns formed on the gate insulating layer, and crossing over the active region. The gate insulating layer includes a discharge region in a predetermined portion between the gate patterns, the discharge region having a lesser thickness than that of the gate insulating layer under the gate pattern, because a thickness portion of the gate insulating layer is removed to form the discharge region.03-10-2011
20090142893OXIDE EPITAXIAL ISOLATION - Non-volatile memory cell structures are described that are formed by a method including forming a first oxide layer on a horizontal strained substrate, forming at least one first recess through the first oxide layer to the strained substrate, and forming at least one vertical epitaxial structure in the recess. A crystal lattice of the vertical epitaxial structure is aligned with a crystal lattice of the strained substrate.06-04-2009
20110129973NONVOLATILE MEMORY DEVICE USING SEMICONDUCTOR NANOCRYSTALS AND METHOD OF FORMING SAME - A method of making a nanoparticle array that includes replicating a dimension of a self-assembled film into a dielectric film, to form a porous dielectric film, conformally depositing a material over the said porous dielectric film, and anisotropically and selectively etching the deposited material.06-02-2011
20110070705MANUFACTURING METHOD OF A NOR FLASH MEMORY WITH PHOSPHOROUS AND ARSENIC ION IMPLANTATIONS - A manufacturing method of a NOR flash memory with phosphorous and arsenic ion implantations mainly implants both phosphorous and arsenic ions on a drain area of a transistor memory unit, and controls specific energy and dosage for the implantation to reduce the defects of a memory device and improve the yield rate of the NOR flash memory.03-24-2011
20100261324Trap-charge non-volatile switch connector for programmable logic - A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.10-14-2010
20080248621Integrated Non-Volatile Memory And Peripheral Circuitry Fabrication - Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.10-09-2008
20100178742METHODS OF FORMING NAND FLASH MEMORY WITH FIXED CHARGE - A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.07-15-2010
20080242022ELECTRONIC DEVICE INCLUDING DISCONTINUOUS STORAGE ELEMENTS WITHIN A DIELECTRIC LAYER AND PROCESS OF FORMING THE ELECTRONIC DEVICE - An electronic device can include a nonvolatile memory cell having DSEs within a dielectric layer. In one aspect, a process of forming the electronic device can include implanting and nucleating a first charge-storage material to form DSEs. The process can also include implanting a second charge-storage material and growing the DSEs such that the DSEs include the first and second charge-storage material. In another aspect, a process of forming the electronic device can include forming a semiconductor layer over a dielectric layer, implanting a charge-storage material, and annealing the dielectric layer. After annealing, substantially none of the charge-storage material remains within a denuded zone within the dielectric layer. In a third aspect, within a dielectric layer, a first set of DSEs can be spaced apart from a second set of DSEs, wherein substantially no DSEs lie between the first set of DSEs and the second set of DSEs.10-02-2008
20080213959Non-volatile memory (NVM) retention improvement utilizing protective electrical shield - An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second polysilicon layer or other conductive material covering the floating gate. The shield may be grounded. Alternately, it may be connected to the cell's control gate electrode resulting in better coupling between the floating gate and the control gate. It is not necessary that the shield cover the floating gate completely, the necessary protective effect is achieved if the coupling to the dielectric layers surrounding the floating gate is reduced.09-04-2008
20090170262VIRTUAL GROUND MEMORY ARRAY AND METHOD THEREFOR - A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer of dielectric material. Chemical mechanical polishing (CMP) is then performed until the top of the conductive layer is exposed. This leaves dielectric spacers over the source/drain lines and conductive material between the dielectric spacers. Word lines are then formed over the conductive material and the dielectric spacers. As an alternative, instead of using a conductive layer, a sacrificial layer is used that is removed after the CMP step. After removing the sacrificial portions, the word lines are formed. In both cases, dielectric spacers reduce gate/drain capacitance and the distance from substrate to gate is held constant across the channel.07-02-2009
20120058613FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.03-08-2012
20120028424MANUFACTURE METHOD OF A SPLIT GATE NONVOLATILE MEMORY CELL - A split gate nonvolatile memory cell is provided with a first diffusion region, a second diffusion region, and a channel region formed between the first and second diffusion regions, including a first channel region having a predetermined dopant concentration. The first channel region is positioned apart from the first and second diffusion regions.02-02-2012
20120156841METHOD OF FABRICATING A SEMICONDUCTOR MEMORY DEVICE - A method of fabricating a semiconductor device according to present invention includes forming a stack layers on a semiconductor substrate having a first area and a second area; forming first gates on the semiconductor substrate of the first area by patterning the stack layers, wherein the first gates are formed a first distance apart from each other; forming a first impurity injection area in the semiconductor substrate of the first area exposed at both sides of each of the first gates; filling a space between the first gates with an insulating layer; forming second gates on the semiconductor substrate of the second area by patterning the stack layers, wherein the second gates are formed a second distance apart from each other, and wherein the second distance is larger than the first distance; and forming a second impurity injection area in the semiconductor device of the second area exposed between the second gates.06-21-2012
20090130809SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes first and second element isolation insulating films, first and second gate insulating films, first and second gate wiring and first and second mask layer. First and second upper surfaces of the first and second element isolation insulating films are higher than an upper surface of the substrate, first and second bottom surfaces of the first and second element isolation insulating films are lower than the upper surface of the substrate, a second height from the upper surface of the substrate to the second upper surface is larger than a first height from the upper surface of the substrate to the first upper surface. A height from the upper surface of the substrate to an upper surface of the first mask layer equals a height from the upper surface of the substrate to an upper surface of the second mask layer.05-21-2009
20090130808METHOD OF FABRICATING FLASH MEMORY - A method of fabricating a flash memory includes successively forming a floating gate insulating layer, a floating gate material layer, a dielectric layer, a control gate material layer, a silicide layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer, removing portions of the silicide layer, the control gate material layer, the dielectric layer, and the floating gate material layer not covered by the hard mask layer to form a stacked structure, forming a silicon cap layer covering the surface of the stacked structure, and performing a thermal process.05-21-2009
20100047979METHOD OF REDUCING COUPLING BETWEEN FLOATING GATES IN NONVOLATILE MEMORY - A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.02-25-2010
20090117698EEPROM and Method of Manufacturing the Same - An EEPROM includes a substrate, a first semiconductor layer and a second semiconductor layer formed on the substrate. The first semiconductor layer is isolated from the second semiconductor layer by a trench. A first source and a first drain are located at two opposing sides of the first semiconductor layer. A first dielectric layer is formed on the first semiconductor layer, and a first floating gate is formed on the first dielectric layer. A second source and a second drain are located at two opposing sides of the second semiconductor layer. A second dielectric layer is formed on the second semiconductor layer, and a second floating gate is formed on the second dielectric layer. The first floating gate and the second floating gate are electrically connected.05-07-2009
20080299724METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH EMBEDDED STRESSOR - A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects.12-04-2008
20120276700READ-ONLY MEMORY AND METHOD OF MANUFACTURE THEREOF - A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.11-01-2012
20130171784METHODS FOR ISOLATING PORTIONS OF A LOOP OF PITCH-MULTIPLIED MATERIAL AND RELATED STRUCTURES - Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.07-04-2013
20080248620Gated semiconductor device and method of fabricating same - A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.10-09-2008
20080242023METHOD FOR PREPARING A METAL-OXIDE-SEMICONDUCTOR TRANSISTOR - A method for preparing a Metal-Oxide-Semiconductor (MOS) transistor comprises the steps of forming a gate oxide layer on a substrate, forming a gate and a first dielectric layer on the gate oxide layer, forming a second dielectric layer on the sidewall of the gate, forming a third dielectric layer covering the first and the second dielectric layers, performing a first etching process to remove a portion of the third dielectric layer and performing a second etching process to form a spacer on the sidewall of the gate. The etching selectivity of the first etching process to the third dielectric layer and to the second dielectric layer is different from that of the second etching process such that the thickness of the second dielectric layer at the center of the substrate is smaller than the thickness of the second dielectric layer at the edge of the substrate.10-02-2008
20080220576MANUFACTURING METHOD OF ANTI-PUNCH-THROUGH SEMICONDUCTOR DEVICE - An anti-punch-through semiconductor device is provided. The anti-punch-through semiconductor device includes a substrate, at least an isolation region and a plurality of trench devices. The trench device is disposed in the substrate. The trench device includes a source/drain region. The source/drain region of the trench device is disposed at the bottom of the trench device. The isolation region is disposed in the substrate and between the source/drain regions of each trench device.09-11-2008
20130143375On Current in One-Time-Programmable Memory Cells - A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (I06-06-2013
20120252179PATTERNING A GATE STACK OF A NON-VOLATILE MEMORY (NVM) WITH FORMATION OF A METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) - A first dielectric layer is formed on a substrate in a transistor region and an NVM region, a first conductive layer is formed on the first dielectric layer, a second dielectric layer is formed on the first conductive layer, and a second conductive layer is formed over the second dielectric layer. A patterned etch is performed to remove at least a portion of the second conductive layer in the transistor region and to expose an extension portion of the first conductive layer. A first mask is formed over the transistor region having a first pattern, wherein the first pattern is of a gate stack of the MOSFET and an extension in the extension portion extending from the gate stack, and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the NVM cell. A patterned etch is then performed.10-04-2012
20110275186FABRICATING AND OPERATING A MEMORY ARRAY HAVING A MULTI-LEVEL CELL REGION AND A SINGLE-LEVEL CELL REGION - Techniques are disclosed herein for applying different process steps to single-level cell (SLC) blocks in a memory array than to multi-level cell (MLC) blocks such that the SLC blocks will have high endurance and the MLC blocks will have high reliability. In some aspects, different doping is used in the MLC blocks than the SLC blocks. In some aspects, different isolation is used in the MLC blocks than the SLC blocks. Techniques are disclosed that apply different read parameters depending on how many times a block has been programmed/erased. Therefore, blocks that have been cycled many times are read using different parameters than blocks that have been cycled fewer times.11-10-2011
20130157426METHOD FOR PRODUCING A CONDUCTIVE NANOPARTICLE MEMORY DEVICE - A method for producing a memory device with nanoparticles, comprising the steps of: 06-20-2013
20120094450MANUFACTURING METHOD OF MULTI-LEVEL CELL NOR FLASH MEMORY - A manufacturing method of a multi-level cell NOR flash memory includes the steps of forming a memory cell area and a peripheral circuit area with the same depth of a shallow trench isolation structure, and the depth ranges from 2400 Å to 2700 Å; forming a non-self-aligned gate structure; performing a self-alignment source manufacturing process; and forming a common source area and a plurality of drain areas. The manufacturing method achieves a high integration density between components and provides a better thermal budget and a better dosage control to the multi-level cell NOR flash memory to improve the production yield rate.04-19-2012

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