Class / Patent application number | Description | Number of patent applications / Date published |
438237000 | Including diode | 40 |
20080206944 | Method for fabricating trench DMOS transistors and schottky elements - A method uses simplified processes to complete the forming of the trench DMOS transistors and Schottky contacts. In the processes, only four masks, i.e. a trench pattern mask, a contact-hole pattern mask, a P+ contact pattern mask and a conductive-wire pattern mask, are applied to create desired trench DMOS transistors. In addition to the trench DMOS transistors, a Schottky contact is simultaneously formed at a junction between a conductive layer and a doped body region in the trench DMOS transistors without additional photolithography process. | 08-28-2008 |
20090035900 | Method of Forming High Density Trench FET with Integrated Schottky Diode - A method of forming a monolithically integrated trench FET and Schottky diode includes the following steps. Two trenches are formed extending through an upper silicon layer and terminating within a lower silicon layer. The upper and lower silicon layers have a first conductivity type. First and second silicon regions of a second conductivity type are formed in the upper silicon layer between the pair of trenches. A third silicon region of the first conductivity type is formed extending into the first and second silicon regions between the pair of trenches such that remaining lower portions of the first and second silicon regions form two body regions separated by a portion of the upper silicon layer. A silicon etch is performed to form a contact opening extending through the first silicon region such that outer portions of the first silicon region remain, the outer portions forming source regions. An interconnect layer is formed filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer. The interconnect layer electrically contacts the second silicon region so as to form a Schottky contact therebetween. | 02-05-2009 |
20090061579 | LAYOUT METHOD OF SEMICONDUCTOR DEVICE WITH JUNCTION DIODE FOR PREVENTING DAMAGE DUE TO PLASMA CHARGE - Provided is a layout method of junction diodes for preventing damage caused by plasma charge. The layout method includes operations of forming an active layer so as to form a plurality of active regions in a unit layout pattern; forming a gate layer so as to form a plurality of gate regions on the active regions; forming a first conductive type doping region in at least one of the plurality of active regions within a well layer where a second conductive type well region is formed so as to form a first conductive type active region; forming a second conductive type doping region in at least one of the plurality of active regions outside of the second conductive type well region so as to form a second conductive type active region; and forming a second conductive type doping region connected with the gate regions so as to form a junction diode in at least one active region between the first and second conductive type active regions. | 03-05-2009 |
20090170260 | Non-Volatile Memory Cell Circuit With Programming Through Band-To-Band Tunneling And Impact Ionization Gate Current - Electronic circuitry is described having a first transistor having a first gate dielectric located between an electrically floating gate and a semiconductor substrate. The first injection current flows through the first gate dielectric to establish a first amount of electrical charge on the gate electrode. The electronic circuitry also includes a second transistor having a second gate dielectric located between the gate electrode and the semiconductor substrate. A band-to-band tunneling current flows between valence and conduction bands of the second transistor to create a second injection current that flows through the second gate dielectric to establish the first amount of electrical charge on the gate electrode. Non-volatile memory cell circuits having the above described circuitry are also described. | 07-02-2009 |
20090275180 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A conventional power MOSFET structure is difficult to improve a breakdown voltage of an element even using a super-junction structure. A power MOSFET according to an embodiment of the invention is a semiconductor device of a super-junction structure, including: a gate electrode filled in a trench formed on a semiconductor substrate; a gate wiring metal forming a surface layer; and a gate electrode plug connecting between the gate electrode and the gate wiring metal. Thus, a polysilicon layer necessary for the conventional typical power MOSFET is unnecessary. That is, column regions of an element active portion and an outer peripheral portion can be formed under the same conditions. As a result, it is possible to improve an element breakdown voltage as compared with the conventional one. | 11-05-2009 |
20090305475 | Method of Manufacturing Trenched Mosfets with Embedded Schottky in the Same Cell - A method for manufacturing a trenched semiconductor power device includes a step of forming said semiconductor power device with a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The method further includes the steps of covering the MOSFET cell with an insulation layer and applying a contact mask for opening a source-body contact trench extending through the source and body regions into an epitaxial layer underneath for filling a contact metal plug therein. And, the method further includes a step of forming an embedded Schottky diode by forming a Schottky barrier layer near a bottom of the source-body contact trench below the contact metal plug with the Schottky barrier layer having a barrier height for reducing a leakage current through the embedded Schottky diode during a reverse bias between the drain and the source. | 12-10-2009 |
20100093140 | GATED RESONANT TUNNELING DIODE - A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region. An insulating layer is formed on the body with the insulating layer extending over the quantum well region and at least a portion of the barrier region, and a control electrode region is formed on the insulating layer. | 04-15-2010 |
20100112767 | Method of Manufacturing a Trench Transistor Having a Heavy Body Region - A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body. | 05-06-2010 |
20100233862 | INTEGRATED LOW LEAKAGE SCHOTTKY DIODE - An integrated low leakage Schottky diode has a Schottky barrier junction proximate one side of an MOS gate with one end of a drift region on an opposite side of the gate. Below the Schottky metal and the gate oxide is a RESURF structure of an N− layer over a P− layer which also forms the drift region that ends at the diode's cathode in one embodiment of the present invention. The N− and P− layers have an upward concave shape under the gate. The gate electrode and the Schottky metal are connected to the diode's anode. A P− layer lies between the RESURF structure and an NISO region which has an electrical connection to the anode. A P+ layer under the Schottky metal is in contact with the P− layer through a P well. | 09-16-2010 |
20110076815 | Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection - A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer. | 03-31-2011 |
20110223729 | INTEGRATED CIRCUIT INCLUDING POWER DIODE - A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode. | 09-15-2011 |
20120040503 | FABRICATION METHOD OF INTEGRATING POWER TRANSISTOR AND SCHOTTKY DIODE ON A MONOLITHIC SUBSTRATE - A fabrication method of integrating a power transistor and a schottky diode on a monolithic substrate is provided. Firstly, a substrate of a first conductive type is provided. Then, at least a polysilicon gate and a second polysilicon structure are formed on the substrate. At least a portion of the second polysilicon structure is located on an upper surface of the substrate. Thereafter, a body of a second conductive type and a source region of the first conductive type are formed between the polysilicon gate and the second polysilicon structure. Then, an interlayer dielectric film is formed on the polysilicon gate to define a source contact window, but the second polysilicon structure is still exposed. Afterward, a portion of the second polysilicon structure is removed to form a schottky contact window to expose the substrate. | 02-16-2012 |
20120149160 | LAYOUT METHOD OF SEMICONDUCTOR DEVICE WITH JUNCTION DIODE FOR PREVENTING DAMAGE DUE TO PLASMA CHARGE - A layout method of junction diodes for preventing damage caused by plasma charge includes forming an active layer to form a plurality of active regions in a unit layout pattern; forming a gate layer to form a plurality of gate regions on the active regions; forming a first conductive type doping region in at least one of the plurality of active regions within a well layer where a second conductive type well region is formed to form a first conductive type active region; forming a second conductive type doping region in at least one of the plurality of active regions outside of the second conductive type well region to form a second conductive type active region; and forming a second conductive type doping region connected with the gate regions to form a junction diode in at least one active region between the first and second conductive type active regions. | 06-14-2012 |
20120156840 | PHASE CHANGE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase change memory device having a strain transistor and a method of making the same are presented. The phase change memory device includes a semiconductor substrate, a junction word line, switching diodes, and a strain transistor. The semiconductor substrate includes a cell area and a core/peri area. The junction word line is formed in the cell area of the semiconductor substrate and includes a strain stress supplying layer doped with impurities. The switching diodes are electrically coupled to the junction word line. The strain transistor is formed in the core/peri area of the substrate and acts as a driving transistor. | 06-21-2012 |
20120252177 | PATTERNING A GATE STACK OF A NON-VOLATILE MEMORY (NVM) WITH FORMATION OF A GATE EDGE DIODE - A gate-edge diode is made in a diode region of a substrate and a non-volatile memory cell is made in an NVM region of the substrate. A first dielectric layer is formed on the substrate in the diode region and the NVM region. A first conductive layer is formed on the first dielectric layer. A second dielectric layer is formed on the first conductive layer. A second conductive layer is formed over the second dielectric layer. A first mask is formed over the diode region having a first pattern. The first pattern is of a plurality of fingers and a second mask over the NVM region has a second pattern. The second pattern is of a gate stack of the non-volatile memory cell. An etch is performed through the second conductive layer, the second dielectric layer, and the first conductive layer to leave the first pattern of the plurality of fingers in the diode region and the second pattern of the gate stack in the NVM region. An implant is performed using the gate stack and the plurality of fingers as a mask to provide source/drain regions adjacent to the gate stack in the NVM region and diode terminals between the fingers in the diode region to form the gate-edge diode with the diode terminals and the substrate. | 10-04-2012 |
20120329222 | PHASE CHANGE MEMORY DEVICE HAVING AN IMPROVED WORD LINE RESISTANCE, AND METHODS OF MAKING SAME - A phase change memory device having an improved word line resistance and a fabrication method of making the same are presented. The phase change memory device includes a semiconductor substrate, a word line, an interlayer insulation film, a strapping line, a plurality of current paths, a switching element, and a phase change variable resistor. The word line is formed in a cell area of the semiconductor substrate. The interlayer insulation film formed on the word line. The strapping line is formed on the interlayer insulation film such that the strapping line overlaps on top of the word line. The current paths electrically connect together the word line with the strapping line. The switching element is electrically connected to the strapping line. The phase change variable resistor is electrically connected to the switching element. | 12-27-2012 |
20130203224 | FABRICATION OF MOSFET DEVICE WITH REDUCED BREAKDOWN VOLTAGE - Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer; forming a source embedded in the body; forming a contact trench that extends through the source and at least part of the body; forming a body contact implant on a sidewall of the contact trench; forming a diode enhancement layer along bottom of the contact trench, the diode enhancement layer having opposite carrier type as the epitaxial layer; disposing an epitaxial enhancement portion below the diode enhancement layer, the epitaxial enhancement portion having the same carrier type as the epitaxial layer; and disposing a contact electrode in the contact trench; wherein: a distance between top surface of the substrate and bottom of the epitaxial enhancement layer is shorter than a distance between the top surface of the substrate and bottom of the body. | 08-08-2013 |
20130203225 | FABRICATION OF MOS DEVICE WITH SCHOTTKY BARRIER CONTROLLING LAYER - Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body; forming a source; forming an active region contact trench that extends through the source and the body into the drain; forming a Schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench; and disposing a contact electrode within the active region contact trench. | 08-08-2013 |
20130237022 | METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING - A semiconductor device ( | 09-12-2013 |
20130309823 | INTEGRATING SCHOTTKY DIODE INTO POWER MOSFET - A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa. | 11-21-2013 |
20140057402 | Methods of Forming Memory Arrays and Semiconductor Constructions - Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material. | 02-27-2014 |
20140073098 | METHOD FOR FORMING A SCHOTTKY BARRIER DIODE INTEGRATED WITH A TRENCH MOSFET - A method for forming a Schottky diode including forming first and second trenches in a semiconductor layer, forming a thin dielectric layer lining sidewalls of the first and second trenches; forming a trench conductor layer in the first and second trenches where the trench conductor layer fills a portion of each of the first and second trenches and being the only one trench conductor layer in the first and second trenches; forming a first dielectric layer in the first and second trenches to fill the remaining portions of the first and second trenches; and forming a Schottky metal layer on a top surface of the lightly doped semiconductor layer between the first trench and the second trench to form a Schottky junction. The Schottky diode is formed with the Schottky metal layer as the anode and the lightly doped semiconductor layer between the first and second trenches as the cathode. | 03-13-2014 |
20140106524 | DIODE ISOLATED DRAIN EXTENDED NMOS ESD CELL - An integrated circuit contains a voltage protection structure having a diode isolated DENMOS transistor with a guard element proximate to the diode and the DENMOS transistor. The guard element includes an active area coupled to ground. The diode anode is connected to an I/O pad. The diode cathode is connected to the DENMOS drain. The DENMOS source is grounded. A process of forming the integrated circuit is also disclosed. | 04-17-2014 |
20140141583 | MEMORY ARCHITECTURE OF 3D ARRAY WITH DIODE IN MEMORY STRING - A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. | 05-22-2014 |
20140235023 | TRENCH METAL OXIDE SEMICONDUCTOR WITH RECESSED TRENCH MATERIAL AND REMOTE CONTACTS - Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided. | 08-21-2014 |
20140235024 | Method of Making MOSFET Integrated with Schottky Diode with Simplified One-time Top-Contact Trench Etching - Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)08-21-2014 | |
20140308784 | THREE-DIMENSIONAL HIGH VOLTAGE GATE DRIVER INTEGRATED CIRCUIT - A three-dimensional (3D) gate driver integrated circuit includes a high-side integrated circuit stacked on a low-side integrated circuit where the high-side integrated circuit and the low-side integrated circuit are interconnected using through-silicon vias (TSV). As thus formed, the high-side integrated circuit and the low-side integrated circuit can be formed without termination regions and without buried layers. The 3D gate driver integrated circuit improves ease of high voltage integration and improves the ruggedness and reliability of the gate driver integrated circuit. | 10-16-2014 |
20140335670 | SEMICONDUCTOR DEVICE INCLUDING FINFET AND DIODE HAVING REDUCED DEFECTS IN DEPLETION REGION - A semiconductor device comprises a first substrate portion and a second substrate portion disposed a distance away from the first substrate portion. The first substrate portion includes a first active semiconductor layer defining at least one semiconductor fin and a first polycrystalline layer formed directly on the fin. The first polycrystalline layer is patterned to define at least one semiconductor gate. The second substrate portion includes a doped region interposed between a second active semiconductor region and an oxide layer. The oxide layer protects the second active semiconductor region and the doped region. The doped region includes a first doped area and a second doped area separated by the first doped region to define a depletion region. | 11-13-2014 |
20140342515 | ESD PROTECTION USING DIODE-ISOLATED GATE-GROUNDED NMOS WITH DIODE STRING - An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. | 11-20-2014 |
20140357030 | FABRICATION OF MOS DEVICE WITH SCHOTTKY BARRIER CONTROLLING LAYER - Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body; forming a source; forming an active region contact trench that extends through the source and the body into a drain; forming a Schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench; and disposing a contact electrode within the active region contact trench. The Schottky barrier controlling layer controls Schottky barrier height of a Schottky diode formed by the contact electrode and the drain. | 12-04-2014 |
20150087122 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a semiconductor device that can be manufactured at low cost and that can reduce a reverse leak current, and a manufacturing method thereof. A semiconductor device has: a source region and a drain region having a body region therebetween; a source trench that reaches the body region, penetrating the source region; a body contact region formed at the bottom of the source trench; a source electrode embedded in the source trench; and a gate electrode that faces the body region. The semiconductor device also has: an n-type region for a diode; a diode trench formed reaching the n-type region for a diode; a p | 03-26-2015 |
20150147855 | SEMICONDUCTOR DEVICE WITH HIGH BREAKDOWN VOLTAGE AND MANUFACTURE THEREOF - A semiconductor device includes: first and second n-type wells formed in p-type semiconductor substrate, the second n-type well being deeper than the first n-type well; first and second p-type backgate regions formed in the first and second n-type wells; first and second n-type source regions formed in the first and second p-type backgate regions; first and second n-type drain regions formed in the first and second n-type wells, at positions opposed to the first and second n-type source regions, sandwiching the first and the second p-type backgate regions; and field insulation films formed on the substrate, at positions between the first and second p-type backgate regions and the first and second n-type drain regions; whereby first transistor is formed in the first n-type well, and second transistor is formed in the second n-type well with a higher reverse voltage durability than the first transistor. | 05-28-2015 |
20150303184 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - A semiconductor device and a fabrication method for the semiconductor device are provided in which an increase of a forward loss is suppressed and a reverse recovery loss is reduced. | 10-22-2015 |
20150311192 | Apparatus for ESD Protection - A method comprises forming an active region including a first fin and a second fin over a substrate, wherein the first fin and the second fin are separated by an isolation region, depositing an epitaxial growth block layer over the active region, patterning the epitaxial growth block layer to define a first growth area and a second growth area and growing an N+ region in the first growth area and a P+ region in the second growth area. | 10-29-2015 |
20150325678 | METHOD FOR FABRICATING ENHANCEMENT MODE TRANSISTOR - A method for making an enhancement-mode transistor is described. The method includes forming a first III-V compound layer on a substrate and forming a second III-V compound layer on the first III-V compound layer. The second III-V compound layer is different from the first III-V compound layer. A gate stack is formed thereon. The forming of the gate stack further includes forming a diode having a pair of a n-type doped III-V compound layer and a p-type doped III-V compound layer. Source and drain features are formed on the second III-V compound layer and interposed by the gate stack. | 11-12-2015 |
20150357324 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH SOURCE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF - Embodiments include methods of forming a semiconductor device having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a source region of the first conductivity type, and the diode circuit is connected between the isolation structure and the source region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s). | 12-10-2015 |
20150380317 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH DRAIN AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF - Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a drain region of the second conductivity type, and the diode circuit is connected between the isolation structure and the drain region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s). | 12-31-2015 |
20160013182 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH AN ACTIVE DEVICE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-14-2016 |
20160035862 | FIELD PLATE TRENCH TRANSISTOR AND METHOD FOR PRODUCING IT - A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials. | 02-04-2016 |
20160087080 | INTEGRATED VERTICAL TRENCH MOS TRANSISTOR - A VTMOS transistor in semiconductor material of a first type of conductivity includes a body region of a second type of conductivity and a source region of the first type of conductivity. A gate region extends into the main surface through the body region and is insulated from the semiconductor material. A region of the gate region extends onto the main surface is insulated from the rest of the gate region. An anode region of the first type of conductivity is formed into said insulated region, and a cathode region of the second type of conductivity is formed into said insulated region in contact with the anode region; the anode region and the cathode region define a thermal diode electrically insulated from the chip. | 03-24-2016 |