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Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.)

Subclass of:

438 - Semiconductor device manufacturing: process

438142000 - MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
438299000 Self-aligned 368
438268000 Vertical channel 344
438199000 Complementary insulated gate field effect transistors (i.e., CMOS) 321
438257000 Having additional gate electrode surrounded by dielectric (i.e., floating gate) 219
438238000 Including passive device (e.g., resistor, capacitor, etc.) 131
438287000 Gate insulator structure constructed of diverse dielectrics (e.g., MNOS, etc.) or of nonsilicon compound 111
438285000 Utilizing compound semiconductor 100
438294000 Including isolation structure 77
438275000 Making plural insulated gate field effect transistors of differing electrical characteristics 68
438289000 Doping of semiconductive channel region beneath gate insulator (e.g., adjusting threshold voltage, etc.) 45
438286000 Asymmetric 42
438283000 Plural gate electrodes (e.g., dual gate, etc.) 41
438308000 Radiation or energy treatment modifying properties of semiconductor regions of substrate (e.g., thermal, corpuscular, electromagnetic, etc.) 24
438198000 Specified crystallographic orientation 23
438237000 Including diode 18
438279000 Making plural insulated gate field effect transistors having common active region 13
438234000 Including bipolar transistor (i.e., BiMOS) 9
438282000 Buried channel 4
20090047766METHOD FOR FABRICATING RECESS CHANNEL MOS TRANSISTOR DEVICE - A method for fabricating recess channel MOS transistors of the present invention utilizes a lithography process to form trenches in the recess channel MOS transistors after finishing a STI process. Furthermore, the method of the present invention can make the critical dimension variation to be controlled in a range required in the precision semiconductor process. Therefore, the short problem between the transistors can be avoided.02-19-2009
20110300681RAISED SOURCE/DRAIN WITH SUPER STEEP RETROGRADE CHANNEL - Systems and methods for raised source/drain with super steep retrograde channel are described. In accordance with a first embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.12-08-2011
20080318384Method of forming quantum wire gate device - The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The method continues by forming a first nitride spacer mask upon the first oxide and by forming a first oxide spacer mask upon the first nitride spacer mask. Thereafter, the method continues by forming a second nitride spacer mask upon the first oxide spacer mask and by forming a plurality of channels in the substrate that are aligned to the second nitride spacer mask. A dielectric is formed upon the channel length and the method continues by forming a gate layer over the plurality of channels. Because of the inventive method and the starting scale, each of the plurality of channels is narrower than the mean free path of semiconductive electron flow therein.12-25-2008
20090221119FABRICATION OF A SEMICONDUCTOR DEVICE WITH STRESSOR - In a semiconductor fabrication process, an epitaxial layer is formed overlying a substrate, wherein there is a lattice mismatch between the epitaxial layer and the substrate. A hard mask having an opening is formed overlying the epitaxial layer. A recess is formed through the epitaxial layer and into the substrate. The recess is substantially aligned to the opening in the hard mask. A channel region of a semiconductor device is formed in the recess.09-03-2009
438284000 Closed or loop gate 4
20100105183SEMICONDUCTOR DEVICE WITH INCREASED CHANNEL AREA AND FABRICATION METHOD THEREOF - A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.04-29-2010
20100197097MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - To provide a manufacturing method of a semiconductor memory device, the method including forming contact plugs to be connected to a drain region or a source region of each of transistors, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having a line-shaped opening provided across the contact plugs. Each of the transistors constituting a sense amplifier that amplifies a potential difference between bit lines is a ring-gate transistor.08-05-2010
20100151645Semiconductor device and method of fabricating the same - A semiconductor device according to an embodiment of the present invention includes: a square pole-shaped channel portion made from a first semiconductor layer formed on a substrate, and surrounded with four side faces; a gate electrode formed on a first side face of the channel portion, and a second side face of the channel portion opposite to the first side face through respective gate insulating films; a source region having a conductivity type different from that of the channel portion and being formed on a third side face of the channel portion, the source region including a second semiconductor layer having a lattice constant different from that of the first semiconductor layer and being formed directly on the substrate; and a drain region having a conductivity type different from that of the channel portion and being formed on a fourth side face of the channel portion opposite to the third side face, the drain region including the second semiconductor layer being formed directly on the substrate.06-17-2010
20120009749METHOD FOR FABRICATING NANO DEVICES - Embodiments relate to a method for fabricating nano-wires in nano-devices, and more particularly to nano-device fabrication using end-of-range (EOR) defects. In one embodiment, a substrate with a surface crystalline layer over the substrate is provided and EOR defects are created in the surface crystalline layer. One or more fins with EOR defects embedded within is formed and oxidized to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wire.01-12-2012
438293000 Fusion or solidification of semiconductor region 4
20090142900METHOD FOR CREATING TENSILE STRAIN BY SELECTIVELY APPLYING STRESS MEMORIZATION TECHNIQUES TO NMOS TRANSISTORS - By selectively applying a stress memorization technique to N-channel transistors, a significant improvement of transistor performance may be achieved. High selectivity in applying the stress memorization approach may be accomplished by substantially maintaining the crystalline state of the P-channel transistors while annealing the N-channel transistors in the presence of an appropriate material layer which may not to be patterned prior to the anneal process, thereby avoiding additional lithography and masking steps.06-04-2009
20080293205METHOD OF FORMING METAL SILICIDE LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A method of forming a metal silicide layer includes sequentially forming a metal layer and a first capping layer on a substrate, performing a first heat treatment on the substrate to cause the substrate to react to the metal layer, removing the first, capping layer and an unreacted metal layer, forming a second capping layer on the substrate, and performing a second heat treatment on the substrate to form a metal silicide layer on the substrate.11-27-2008
20090029514METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, by which a bottom gate thin film transistor that has an improved S value and a channel forming region with a smaller thickness than that of a source region and a drain region can be manufactured in a simple process. An island-like conductive film is formed over a surface of an insulating substrate in a portion corresponding to a channel forming region, and is covered with an insulating film to form a projection portion. After an amorphous semiconductor film is deposited to cover the projection portion, the amorphous semiconductor film is irradiated with laser light so as to be melted and crystallized. Part of the melted semiconductor over the projection portion flows into regions adjacent to both sides of the projection portion, which results in reduction in thickness of the semiconductor film over the projection portion (channel forming region).01-29-2009
20080220581OPTO-THERMAL ANNEALING METHODS FOR FORMING METAL GATE AND FULLY SILICIDED GATE-FIELD EFFECT TRANSISTORS - An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.09-11-2008
438281000 Having fuse or integral short 1
20130183802SEMICONDUCTOR DEVICES HAVING E-FUSE STRUCTURES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes: an e-fuse gate, a floating pattern between the e-fuse gate and an e-fuse active portion, a blocking dielectric pattern between the floating pattern and the e-fuse gate, and an e-fuse dielectric layer between the floating pattern and the e-fuse active portion. The floating pattern includes a first portion between the e-fuse gate and the e-fuse active portion and a pair of second portions extended upward along both sidewalls of the e-fuse gate from both edges of the first portion.07-18-2013
Entries
DocumentTitleDate
20090104739METHOD OF FORMING CONFORMAL SILICON LAYER FOR RECESSED SOURCE-DRAIN - Processes for non-selectively forming one or more conformal silicon-containing epitaxial layers on recess corners are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of a non-selective epitaxial layer involves exposing a substrate in a process chamber to deposition gases including a silicon source such as silane and a higher order silane, followed by heating the substrate to promote solid phase epitaxial growth.04-23-2009
20110207271WIRING STRUCTURE IN A SEMICONDUCTOR DEVICE, METHOD OF FORMING THE WIRING STRUCTURE, SEMICONDUCTOR DEVICE INCLUDING THE WIRING STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A wiring structure in a semiconductor device may include a first insulation layer formed on a substrate, a first contact plug, a capping layer pattern, a second insulation layer and a second contact plug. The first insulation layer has a first opening that exposes a contact region of the substrate. The first contact plug is formed on the contact region to partially fill up the first opening. The capping layer pattern is formed on the first contact plug to fill up the first opening. The second insulation layer is formed on the capping layer pattern and the first insulation layer. The second insulation layer has a second opening passing through the capping layer pattern to expose the first contact plug. The second contact plug is formed on the first contact plug in the second opening. Since the wiring structure includes the capping layer pattern, the wiring structure may prevent a contact failure by preventing chemicals from permeating into the first contact plug.08-25-2011
20080233690Method of Selectively Forming a Silicon Nitride Layer - A method for selectively forming a dielectric layer. An embodiment comprises forming a dielectric layer, such as an oxide layer, on a semiconductor substrate, depositing a silicon layer on the dielectric layer, and treating the silicon layer with nitrogen, thereby converting the silicon layer into a silicon nitride layer. This method allows for a protective silicon nitride layer to be formed, while also preventing and/or reducing the nitrogen itself from penetrating far enough to contaminate the substrate. In another embodiment the treating with nitrogen is continued to form not only a silicon nitride, but to also diffuse a small portion of nitrogen into the dielectric layer to nitridized a portion of the dielectric layer. Optionally, an anneal could be performed to repair any damage that has been done by the treatment process.09-25-2008
20090197376PLASMA CVD METHOD, METHOD FOR FORMING SILICON NITRIDE FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A plasma processing apparatus generates plasma by introducing microwaves into a processing chamber by using a planar antenna having a plurality of slots. By using the plasma processing apparatus, a nitrogen containing gas and a silicon containing gas introduced into the processing chamber are brought into the plasma state, and at the time of depositing by using the plasma a silicon nitride film on the surface of the a substrate to be processed, stress to the silicon nitride film to be formed is controlled by the combination of the type and the processing pressure of the nitrogen containing gas.08-06-2009
20100159653METHOD FOR MANUFACTURING ION IMPLANTATION MASK, AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.06-24-2010
20100047976METHOD FOR FORMING NITRIDE SEMICONDUCTOR LAMINATED STRUCTURE AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR ELEMENT - The method for forming a nitride semiconductor laminated structure according to the present invention includes: a first layer forming step of forming an n-type or i-type first layer composed of a group III nitride semiconductor; a second layer forming step of laminating a p-type second layer composed of a group III nitride semiconductor and containing Mg on the first layer; and a third layer forming step of forming an n-type or i-type third layer composed of a group III nitride semiconductor on the second layer after the second layer forming step.02-25-2010
20100075475METHOD FOR PRODUCING A THIN FILM TRANSISTOR AND METHOD FOR FORMING AN ELECTRODE - An electrode is prevented from being peeled from a substrate or a silicon layer. After the surface of a first copper thin film composed mainly of copper is treated by exposing it to an ammonia gas, a film of silicon nitride is formed on the surface of the first copper thin film by generating a plasma of a raw material gas containing a silane gas and an ammonia gas in an atmosphere in which an object to be processed is placed. Since the surface is preliminarily treated with the ammonia gas, the silane gas is prevented from being diffused into the first copper thin film. Therefore, an electrode constituted by the surface-treated first copper thin film is not peeled from the glass substrate or the silicon layer. In addition, its electric resistance value does not rise.03-25-2010
20100075474SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A gate electrode 03-25-2010
20130034939METHOD OF MANUFACTURING POWER DEVICE - A method of manufacturing a power device includes forming a first drift region on a substrate. A trench is formed by patterning the first drift region. A second drift region is formed by growing n-gallium nitride (GaN) in the trench, and alternately disposing the first drift region and the second drift region. A source electrode contact layer is formed on the second drift region. A source electrode and a gate electrode are formed on the source electrode contact layer. A drain electrode is formed on one side of the substrate which is an opposite side of the first drift region.02-07-2013
20090155964METHODS FOR FABRICATING AN ELECTRONIC DEVICE - A method for fabricating an electronic device is provided. The method for fabricating the electrical device comprises providing a substrate. A patterned first self-assembled monolayer (SAM) and an adjacent patterned second SAM are formed on the substrate, wherein the patterned first SAM has a higher affinity then that of the patterned second SAM. A conductive, semiconductor or insulating material is dissolved or suspended in a solvent to form a solution. The solution is coated on the substrate. The solvent in the solution is removed to selectively form a patterned conductive, semiconductor or insulating layer on the patterned first SAM.06-18-2009
20090155965METHOD OF FABRICATING A NON-FLOATING BODY DEVICE WITH ENHANCED PERFORMANCE - Provided is a method that includes forming a first semiconductor layer on a semiconductor substrate, growing a second semiconductor layer on the first semiconductor layer, forming composite shapes on the first semiconductor layer, each composite shape comprising of an overlying oxide-resistant shape and an underlying second semiconductor shape, with portions of the first semiconductor layer exposed between the composite shapes, forming spacers on sides of the composite shapes, forming buried silicon oxide regions in exposed top portions of the first semiconductor layer, and in portions of the first semiconductor layer located underlying second semiconductor shapes, selectively removing the oxide-resistant shapes and spacers resulting in the second semiconductor shapes, and forming a semiconductor device in a second semiconductor shape wherein a first portion of the semiconductor device overlays the first semiconductor layer and wherein second portions of the semiconductor device overlays a buried silicon oxide region.06-18-2009
20100144103Method, System and Apparatus for Gating Configurations and Improved Contacts in Nanowire-Based Electronic Devices - Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.06-10-2010
20090124053FABRICATION OF NANOWIRES AND NANODEVICES - Methods of fabricating nanowire structures and nanodevices are provided. The methods involve photolithographically depositing a nucleation center on a crystalline surface of a substrate, generating a nanoscale seed from the nucleation center, and epitaxially growing a nanowire across at least a portion of the crystalline surface starting at a nucleation site where the nanoscale seed is located.05-14-2009
20130052778SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure.02-28-2013
20130089958Finlike Structures and Methods of Making Same - Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer.04-11-2013
20120115290MANUFACTURING METHOD OF CRYSTALLINE SEMICONDUCTOR FILM AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The crystalline semiconductor film is formed following steps that supplying a film formation gas to a second gas diffusion area from a gas introduction port provided in an upper electrode; supplying the film formation gas to a first gas diffusion area from the second gas diffusion area through holes provided in a dispersion plate between the first gas diffusion area and the second gas diffusion area; supplying the film formation gas into a treatment room from the first gas diffusion area through holes in a shower plate between the first gas diffusion area and the treatment room; generating glow discharge plasma by supplying high frequency electricity from an electrode surface of the upper electrode; generating crystal nuclei on a substrate provided over a lower electrode facing the upper electrode; and growing the crystal nuclei. A portion of the dispersion plate which faces the gas introduction port has no hole.05-10-2012
20110281408METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.11-17-2011
20110281407STRAINED SEMICONDUCTOR BY FULL WAFER BONDING - One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein.11-17-2011
20110300677Novel Method to Enhance Channel Stress in CMOS Processes - The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current.12-08-2011
20120108019METHOD FOR FABRICATING A SUBSTRATE PROVIDED WITH TWO ACTIVE AREAS WITH DIFFERENT SEMICONDUCTOR MATERIALS - A layer of second semiconductor material is deposited on the layer of first semiconductor material of a substrate. Two active areas are then defined by means of selective elimination of the first and second semiconductor materials. One of the two active areas is then covered by a protective material. The layer of second semiconductor material is then eliminated by means of selective elimination of material. A first active area comprising a main surface made from a first semiconductor material, and a second active area comprising a main surface made from second semiconductor material are thus obtained.05-03-2012
20110287593METHOD FOR FORMING SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a method for forming an oxide semiconductor film with little variation in electrical characteristics. Another object is to provide a method for manufacturing a semiconductor device including an oxide semiconductor film with little variation in electrical characteristics. To reduce the amount of light scattered by a substrate stage or the amount of the scattered light which travels to enter a light-transmitting oxide semiconductor layer when the light-transmitting oxide semiconductor layer is patterned, a layer having a function of preventing light transmission may be provided in a lower layer than a photoresist layer so that light does not reach the substrate stage. In addition, a semiconductor device may be manufactured using the oxide semiconductor layer formed by the above patterning method.11-24-2011
20110294270METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Extension regions 12-01-2011
20100035392SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.02-11-2010
20090117694NANOWIRE BASED NON-VOLATILE FLOATING-GATE MEMORY - A non-volatile memory transistor with a nanocrystal-containing floating gate formed by nanowires is disclosed. The nanocrystals are formed by the growth of short nanowires over a crystalline program oxide. As a result, the nanocrystals are single-crystals of uniform size and single-crystal orientation.05-07-2009
20100120210FLASH MEMORY HAVING INSULATING LINERS BETWEEN SOURCE/DRAIN LINES AND CHANNELS - A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.05-13-2010
20100093139METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device with improved reliability which includes a metal silicide layer formed by a salicide process. After forming gate electrodes, an n04-15-2010
20120142150METHOD FOR FORMING METAL GATE AND MOS TRANSISTOR - The invention provides a method for forming a metal gate and a method for forming a MOS transistor. The method for forming a metal gate includes: providing a substrate; forming a sacrificial oxide layer and a polysilicon gate on the substrate; forming a silicon oxide layer on sidewalls of the sacrificial oxide layer and the polysilicon gate; forming a stop layer that covers the substrate; removing a part of the stop layer in the spacers; forming a second interlayer dielectric layer that covers the first interlayer dielectric layer, the spacers and the polysilicon gate; polishing the second interlayer dielectric layer to expose the spacers and the polysilicon gate; removing the polysilicon gate to form a trench; removing the sacrificial oxide layer in the trench; and forming a metal gate in the trench. The invention prevents from recesses and therefore metal bridge and metal residuals in the recesses.06-07-2012
20090263943METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.10-22-2009
20110201163SEMICONDUCTOR NANOSTRUCTURES, SEMICONDUCTOR DEVICES, AND METHODS OF MAKING SAME - A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.08-18-2011
20090093094Selective Formation of Silicon Carbon Epitaxial Layer - Methods for formation of epitaxial layers containing n-doped silicon are disclosed, including methods for the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. Formation of the n-doped epitaxial layer involves exposing a substrate in a process chamber to deposition gases including a silicon source, a carbon source and an n-dopant source at a first temperature and pressure and then exposing the substrate to an etchant at a second higher temperature and a higher pressure than during deposition.04-09-2009
20090286365Modulation of Stress in Stress Film through Ion Implantation and Its Application in Stress Memorization Technique - Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.11-19-2009
20090286364METHODS OF LOW TEMPERATURE OXIDATION - A method for forming a dielectric is provided. The method includes providing a substrate having a silicon-containing semiconductor layer within a process chamber. The process chamber is capable of ionizing a process precursor to a plasma comprising an oxygen-containing element and a fluorocarbon-containing element. A surface portion of the silicon-containing material is oxidized by using the plasma to convert the surface portion into an oxidized dielectric material.11-19-2009
20080318370Semiconductor Integrated Circuit Switch Matrix - There is provided a small-type semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a first semiconductor layer, a first semiconductor layer transistor formed in the first semiconductor layer, a wiring layer which is deposited on the first semiconductor layer and in which metal wires are formed, a second semiconductor layer deposited on the wiring layer and a second semiconductor layer transistor formed in the second semiconductor layer. It is noted that insulation of a gate insulating film of the first semiconductor layer transistor is almost equal with that of a gate insulating film of the second semiconductor layer transistor and the gate insulating film of the second semiconductor layer transistor is formed by means of radical oxidation or radical nitridation.12-25-2008
20090042346Electrolyte pattern and method for manufacturing an electrolyte pattern - A method for manufacturing a gel electrolyte pattern is disclosed, the method comprising depositing an electrolyte precursor by inkjet printing onto a gelling agent layer. A gel electrolyte pattern is also disclosed, the gel electrolyte pattern comprising either a mixture of a gelling agent and an electrolyte precursor or the products of a chemical reaction between a gelling agent and an electrolyte precursor.02-12-2009
20090170252Formation method of metallic compound layer, manufacturing method of semiconductor device, and formation apparatus for metallic compound layer - A formation method of a metallic compound layer includes preparing, in a chamber, a substrate having a surface on which a semiconductor material of silicon, germanium, or silicon germanium is exposed, and forming a metallic compound layer, includes: supplying a raw material gas containing a metal for forming a metallic compound with the semiconductor material to the chamber; heating the substrate to a temperature at which the raw material gas is pyrolyzed; and forming a metallic compound layer by reaction of the metal with the semiconductor material so that no layer of the metal is deposited on the substrate. A manufacturing method of a semiconductor device employs this formation method of a metallic compound layer.07-02-2009
20090170253Method of manufacturing semiconductor device - The present invention relates to a method of manufacturing a semiconductor device, in which a gate electrode is formed in a T-shape in order to increase the size of a top surface of the gate electrode, thereby providing a stable silicide forming condition and preventing contact misalignment.07-02-2009
20090170251Fabrication of germanium nanowire transistors - In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.07-02-2009
20080242013SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing such a semiconductor device having a field effect transistor with improved current driving performance (e.g., an increase of drain current) of the field effect transistor comprising the steps of ion implanting an element from the main surface to the inside of a silicon layer as a semiconductor substrate to a level shallower than the implantation depth of the impurities in the step of forming the semiconductor region before the step of ion implanting impurities from the main surface to the inside of the silicon layer as a semiconductor substrate to form the semiconductor region being aligned with the gate electrode.10-02-2008
20080311712Insulated gate silicon nanowire transistor and method of manufacture - An insulated gate silicon nanowire transistor amplifier structure is provided and includes a substrate formed of dielectric material. A patterned silicon material may be disposed on the substrate and includes at least first, second and third electrodes uniformly spaced on the substrate by first and second trenches. A first nanowire formed in the first trench operates to electrically couple the first and second electrodes. A second nanowire formed in the second trench operates to electrically couple the second and third electrodes. First drain and first source contacts may be respectively disposed on the first and second electrodes and a first gate contact may be disposed to be capacitively coupled to the first nanowire. Similarly, second drain and second source contacts may be respectively disposed on the second and third electrodes and a second gate contact may be disposed to be capacitively coupled to the second nanowire.12-18-2008
20080286916METHODS OF STRESSING TRANSISTOR CHANNEL WITH REPLACED GATE - Methods of stressing a channel of a transistor with a replaced gate and related structures are disclosed. A method may include providing an intrinsically stressed material over the transistor including a gate thereof; removing a portion of the intrinsically stressed material over the gate; removing at least a portion of the gate, allowing stress retained by the gate to be transferred to the channel; replacing (or refilling) the gate with a replacement gate; and removing the intrinsically stressed material. Removing and replacing the gate allows stress retained by the original gate to be transferred to the channel, with the replacement gate maintaining (memorizing) that situation. The methods do not damage the gate dielectric.11-20-2008
20080293192SEMICONDUCTOR DEVICE WITH STRESSORS AND METHODS THEREOF - A semiconductor device is formed in a semiconductor layer. A gate dielectric is formed over a top surface of the semiconductor layer. A gate stack is over the gate dielectric. A sidewall spacer is formed around the gate stack. Using the sidewall spacer as a mask, an implant is performed to form deep source/drain regions in the semiconductor layer. Silicon carbon regions are formed on the deep source/drain regions and a top surface of the gate stack. The silicon carbon regions are silicided with nickel.11-27-2008
20080280403TRANSISTOR FABRICATION METHOD - A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.11-13-2008
20080206940FORMING A SEMICONDUCTOR DEVICE HAVING EPITAXIALLY GROWN SOURCE AND DRAIN REGIONS - A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is formed over the first and second regions. The first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers. The first insulating layer is removed from over the first region to leave a remaining portion of the first insulating layer over the second region. The semiconductor layer is recessed in the first region adjacent to the first gate to form recesses. A semiconductor material is epitaxially grown in the recesses. The remaining portion of the first insulating layer is removed.08-28-2008
20080206939SEMICONDUCTOR DEVICE WITH INTEGRATED RESISTIVE ELEMENT AND METHOD OF MAKING - A resistive device (08-28-2008
20100144104SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A plurality of origin patterns (06-10-2010
20100151638ANISOTROPIC STRESS GENERATION BY STRESS-GENERATING LINERS HAVING A SUBLITHOGRAPHIC WIDTH - A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on the stress-generating liner, and is annealed to allow phase separation of immiscible components. The polymeric resist is developed to remove at least one of the at least two polymeric block components, which formed a pattern of nested lines due to the linear edge of the protruding structure. Linear nanoscale stripes are formed in the polymeric resist which is self-aligning and self-assembled. The stress-generating layer is patterned into linear stress-generating stripes having a sublithographic width. The linear stress-generating stripes provide a predominantly uniaxial stress along their lengthwise direction, providing an anisotropic stress to an underlying semiconductor device.06-17-2010
20100151639METHOD FOR MAKING A THERMALLY-STABLE SILICIDE - Provided is a method of fabrication a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, the gate structure including a gate dielectric and a gate electrode disposed over the gate dielectric, forming source/drain regions in the semiconductor substrate at either side of the gate structure, forming a metal layer over the semiconductor substrate and the gate structure, the metal layer including a refractory metal layer or a refractory metal compound layer; forming an alloy layer over the metal layer; and performing an annealing thereby forming metal alloy silicides over the gate structure and the source/drain regions, respectively.06-17-2010
20090023255Method for Reshaping Silicon Surfaces with Shallow Trench Isolation - A method for making a semiconductor device by reshaping a silicon surface with a sacrificial layer is presented. In the present invention the steps of forming a sacrificial dielectric layer and removing the sacrificial dielectric layer are repeated multiple times in order to remove sharp edges from the silicon surface near the field oxides. Another aspect of the present invention includes making a MOSFET transistor that incorporates the forming and removing of multiple sacrificial layers into the process.01-22-2009
20090142890Phosphorus Activated NMOS Using SiC Process06-04-2009
20130217194MOS TRANSISTOR, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE - A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode.08-22-2013
20100003793METHOD FOR FORMING SILICIDE IN SEMICONDUCTOR DEVICE - A method for forming silicide in a semiconductor device includes simultaneously performing a cleaning process and an etching process to remove a silicide metal layer if an excessive delay in time lapses after forming the silicide metal layer. This may prevent the occurrence of liquid marks due to an oxidation reaction at an interface of the semiconductor substrate in contact with the silicide metal layer, thereby preventing silicide defects due to the excessive delay.01-07-2010
20090239344Methods of Forming Field Effect Transistors Having Silicided Source/Drain Contacts with Low Contact Resistance - Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.09-24-2009
20080261359LDMOS Transistor Device, Integrated Circuit, and Fabrication Method Thereof - An LDMOS transistor device in an integrated circuit comprises a semiconductor substrate (10-23-2008
20080261358Manufacture of Lateral Semiconductor Devices - A method of manufacturing a lateral semiconductor device comprising a semiconductor body (10-23-2008
20100227444MASK, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A mask having mask patterns for the transfer of a desired circuit pattern, a method for manufacturing the mask, and a semiconductor device manufacturing method using the mask, are provided. There are extracted two rectangular aperture patterns which are adjacent each other in an obliquely disposed state with respect to an X axis in an XY plane. The thus-extracted two rectangular aperture patterns are rotated at a certain angle so that a pattern edge corresponding to one side of one of the rectangular aperture patterns and a pattern edge corresponding to one side of the other rectangular aperture pattern are opposed in parallel to each other. The two rectangular aperture patterns thus rotated at a certain angle are then subjected to optical proximity effect correction to form two corrected rectangular aperture patterns.09-09-2010
20090075441Method of removing a spacer, method of manufacturing a metal-oxide-semiconductor transistor device, and metal-oxide-semiconductor transistor device - A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.03-19-2009
20080311711Gapfill for metal contacts - A method of making a semiconductor interconnect is disclosed. A semiconductor body on which a transistor comprising a doped region is formed is provided. A dielectric region is formed over the doped region, and a contact hole is formed in the dielectric to expose the doped region. The contact hole is cleaned and a first layer of metal is formed over a bottom and sidewalls of the contact hole. The first layer of metal is thinned so that the thickness of the first layer of metal on the sidewalls is made more uniform. A barrier is formed over the first layer of metal and the contact hole is filled with conductive material.12-18-2008
20110129970ENHANCING INTERFACE CHARACTERISTICS BETWEEN A CHANNEL SEMICONDUCTOR ALLOY AND A GATE DIELECTRIC BY AN OXIDATION PROCESS - In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material.06-02-2011
20130137226METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A highly reliable semiconductor device that includes a transistor including an oxide semiconductor is provided. In a manufacturing process of a semiconductor device that includes a bottom-gate transistor including an oxide semiconductor, an insulating film which is in contact with an oxide semiconductor film is subjected to dehydration or dehydrogenation treatment by heat treatment and oxygen doping treatment in this order. The insulating film which is in contact with the oxide semiconductor film refers to a gate insulating film provided under the oxide semiconductor film and an insulating film which is provided over the oxide semiconductor film and functions as a protective insulating film. The gate insulating film and/or the insulating film are/is subjected to dehydration or dehydrogenation treatment by heat treatment and oxygen doping treatment in this order.05-30-2013
20110244639METHOD FOR MANUFACTURING A PATTERN FORMED BODY, METHOD FOR MANUFACTURING A FUNCTIONAL ELEMENT, AND METHOD FOR MANUFACTURING A SEMICONDUCTOR ELEMENT - A main object of the present invention is to disclose a manufacturing method of the pattern formed body capable of attaining patterning efficiently with a high precision. To attain the object, the present invention provides a method comprising: a photoresist pattern formation step of forming a photoresist pattern on a hydrophobic layer formed on a substrate and having a surface exhibiting hydrophobicity; a hydrophilicity imparting step of radiating an energy onto the surface of the hydrophobic layer on which the photoresist pattern is formed, thereby making the surface hydrophilic to form hydrophilic areas; and a photoresist pattern peeling step of peeling the photoresist pattern and forming a hydrophilic/hydrophobic pattern on the hydrophobic layer surface, in which the hydrophilic area and hydrophobic area covered previously with the photoresist pattern in the hydrophilicity imparting step are formed in a pattern form.10-06-2011
20100055855Method of preventing sliding in manufacturing semiconductur device - A method for manufacturing transistors includes forming a gate electrode and a side wall insulating film over the device-forming surface of a silicon substrate. A source/drain region is formed in a periphery of the gate electrode on the silicon substrate. A Ni film is formed on the entire device-forming surface of the silicon substrate that is provided with a side wall formed thereon, and then, a reaction of the silicon substrate with the Ni film on the source/drain region by heating the silicon substrate.03-04-2010
20100055854Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device includes forming a trench in an interlayer dielectric film on the semiconductor substrate, the trench reaching a semiconductor substrate and having a sidewall made of silicon nitride film; depositing a gate insulation film made of a HfSiO film at a temperature within a range of 200 degrees centigrade to 260 degrees centigrade, so that the HfSiO film is deposited on the semiconductor substrate which is exposed at a bottom surface of the trench without depositing the HfSiO film on the silicon nitride film; and filling the trench with a gate electrode made of metal.03-04-2010
20110097858Transition metal alloys for use as a gate electrode and devices incorporating these alloys - Embodiments of a transition metal alloy having an n-type or p-type work function that does not significantly shift at elevated temperature. The disclosed transition metal alloys may be used as, or form a part of, the gate electrode in a transistor. Methods of forming a gate electrode using these transition metal alloys are also disclosed.04-28-2011
20120202325METHOD FOR MANUFACTURING A SINGLE CRYSTAL NANO-WIRE - A method for manufacturing a single crystal nano-structure includes providing a device layer with a 08-09-2012
20100081241SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR, CAPACITIVE ELEMENT AND FABRICATION METHOD THEREFOR, AND MIS TYPE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - A semiconductor device includes an operating layer made of a semiconductor and a silicon nitride film formed on the operating layer with the use of a mixed gas that includes mono-silane gas, hydrogen gas, and nitrogen gas, by a plasma CVD apparatus, under a condition that a flow rate of the hydrogen gas is 0.2 percent to 5 percent to an overall flow rate.04-01-2010
20080213956FIELD EFFECT TRANSISTOR DEVICE INCLUDING AN ARRAY OF CHANNEL ELEMENTS - The present invention relates to a semiconductor structure such as a field effect transistors (FETs) in which the channel region of each of the FETs is composed of an array of more than one electrically isolated channel. In accordance with the present invention, the distance between each of the channels present in the channel region is within a distance of no more than twice their width from each other. The FETs of the present invention are fabricated using methods in which self-assembled block copolymers are employed in forming the channel.09-04-2008
20080213957Integrated circuit with multi-length output transistor segments - A monolithic integrated circuit fabricated on a semiconductor die includes a control circuit and a first output transistor having segments substantially equal to a first length. A second output transistor has segments substantially equal to a second length. The first and second output transistors occupy an L-shaped area of the semiconductor die, the L-shaped area having first and second inner sides that are respectively disposed adjacent first and second sides of the control circuit. At least one of the first and second output transistors is coupled to the control circuit. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.09-04-2008
20110256675SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETs - A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.10-20-2011
20100190303Semiconductor device having sufficient process margin and method of forming same - According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.07-29-2010
20100029050STRESS ENGINEERING FOR CAP LAYER INDUCED STRESS - Improved layouts take better advantage of desirable cap-layer induced transverse and vertical stress. In one aspect, roughly described, a tensile strained cap material overlies the transistor channels in the N-channel diffusion regions but not the P-channel diffusion regions. The material terminates at an edge that is located as far as practical from the N-channel diffusion, toward the P-channel diffusion. In another aspect, roughly described, a gate conductor crosses a P-channel diffusion region and terminates as far as practical beyond the edge without making undesirable electrical contact with any other features of the integrated circuit design, and without overlying any other diffusion regions. A compressively strained cap layer overlies the P-channel diffusion. In yet another aspect, roughly described, a gate conductor crosses an N-channel diffusion and extends by as short a distance as practical before terminating or turning. A tensile strained cap material overlies the N-channel diffusion.02-04-2010
20110306170Novel Method to Improve Performance by Enhancing Poly Gate Doping Concentration in an Embedded SiGe PMOS Process - A method for forming an embedded SiGe (eSiGe) PMOS transistor (12-15-2011
20120302017Method and System for Providing Contact to a First Polysilicon Layer in a Flash Memory Device - A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.11-29-2012
20120302016MANUFACTURING METHOD OF LOW TEMPERATURE POLY-SILICON TFT ARRAY SUBSTRATE - A manufacturing method of an LTPS-TFT array substrate is provided. The exemplary method comprises a step of sequentially forming a poly-silicon layer and a data-line-metal layer on a base substrate, and performing a patterning process by using a third mask to simultaneously form an active layer and source and drain electrodes, the active layer being provided on the gate insulating layer and corresponding to the gate electrode, and the source and drain electrodes being provided on the active layer.11-29-2012
20120003798REPLACEMENT GATES TO ENHANCE TRANSISTOR STRAIN - Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.01-05-2012
20120208332SEMICONDUCTOR STRUCTURES HAVING IMPROVED CONTACT RESISTANCE - Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.08-16-2012
20120045872Semiconductor Memory Device - Disclosed herein is a semiconductor memory device for reducing a junction resistance and increasing amount of current throughout the unit cell. A semiconductor memory device comprises plural unit cells, each coupled to contacts formed in different shape at both sides of a word line in a cell array.02-23-2012
20120009744SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor substrate according to an embodiment includes: a first semiconductor wafer having a first crystal; and a second semiconductor wafer formed of a second crystal substantially same as the first crystal on the first semiconductor wafer, a crystal-axis direction of unit cell thereof being twisted at a predetermined angle around a direction vertical to a principal surface of the second semiconductor wafer from that of the first semiconductor wafer.01-12-2012
20110165743METHOD FOR MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - When a natural oxide film is left at the interface between a metal silicide layer and a silicon nitride film, in various heating steps (steps involving heating of a semiconductor substrate, such as various insulation film and conductive film deposition steps) after deposition of the silicon nitride film, the metal silicide layer partially abnormally grows due to oxygen of the natural oxide film occurring on the metal silicide layer surface. A substantially non-bias (including low bias) plasma treatment is performed in a gas atmosphere containing an inert gas as a main component on the top surface of a metal silicide film of nickel silicide or the like over source/drain of a field-effect transistor forming an integrated circuit. Then, a silicon nitride film serving as an etching stop film of a contact process is deposited. As a result, without causing undesirable cutting of the metal silicide film, the natural oxide film over the top surface of the metal silicide film can be removed.07-07-2011
20120070947INDUCING STRESS IN FIN-FET DEVICE - A method of forming a fin-shaped field effect transistor (fin-FET) is disclosed. In one embodiment, the method comprises: partially amorphizing a fin overlying a substrate; forming a stress layer over a portion of the partially amorphized fin; annealing to impart stress in the partially amorphized fin to form a stressed fin; removing the stress layer from over the portion of stressed fin; and forming a gate over the stressed fin after the removing of the stress layer.03-22-2012
20110065245METHOD FOR FABRICATING MOS TRANSISTOR - A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate and a source/drain region in the semiconductor substrate adjacent to two sides of the gate structure; covering a stress layer on the gate structure and the source/drain region; etching away the stress layer to form a plurality of openings with larger top and smaller bottom to expose surface of the gate structure and the source/drain region; forming a metal layer in the openings; and using the stress layer as a salicide block to react the metal layer with the gate structure and the source/drain region for forming a plurality of silicide layers.03-17-2011
20100210080METHOD OF MANUFACTURING GAN-BASED TRANSISTORS - A method of manufacturing a GaN-based field effect transistor is provided by which a lower resistance and a higher breakdown voltage are obtained and which is less affected by a current collapse. A method of manufacturing the GaN-based field effect transistor(s) can comprise performing an epitaxial growth of an AlN layer (08-19-2010
20090061577METHOD OF PRODUCING PRODUCT INCLUDING SILICON WIRES - A product including a plurality of wires, in which longitudinal directions of the wires are arranged in one direction so that each one of the wires is positioned end to end to one another, and a method of producing the same are disclosed. The longitudinal directions of the plurality of wires each covered with a polymer are arranged in one direction in a solvent, and the plurality of the wires whose longitudinal directions are arranged in one direction is fixed by using the polymer.03-05-2009
20120315732METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND DEVICE USING SAME - In a method for fabricating a semiconductor device, a substrate may be provided that includes: a base, an active fin that projects from an upper surface of the base and is integrally formed with the base, and a buffer oxide film pattern formed on the active fin in contact with the active fin. A first dummy gate film may be formed on the substrate to cover the buffer oxide film pattern and the first dummy gate film may be smoothed to expose the buffer oxide film pattern. A second dummy gate film may be formed on the exposed buffer oxide film pattern and the first dummy gate film.12-13-2012
20080299718DAMASCENE PROCESS HAVING RETAINED CAPPING LAYER THROUGH METALLIZATION FOR PROTECTING LOW-K DIELECTRICS - A method of forming single or dual damascene interconnect structures using either a via-first or trench first approach includes the steps of providing a substrate surface having an etch-stop layer thereon, a low-k dielectric layer on the etch-stop layer, and a dielectric capping layer on the low-k dielectric layer. In the single damascene process using trench pattern, a trench is etched through the capping layer, the low-k dielectric layer and the etch-stop layer to reach the substrate surface. In the via-first process, using a via pattern, the via is etched through the capping layer, the low-k dielectric layer and the etch-stop layer to reach the substrate surface. In the trench first process, using the via pattern the via is etched through the capping layer, the low-k dielectric layer and the etch-stop layer to reach the substrate surface. In the single damascene or either via-first or trench-first dual damascene embodiment, the capping layer is retained over the low-k dielectric layer on top surfaces of the trench into the metal processing, generally including CMP processing, wherein the CMP process removes at least a portion, and in one embodiment the entire, capping layer.12-04-2008
20080299719MOSFET-type semiconductor device, and method of manufacturing the same - A MOSFET-type semiconductor device includes a monocrystalline semiconductor layer formed in a shape of a thin wall on a insulating film, a gate electrode straddling over the semiconductor layer around the middle portion of the wall-shaped semiconductor layer via a gate insulating film, source and drain regions formed at the both ends of the semiconductor layer, a first metal-semiconductor compound layer formed on one of the side walls of each of source and drain regions of the semiconductor layer, and a second metal-semiconductor compound layer having a different composition and Shottky barrier height from that of the first metal-semiconductor compound layer on the other side wall of each of source and drain regions of the semiconductor layer.12-04-2008
20080299717METHOD OF FORMING A SEMICONDUCTOR DEVICE FEATURING A GATE STRESSOR AND SEMICONDUCTOR DEVICE - A semiconductor device (12-04-2008
20120264261METHOD FOR MANUFACTURING AN NMOS WITH IMPROVED CARRIER MOBILITY - Tensile stress is applied to the channel region of an N-type metal oxide semiconductor (NMOS) transistor by directly forming a material having a tensile stress, for example, tungsten, in the contact holes on the source region and drain region of the NMOS. Then, the dummy gate layer in the gate stack of the NMOS transistor is removed, so as to further reduce the counter force of the gate stack on the channel region, thereby increasing the tensile stress in the channel region, enhancing the drift mobility of the carrier, and improving the performance of the transistor. The present invention avoids using a separate stress layer to create tensile stress in the channel region of an NMOS transistor, which advantageously simplifies the transistor manufacturing process and improves sizes and performance of the transistor.10-18-2012
20120264262Method for forming semiconductor structure - The invention relates to a method for forming a semiconductor structure, comprising: providing a semiconductor substrate which comprises a dummy gate formed thereon, a spacer surrounding the dummy gate, source and drain regions formed on two sides of the dummy gate, respectively, and a channel region formed in the semiconductor substrate and below the dummy gate; removing the dummy gate to form a gate opening; forming a stressed material layer in the gate opening; performing an annealing to the semiconductor substrate, the stressed material layer having tensile stress characteristics during the annealing; removing the stressed material layer in the gate opening; and forming a gate in the gate opening. By the above steps, the stress memorization technique can be applied to the pMOSFET.10-18-2012
20100203688SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a semiconductor layer having a first major surface, a second major surface provided on opposite side of the first major surface, and a channel formation region provided in a surface portion on the first major surface side; a first main electrode provided inside a dicing street on the first major surface of the semiconductor layer; a second main electrode provided inside a dicing street on the second major surface of the semiconductor layer; and a control electrode opposed to the channel formation region across an insulating film.08-12-2010
20110230021Inverter, method of manufacturing the same, and logic circuit including the inverter - Provided are an inverter, a method of manufacturing the inverter, and a logic circuit including the inverter. The inverter may include a first transistor and a second transistor having different channel layer structures. A channel layer of the first transistor may include a lower layer and an upper layer, and a channel layer of the second transistor may be the same as one of the lower layer and the upper layer. At least one of the lower layer and the upper layer may be an oxide layer. The inverter may be an enhancement/depletion (E/D) mode inverter or a complementary inverter.09-22-2011
20110237035Formation of Active Area Using Semiconductor Growth Process without STI Integration - A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., silicon, is grown over the exposed semiconductor body. A device, such as a transistor, can then be formed in the grown semiconductor material.09-29-2011
20100233860SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device including an n-channel MISFET including source/drain regions 09-16-2010
20120329219THROUGH WAFER VIAS AND METHOD OF MAKING SAME - A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.12-27-2012
20120100678METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes the following processes. A first interlayer insulating film is formed over a cell transistor and a peripheral transistor. A cell contact hole is formed in the first interlayer insulating film, the cell contact hole reaching the cell transistor. A lower contact plug is formed at a bottom of the cell contact hole. A peripheral contact hole is formed in the first interlayer insulating film, the peripheral contact hole reaching the peripheral transistor. A first peripheral contact plug is simultaneously formed in the peripheral contact hole and an upper contact plug in the cell contact hole, the upper contact plug being disposed on the lower contact plug.04-26-2012
20110159648METHODS OF FOMRING ARRAY OF NANOSCOPIC MOSFET TRANSISTORS - A nanoscopic transistor is made by forming an oxide layer on a semiconductor substrate, applying resist, patterning the resist using imprint lithography to form a pattern aligned along a first direction, applying a first ion-masking material over the pattern, selectively lifting it off to leave a first ion mask to form a gate, forming doped regions by implanting a suitable dopant, applying another layer of resist and patterning the second resist layer using imprint lithography to form a second pattern aligned along a second direction, applying a second ion-masking material over the second pattern, selectively lifting it off to leave a second ion mask defined by the second pattern, and forming second doped regions in the substrate by implanting a suitable second dopant selectively in accordance with the second ion mask. The method may be used to make an array of nanoscopic transistors.06-30-2011
20130023093RECESSED CONTACT FOR MULTI-GATE FET OPTIMIZING SERIES RESISTANCE - A method to fabricate a transistor including forming at least one electrically conductive channel structure over a substrate, the channel having a length, a width and a first height (h01-24-2013
20130171781GRAPHENE ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a graphene electronic device may include forming a metal compound layer and a catalyst layer on a substrate, the catalyst layer including a metal element in the metal compound layer, growing a graphene layer on the catalyst layer, and converting the catalyst layer into a portion of the metal compound layer.07-04-2013
20080242012High quality silicon oxynitride transition layer for high-k/metal gate transistors - A method for fabricating a high quality silicon oxynitride layer for a high-k/metal gate transistor comprises depositing a high-k dielectric layer on a substrate, depositing a barrier layer on the high-k dielectric layer, wherein the barrier layer includes at least one of nitrogen or oxygen, depositing a capping layer on the barrier layer, and annealing the substrate at a temperature that causes at least a portion of the nitrogen and/or oxygen in the barrier layer to diffuse to an interface between the high-k dielectric layer and the substrate. The diffused nitrogen or oxygen forms a high-quality silicon oxynitride layer at the interface. The high-k dielectric layer, the barrier layer, and the capping layer may then be etched to form a gate stack for use in a high-k/metal gate transistor. The capping layer may be replaced with a metal gate electrode using a replacement metal gate process.10-02-2008
20080233692Method and System for Forming a Controllable Gate Oxide - Method and system for forming gate structure with controllable oxide. The method includes a step for providing a semiconductor substrate and defining a source region and a drain region within the semiconductor substrate. Furthermore, the method includes a step for defining a gate region positioned between the source region and the drain region. Moreover, the method provides a step for forming a first layer overlaying the gate region. The first layer includes silicon nitride and/or silicon oxynitride material. Also, the method includes a step for forming a second layer by subjecting the semiconductor substrate to at least oxygen at a predetermined temperature range for a period of time. The second layer has a thickness less than 20 Angstroms.09-25-2008
20080233691METHOD OF FORMING ASYMMETRIC SPACERS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING ASYMMETRIC SPACERS - A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer.09-25-2008
20080227247BARRIER DIELECTRIC STACK FOR SEAM PROTECTION - The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric passivation stack comprising a plurality of conformal dielectric layers, wherein no electrical path extends entirely through the stack; and a contact to the source and drain regions, wherein the discontinuous seam through the conformal dielectric passivation stack substantially eliminates shorting between the contact and the gate conductor. The present invention also provides a method for forming the above-described semiconducting device.09-18-2008
20130143374METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD FOR GROWING GRAPHENE - A catalyst film (06-06-2013
20120252176METHOD FOR FABRICATING A POWER TRANSISTOR - A method for fabricating a power transistor includes: (a) forming a trench in a substrate with a first electrical type; (b) diffusing second electrical type carriers into the substrate from the trench such that the substrate is formed into a first part and a second part that is diffused with the second electrical type carriers and that adjoins the trench, the first and second parts being crystal lattice continuous to each other; (c) forming a filling portion in the trench, the filling portion adjoining the second part; (d) performing a carrier-implanting process in the second part and the filling portion; and (e) forming over the substrate a gate structure that has a dielectric layer and a conductive layer.10-04-2012
20130115741PROCESS TO REMOVE Ni AND Pt RESIDUES FOR NiPtSi APPLICATIONS USING AQUA REGIA WITH MICROWAVE ASSISTED HEATING - The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process, comprising using an aqua regia cleaning solution (comprising a mixture of nitric acid and hydrochloric acid) with microwave assisted heating. Low boiling temperature of hydrochloric acid prevents heating the aqua regia solution to a high temperature, impeding the effectiveness of post silicidation nickel and platinum residue removal. Therefore, embodiments of the invention provide a microwave assisted heating of the substrate in an aqua regia solution, selectively heating platinum residues without significantly increasing the temperature of the aqua regia solution, rendering platinum residues to be more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.05-09-2013
20090111224FUSI INTEGRATION METHOD USING SOG AS A SACRIFICIAL PLANARIZATION LAYER - A method for making a transistor 04-30-2009
20110212584Phosphorus Activated NMOS Using SiC Process09-01-2011
20130157423MOSFETs WITH REDUCED CONTACT RESISTANCE - A method and structure for forming a field effect transistor with reduced contact resistance are provided. The reduced contact resistance is manifested by a reduced metal semiconductor alloy contact resistance and a reduced conductively filled via contact-to-metal semiconductor alloy contact resistance. The reduced contact resistance is achieved in this disclosure by texturing the surface of the transistor's source region and/or the transistor's drain region. Typically, both the source region and the drain region are textured in the present disclosure. The textured source region and/or the textured drain region have an increased area as compared to a conventional transistor that includes a flat source region and/or a flat drain region. A metal semiconductor alloy, e.g., a silicide, is formed on the textured surface of the source region and/or the textured surface of the drain region. A conductively filled via contact is formed atop the metal semiconductor alloy.06-20-2013
20130122671PROCESS TO REMOVE Ni AND Pt RESIDUES FOR NiPtSi APPLICATIONS - The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Embodiments of the invention provide a multi-step cleaning process, comprising exposing the substrate to a nitric acid solution after a first anneal, followed by an aqua regia solution after a second anneal. The substrate can be optionally exposed to a hydrochloric acid solution afterward to completely remove any remaining platinum residues.05-16-2013
20130122670PROCESS TO REMOVE Ni AND Pt RESIDUES FOR NiPtSi APPLICATIONS USING CHLORINE GAS - The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.05-16-2013
20110294269Transistor With Embedded Strain-Inducing Material Formed in Diamond-Shaped Cavities Based on a Pre-Amorphization - When forming cavities in active regions of semiconductor devices in order to incorporate a strain\-inducing semiconductor material, superior uniformity may be achieved by using an implantation process so as to selectively modify the etch behavior of exposed portions of the active region. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility, while at the same time the dependence on pattern loading effect may be reduced. Consequently, a significantly reduced variability of transistor characteristics may be achieved.12-01-2011
20110312136STRUCTURE AND METHOD FOR COMPACT LONG-CHANNEL FETs - A compact semiconductor structure including at least one FET located upon and within a surface of a semiconductor substrate in which the at least one FET includes a long channel length and/or a wide channel width and a method of fabricating the same are provided. In some embodiments, the ordered, nanosized pattern is oriented in a direction that is perpendicular to the current flow. In such an embodiment, the FET has a long channel length. In other embodiments, the ordered, nanosized pattern is oriented in a direction that is parallel to that of the current flow. In such an embodiment, the FET has a wide channel width. In yet another embodiment, one ordered, nanosized pattern is oriented in a direction perpendicular to the current flow, while another ordered, nanosized pattern is oriented in a direction parallel to the current flow. In such an embodiment, a FET having a long channel length and wide channel width is provided.12-22-2011
20120021573Methods Of Forming An Array Of Memory Cells, Methods Of Forming A Plurality Of Field Effect Transistors, Methods Of Forming Source/Drain Regions And Isolation Trenches, And Methods Of Forming A Series Of Spaced Trenches Into A Substrate - A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed.01-26-2012

Patent applications in class Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.)

Patent applications in all subclasses Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.)