| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438124000 | And encapsulating | 75 |
| 20130040428 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided. The semiconductor package includes a package body, a plurality of semiconductor chips, and an external connection terminal. The package body is stacked with a plurality of sheets where conductive patterns and vias are disposed. The plurality of semiconductor chips are inserted into insert slots extending from one surface of the package body. The external connection terminal is provided on other surface opposite to the one surface of the package body. Here, the plurality of semiconductor chips are electrically connected to the external connection terminal. | 02-14-2013 |
| 20100041183 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device including a semiconductor chip encapsulated by an encapsulation resin and a manufacturing method thereof, in which a size reduction may be attempted. The device includes a semiconductor chip, an external connection terminal pad electrically connected to the semiconductor chip, and an encapsulation resin encapsulating the semiconductor chip, wherein a wiring pattern on which the external connection terminal pad is formed is provided between the semiconductor chip and the external connection terminal pad, and the semiconductor chip is flip-chip bonded to the wiring pattern. | 02-18-2010 |
| 20130029458 | SUBSTRATE FOR SEMICONDUCTOR PACKAGE HAVING COATING FILM AND METHOD FOR MANUFACTURING THE SAME - A substrate for a semiconductor package includes a ball land disposed on one surface of an insulating layer. A solder resist is applied to the surface of insulating layer while leaving the ball land exposed. A coating film is applied on the exposed surface of the ball land. The coating film includes a high molecular compound having metal particles. In the substrate having the ball land with the coating film formed thereon, it is not necessary to subject the substrate to a UBM formation process. | 01-31-2013 |
| 20130045574 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package and a method of manufacturing the semiconductor package are disclosed. A semiconductor package in accordance with an embodiment of the present invention includes a substrate, which has a ground circuit formed thereon, a semiconductor chip, which is mounted on the substrate, a conductive first shield, which is formed on an upper surface of the semiconductor chip and connected with the ground circuit, and a conductive second shield, which covers the substrate and the semiconductor chip and is connected with the first shield. With a semiconductor package in accordance with an embodiment of the present invention, grounding is possible between semiconductor chips because a shield is also formed on an upper surface of the semiconductor chip, and the shielding property can be improved by a double shielding structure. | 02-21-2013 |
| 20090269890 | SEMICONDUCTOR DEVICE - The method of manufacture includes preparing a wiring board which has a front surface and an opposing rear surface, a plurality of conductive portions which are formed on the front and rear surfaces of the core material thereof, respectively, forming a first resist film and a second resist film on the front surface and rear surface of the core material, respectively, such that the conductive portions are exposed therefrom; mounting the semiconductor chip to the main surface side of the wiring board via adhesive material; electrically connecting the pads provided on the semiconductor chip, with the first conductive portions of the wiring board via bonding wires, respectively; and sealing the semiconductor chip and the bonding wires. | 10-29-2009 |
| 20090011549 | PROCESS AND SYSTEM FOR MANUFACTURING AN ENCAPSULATED SEMICONDUCTOR DEVICE - A process for manufacturing a semiconductor device envisages the steps of: positioning a frame structure, provided with a supporting plate carrying a die of semiconductor material, within a molding cavity of a mold; and introducing encapsulating material within the molding cavity for the formation of a package, designed to encapsulate the die. The frame structure is further provided with a prolongation element mechanically coupled to the supporting plate inside the molding cavity and coming out of the molding cavity, and the process further envisages the steps of: controlling positioning of the supporting plate within the molding cavity with the aid of the prolongation element; and, during the step of introducing encapsulating material, separating and moving the prolongation element away from the supporting plate. | 01-08-2009 |
| 20130122657 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - There is provided a method of manufacturing a semiconductor package. The method includes: (a) providing a semiconductor chip having a first surface and a second surface opposite to the first surface, wherein a pad is formed on the first surface; (b) disposing the semiconductor chip on a supporting substrate such that the first surface is directed upward; (c) forming an encapsulation resin layer on the supporting substrate so as to cover the semiconductor chip; and (d) polishing the encapsulation resin layer to expose a top surface of the pad. | 05-16-2013 |
| 20110281402 | FORMATION OF A MASKING LAYER ON A DIELECTRIC REGION TO FACILITATE FORMATION OF A CAPPING LAYER ON ELECTRICALLY CONDUCTIVE REGIONS SEPARATED BY THE DIELECTRIC REGION - A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g., a cobalt alloy, a nickel alloy, tungsten, tantalum, tantalum nitride), a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition. | 11-17-2011 |
| 20110300672 | SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREFOR - To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device. | 12-08-2011 |
| 20090298237 | SEMICONDUCTOR MODULE - A semiconductor module includes a semiconductor chip sealed with an encapsulation resin prevented from overflowing from an inside of the outer edge by a wiring pattern extended portion extending from the wiring pattern along an outer edge of a solder resist pattern at an outside of the outer edge of the solder resist pattern. | 12-03-2009 |
| 20090098687 | Integrated circuit package including wire bonds - It has been found that integrated packages having dies with at least 10 bonding pads separated by a pitch of 65 μm or less are susceptible to corrosion upon wire bonding to these pads and subsequent encapsulation in a passivating material. In particular, crevices are potentially formed between the bonding wire and bonding pad that are not passivated and that promote corrosion. Avoidance of crevice formation through, for example, appropriately choosing the bonding pad and wire configuration substantially avoids such corrosion. | 04-16-2009 |
| 20100267207 | INTEGRATED CIRCUIT MODULE AND METHOD OF PACKAGING SAME - An integrated circuit (IC) module ( | 10-21-2010 |
| 20100124802 | Method of manufacturing a semiconductor package using a carrier - A method of manufacturing a semiconductor package includes providing a carrier, forming a post slot and a terminal slot in the carrier, depositing a post in the post slot, depositing a terminal in the terminal slot, forming an encapsulant slot in the carrier, wherein the post extends into and is located within a periphery of the encapsulant slot and the terminal extends into the encapsulant slot, mechanically attaching a semiconductor chip to the post, electrically connecting the chip to the terminal, depositing an encapsulant in the encapsulant slot, and removing the carrier from the terminal. | 05-20-2010 |
| 20100015762 | Solder Interconnect - Various solder interconnect methods and apparatus are disclosed. In aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a circuit board with plural solder joints whereby an interstitial space is left between the semiconductor chip and the circuit board. The semiconductor chip and the circuit board are heated at a first temperature lower than a melting point of constituents of the plural solder joints to liberate contaminants from the interstitial space. The semiconductor chip and the circuit board are heated again at a second temperature higher than a melting point of at least one the constituents but not all of the constituents of the plural solder joints to shrink grain sizes of the at least one constituent. An underfill is placed in the interstitial space. | 01-21-2010 |
| 20100120207 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor chip has a rectangular main surface with first and second vertices on a diagonal line and first and second sides connecting the first and second vertices. A wire is formed between an electrode and a pad of the semiconductor chip. The wire is enclosed in a cavity of a mold. A liquid resin is poured into the cavity to flow from the first vertex toward the second vertex along the first and second sides. The liquid resin is cured to form a resin portion. The wire is formed such that the wire extends on the side relatively further from the first vertex with respect to a straight line connecting the pad and electrode as seen in plan view. Wires are thus prevented from contacting each other in the process of pouring the liquid resin and accordingly electrical short circuit between the wires can be prevented. | 05-13-2010 |
| 20100190301 | CAVITY CLOSURE PROCESS FOR AT LEAST ONE MICROELECTRONIC DEVICE - A process for closure of at least one cavity intended to encapsulate or be part of a microelectronic device, comprising the following steps:
| 07-29-2010 |
| 20090263938 | Method for manufacturing semiconductor device - In a double-sided electrode package, a sealing resin layer is formed so as to fill peripheries of surface-side terminals formed on a package substrate. Since the side surfaces of the surface-side terminals have plural protruded rims, adhesion with the sealing resin layer is improved by an anchor effect. At a sealing step, since supplied liquid resin is naturally flowed to form the sealing resin layer, a “mold step” and a “grinding step” may be omitted, and thus the sealing step may be simplified more greatly than a case where the resin sealing is carried out by a transfer molding method. | 10-22-2009 |
| 20110201160 | METAL-EMBEDDED SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME - A metal-embedded substrate includes a core layer having first circuit wiring lines with bond fingers formed on a first surface of the core layer and second circuit wiring lines with ball lands formed on a second surface of the core layer. Via wiring lines are formed so as to pass through the core layer and connect the first and second circuit wiring lines. Solder masks are selectively formed on the first and second surfaces of the core layer, including the first and second circuit wiring lines, so as to expose the bond fingers and the ball lands. Metal patterns are formed on the ball lands exposed through the solder masks. A metal active material is formed on the solder mask formed on the second surface of the core layer, and covers side surfaces of the metal patterns. | 08-18-2011 |
| 20100285638 | METHOD FOR FABRICATING QFN SEMICONDUCTOR PACKAGE - A method for making a quad flat non-lead (QFN) semiconductor package includes half etching a first side of a carrier to form top portions of a lead array and a die attach surface of a die attach pad, wherein the lead array includes at least one inner terminal lead disposed adjacent to the die attach pad, at least one extended, outer terminal lead disposed along periphery of the QFN semiconductor package, and at least one intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead, wherein the intermediary terminal is disposed between the inner terminal lead and the extended, outer terminal lead. | 11-11-2010 |
| 20090155959 | Semiconductor Device and Method of Forming Integrated Passive Device Module - A method of manufacturing a semiconductor device includes providing a substrate with an insulation layer disposed on a top surface of the substrate, forming a passive device over the top surface of the substrate, removing the substrate, depositing an insulating polymer film layer over the insulation layer, and depositing a metal layer over the insulating polymer film layer. A solder mask can be formed over the metal layer. A conformal metal layer can then be formed over the solder mask. A notch can be formed in the insulation layer to enhance the connection between the insulating polymer film layer and the insulation layer. Additional semiconductor die can be electrically connected to the passive device. The substrate is removed by removing a first amount of the substrate using a back grind process, and then removing a second amount of the substrate using a wet dry, dry etch, or chemical-mechanical planarization process. | 06-18-2009 |
| 20090004783 | METHOD OF PACKAGE STACKING USING UNBALANCED MOLDED TSOP - A semiconductor package assembly is disclosed including a pair of stacked leadframe-based semiconductor packages. The first package is encapsulated in a mold compound so that the electrical leads emanate from the sides of the package, near a bottom surface of the package. The first package may be stacked atop the second package by aligning the exposed leads of the first package with the exposed leads of the second package and affixing the respective leads of the two packages together. The vertical offset of leads toward a bottom of the first package provides a greater overlap with leads of the second package, thus allowing a secure bonding of the leads of the respective packages. | 01-01-2009 |
| 20090186453 | Power Semiconductor Devices Having Integrated Inductor - An electronic device ( | 07-23-2009 |
| 20110223720 | FABRICATION METHOD FOR RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE - A fabrication method for a resin encapsulated semiconductor device includes the steps of: (1) die-bonding a semiconductor device to a first electrical connection metallic terminal of a wiring substrate; (2) electrically connecting an electrode of the semiconductor device and a second electrical connection metallic terminal of the wiring substrate via an electrical connector; (3) surface treating such an assembly by applying a solution to a surface of the assembly and baking the applied solution; and (4) transfer-molding an insulating encapsulating resin onto the surface-treated assembly. | 09-15-2011 |
| 20100248430 | High Frequency Flip Chip Package Process of Polymer Substrate and Structure thereof - In a high frequency flip chip package process of a polymer substrate and a structure thereof, the structure is a one-layer structure packaged by a high frequency flip chip package process to overcome the shortcomings of a conventional two-layer structure packaged by the high frequency flip chip package process. The conventional structure not only incurs additional insertion loss and return loss in its high frequency characteristic, but also brings out a reliability issue. Thus, the manufacturing process of a ceramic substrate in the conventional structure still has the disadvantages of a poor yield rate and a high cost. | 09-30-2010 |
| 20110230014 | METHOD OF PROVIDING AN ELECTRONIC DEVICE INCLUDING DIES, A DIELECTRIC LAYER, AND AN ENCAPSULATING LAYER - A method of packaging an electronic device includes providing a patterned dielectric layer with an area sized to receive a first die, and another area sized to receive a second die, placing the first and second dies within the first and second areas, encapsulating the dies with an encapsulating material that has a different composition from the dielectric layer, forming a first signal line between the dies, forming a second signal line to the first die, and forming an additional signal line to the first die. The dielectric layer is disposed between the first signal line and the encapsulating material, the electronic device transmits a signal in an approximate range of 1 GHz to 100 GHz along the second signal line, and a signal that does not exceed approximately 900 MHz along the additional signal line. | 09-22-2011 |
| 20090280603 | METHOD OF FABRICATING CHIP PACKAGE - A method of fabricating a chip package is provided. A thin metal plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts are provided. A chip is disposed on the thin metal plate, and a plurality of bonding wires for electrically connecting the chip to the second protrusion part and the second protrusion part to the third protrusion parts is formed. An upper encapsulant and a lower encapsulant are formed on the upper surface and the lower surface of the thin metal plate respectively. The lower encapsulant has a plurality of recesses for exposing a portion of the thin metal plate at locations where the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another. Finally, the thin metal plate is etched by using the lower encapsulant as an etching mask. | 11-12-2009 |
| 20100178735 | Fusible I/O Interconnection Systems and Methods for Flip-Chip Packaging Involving Substrate-Mounted Stud Bumps - A semiconductor device is made by providing a semiconductor die having bond pads formed on a surface of the semiconductor die, forming a UBM over the bond pads of the semiconductor die, forming a fusible layer over the UBM, providing a substrate having bond pads formed on a surface of the substrate, and forming a plurality of stud bumps containing non-fusible material over the bond pads on the substrate. Each stud bump includes a wire having a first end attached to the bond pad of the substrate and second end of uniform height. The method further includes electrically connecting the second end of the wire for each stud bump to the bond pads of the semiconductor die by reflowing the fusible layer or applying thermal compression bonding, depositing an underfill material between the semiconductor die and substrate, and depositing an encapsulant over the semiconductor die and substrate. | 07-15-2010 |
| 20100159647 | MULTILAYER PRINTED CIRCUIT BOARD AND THE MANUFACTURING METHOD THEREOF - A multilayer printed circuit board, wherein, on a resin-insulating layer that houses a semiconductor element, another resin-insulating layer and a conductor circuit are formed with conductor circuits electrically connected through a via hole, wherein a electromagnetic shielding layer is formed on a resin-insulating layer surrounding a concave portion for housing a semiconductor element or on the inner wall surface of the concave portion, and the semiconductor element is embedded in the concave portion. | 06-24-2010 |
| 20120196406 | Semiconductor Package with Embedded Die - A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration. | 08-02-2012 |
| 20100221873 | Semiconductor Device and Method of Forming an Interconnect Structure for 3-D Devices Using Encapsulant for Structural Support - A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV. | 09-02-2010 |
| 20110027944 | METHOD OF FORMING ELECTRICAL CONNECTIONS - A method of forming electrical connections to a semiconductor wafer. A semiconductor wafer comprising an insulation layer is provided. The insulation layer has a surface. A patterned mask layer is formed over the surface of the insulation layer. The patterned mask layer exposes portions of the surface of the insulation layer through a plurality of holes. The portions of the plurality of holes are filled with a metal material comprising copper to form elongated columns of the metal material. The elongated columns of the metal material have a sidewall surface. The patterned mask layer is removed to expose the sidewall surface of the elongated columns of the metal material. A protection layer is formed on the exposed sidewall surface of the elongated columns of the metal material. | 02-03-2011 |
| 20100197082 | Implantable Microelectronic Device and Method of Manufacture - An implantable hermetically sealed microelectronic device and method of manufacture are disclosed. The microelectronic device of the present invention is hermetically encased in a insulator, such as alumina formed by ion bean assisted deposition (“IBAD”), with a stack of biocompatible conductive layers extending from a contact pad on the device to an aperture in the hermetic layer. In a preferred embodiment, one or more patterned titanium layers are formed over the device contact pad, and one or more platinum layers are formed over the titanium layers, such that the top surface of the upper platinum layer defines an external, biocompatible electrical contact for the device. Preferably, the bottom conductive layer is larger than the contact pad on the device, and a layer in the stack defines a shoulder. | 08-05-2010 |
| 20100221872 | REVERSIBLE LEADLESS PACKAGE AND METHODS OF MAKING AND USING SAME - A method for manufacturing a semiconductor device package including an electrically conductive lead frame having a plurality of posts disposed at a perimeter of the package. Each of the posts has a first contact surface at the first package face and a second contact surface at the second package face. The lead frame also includes a plurality of post extensions disposed at the second package face. Each of the post extensions includes a bond site formed on a surface of the post extension opposite the second package face. At least one I/O pad on the semiconductor device is electrically connected to the post extension at the bond site using wirebonding, tape automated bonding, or flip-chip methods. The package can be assembled using a lead frame having pre-formed leads, with or without taping, or using partially etched lead frames. A stack of the semiconductor device packages may be formed. | 09-02-2010 |
| 20090111222 | SEMICONDUCTOR CHIP MOUNTING METHOD, SEMICONDUCTOR MOUNTING WIRING BOARD PRODUCING METHOD AND SEMICONDUCTOR MOUNTING WIRING BOARD - A method of producing a wiring board on which a semiconductor chip is to be mounted, includes: adhering an aluminum foil to one surface of a resin substrate; providing a heat-hardening resin layer having a predetermined shape on the aluminum foil; removing a part of the aluminum foil which is exposed from the heat-hardening resin layer to form a wiring circuit; and providing a thermoplastic resin layer on the wiring circuit. The heat-hardening resin layer has strength that enables the wiring board to prevent short between the semiconductor chip and the wiring circuit and has a crosslinking degree that is so reduced as to enable the bump to remove the heat-hardening resin layer to reach the wiring circuit, when the heat is applied to the wiring board and the bump to which the ultrasonic wave is applied is pressed to the wiring board. | 04-30-2009 |
| 20090111221 | Fabrication method of semiconductor device - A fabrication method of semiconductor device includes providing a substrate which has a plurality of electrical connection pads and is covered with an insulative layer, wherein the insulative layer has an opening formed for exposing the electrical connection pads; forming a filling material on the insulative layer of the substrate and compressing a semiconductor chip to the substrate through a plurality of bumps, the bumps electrically connecting the electrical connection pads and the filling material filling spacing between the semiconductor chip and the substrate so as to form a filling layer. By replacing the conventional underfilling process with the preprinting process of the filling material, the fabrication cost of the semiconductor device is reduced and the fabrication process is simplified. | 04-30-2009 |
| 20090068797 | MANUFACTURING PROCESS FOR A QUAD FLAT NON-LEADED CHIP PACKAGE STRUCTURE - A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having a plurality of recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A plurality of chips are bonded onto the patterned solder resist layer such that the patterned solder resist layer is between the chips and the conductive layer. The chips are electrically connected to the conductive layer by a plurality of bonding wires. At least one molding compound is formed to encapsulate the conductive layer, the patterned solder resist layer, the chips and the bonding wires. A part of the conductive layer uncovered by the patterned solder resist layer is removed so as to form a patterned conductive layer. Then, the molding compound and the patterned conductive layer are separated. | 03-12-2009 |
| 20100112760 | SEMICONDUCTOR MODULE INCLUDING CIRCUIT COMPONENT AND DIELECTRIC FILM, MANUFACTURING METHOD THEREOF, AND APPLICATION THEREOF - Multiple semiconductor device components and passive device components fixed to a substrate are embedded within an electroconductive-film/insulating-resin-film structure, and are thermally bonded to an insulating resin film. | 05-06-2010 |
| 20110244635 | METHOD FOR MANUFACTURE OF INLINE INTEGRATED CIRCUIT SYSTEM - A method for manufacture of an integrated circuit package system includes: providing a leadframe with an integrated circuit mounted thereover; encapsulating the integrated circuit with an encapsulation; mounting an etch barrier below the leadframe; and etching the leadframe. | 10-06-2011 |
| 20110244634 | SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING THE SAME - A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package includes a first package that a first semiconductor chip is mounted on a front side of a first substrate and a redistributed pad including a first redistributed pad electrically connected to the first substrate and a second redistributed pad electrically connected to the first redistributed pad is disposed on the first semiconductor chip and a second package that a second semiconductor chip is mounted on a front side of a second substrate, the second package including a connection member electrically connected to the second redistributed pad. The connection member electrically connected to the redistributed pad electrically connects the first and second packages to each other. | 10-06-2011 |
| 20090311833 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Performing electrolysis plating to a wiring is made possible, aiming at the increasing of pin count of a semiconductor device. Package substrate | 12-17-2009 |
| 20100055846 | SEMICONDUCTOR PACKAGE STRUCTURES - A semiconductor structure includes a plurality of solder structures between a first substrate and a second substrate. A first encapsulation material is substantially around a first one of the solder structures and a second encapsulation material is substantially around a second one of the solder structures. The first one and the second one of the solder structures are near to each other and a gap is between the first encapsulation material and the second encapsulation material. | 03-04-2010 |
| 20110014752 | SUBSTRATE FOR SEMICONDUCTOR DEVICE, RESIN-SEALED SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAID SUBSTRATE FOR SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAID RESIN-SEALED SEMICONDUCTOR DEVICE - A substrate for a semiconductor device includes: a base plate, a plurality of external terminal portions respectively arranged in a plane on the base plate and having external terminal faces respectively facing the base plate; a plurality of internal terminal portions, respectively arranged in the plane on the base plate and having internal terminal faces respectively facing an opposite side to the base plate. The internal terminal portions are connected with the external terminal portions via wiring portions, respectively. A part of the external terminal portions are located on the base plate in a predetermined arrangement area in which a semiconductor element is arranged. | 01-20-2011 |
| 20090215230 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The radiation performance of a resin sealed semiconductor package is enhanced and further the fabrication yield thereof is enhanced. A drain terminal coupled to the back surface drain electrode of a semiconductor chip is exposed at the back surface of an encapsulation resin section. Part of the following portion and terminal is exposed at the top surface of the encapsulation resin section: the first portion of a source terminal coupled to the source pad electrode of the semiconductor chip and a gate terminal coupled to the gate pad electrode of the semiconductor chip. The remaining part of the second portion of the source terminal and the gate terminal is exposed at the back surface of the encapsulation resin section. When this semiconductor device is manufactured, bonding material and a film member are placed between the drain terminal and the semiconductor chip. At the same time, paste-like bonding material and a film member are placed between the source terminal | 08-27-2009 |
| 20100129964 | METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE WITH A BUMP USING A CARRIER - A method of manufacturing a semiconductor package with a bump using a carrier. One embodiment provides forming a bump on a carrier. A gap is formed in the carrier that undercuts the bump. A semiconductor chip is attached to the carrier. The chip is electrically connected to the bump. An encapsulant is deposited into the gap. The carrier is removed from the bump. | 05-27-2010 |
| 20110033986 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR CHIP AND RESIN SEALING PORTION - A method of manufacturing a semiconductor device includes preparing a semiconductor chip having a main surface, forming a conductive portion made from a material having conductivity and malleability on the main surface, arranging the semiconductor chip within a die after the step of forming the conductive portion, the die having an inner surface facing the main surface with a spacing therebetween, and a protruding portion protruding from the inner surface to press the conductive portion, and forming a sealing resin portion having a surface and an opening by filling the die with a resin and then removing the die, the surface facing the main surface, the opening passing through between the conductive portion and the surface. | 02-10-2011 |
| 20100304535 | PACKAGE STRUCTURE OF COMPOUND SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A package structure of a compound semiconductor device comprises a thin film substrate, a die, at least one metal wire and a transparent encapsulation material. The thin film substrate comprises a first conductive film, a second conductive film, and an insulating dielectric material. The die is mounted on the surface of the first conductive film, and is electrically connected to the first conductive film and the second conductive film through the metal wire. The transparent encapsulation material overlays the first conductive film, second conductive film, and die. The surfaces of the first conductive film and second conductive film which is opposite the transparent encapsulation material act as electrodes. The insulating dielectric material is between the first conductive film and second conductive film. | 12-02-2010 |
| 20110212578 | SEMICONDUCTOR DEVICE WITH COPPER WIREBOND SITES AND METHODS OF MAKING SAME - Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a method for fabricating a semiconductor device comprises forming a dielectric layer on an active side of a semiconductor substrate. The dielectric layer has openings aligned with corresponding wirebond sites at the active side of the substrate. The method further includes forming a plurality of wirebond sites located at the openings in the dielectric layer. The wirebond sites are electrically coupled to an integrated circuit in the semiconductor substrate and electrically isolated from each other. Individual wirebond sites are formed by electrolessly depositing nickel into the openings and forming a wirebond film on the nickel without forming a seam between the nickel and the dielectric layer. | 09-01-2011 |
| 20090004784 | METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE FREE OF SUBSTRATE - A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package. | 01-01-2009 |
| 20100003789 | METHOD OF ENCAPSULATING A MICROELECTRONIC DEVICE BY A GETTER MATERIAL - A method of encapsulating a microelectronic device arranged on a substrate, comprising at least the following steps: a) formation of a portion of sacrificial material covering at least one part of the microelectronic device, the volume of which occupies a space intended to form at least one part of a cavity in which the device is intended to be encapsulated; b) deposition of a layer based on at least one getter material, covering at least one part of the portion of sacrificial material; c) formation of at least one orifice through at least the layer of getter material, forming an access to the portion of sacrificial material; d) elimination of the portion of sacrificial material via the orifice, forming the cavity in which the microelectronic device is encapsulated; and e) sealing of the cavity. | 01-07-2010 |
| 20080268578 | Manufacturing method of a semiconductor device - A non-leaded resin-sealed semiconductor device is manufactured by the steps of providing a conductive flat substrate (metal plate) of copper plate or the like, fixing semiconductor elements respectively to predetermined positions on the principal surface of the substrate by an insulating adhesive, electrically connecting electrodes on the surfaces of the semiconductor elements with predetermined partition parts of the substrate separate from the semiconductor elements by conductive wires, forming an insulating resin layer on the principal surface of the substrate to cover the semiconductor elements and wires, selectively removing the substrate from the rear of said substrate to form electrically independent partition parts whereof at least some are external electrode terminals, and selectively removing said resin layer to fragment the device into regions containing the semiconductor elements and the plural partition parts around the semiconductor elements. Thus, there is provided a compact non-leaded semiconductor device having a large number of electrode terminals. | 10-30-2008 |
| 20080268577 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals | 10-30-2008 |
| 20110020985 | Integrated Circuit Package and a Method for Forming an Integrated Circuit Package - A method of forming an integrated circuit package, such as a Flip Chip package, in which a void is provided in the underfill material in the central region of the package between the chip or die and the substrate on which the chip or die is mounted. This reduces delamination of the package as a result of moisture. | 01-27-2011 |
| 20110136299 | LEADFRAME FOR LEADLESS PACKAGE, STRUCTURE AND MANUFACTURING METHOD USING THE SAME - A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins. | 06-09-2011 |
| 20100323478 | METHOD FOR FABRICATING THROUGH-SILICON VIA STRUCTURE - A method for fabricating through-silicon via structure is disclosed. The method includes the steps of: providing a semiconductor substrate; forming at least one semiconductor device on surface of the semiconductor substrate; forming a dielectric layer on the semiconductor device, in which the dielectric layer includes at least one via hole; forming a first conductive layer on the dielectric layer and filling the via hole; performing an etching process to form a through-silicon via in the first conductive layer, the dielectric layer, and the semiconductor substrate; depositing a second conductive layer in the through-silicon via and partially on the first conductive layer; and planarizing a portion of the second conductive layer until reaching the surface of the first conductive layer. | 12-23-2010 |
| 20120309133 | ELECTRONIC COMPONENT MOUNTING METHOD - A method of mounting an electronic component allows bumps to land onto electrodes via thermosetting flux formed of first thermosetting resin containing a first active ingredient, and brings a resin reinforcing member formed of second thermosetting resin containing a second active ingredient into contact with the electronic component at reinforcement sections, and then heats the substrate to form solder junction sections that bond the bumps to the electrodes. At the same time, the method forms resin reinforcement sections that reinforce the solder junction sections from the surroundings. A mixing ratio of the second active ingredient in the resin reinforcing member is set greater than a mixing ratio of the first active ingredient in the thermosetting flux. | 12-06-2012 |
| 20120040499 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE, METHOD FOR ENCAPSULATING SEMICONDUCTOR, AND SOLVENT-BORNE SEMICONDUCTOR ENCAPSULATING EPOXY RESIN COMPOSITION - Disclosed is a novel method for manufacturing a semiconductor package, which can suppress the formation of voids in an encapsulating resin. Specifically disclosed is a method for manufacturing a semiconductor package, which comprises: (1) a step wherein a first member, which is selected from a group consisting of semiconductor chips and circuit boards, is coated with solvent borne semiconductor encapsulating epoxy resin composition that essentially contains (A) an epoxy resin, (B) a phenol novolac resin in such an amount that the mole number of phenolic hydroxyl groups is 0.8-1.2 times the mole number of epoxy groups in the component (A), (C) a curing accelerator and (D) a solvent: (2) a step wherein the coated composition is dried by volatilizing the solvent therefrom; and (3) a step wherein the first member and a second member, which is selected from a group consisting of semiconductor chips and circuit boards to form, together with the first member, a semiconductor chip/circuit board pair or a semiconductor chip/semiconductor chip pair, are thermally compression bonded with each other with the coated and dried composition interposed therebetween. | 02-16-2012 |
| 20110318885 | Thermally and Electrically Enhanced Ball Grid Array Package - In one embodiment, a method for assembling a ball grid array (BGA) package is provided. The method includes providing a stiffener that has opposing first and second surfaces, wherein the first surface is capable of mounting an integrated circuit (IC) die in a central area and forming a pattern in at least a portion of the first surface to enhance the adhesiveness of an encapsulant material to the first surface. | 12-29-2011 |
| 20120208325 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Manufacturing a semiconductor package includes preparing a semiconductor chip having a top surface with bumps electrically connected to bonding pads, a bottom surface opposite to the top surface and side surfaces joining the top surface to the bottom surface. The bottom surface of the semiconductor chip is attached to a base substrate. A heat pressure process is performed to form a wiring support member on the base substrate to cover the top surface and the side surfaces of the semiconductor chip while exposing each of the bumps. Wirings are formed to be electrically connected to the bumps on the wiring support member. The base substrate is removed from the semiconductor chip and the wiring support member. | 08-16-2012 |
| 20100112761 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME - A semiconductor device is disclosed wherein first wiring lines in a first row extend respectively from first connecting portions toward one side of a semiconductor chip, while second wiring lines extend respectively from second connecting portions toward the side opposite to the one side of the semiconductor chip. The reduction in size of the semiconductor device can be attained. | 05-06-2010 |
| 20120252169 | REDISTRIBUTED CHIP PACKAGING WITH THERMAL CONTACT TO DEVICE BACKSIDE - An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board. | 10-04-2012 |
| 20120252168 | Copper Post Solder Bumps on Substrate - A method comprises forming semiconductor flip chip interconnects where the flip chip comprises a wafer and a substrate having electrical connecting pads and electrically conductive posts operatively associated with the pads and extending away from the pads to terminate in distal ends. Solder bumping the distal ends by injection molding solder onto the distal ends produces a solder bumped substrate. Another embodiment comprises providing the substrate having the posts on the pads with a mask having a plurality of through hole reservoirs and aligning the reservoirs in the mask to be substantially concentric with the distal ends. This is followed by injecting liquid solder into the reservoirs to provide a volume of liquid solder on the distal ends, cooling the liquid solder in the reservoirs to solidify the solder, removing the mask to expose the solidified solder after the cooling and thereby provide a solder bumped substrate. This is followed by positioning the solder bumped substrate on a wafer in a manner that leaves a gap between the wafer and the substrate. The wafer has electrically conductive sites on the surface for soldering to the posts. Abutting the sites and the solder bumped posts followed by heating the solder to its liquidus temperature joins the wafer and substrate, after which, the gap is optionally filled with a material comprising an underfill. | 10-04-2012 |
| 20100093134 | SEMICONDUCTOR PACKAGE HAVING INSULATED METAL SUBSTRATE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor package in which an adhesion force between an insulation metal substrate and a molding member is increased by removing a solder mask layer from the insulation metal substrate and a method of fabricating the semiconductor package. The semiconductor package includes an insulation metal substrate that includes a base member, an insulating layer disposed on the base member, and conductive patterns formed on the insulating layer. Semiconductor chips are arranged on the conductive patterns. Solder mask patterns are arranged on the conductive patterns to surround the semiconductor chips. Leads are electrically connected to the conductive patterns through wires. A sealing member is arranged on an upper surface and side surfaces of the substrate to cover portions of the leads, the wires, the semiconductor chips, and the solder mask patterns. | 04-15-2010 |
| 20100210073 | Method for Encapsulating a Device in a Microcavity - Manufacturing a semiconductor device involves forming ( | 08-19-2010 |
| 20120077317 | MULTILAYERED PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME - A multilayered printed circuit board or a substrate for mounting a semiconductor device includes a semiconductor device, a first resin insulating layer accommodating the semiconductor device, a second resin insulating layer provided on the first resin insulating layer, a conductor circuit provided on the second resin insulating layer, and via holes for electrically connecting the semiconductor device to the conductor circuit, wherein the semiconductor device is accommodated in a recess provided in the first resin insulating layer, and a metal layer for placing the semiconductor device is provided on the bottom face of the recess. A multilayered printed circuit board in which the installed semiconductor device establishes electrical connection through the via holes is provided. | 03-29-2012 |
| 20120220081 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE STRUCTURE - A method of fabricating a semiconductor package structure is provided that includes: providing a chip having an active surface and a plurality of conductive bumps formed on the active surface, and a base substrate having an underfill layer formed on a surface thereof; attaching the active surface of the chip to the underfill layer, such that the conductive bumps are embedded in the underfill layer; removing the base substrate to expose the underfill layer; and attaching the chip to a package substrate via the underfill layer, such that the chip is electrically connected to the package substrate by the conductive bumps. Since the underfill layer is attached to the active surface of the chip first, and the underfill layer is provided on the package substrate, performing a soldering process is not needed, material cost is decreased, and the fabrication process is simplified. | 08-30-2012 |
| 20120220082 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - Semiconductor packages and methods of forming a semiconductor package are disclosed. The method includes providing at least one die having first and second surfaces. The second surface of the die includes a plurality of conductive pads. A permanent carrier is provided and the at least one die is attached to the permanent carrier. The first surface of the at least one die is facing the permanent carrier. A cap having first and second surfaces is formed to encapsulate the at least one die. The first surface of the cap contacts the permanent carrier and the second surface of the cap is disposed at a different plane than the second surface of the die. | 08-30-2012 |
| 20100291739 | DICING DIE BONDING FILM AND DICING METHOD - The present invention relates to a dicing die bonding film, which is able to maintain good workability and reliability in any semiconductor packaging process, such as adhesive property, gap filling property and pick-up property, while controlling burr incidence in a dicing process and thus contamination of die, and a dicing method. Specifically, the present invention is characterized by optimizing tensile characteristics of the dicing die bonding film, or carrying out the dicing on the parts of the die bonding film in the dicing process and separating it through an expanding process. Therefore, the present invention may regulate physical properties of films so as to have the maximized adhesive property, pick-up property and gap filling property without any specific restriction, while controlling burr incidence in the dicing process and contamination of die. As a result, workability and reliability in a packaging process may be excellently maintained. | 11-18-2010 |
| 20110003439 | SEMICONDUCTOR DEVICE PACKAGE HAVING FEATURES FORMED BY ELECTROPLATING - Embodiments in accordance with the present invention relate to the fabrication of packages for semiconductor devices, and in particular to the use of electroplating techniques to form features on the surface of a metal lead frame. In accordance with one embodiment, electroplating is used to fabricate non-integral pin portions shaped to remain securely encapsulated within the plastic molding of the package. In accordance with another embodiment, electroplating may be used to fabricate protrusions on the underside of the lead frame for elevating the package above the PC board, thereby preserving the rounded shape of solder balls used to secure the diepad to the PC board. In accordance with yet another embodiment, electroplating may be used to fabricate raised patterns on the upper surface of the diepad for ensuring uniform spreading of adhesive used to secure the die to the diepad, thereby ensuring level attitude of the die within the package. | 01-06-2011 |
| 20120238060 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device, includes mounting a semiconductor chip on a wiring substrate such that one surface of the semiconductor chip is faced to one surface of the wiring substrate, and filling a first resin in a gap between the surface of the wiring substrate and the surface of the semiconductor chip such that part of the first resin protrudes from the gap. In the filling of the first resin, the first resin is injected into the gap by use of a first resin injection nozzle while the first resin injection nozzle is being moved along any one of sides of the semiconductor chip or along two sides of the semiconductor chip which are adjacent to each other. | 09-20-2012 |
| 20100203684 | SEMICONDUCTOR PACKAGE FORMED WITHIN AN ENCAPSULATION - Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns. | 08-12-2010 |
| 20120094444 | Semiconductor Package Having Semiconductor Die with Internal Vertical Interconnect Structure and Method Therefor - A semiconductor wafer is made by forming a first conductive layer over a sacrificial substrate, mounting a semiconductor die to the sacrificial substrate, depositing an insulating layer over the semiconductor die and first conductive layer, exposing the first conductive layer and contact pad on the semiconductor die, forming a second conductive layer over the insulating layer between the first conductive layer and contact pad, forming solder bumps on the second conductive layer, depositing an encapsulant over the semiconductor die, first conductive layer, and interconnect structure, and removing the sacrificial substrate after forming the encapsulant to expose the conductive layer and semiconductor die. A portion of the encapsulant is removed to expose a portion of the solder bumps. The solder bumps are sized so that each extends the same outside the encapsulant. The semiconductor die are stacked by electrically connecting the solder bumps. | 04-19-2012 |
| 20120282738 | CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a circuit structure is provided. A metal layer having an upper surface is provided. A surface passivation layer is formed on the metal layer. The surface passivation layer exposes a portion of the upper surface of the metal layer, and a material of the metal layer is different from a material of the surface passivation layer. The metal layer and the surface passivation layer are dipped into a modifier, and the modifier is selectively absorbed and attached to the surface passivation layer, so as to form a covering layer. The covering layer has a plurality of nanoparticles and covers the surface passivation layer. | 11-08-2012 |
| 20100167469 | RESIN SEALING METHOD OF SEMICONDUCTOR DEVICE - A resin sealing method of a semiconductor device, is provided with: providing a semiconductor device on which a dummy dump is formed; providing a support body including an adhesive layer provided on a surface of the support body; forming a recess in the adhesive layer; inserting the dummy bump of the semiconductor device into the recess of the adhesive layer; adhering the semiconductor device to the adhesive layer with the semiconductor device positioned on the support body; setting the supporting body having the semiconductor device in a resin sealing mold; supplying a resin into a cavity of the resin sealing mold; sealing the semiconductor device with the resin on the support body while using the dummy bump to inhibit displacement of the semiconductor device caused by a flow of the resin supplied into the cavity of the resin sealing mold; and removing the support body, the adhesive layer, and the dummy bump from the semiconductor device sealed with the resin. | 07-01-2010 |
| 20100167470 | POWER MODULE FOR LOW THERMAL RESISTANCE AND METHOD OF FABRICATING THE SAME - A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented. | 07-01-2010 |
| 20110159643 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE STRUCTURE - A fabrication method of a semiconductor package structure includes: patterning a metal plate having first and second surfaces; forming a dielectric layer on the metal plate; forming a metal layer on the first surface and the dielectric layer; forming metal pads on the second surface, the metal layer having a die pad and traces each having a bond pad; mounting a semiconductor chip on the die pad, followed by connecting electrically the semiconductor chip to the bond pads through bonding wires; forming an encapsulant to cover the semiconductor chip and the metal layer; removing portions of the metal plate not covered by the metal pads so as to form metal pillars; and performing a singulation process. The fabrication method is characterized by disposing traces with bond pads close to the die pad to shorten the bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging. | 06-30-2011 |
