| Entries |
| Document | Title | Date |
|---|
| 20110201159 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package | 08-18-2011 |
| 20130034937 | Exposed Die Package for Direct Surface Mounting - A method of forming an electronic assembly includes attaching a backside metal layer the bottomside of a semiconductor die. An area of the backside metal layer matches an area of the bottomside of the die. A die pad and leads are encapsulated within the molding material. The leads include an exposed portion that includes a bonding portion. A gap exposes the backside metal layer along a bottom surface of the package. Bond wires couple the pads on the topside of the die to the leads and the bonding portions. Packaged semiconductor device is soldered to a printed circuit board (PCB). The backside metal layer and the bonding portions of the leads are soldered substrate pads on said PCB. | 02-07-2013 |
| 20120208323 | Method for Mounting a Semiconductor Chip on a Carrier - A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 μm. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm | 08-16-2012 |
| 20130045573 | CHIP ON LEADS - Described herein are microelectronic packages including a plurality of bonding fingers and multiple integrated circuit chips, at least one integrated circuit chip being mounted onto the bonding fingers. According to various embodiments of the present invention, mounting the integrated circuit chip onto the bonding fingers may reduce the pin-out count by allowing multiple integrated circuit chips to be interconnected within the same microelectronic package. Other embodiments may be described and claimed. | 02-21-2013 |
| 20130115737 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH OUTER LEADS HAVING A LEAD-FREE PLATING - A semiconductor device has a tab having a semiconductor chip fixed thereto, a plurality of inner leads, a plurality of outer leads formed integrally with the inner leads, a plurality of wires coupling the electrode pads of the semiconductor chip to the inner leads, and a molded body having the semiconductor chip molded therein. Over a surface of each of the outer leads protruding from the molded body, an outer plating including lead-free platings is formed. The outer plating has, in a thickness direction thereof, a first lead-free plating and a second lead-free plating, the first and second lead-free platings having the same composition and meeting at an interface. The first and second lead-free platings are formed under different conditions and may have different physical properties. | 05-09-2013 |
| 20130071971 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided. | 03-21-2013 |
| 20090269889 | Apparatus for Manufacturing Semiconductor Package for Wide Lead Frame and Method of Constructing Semiconductor Package Using the Same - An apparatus for manufacturing a semiconductor package includes an index rail transferring a lead frame in forward and backward directions, the lead frame having a first surface and a second surface that is opposite to the first surface, a loader portion connected to an end portion of the index rail and supplying the lead frame to the index rail, a frame driving portion connected to the opposite end portion of the end portion of the index rail and rotating the lead frame around a normal to the first surface, and a wire bonding portion electrically connecting the lead frame and a semiconductor chip attached to the lead frame supplied to the index rail using a wire bond. | 10-29-2009 |
| 20090233403 | DUAL FLAT NON-LEADED SEMICONDUCTOR PACKAGE - A DFN semiconductor package includes a leadframe having a die bonding pad formed integrally with a drain lead, a gate lead and a source lead, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead and a die gate bonding area coupled to the gate lead, and an encapsulant at least partially covering the die, drain lead, gate lead and source lead. | 09-17-2009 |
| 20090011548 | HYBRID INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a hybrid integrated circuit device of the present invention includes the steps of preparing a lead frame which constituted by units each having a plurality of leads, and fixing a circuit substrate on each unit of the lead frame by fixing pads which are formed on the surface of the circuit substrate to the leads, where a space between a first pad which is formed at an end edge of the circuit substrate and a second pad which is adjacent to the first pad is set narrower than a space between the pads themselves. | 01-08-2009 |
| 20110300671 | LEADFRAME-BASED SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A leadframe-based semiconductor package and a fabrication method thereof are provided. The leadframe-based semiconductor package includes a chip implanted with a plurality of first and second conductive bumps thereon, and a leadframe having a plurality of leads. The first conductive bumps are bonded to the leads to electrically connect the chip to the leadframe. The chip, the first and second conductive bumps, and the leadframe are encapsulated by an encapsulant, with bottom ends of the second conductive bumps and bottom surfaces of the leads being exposed from the encapsulant. This allows the second conductive bumps to provide additional input/output electrical connections for the chip besides the leads. | 12-08-2011 |
| 20120108013 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In QFN packages for vehicles which are required to have high reliability, the side surface of leads is mostly covered with lead-to-lead resin protrusions, which prevent smooth formation of solder fillets during reflow mounting. When the lead-to-lead protrusions are mechanically removed using a punching die, there is a high possibility of causing cracks of the main body of the package or terminal deformation. When a spacing is provided between the punching die and the main body of the package in order to avoid such damages, a resin residue is produced to hinder complete removal of this lead-to-lead resin protrusion. The present invention provides a method for manufacturing semiconductor device of a QFN type package using multiple leadframes having a dam bar for tying external end portions of a plurality of leads. This method includes a step of removing a sealing resin filled between the circumference of a mold cavity and the dam bar by using laser and then carrying out surface treatment, for example, solder plating. | 05-03-2012 |
| 20080268576 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device improved in packaging reliability is disclosed. Each of leads used in the semiconductor device has a first surface positioned between a main surface of a resin sealing body and a back surface opposite to the main surface of the resin sealing body, a second surface positioned on the side opposite to the first surface and exposed from the back surface of the resin sealing body, a first end face positioned on a semiconductor chip side, a second end face positioned on the side opposite to the first end face and exposed from a side face of the resin sealing body, and a recessed portion depressed from the second surface to the first surface side and contiguous to the second end face, the second surface and an inner wall surface of the recessed portion being covered with a plating layer which is higher in solder wettability than the second end face of each of the leads. | 10-30-2008 |
| 20100055844 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device, which is capable of easily removing a sealing sheet building up terminal surfaces of leads, includes arranging, on molds, terminal surfaces of leads in a lead frame on which semiconductor elements are mounted so as to come in contact with a sealing sheet, pouring a resin into the molds to form a resin sealed body including the semiconductor elements, and cleaning the resin sealed body, and the cleaning of the resin sealed body ravels the sealing sheet by a cleaning solvent and removes the sealing sheet. | 03-04-2010 |
| 20120034742 | SEMICONDUCTOR DEVICE - To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire. | 02-09-2012 |
| 20090263937 | LEADFRAME PACKAGE FOR MEMS MICROPHONE ASSEMBLY - A cavity semiconductor package has a pre-molded leadframe construction. The leadframe is formed by molding around a die pad, and plural terminal lands. The leadframe has a hole for an acoustic port, such that the package can be soldered on a back side of a printed circuit board and have air access to a sensor die in the package from a front side of the printed circuit board via the acoustic port. The leadframe may also have a hollow or concave recess that defines an acoustic cavity in conjunction with the sensor die or printed circuit board. | 10-22-2009 |
| 20090093090 | METHOD FOR PRODUCING A POWER SEMICONDUCTOR MODULE COMPRISING SURFACE-MOUNTABLE FLAT EXTERNAL CONTACTS - A method for producing a power semiconductor module having surface mountable flat external contact areas is disclosed. At least one power semiconductor chip is fixed by its rear side on a drain external contact. An insulation layer covers the top side over the side edges of the semiconductor chip as far as the inner housing plane was a leaving free the source and gate contact areas on the top side of the semiconductor chip and also was partly leaving free the top sides of the corresponding external contacts. | 04-09-2009 |
| 20090093091 | Method of fabricating semiconductor package - A semiconductor package of this invention achieves higher wiring densities and increases the degree of freedom of the wiring design. The semiconductor package includes a first substrate having first and second faces, and first wiring provided on the first face of the first substrate. The semiconductor package also includes a second substrate having first and second faces, and second wiring provided on the first face of the second substrate. The semiconductor package also includes a semiconductor chip connected to the first and second wiring. The first face of the first substrate faces the first face of the second substrate, and the first and second wiring intersect one another in three dimensions in an isolated state. | 04-09-2009 |
| 20110201158 | Selective Removal of Gold From a Lead Frame - A method of packaging an integrated circuit, including providing a lead frame having lead fingers, where the lead frame has a gold layer thereon on a top surface and a bottom surface. An integrated circuit die is attached to the lead frame. The gold layer is substantially removed from portions of the top surface of the lead frame. The integrated circuit die is wire bonded to the lead fingers with a plurality of wire stitches subsequent to substantially removing the gold. The die is encapsulated in a mold compound to form a packaged integrated circuit. | 08-18-2011 |
| 20100279470 | PACKAGE WITH MULTIPLE DIES - A semiconductor die package is disclosed. It includes a leadframe structure comprising a first die attach pad and a second die attach pad. A plurality of leads extend from the first and second die attach pads. The plurality of leads includes at least a first control lead and a second control lead. A first semiconductor die including a first device is mounted on the first die attach pad, and a second semiconductor die has a second device is mounted on the second die attach pad. A housing is provided in the semiconductor die package and protects the first and second dies. The housing may have an exterior surface and at least partially covers the first semiconductor die and the second semiconductor die. The first control lead and the second control lead are at opposite sides of the semiconductor die package. | 11-04-2010 |
| 20100136750 | Etched Leadframe Structure - A leadframe structure is disclosed. The leadframe structure includes a first leadframe structure portion with a first thin portion and a first thick portion, where the first thin portion is defined in part by a first recess. It also includes a second leadframe structure portion with a second thin portion and a second thick portion, where the second thin portion is defined in part by a second recess. The first thin portion faces the second recess, and the second thin portion faces the first recess. | 06-03-2010 |
| 20080311705 | Lead frame and method for fabricating semiconductor package employing the same - A lead frame and a method of fabricating a semiconductor package including the lead frame, where the lead frame includes a die pad, a tie bar supporting the die pad, and a plurality of leads. The leads may include inner and outer leads arranged along an outer periphery of the die pad, with each of the inner and outer leads having tip terminals. The lead frame may include a connecting bar connected to tip terminals of each of the inner leads. In the method, a bonding pad of a semiconductor chip is mounted on the die pad and connected via a conductive wire to the inner leads of the lead frame. The semiconductor chip, wire and inner leads may be subjected to a molding process, and the connecting bar which connects the tip terminals of the inner leads may be cut so as to independently separate each of the inner leads from the die pad. | 12-18-2008 |
| 20080293190 | Semiconductor package, method for fabricating the same, and semiconductor device - A semiconductor device includes a semiconductor chip, leads for sending and receiving signals between the semiconductor chip and an external device, fine metal wires, an encapsulant for sealing the leads, and a lid member. On the surface of each of the leads, a metal oxide film is formed by an oxidation treatment. The metal oxide film has a thickness larger than a natural oxide film and no more than 80 nm. | 11-27-2008 |
| 20100136749 | MICROARRAY PACKAGE WITH PLATED CONTACT PEDESTALS - A microarray package includes a leadframe having an array of contact posts, a die carried by the lead frame, and a plurality of bonding wires that electrically connect the die to the lead frame. An encapsulant is included that encapsulates the die, the bonding wire and the leadframe while leaving the distal ends of the contact posts exposed and substantially co-planar with a bottom surface of the microarray package. A plurality of pedestal members is plated to the distal end of a respective contact pad. A distal surface of each pedestal member protrudes outwardly beyond the bottom surface of the microarray package in the range of about 15 μm to about 35 μm. | 06-03-2010 |
| 20090087953 | Manufacturing process of leadframe-based BGA packages - A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed. | 04-02-2009 |
| 20090117690 | INTEGRATED TRANSISTOR MODULE AND METHOD OF FABRICATING SAME - An integrated transistor module includes a lead frame that defines at least one low-side land and at least one high-side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low-side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land. A high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land. | 05-07-2009 |
| 20090162976 | Method of manufacturing pins of miniaturization chip module - A method of manufacturing a miniaturization chip module includes steps of providing a chip module having a substrate, wherein the substrate has a plurality of bonding pads spaced on a rear surface of substrate; providing a lead frame including a plurality of spaced metallic studs, wherein the metallic studs are attached onto the bonding pads; and forming metallic blocks as I/O pins by removing a part of each metallic stud and a part of the lead frame which is not in contact with the substrate. | 06-25-2009 |
| 20090004782 | METHOD OF FABRICATING A TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE - A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe. | 01-01-2009 |
| 20110223719 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A wire short-circuit defect during molding is prevented. A semiconductor device has a tab, a plurality of leads arranged around the tab, a semiconductor chip mounted over the tab, a plurality of wires electrically connecting the electrode pads of the semiconductor chip with the leads, and a molded body in which the semiconductor chip is resin molded. By further stepwise shortening the chip-side tip end portions of the leads as the first edge or side of the principal surface of the semiconductor chip goes away from the middle portion toward the both end portions thereof, and shortening the tip end portions of those of first leads corresponding to the middle portion of the first edge or side of the principal surface which are adjacent to second leads located closer to the both end portions of the first edge or side, the distances between second wires connected to the second leads and the tip end portions of the first leads adjacent to the second leads can be increased. As a result, it is possible to prevent the wire short-circuit defect even when wire sweep occurs due to the flow resistance of a mold resin. | 09-15-2011 |
| 20080233684 | MICROELECTRONIC COMPONENT ASSEMBLIES EMPLOYING LEAD FRAMES HAVING REDUCED-THICKNESS INNER LENGTHS - The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, at least two leads, and at least two bond wires. Each of the leads may have a reduced-thickness inner length adjacent terminals of the microelectronic component and a body having an outer surface spaced farther from the microelectronic component than a bond surface of the inner length. Each of the bond wires couples the microelectronic component to one of the leads and has a maximum height outwardly from the microelectronic component that is no greater than the height of the outer surface of the lead. | 09-25-2008 |
| 20120196405 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprises: preparing a lead frame including a package external region and a package internal region, a burred surface being provided at a top end of a side of the lead frame, and a fracture surface being provided in the vicinity of the top end of the side; chamfering the top end of the side in the package external region; mounting a semiconductor element on the lead frame and sealing the semiconductor element with mold resin in the package internal region; and removing resin burr provided on the side of the lead frame in the package external region after the chamfering and the sealing. | 08-02-2012 |
| 20100261316 | SEMICONDUCTOR DEVICE WITH SURFACE MOUNTING TERMINALS - A semiconductor device has a sealing body formed of an insulating resin and a semiconductor chip positioned within the sealing body. A gate electrode and a source electrode are on a first main surface of the semiconductor chip and a back electrode (drain electrode) is on a second main surface thereof. An upper surface of a portion of a drain electrode plate that projects in a gull wing shape is exposed from the sealing body and a lower surface thereof is connected to the back electrode through an adhesive. A gate electrode plate projects in a gull wing shape on an opposite end side of the sealing body and is connected to the gate electrode within the sealing body. A source electrode plate projects in a gull wing shape on the opposite end side of the sealing body and is connected to the source electrode within the sealing body. | 10-14-2010 |
| 20110059582 | MOLDED ULTRA THIN SEMICONDUCTOR DIE PACKAGES, SYSTEMS USING THE SAME, AND METHODS OF MAKING THE SAME - Disclosed are molded ultra-thin semiconductor die packages, systems that incorporate such packages, and methods of making such packages. An exemplary package comprises a leadframe having an aperture formed between the leadframe's first and second surfaces, and a plurality of leads disposed adjacent to the aperture. The package further comprises a semiconductor disposed in the aperture of the leadframe with its top surface substantially flush with the leadframe's first surface, and at least one gap between at least one side surface of the semiconductor die and at least one lead of the leadframe. A body of electrically insulating material is disposed in the at least one gap. A plurality of conductive members interconnect leads of the leadframe with conductive regions on the die's top surface, with at least one conductive member having a portion disposed over at least a portion of the body of insulating material. | 03-10-2011 |
| 20110059581 | Method for manufacturing semiconductor module - A method for manufacturing a semiconductor module, includes the steps of preparing a board; mounting a semiconductor device on the second metal foil; placing a resin case onto the board for surrounding a first metal foil, an insulating sheet, the second metal foil, and the semiconductor device; pouring a resin in a paste form into the case to fill a space relative to the first metal foil, insulating sheet, the second metal foil and the semiconductor device; and heat-curing the resin. A bottom end of a peripheral wall of the case is located above a bottom surface of the first metal. The bottom surface of the first metal foil and the resin form a flat bottom surface to contact an external mounting member. | 03-10-2011 |
| 20100216283 | ELECTRONIC DEVICE AND LEAD FRAME - A lead frame facilitates the handling, positioning, attachment, and/or continued integrity of multiple dies, without the use of multiple separate parts, such as jumpers. The lead frame includes a number of structures, each of which is attached to at least one lead. At least one receiving surface, arranged to receive a die, is associated with each structure. When dies are disposed on the receiving surfaces, anodes are similarly-oriented. A number of fingers are attached to the lead frame, and one or more electrode contact surfaces are attached to each finger. Each electrode contact surface can be positioned (for example, bent) with respect to one receiving surface, to facilitate electrical connection between the anode of a die and a lead. The lead frame may be used in connection with surface- and through-hole-mountable electronic devices, such as bridge rectifier modules. | 08-26-2010 |
| 20100227436 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE WITH MOLD LOCK OPENING - A method of fabricating a semiconductor package. In one embodiment the method includes forming a mold cavity about a portion of a first major surface of a leadframe, including about a mold lock opening extending through the leadframe between the first major surface and a second major surface. A spacer is inserted to fill at least a portion of the mold lock opening. The mold cavity is filled with an encapsulating material including filling a portion of the mold lock opening not occupied by the spacer. | 09-09-2010 |
| 20080305586 | METHOD OF MANUACTURING A SEMICONDUCTOR DEVICE - According to the method of manufacturing a semiconductor device, a lead frame is provided wherein the thickness of a tab-side end portion of a silver plating for wire connection formed on each suspending lead | 12-11-2008 |
| 20120270370 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A disclosed semiconductor device includes a wiring board, a semiconductor element mounted on a principal surface of the wiring board with flip chip mounting, a first conductive pattern formed on the principal surface along at least an edge portion of the semiconductor element, a second conductive pattern formed on the principal surface along the first conductive pattern and away from the first conductive pattern, a passive element bridging between the first conductive pattern and the second conductive pattern on the principal surface of the wiring board, and a resin layer filling a space between the wiring board and the semiconductor chip, wherein the resin layer extends between the semiconductor element and the first conductive pattern on the principal surface of the wiring board. | 10-25-2012 |
| 20110008936 | Semiconductor Device Having Grooved Leads to Confine Solder Wicking - A packaged surface-mount semiconductor device has the outer, un-encapsulated lead segments structured in five adjoining portions: The first portion protrudes from the encapsulation about horizontally; the second portion forms a convex bend downwardly; the third portion is approximately straight downwardly; the fourth portion forms a concave bend upwardly; and the fifth portion is straight horizontally. Each segment has across the width a first groove in the third portion, either on the bottom surface or on the top surface. Preferably, the groove is about 2 leadframe thicknesses vertically over the bottom surface of the fifth lead portion. When stamped, the groove may have an angular outline about 5 and 50 μm deep; when etched, the groove may have an approximately semicircular outline about 50 to 125 μm deep. A second groove may be located in the second segment portion; a third groove may be located in the transition region from the third to the fourth segment portions. | 01-13-2011 |
| 20100178734 | Leadless Semiconductor Package with Electroplated Layer Embedded in Encapsulant and the Method for Manufacturing the Same - A leadless semiconductor package with an electroplated layer embedded in an encapsulant and its manufacturing processes are disclosed. The package primarily includes a half-etched leadframe, a chip, an encapsulant, and an electroplated layer. The half-etched leadframe has a plurality of leads and a plurality of outer pads integrally connected to the leads. The encapsulant encapsulates the chip and the leads and has a plurality of cavities reaching to the outer pads to form an electroplated layer on the outer pads and embedded in the cavities. Accordingly, under the advantages of lower cost and higher thermal dissipation, the conventional substrates and their solder masks for BGA (Ball Grid Array) or LGA (Land Grid Array) packages can be replaced. The leads encapsulated in the encapsulant have a better bonding strength and the electroplated layer embedded in the encapsulant will not be damaged during shipping, handling, or storing the semiconductor packages. Furthermore, the manufacturing processes include two half-etching steps to form the half-etched leadframe where a second half-etching step is performed after forming the encapsulant and before forming the electroplated layer. | 07-15-2010 |
| 20110033984 | MOLD CLEANING SHEET AND METHOD OF PRODUCING SEMICONDUCTOR DEVICES USING THE SAME - A cleaning sheet ( | 02-10-2011 |
| 20110117704 | CIRCUIT MEMBER, MANUFACTURING METHOD OF THE CIRCUIT MEMBER, AND SEMICONDUCTOR DEVICE INCLUDING THE CIRCUIT MEMBER - A circuit member includes a lead frame material having a die pad, a lead part to be electrically connected with a semiconductor chip, and an outer frame configured to support the die pad and the lead part. The lead frame material includes a resin sealing region. Roughened faces | 05-19-2011 |
| 20120244665 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: forming a first layer including crystals by processing a surface of a first electrode of a semiconductor element; forming a second layer including crystals by processing a surface of a second electrode of a mounting member on which the semiconductor element is mounted; reducing a first oxide film present over or in the first layer and a second oxide film present over or in the second layer at a first temperature, the first temperature being lower than a second temperature at which a first metal included in the first electrode diffuses in a solid state and being lower than a third temperature at which a second metal included in the second electrode diffuses in a solid state; and bonding the first layer and the second layer to each other by solid-phase diffusion. | 09-27-2012 |
| 20090311832 | Flex Chip Connector For Semiconductor Device - A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It also includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure. | 12-17-2009 |
| 20100062570 | LEADFRAME SURFACE WITH SELECTIVE ADHESION PROMOTER APPLIED WITH AN OFFSET GRAVURE PRINTING PROCESS FOR IMPROVED MOLD COMPOUND AND DIE ATTACH ADHESIVE ADHESION - Placement of an encapsulation material adhesion promoter onto a semiconductor device leadframe can be performed through the use of an offset printing apparatus such as a rotogravure printing apparatus or a tampoprint printing apparatus. This can provide accurate and low-cost placement of the adhesion promoter. | 03-11-2010 |
| 20100062571 | MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a device includes a support member and a flexed microelectronic die mounted to the support member. The flexed microelectronic die has a plurality of terminals electrically coupled to the support member and an integrated circuit operably coupled to the terminals. The die can be a processor, memory, imager, or other suitable die. The support member can be a lead frame, a plurality of electrically conductive leads, and/or an interposer substrate. | 03-11-2010 |
| 20110177657 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized. | 07-21-2011 |
| 20100055845 | POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - A power semiconductor module and a method of manufacture thereof includes lead a frame carrying lead having inner and outer lead portions. The outer lead portions, which are connected by soldering to semiconductor chips simultaneously, eliminate the need for using bonding wires. Since no bonding wire is used for connecting the leads and the semiconductor chips, a sufficient current capacity is obtained. The bonding between an insulating circuit board and the semiconductor chips and the bonding between the semiconductor chips and the leads can be made simultaneously in a single step of reflow-soldering. As a result, the mounting time can be shortened and the power semiconductor module can be manufactured more efficiently. | 03-04-2010 |
| 20110097854 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING ELECTRONIC DEVICE - Foreign matter formed over (or adhered to) a surface of a lead is reliably removed. A laser beam is applied to a residual resin (sealing body) which is formed in (or adhered to) a region surrounded by a sealing body (a first sealing body), a lead exposed (projected) from the sealing body, and a dam bar. The foreign matter formed over (or adhered to) the surface of the lead can be reliably removed by washing the surface of the lead after the removal of the residual resin. Thus, in a subsequent plating step, the reliability (wettability, adhesion with the lead) of a plating film to be formed over the surface of the lead can be improved. | 04-28-2011 |
| 20110097855 | SEMICONDUCTOR DEVICE - A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier. | 04-28-2011 |
| 20110081750 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES - The reliability of a semiconductor device is enhanced. A first lead frame, a first semiconductor chip, a second lead frame, and a second semiconductor chip are stacked over an assembly jig in this order with solder in between and solder reflow processing is carried out to fabricate their assembly. Thereafter, this assembly is sandwiched between first and second molding dies to form an encapsulation resin portion. The upper surface of the second die is provided with steps. At a molding step, the second lead frame is clamped between the first and second dies at a position higher than the first lead frame; and a third lead frame is clamped between the first and second dies at a higher position. The assembly jig is provided with steps at the same positions as those of the steps in the upper surface of the second die in positions corresponding to those of the same. | 04-07-2011 |
| 20100304534 | METHOD FOR CONNECTING A DIE ATTACH PAD TO A LEAD FRAME AND PRODUCT THEREOF - Disclosed in this specification is a semiconductor package with a die attach pad and a lead frame which are electrically and mechanically connected to one another through a conductive wire ribbon. Such a configuration reduces the package footprint and also permits different styles of die attach pads and lead frames to be interchanged, thus reducing production costs. | 12-02-2010 |
| 20120276693 | Module Comprising a Semiconductor Chip - A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element. | 11-01-2012 |
| 20120276692 | Method for Assemblying a Semiconductor Chip Package with Deflection-Resistant Leadfingers - Embodiments of the invention relate to methods for semiconductor chip package assembly. An embodiment of the invention includes providing a metallic leadframe with a chip mounting surface and a plurality of leadfingers. The leadfingers have a proximal end for receiving one or more wirebonds and a distal end for providing an electrical path from the proximal end. One or more of the leadfingers also has an offset portion and underlying heat spreader, increasing the stiffness of the leadfinger, and increasing leadfinger deflection-resistance and spring-back. The offset is in the direction opposite the plane of a heat spreader thermally coupled to the mounting surface. A semiconductor chip is affixed to the mounting surface and a plurality of bond pads of the chip are wirebonded to the offset portions of the proximal ends of individual leadfingers. The chip, the bondwires, portions of the heat spreader and leadfingers are encapsulated. | 11-01-2012 |
| 20110033985 | Manufacturing Method for Integrating a Shunt Resistor into a Semiconductor Package - An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to the integrated circuit. The shunt resistor has a lower temperature coefficient of resistance than the lead frame, and the lead frame has a lower resistivity than the shunt resistor. The shunt resistor has a low-resistance coupling to external leads of the lead frame, or, the shunt resistor has its own integrated external leads. | 02-10-2011 |
| 20110076806 | Low Cost Lead-Free Preplated Leadframe Having Improved Adhesion and Solderability - A leadframe with a structure made of a base metal ( | 03-31-2011 |
| 20110256670 | METHOD FOR MANUFACTURING INTEGRATED CIRCUIT PACKAGE SYSTEM WITH UNDER PADDLE LEADFINGERS - A method for manufacturing an integrated circuit package system includes: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing a bottom surface of the under paddle leadframe to separate the lower leadfingers under the die paddle. | 10-20-2011 |
| 20110076807 | SELF LOCKING AND ALIGNING CLIP STRUCTURE FOR SEMICONDUCTOR DIE PACKAGE - A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip aligner structure, where the clip aligner structure is cooperatively structured with the lead with the flat surface, and an intermediate portion coupling the contact portion and the clip aligner structure. | 03-31-2011 |
| 20100105174 | SEMICONDUCTOR DEVICE - To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire. | 04-29-2010 |
| 20090176335 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - According to the method of manufacturing a semiconductor device, a lead frame is provided wherein the thickness of a tab-side end portion of a silver plating for wire connection formed on each suspending lead | 07-09-2009 |
| 20090042339 | PACKAGED INTEGRATED CIRCUITS AND METHODS TO FORM A PACKAGED INTEGRATED CIRCUIT - Packaged integrated circuits and methods to form a packaged integrated circuit are disclosed. A disclosed method comprises attaching an integrated circuit to a substrate, coupling a first end of a bond wire directly to the substrate without an intervening bonding pad and a second end of the bond wire to a contact of the integrated circuit, encapsulating the integrated circuit and the bond wire, and removing the substrate to expose the first end of the bond wire. | 02-12-2009 |
| 20090111220 | COATED LEAD FRAME - A lead frame having a coating of organic compounds on its lead fingers prevents tin and flux from contaminating the lead fingers after die attach. The coating is removed prior to wire bonding. The coating allows for reliable second bonds (bond between wires and lead fingers) to be formed, decreasing the likelihood of non-stick and improving wire peel strength. | 04-30-2009 |
| 20110070700 | Apparatus for Connecting Integrated Circuit Chip to Power and Ground Circuits - In a method and system for transferring at least one of power and ground signal between a die and a package base of a semiconductor device, a connector is formed there between. The connector, which is disposed above the die attached to the package base, includes a center pad electrically coupled to the die by a plurality of conductive bumps and a finger extending outward from the center pad towards the package base. The finger is electrically coupled to the package base by a conductive pad. A plurality of bond wires are formed to electrically couple the package base and the die. A resistance of a conductive path via the connector is much less than a resistance of a conductive path via any one of the plurality of bond wires to facilitate an efficient transfer of the at least one of power and ground signal. | 03-24-2011 |
| 20090203173 | MOLD CLEANING SHEET AND MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE USING THE SAME - A cleaning sheet with frame for cleaning a molding die comprising a cleaning heat main body that covers the entire mating surface of a molding die and a reinforcing frame which can be disposed along the peripheral edge to the outside of the plural cavities of the mating surface of the molding die, the cleaning sheet main body being formed with first through holes at positions corresponding to the cavities of the molding die, air vent slits and flow cavity recesses at positions corresponding to the air vents of the cavities, second through holes at positions corresponding to the pots of the molding die, and slits at positions corresponding to the runners of the molding die, thereby capable of improving the cleaning effect of the molding die and shortening the time for the cleaning operation to improve the productivity. | 08-13-2009 |
| 20080233683 | PRE-PLATED LEADFRAME HAVING ENHANCED ENCAPSULATION ADHESION - A process for producing a pre-plated leadframe that has enhanced adhesion by molding compound is provided, wherein a base leadframe material is first plated with multiple layers of metallic material. Thereafter, the plated base leadframe material is covered with a mask, so as to expose selected surfaces thereof at unmasked areas where enhanced adhesion of molding compound is desired. The said unmasked areas are plated with a layer of copper before removing the mask. Optionally, the layer of copper may further be oxidized to form a layer of specially controlled copper oxide. | 09-25-2008 |
| 20100035385 | ALUMINUM BUMP BONDING FOR FINE ALUMINUM WIRE - The invention includes a packaged semiconductor device in which the bond wires are bonded to the leads with an aluminum bump bond. The semiconductor device is mounted on a leadframe having leads with a nickel plating. To form the bump bond between a fine aluminum wire, such as a 2 mil diameter wire, and the lead, an aluminum bump is bonded to the nickel plating and the wire is bonded to the bump. The bump is aluminum doped with nickel and is formed from a large diameter wire, such as a 6 mil diameter wire. | 02-11-2010 |
| 20110143500 | SEMICONDUCTOR CONNECTION COMPONENT - There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire | 06-16-2011 |
| 20090098686 | METHOD OF FORMING PREMOLDED LEAD FRAME - A method of forming a pre-molded lead frame having increased stand-offs includes the steps of attaching a first tape to a first side of the lead frame and a second tape to a second side of the lead frame. The taped lead frame is placed in a mold and a first flow of mold compound is initiated. The first flow of the mold compound fills a space between the first tape and an upper mold chase of the mold. A second flow of the mold compound then is initiated. The second flow of the mold compound fills the spaces between a die pad and leads of the lead frame. The first and second tapes then are removed from the lead frame. Improved stand-offs are provided because the first tape was depressed by the first flow of the mold compound. | 04-16-2009 |
| 20100124801 | ELECTRONIC PACKAGE STRUCTURE AND METHOD - An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken. | 05-20-2010 |
| 20120208324 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In a multichip thin package requiring a thickness of submillimeter region, it is difficult to thin the package if the chips are mounted over a usual die pad. According to a technique of the present application, in a manufacturing method of a semiconductor device of a thin resin sealed multichip rectangular package having wire connection between the chips, at least one chip is fixed to a die pad thinned more than a die pad support lead, the die pad is supported by die pad support leads arranged to respectively connect a pair of long sides of the rectangle, and sealing resin is introduced from one side of the pair of long sides when resin molding is performed. | 08-16-2012 |
| 20120009739 | Metallic Leadframes Having Laser-Treated Surfaces for Improved Adhesion to Polymeric Compounds - A leadframe for the assembly of a semiconductor chip has regions ( | 01-12-2012 |
| 20110165735 | Flexible Interposer for Stacking Semiconductor Chips and Connecting Same to Substrate - A semiconductor device with a first ( | 07-07-2011 |
| 20090317948 | METHOD FOR MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A method is provided for manufacturing a QFN type semiconductor integrated circuit device using a multi-device lead frame having a tie bar for tying external end portions of plural leads, wherein sealing resin filled between an outer periphery of a mold cavity and the tie bar is removed by a laser and thereafter a surface treatment such as solder plating is performed. | 12-24-2009 |
| 20120156832 | ELECTRONIC COMPONENT - An electronic component and method of making an electronic component is disclosed. In one embodiment, the electronic component includes a frame having a base layer, a first layer, a second layer including palladium placed on the first layer, and a third layer including gold placed on the second layer. A semiconductor chip is positioned on the frame. | 06-21-2012 |
| 20110076805 | MOLDED LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE - A process for forming land grid array semiconductor packages includes a leadframe that is supported by a substrate comprising mold compound. In some embodiments, at least one die is electrically coupled to the leadframe by bondwires. The package comprises a second mold compound to act as an encapsulant. An apparatus for forming a land grid array semiconductor package includes means for molding a leadframe, assembling thereon at least one semiconductor device, applying a second mold, and singulating to form individual devices. A land grid array package comprises a leadframe, a substrate for supporting the leadframe, at least one semiconductor device and a mold compound. | 03-31-2011 |
| 20110092028 | Lead frame and method of manufacturing the same - A lead frame includes a base material having a front surface for mounting of a semiconductor chip and a back surface for connection with an external board, and an Ni layer having a thick section and thin section. The thick section is formed on the back surface of the base material, whereas the thin section is formed on all or a part of the front surface of the base material. It is preferable that the thick section has a thickness ranging from 2.5 to 5 μm, and the thin section is 0.5-2 μm thinner than the thick section. The lead frame can be manufactured with improved productivity by forming an Ni layer on both front and back surfaces of the base material, and then etching only the Ni layer formed on the front surface of the base material. | 04-21-2011 |
| 20090130802 | SUBSTRATE BASED UNMOLDED PACKAGE - A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. | 05-21-2009 |
| 20090130801 | RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND LEAD FRAME, AND METHOD FOR MANUFACTURING THE SAME - There are provided a lead frame including a plurality of first external terminal portions | 05-21-2009 |
| 20110183473 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - To solve a problem in that a die processing cost increases when employing a method involving providing a suction hole in the die to fix an island onto a bottom surface, provided is a semiconductor device, which includes: a semiconductor chip, an island having a first surface, on which the semiconductor chip is mounted, and a second surface opposing to the first surface, a hanger pin extended from the island, a branch portion extended from one of the island and the hanger pin, and a resin encapsulating the semiconductor chip, the island, the hanger pin and the brunch portion while exposing the second surface of the island. | 07-28-2011 |
| 20120164795 | Ultrasonic Wire Bonding Method for a Semiconductor Device - A risk of an electrical short between electrode pads of a semiconductor device can be reduced to thereby improve quality of the semiconductor device. During ball bonding in wire bonding, in each of the electrode pads of a semiconductor chip which are arrayed along an ultrasonic wave application direction (ultrasonic vibration direction), a ball at the tip of a copper wire and the electrode pad are coupled to each other while being rubbed against each other in a direction intersecting the ultrasonic wave application direction. Thus, the amount of AL splash formed on the electrode pad can be minimized to make the AL splash smaller. As a result, the quality of the semiconductor device assembled by the above-mentioned ball bonding can be improved. | 06-28-2012 |
| 20120164794 | METHOD OF MAKING A COPPER WIRE BOND PACKAGE - A method for making a wire bond package comprising the step of providing a lead frame array comprising a plurality of lead frame units therein, each lead frame unit comprises a first die pad and a second die pad each having a plurality of tie bars connected to the lead frame array, a plurality of reinforced bars interconnecting the first and second die pads; the reinforced bars are removed after molding compound encapsulation. | 06-28-2012 |
| 20120077316 | BRACE FOR WIRE BOND - An electrical connection includes a first wire having one end stitch bonded to a surface, such as the lead finger of a lead frame or the connection pad of a substrate. A second wire has a first end attached to the surface on a first side of the first wire and a second end attached to the surface on a second, opposing side of the first wire. The second wire acts as a brace that prevents the first wire from lifting off of the surface. If necessary, a third wire can be added that, like the second wire, acts as a brace to prevent the first wire from lifting off of the surface. | 03-29-2012 |
| 20090068796 | SEMICONDUCTOR CONNECTION COMPONENT - There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire | 03-12-2009 |
| 20120083072 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Performing electrolysis plating to a wiring is made possible, aiming at the increasing of pin count of a semiconductor device. Package substrate | 04-05-2012 |
| 20110124159 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Performing electrolysis plating to a wiring is made possible, aiming at the increasing of pin count of a semiconductor device. Package substrate | 05-26-2011 |
| 20120264259 | Method for Forming a Semiconductor Device and a Semiconductor Device - A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate having a main horizontal surface, an opposite surface and a completely embedded dielectric region. A deep vertical trench is etched from the main horizontal surface into the semiconductor substrate using the dielectric region as an etch stop. A vertical transistor structure is formed in the semiconductor substrate. A first metallization in ohmic contact with the transistor structure is formed on the main horizontal surface. The semiconductor substrate is thinned at the opposite surface at least close to the dielectric region. Further, a semiconductor device is provided. | 10-18-2012 |
| 20100203683 | SEMICONDUCTOR SYSTEM WITH FINE PITCH LEAD FINGERS AND METHOD OF MANUFACTURE THEREOF - A method for manufacturing a semiconductor package system includes: providing a die having a plurality of contact pads; forming a leadframe having a plurality of lead fingers with flat tops of predetermined lengths, the plurality of lead fingers having a fine pitch and each having a trapezoidal cross-section; attaching a plurality of bumps to the plurality of lead fingers, the plurality of bumps on the tops, extending beyond the widths of the trapezoidal cross-sections, and clamping down on the two sides of each of the plurality of lead fingers; attaching a plurality of bond wires to the plurality of contact pads; attaching the plurality of bond wires to the plurality of bumps; and forming an encapsulant over the plurality of lead fingers, the die, and the plurality of bond wires, the encapsulant leaving lower surfaces of the plurality of lead fingers exposed. | 08-12-2010 |
| 20100203682 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device including a semiconductor device, an integrated circuit chip, a sealing resin encapsulating the integrated circuit chip and an insulating waterproof film covering at least a portion of a surface of said sealing resin and preventing penetration of moisture into the sealing resin. | 08-12-2010 |
| 20100203681 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND WIRE BONDER - An improvement in the quality of wire bonding is achieved by reducing the vibration of a lead frame or a wiring substrate after wire bonding. Over a heat block in a wire bond portion of a wire bonder, there is provided a cooling blower for cooling a wire-bonded matrix frame so that the temperature thereof may decrease stepwise. After wire bonding, cold air is blown from the cooling blower to the matrix frame, and temperature control of the matrix frame is performed so that the temperature of the matrix frame after wire bonding may decrease stepwise. Or, the wire-bonded matrix frame is fixed with a holding tool such as a frame holding member, a guide member, a roller means, or an elastic means until cooling is completed. | 08-12-2010 |
| 20110039376 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A high positional accuracy of a semiconductor chip is attained to stabilize the quality of a semiconductor device. In a die bonding process during assembly of an SIP, a microcomputer chip not required to have a high positional accuracy is picked up with a surface non-contact type collet and is die-bonded onto a first chip mounting portion, thereafter, an ASIC chip required to have a high positional accuracy is picked up with a surface contact type collet and die-bonded onto a second chip mounting portion. By thus using two types of collets properly, not only a high positional accuracy of the ASIC chip which has been die-bonded with the surface contact type collet is attained, but also the quality of the SIP is stabilized. | 02-17-2011 |
| 20110045641 | Semiconductor Device Having Solder-Free Gold Bump Contacts for Stability in Repeated Temperature Cycles - A semiconductor device has a chip ( | 02-24-2011 |
| 20110212577 | SEMICONDUCTOR POWER DEVICE HAVING A STACKED DISCRETE INDUCTOR STRUCTURE - A power device includes a discrete inductor having contacts formed on a first surface of the discrete inductor and at least one semiconductor component mounted on the first surface of the discrete inductor and coupled to the contacts. The discrete inductor further includes contacts formed on a second surface opposite the first surface and routing connections connecting the first surface contacts to corresponding second surface contacts. The semiconductor components may be flip chip mounted onto the discrete inductor contacts or wire bonded thereto. | 09-01-2011 |
| 20110237032 | Semiconductor Package and Method for Making the Same - The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, a second metal layer and a third metal layer. The substrate has a surface having at least one first pad and at least one second pad. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer. | 09-29-2011 |
| 20120322211 | DIE BACKSIDE STANDOFF STRUCTURES FOR SEMICONDUCTOR DEVICES - Standoff structures that can be used on the die backside of semiconductor devices and methods for making the same are described. The devices contain a silicon substrate with an integrated circuit on the front side of the substrate and a backmetal layer on the backside of the substrate. Standoff structures made of Cu of Ni are formed on the backmetal layer and are embedded in a Sn-containing layer that covers the backmetal layer and the standoff structures. The standoff structures can be isolated from each other so that they are not connected and can also be configured to substantially mirror indentations in the leadframe that is attached to the Sn-containing layer. Other embodiments are described. | 12-20-2012 |
| 20120088337 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, includes the steps of mounting a lead frame in a recessed portion of a lower die, bringing the lower die and an upper die to overlap each other so that a portion for sliding the lead frame slides the lead frame toward injection surfaces, the sliding portion being formed on the recessed portion of the lower die or on the recessed portion of the upper die, clamping the lower die and the upper die together so that at least one projection formed on the upper die crushes down an end portion of the lead frame so as to form lateral projections on the left and right sides of the gate, the lateral projections blocking up the gap between the injection surfaces and the lead frame, and injecting a molding resin through the gate. | 04-12-2012 |
| 20110312134 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES - The reliability of a semiconductor device is enhanced. A first lead frame, a first semiconductor chip, a second lead frame, and a second semiconductor chip are stacked over an assembly jig in this order with solder in between and solder reflow processing is carried out to fabricate their assembly. Thereafter, this assembly is sandwiched between first and second molding dies to form an encapsulation resin portion. The upper surface of the second die is provided with steps. At a molding step, the second lead frame is clamped between the first and second dies at a position higher than the first lead frame; and a third lead frame is clamped between the first and second dies at a higher position. The assembly jig is provided with steps at the same positions as those of the steps in the upper surface of the second die in positions corresponding to those of the same. | 12-22-2011 |
| 20120329214 | SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME - A semiconductor die package. The semiconductor die package includes a premolded clip structure assembly having a clip structure, a semiconductor die attached to the clip structure, and a first molding material covering at least a portion of the clip structure and the semiconductor die. The semiconductor die package also includes a leadframe structure having a die attach pad, where the leadframe structure is attached to premolded clip structure assembly. | 12-27-2012 |
| 20120100672 | METHODS AND APPARATUS FOR A STACKED-DIE INTERPOSER - An improved stacked-die package includes an interposer which improves the manufacturability of the package. A semiconductor package includes a package substrate having a plurality of bond pads; a first semiconductor device mounted on the package substrate, the first semiconductor device having a plurality of bond pads provided thereon; an interposer mounted on the first semiconductor device, the interposer having a first interposer bond pad and a second interposer bond pad, wherein the first and second interposer bond pads are electrically coupled; a second semiconductor device mounted on the interposer, the second semiconductor device having a plurality of bond pads provided thereon; a first bond wire connected to one of the plurality of bond pads on said first semiconductor and to the first interposer bond pad; and a second bond wire connected to the second interposer bond pad and to one of the plurality of bond pads on the semiconductor device. | 04-26-2012 |
| 20130011973 | LEADFRAME STRIP AND MOLD APPARATUS FOR AN ELECTRONIC COMPONENT AND METHOD OF ENCAPSULATING AN ELECTRONIC COMPONENT - A leadframe strip comprises a plurality of units arranged in a line. Each unit provides two component positions, each having a chip support substrate. The chip support substrates of the two component positions are mechanically linked by at least one support bar. The two component positions of a unit are molded at essentially the same time to produce a plastic housing for a package in each component position. The central portion of the first support bars remains outside of the plastic housing of the two packages. | 01-10-2013 |
| 20130017653 | Integrated Antennas in Wafer Level Package - A semiconductor module comprises components in one wafer level package. The module comprises an integrated circuit (IC) chip embedded within a package molding compound. The package comprises a molding compound package layer coupled to an interface layer for integrating an antenna structure and a bonding interconnect structure to the IC chip. The bonding interconnect structure comprises three dimensional interconnects. The antenna structure and bonding interconnect structure are coupled to the IC chip and integrated within the interface layer in the same wafer fabrication process. | 01-17-2013 |
