Entries |
Document | Title | Date |
20080213946 | SUBSTRATE BASED UNMOLDED PACKAGE - A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. The die attach surface and the lead surface can be in different planes. | 09-04-2008 |
20080233682 | METHODS OF FORMING A CORED METALLIC THERMAL INTERFACE MATERIAL AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a core portion of a TIM, wherein the core portion comprises a high thermal conductivity and does not comprise indium, and forming an outer portion of the TIM on the core portion. | 09-25-2008 |
20080242003 | INTEGRATED CIRCUIT DEVICES WITH INTEGRAL HEAT SINKS - A method for forming integral heat sinks on back surfaces of integrated circuit devices at wafer level is described. A first metallic layer is deposited over the back surface of a wafer. A second metallic layer is deposited over the first metallic layer. Optionally, a third metallic layer is deposited over the second metallic layer. The first metallic layer, the second metallic layer, and optionally the third metallic layer form the integral heat sink for the wafer. When the wafer is diced into multiple semiconductor devices, each semiconductor device has an integral heat sink formed on its back surface that includes the first metallic layer, the second metallic layer, and optionally the third metallic layer. Optionally, each semiconductor device is connected to a lead frame via solder bumps or bonding wires to form an integrated circuit (IC) package. | 10-02-2008 |
20080254573 | INTEGRATED CIRCUIT THERMAL MANAGEMENT METHOD AND APPARATUS - An apparatus, method, and system for providing thermal management for an integrated circuit includes a first metallic layer directly placed on a back surface of the integrated circuit. An integrated heat spreader with a substantially cap-like shape is placed over the integrated circuit, with an aperture of a ceiling wall of the integrated heat spreader exposing a back surface of the integrated circuit at least in part. The first metallic layer is directly placed on top of an exterior surface of the ceiling wall of the integrated heat spreader as well as the back surface of the integrated circuit. | 10-16-2008 |
20080305584 | HEAT SPREADER FOR CENTER GATE MOLDING - A heat spreader for an integrated circuit has a base portion and a top portion. The base portion is attachable to a surface of the integrated circuit, and has at least one channel extending therethrough. The top portion that is larger than the base portion such that the heat spreader is generally T-shaped in cross-section. The top portion has a hole at its center that extends from a top surface of the top portion to the at least one channel of the base portion. Mold compound is injected through the hole and out through the channels. | 12-11-2008 |
20080305585 | Method for Direct Heat Sink Attachment - A system and method of attaching a heat sink to an integrated circuit chip includes providing a compliant material for constraining the heat sink's mechanical motion while simultaneously allowing for thermal expansion of the heat sink. | 12-11-2008 |
20090011546 | COOLING OF SUBSTRATE USING INTERPOSER CHANNELS - A method of forming structure. A substrate and an interposer are provided. The substrate includes a heat source and N continuous substrate channels on a first side of the substrate (N≧2). N interposer channels are coupled to the N substrate channels so as to form M continuous loops (1≦M≦N). Each loop independently consists of K substrate channels and K interposer channels in an alternating sequence. For each loop, K is at least 1 and is subject to an upper limit consistent with a constraint of the M loops collectively consisting of the N interposer channels and the N substrate channels. Each loop is independently open ended or closed. The first side of the substrate is connected to the interposer. The interposer is adapted to be thermally coupled to a heat sink such that the interposer is interposed between the substrate and the heat sink. | 01-08-2009 |
20090011547 | COOLING OF SUBSTRATE USING INTERPOSER CHANNELS - A method of forming a structure. An interposer is provided. The interposer is adapted to be interposed between a heat source and a heat sink and to transfer heat from the heat source to the heat sink. The interposer includes an enclosure that encloses a cavity. The enclosure is made of a thermally conductive material. The cavity includes a thermally conductive foam material. The foam material includes pores and includes at least one serpentine channel. Each serpentine channel has at least two contiguously connected channel segments. Each serpentine channel independently forms a closed loop or an open ended loop. The foam material is adapted to be soaked by a liquid filling the pores. Each serpentine channel is adapted to be partially filled with a fluid that serves to transfer heat from the heat source to the heat sink. | 01-08-2009 |
20090023252 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING A HEAT SINK WITH A BORED PORTION - A heatsink plate is to be fixed to a substrate with sufficient strength, so as to prevent the heatsink plate from being stripped off, to thereby secure reliability on the performance of the semiconductor chip. The heatsink plate has both the upper and lower surfaces of the fixing section sandwiched by an adhesive resin. Such structure provides an increased adhesion area between the heatsink plate and the upper surface of the substrate, thereby securing greater fixing strength compared with the conventional structure in which simply the lower surface of the heatsink plate and the upper surface of the substrate are adhered to each other. Accordingly, the heatsink plate can be fixed to the upper surface of substrate with greater strength. | 01-22-2009 |
20090075430 | THERMAL INTERMEDIATE APPARATUS, SYSTEMS, AND METHODS - Apparatus and system, as well as fabrication methods therefor, may include a thermal intermediate structure comprised of a plurality of carbon nanotubes some of which have organic moieties attached thereto to tether the nanotubes to at least one of a die and a heat sink. The organic moieties include thiol linkers and amide linkers. | 03-19-2009 |
20090087952 | Void free soldering semiconductor chip attachment method for wafer scale chip size - Methods for attaching the wafer scale semiconductor chip, up to 4 square inch (2.times.2 inchs), are comprises of following steps. Stack assembles following materials from bottom to top. First lower integrated heat spreader (IHS). Second thermal interface material (TIM). Third semiconductor chip with backside metallization deposit. Forth polyimide film. Fifth the dummy upper IHS. Then put the stack-assembled set into the metal box and fix in place. Then the metal box and stack-assembled set in it are heated to wetting temperature of TIM. During cool down, the environment temperature must be set at a few degrees lower than the melting point of TIM, to soak the stack-assembled set at melting point of TIM until the TIM completely become solid, then cool down to room temperature. After de-assemble and remove upper IHS and polyimide film, we will get the void free soldering of semiconductor chip on lower IHS. | 04-02-2009 |
20090093089 | METHOD FOR FABRICATING HEAT DISSIPATING SEMICONDUCTOR PACKAGE - A heat dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted on a chip carrier. A heat sink is mounted on the chip, and includes an insulating core layer, a thin metallic layer formed on each of an upper surface and a lower surface of the insulating core layer and a thermal via hole formed in the insulating core layer. A molding process is performed to encapsulate the chip and the heat sink with an encapsulant to form a package unit. A singulation process is performed to peripherally cut the package unit. A part of the encapsulant above the thin metallic layer on the upper surface of the heat sink is removed, such that the thin metallic layer on the upper surface of the heat sink is exposed, and heat generated by the chip can be dissipated through the heat sink. | 04-09-2009 |
20090130800 | Manufacturing method of semiconductor device - A method of manufacturing a semiconductor device includes the steps of bonding a semiconductor chip to a first side of a circuit board, bonding a metal base for dissipating heat produced by the semiconductor chip to a second side of the circuit board, and forming a dam on the metal base by a dam material so as to restrict flow of a solder used in bonding a plurality of the circuit boards to the metal base. | 05-21-2009 |
20090203172 | Enhanced Die-Up Ball Grid Array and Method for Making the Same - Methods of assembling a ball grid array (BGA) package is provided. One method includes providing a tape substrate that has a first surface and a second surface, attaching a first surface of a stiffener to the first substrate surface, mounting an IC die to the second stiffener surface, mounting a heat spreader to the IC die, and attaching a plurality of solder balls to the second substrate surface. | 08-13-2009 |
20090269888 | CHIP-BASED THERMO-STACK - A chip unit has a stack of at least two electronic chips stacked one on top of the other, a through-chip connection within the stack, the through-chip connection including a bounding material having an inner and outer perimeter, the inner perimeter defining an interior volume longitudinally extending through at least one of the at least two chips and at least partially into another of the at least two chips so as to form a tube extending between the one and the other of the chips, and an amount of working fluid hermetically sealed within the tube, the working fluid having a volume and being at a pressure such that the working fluid and tube will operate as a heat pipe and transfer heat from the stack of chips to the working fluid. | 10-29-2009 |
20090286359 | OPTIMIZED LID ATTACH PROCESS FOR THERMAL MANAGEMENT AND MULTI-SURFACE COMPLIANT HEAT REMOVAL - A multi-surface compliant heat removal process includes: identifying one or more components to share a heat rejecting device; applying non-adhesive film to the one or more components; identifying a primary component of the one or more components; and applying phase change material on each of the one or more components other than the primary component. The phase change material is placed on top of the non-adhesive film. The process further includes placing the heat rejecting device on the corresponding one or more components; and removing the heat rejecting device from the corresponding one or more components. The phase change material and the non-adhesive film remain with the heat rejecting device. The process also includes reflowing the phase change material on the heat rejecting device; removing the non-adhesive film from the heat rejecting device; placing a heatsink-attach thermal interface material on the one or more components; and placing the heat rejecting device on the corresponding one or more components. | 11-19-2009 |
20090317947 | Semiconductor package with heat sink, stack package using the same and manufacturing method thereof - A semiconductor package may include a heat sink. The heat sink may be disposed above and spaced apart from a substrate, which may support a semiconductor chip. The heat sink may have a hole. A liquid molding compound may be provided through the hole of the heat sink to form an encapsulant. The encapsulant may seal the semiconductor chip, leaving an upper portion of the heat sink exposed. A tape supporting the heat sink may be provided on the substrate. The tape may be removed after the encapsulant is provided. | 12-24-2009 |
20100015761 | Thermally Enhanced Single Inline Package (SIP) - In a method and system for fabricating a thermally enhanced semiconductor device ( | 01-21-2010 |
20100047971 | Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages - A nano-sized metal particle composite includes a first metal that has a particle size of about 50 nanometer or smaller. A wire interconnect is in contact with a reflowed nanosolder and has the same metal or alloy composition as the reflowed nanosolder. A microelectronic package is also disclosed that uses the reflowed nanosolder composition. A method of assembling a microelectronic package includes preparing a wire interconnect template. A computing system includes a nanosolder composition coupled to a wire interconnect. | 02-25-2010 |
20100055843 | CHIP PACKAGE MODULE HEAT SINK - A heat sink mechanism including multiple heat passages in the base of a casing of a chip package module penetrating through a substrate packed in the module; a metal material being deposited in each heat passage to become a heat sink conductor connecting the substrate and the surface of the casing to effectively solve the problem of excessive heat generated in the course of HF operation of the chip package module thus to prevent chip failure. | 03-04-2010 |
20100087036 | MODULE HAVING A STACKED PASSIVE ELEMENT AND METHOD OF FORMING THE SAME - A module having a discrete passive element and a semiconductor device, and method of forming the same. In one embodiment, the module includes a patterned leadframe, a discrete passive element mounted on an upper surface of the leadframe, and a thermally conductive, electrically insulating material formed on an upper surface of the discrete passive element. The module also includes a semiconductor device bonded to an upper surface of the thermally conductive, electrically insulating material. | 04-08-2010 |
20100120206 | INTEGRATED CIRCUIT PACKAGE AND A METHOD FOR DISSIPATING HEAT IN AN INTEGRATED CIRCUIT PACKAGE - An IC package that is suitable for surface mounting arrangements includes a heat spreader device that is coupled to a bottom portion of the package below the IC die. Coupling the heat spreader device to the bottom portion of the package reduces or eliminates the possibility that placement of the heat spreader device will result in the molding compound bleeding on top of the heat spreader device, and delamination at the footings of the heat spreader device that can cause the package to delaminate, or “popcorn”. | 05-13-2010 |
20100129963 | INTEGRATED CIRCUIT PACKAGE AND FABRICATING METHOD THEREOF - The invention discloses an integrated circuit package. The integrated circuit package comprises a substrate having a first surface and a second surface opposite thereto and a first hole passing through the substrate from the first surface to the second surface. A plurality of conductive lines is disposed on a portion of the second surface of the substrate. A semiconductor chip is disposed above the second surface of the substrate, wherein a chamber is formed between the semiconductor chip and the substrate. A plurality of bonding pads are disposed on a side of the semiconductor chip which is toward the second surface of the substrate, wherein at least one of the bonding pads are electrically connected to one of the plurality of conductive lines. A first heat dissipation layer is disposed in the first hole, and extends into the chamber. A method for fabricating the integrated circuit package is also provided. | 05-27-2010 |
20100151631 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE HAVING HEAT DISSIPATION DEVICE - A semiconductor package with a heat dissipating device and a fabrication method of the semiconductor package are provided. A chip is mounted on a substrate. The heat dissipating device is mounted on the chip, and includes an accommodating room, and a first opening and a second opening that communicate with the accommodating room. An encapsulant is formed between the heat dissipating device and the substrate to encapsulate the chip. A cutting process is performed to remove a non-electrical part of structure and expose the first and second openings from the encapsulant. A cooling fluid is received in the accommodating room to absorb and dissipate heat produced by the chip. The heat dissipating device covers the encapsulant and the chip to provide a maximum heat transfer area for the semiconductor package. | 06-17-2010 |
20100151632 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE - A semiconductor device includes a multi-layer substrate and a semiconductor element mounted on the multi-layer substrate. The multi-layer substrate contains a plurality of circuit-formation layers joined by a first resin material. The semiconductor element is mounted on the multi-layer substrate by being joined to the multi-layer substrate by a second resin material. The first resin material and the second resin material are curable in the same heating condition. | 06-17-2010 |
20100190300 | METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A BASE HEAT SPREADER AND A CAVITY IN THE BASE - A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a substrate on the adhesive including aligning the post with an aperture in the substrate, then flowing the adhesive into and upward in a gap located in the aperture between the post and the substrate, solidifying the adhesive, then etching the post and the base to form a cavity that extends through the adhesive into the base, then mounting a semiconductor device on the base, wherein a heat spreader includes the base and the semiconductor device extends into the cavity, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader. | 07-29-2010 |
20100197081 | MICROELECTRONIC PACKAGE WITH THERMAL ACCESS - A method of forming a microelectronic package including the steps of providing a three-layer metal plate, having a first layer, a second layer and a third layer. A plurality of conductive elements is formed from the first layer of the metal plate. A dielectric sheet is attached to the first layer of the metal plate, such that the dielectric sheet is remote from the third layer. A plurality of conductive features is then formed from the third layer of the metal plate which are also remote from the dielectric sheet. A microelectronic element is next electrically conducted to the conductive elements and a heat spreader is thermally connected the microelectronic element. | 08-05-2010 |
20100267205 | CARBON NANOTUBES FOR THE SELECTIVE TRANSFER OF HEAT FROM ELECTRONICS - Under one aspect, a method of cooling a circuit element includes providing a thermal reservoir having a temperature lower than an operating temperature of the circuit element; and providing a nanotube article in thermal contact with the circuit element and with the reservoir, the nanotube article including a non-woven fabric of nanotubes in contact with other nanotubes to define a plurality of thermal pathways along the article, the nanotube article having a nanotube density and a shape selected such that the nanotube article is capable of transferring heat from the circuit element to the thermal reservoir. | 10-21-2010 |
20100267206 | SEMICONDUCTOR DIE PACKAGE INCLUDING HEAT SINKS - A semiconductor die package including at least two heat sinks. The semiconductor die package includes a first heat sink, a second heat sink coupled to the first heat sink, and a semiconductor die between the first heat sink and the second heat sink. The semiconductor die is electrically coupled to the first heat sink and the second heat sink. The semiconductor die may also be attached to a lead. | 10-21-2010 |
20100285637 | Die Down Ball Grid Array Packages and Method for Making Same - A method of forming a ball grid array (BGA) package is provided. The method includes coupling an integrated circuit (IC) die to a heat spreader in an opening of a substrate, the opening of the substrate extending through the substrate, such that a portion of the heat spreader is accessible through the opening and coupling a first surface of a second substrate to the IC die via a bump interconnect. The second surface of the second substrate has an array of contact pads capable of coupling to a board. | 11-11-2010 |
20110027943 | Stud Bumps as Local Heat Sinks During Transient Power Operations - A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of interconnects are formed on the metal surface and connected to a substrate. A plurality of thermal management stud bumps are formed on the metal bonding surface, the thermal management stud bumps positioned distinct from the interconnects and local to die hot spots, exposed ends of the thermal management stud bumps spaced from the substrate. | 02-03-2011 |
20110059579 | METHOD OF FORMING TAPE BALL GRID ARRAY PACKAGE - A method of forming a semiconductor package including providing a substrate having a through hole formed therein. A tape is attached to a surface of the substrate such that the through hole is covered by the tape. An integrated circuit (IC) die is attached to the tape. The IC die is electrically connected to the substrate via a plurality of electrical connections. The IC die and the electrical connections are encapsulated and the tape is removed from the substrate. | 03-10-2011 |
20110059580 | HIGH-POWER SEMICONDUCTOR DIE PACKAGES WITH INTEGRATED HEAT-SINK CAPABILITY AND METHODS OF MANUFACTURING THE SAME - An exemplary semiconductor die package of the invention has a metal-oxide substrate disposed between a first surface of a semiconductor die and a heat-sinking component, with a conductive die clip or one or more electrical interconnect traces disposed between the metal-oxide substrate and the first surface of the semiconductor die. The heat-sinking component may comprise a heat sink, or an adaptor plate to which a heat sink may be coupled. The conductive die clip or electrical trace(s) provides electrical connection(s) to the first surface of the semiconductor die, while the metal-oxide substrate electrically insulates the die from the heat-sinking component, and provides a path of high thermal conductivity between the die and the heat-sinking component. The second surface of the semiconductor die may be left free to connect to a circuit board, or a leadframe or interconnect substrate may be attached to it. | 03-10-2011 |
20110070699 | 3D SMART POWER MODULE - A 3D smart power module for power control, such as a three phase power control module, includes a two sided printed circuit (PC) board with power semiconductor devices attached to one side and control semiconductor devices attached to the other side. The power semiconductor devices are die bonded to a direct bonded copper substrate which has a bottom surface exposed in the molded package. In one embodiment the module has 27 external connectors attached to one side of the PC board and arranged in the form of a ball grid array. | 03-24-2011 |
20110092026 | FLUORINATION PRE-TREATMENT OF HEAT SPREADER ATTACHMENT INDIUM THERMAL INTERFACE MATERIAL - The formation of electronic assemblies including a heat spreader coupled to a die through a thermal interface material formed from an indium preform, is described. One embodiment relates to a method including providing a preform comprising indium, the preform including an indium oxide layer thereon. The method also includes exposing the preform to fluorine so that part of the indium oxide layer is transformed into an indium oxy-fluoride. The method may also include, after the exposing the preform to fluorine so that part of the indium oxide layer is transformed into an indium oxy-fluoride, positioning the preform between a die and a heat sink, and applying pressure to and heating the preform positioned between the die and the heat sink so that reflow occurs and a bond is formed between the die and the heat sink. | 04-21-2011 |
20110092027 | INTEGRATED CIRCUIT PACKAGE HAVING A CASTELLATED HEATSPREADER - In one aspect, an embodiment of an IC package includes an IC chip electrically connected to a substrate, a heatspreader disposed over the IC chip, wherein the heatspreader does not directly contact the IC chip, and an encapsulant material encapsulating at least a portion of the IC chip and a portion of the heatspreader such that a top portion of the heatspreader is exposed to the surroundings of the IC package. In another embodiment, the heatspreader comprises at least one castellation to improve adhesion to the encapsulation compound. A method of manufacturing such IC package is also disclosed. | 04-21-2011 |
20110124158 | THERMAL ENHANCED UPPER AND DUAL HEAT SINK EXPOSED MOLDED LEADLESS PACKAGE - A semiconductor package includes a semiconductor device | 05-26-2011 |
20110171784 | SUBASSEMBLY THAT INCLUDES A POWER SEMICONDUCTOR DIE AND A HEAT SINK HAVING AN EXPOSED SURFACE PORTION THEREOF - The semiconductor assembly includes a first subassembly having a heat sink. Solder material is disposed on the exposed portion of a first surface of heat sink. A power semiconductor die is located on the first surface of the heat sink and is thermally coupled thereto by the solder material. A packaging patterned polymer layer is disposed on a second surface of the heat sink opposing the first surface and defines an interior surface portion of the heat sink. A semiconductor package is provided in which the first subassembly, solder material and die are located such that the interior surface portion of the second surface of the heat sink is not enclosed by the semiconductor package. | 07-14-2011 |
20110171785 | METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A BUMP/BASE HEAT SPREADER AND AN INVERTED CAVITY IN THE BUMP - A method of making a semiconductor chip assembly includes providing a bump and a ledge, mounting an adhesive on the ledge including inserting the bump into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the bump with an aperture in the conductive layer, then flowing the adhesive between the bump and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal and a selected portion of the conductive layer, then mounting a semiconductor device on the bump opposite a cavity in the bump, wherein a heat spreader includes the bump and a base that includes a portion of the ledge adjacent to the bump, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader. | 07-14-2011 |
20110177656 | OPTIMIZED LID ATTACH PROCESS FOR THERMAL MANAGEMENT AND MULTI-SURFACE COMPLIANT HEAT REMOVAL - A multi-surface compliant heat removal process includes: identifying one or more components to share a heat rejecting device; applying non-adhesive film to the one or more components; identifying a primary component of the one or more components; and applying phase change material on each of the one or more components other than the primary component. The phase change material is placed on top of the non-adhesive film. The process further includes placing the heat rejecting device on the corresponding one or more components; and removing the heat rejecting device from the corresponding one or more components. The phase change material and the non-adhesive film remain with the heat rejecting device. The process also includes reflowing the phase change material on the heat rejecting device; removing the non-adhesive film from the heat rejecting device; placing a heatsink-attach thermal interface material on the one or more components; and placing the heat rejecting device on the corresponding one or more components. | 07-21-2011 |
20110207265 | Nonvolatile memory devices and method of manufacturing the same - Example embodiments provide a nonvolatile memory device using resistive elements. The nonvolatile memory device may include a semiconductor substrate, a plurality of variable resistance patterns on the semiconductor substrate, and a plurality of heat sink patterns that are level with the variable resistance patterns and coupled to a ground voltage. | 08-25-2011 |
20110244633 | PACKAGE ASSEMBLY FOR SEMICONDUCTOR DEVICES - Semiconductor packages and methods for making and using such semiconductor packages are described. The semiconductor packages contain a dual gauge heat sink exposed on an upper part of the package, a leadframe containing a gate lead and an exposed drain pad on a lower part of the package, and a semiconductor die containing an IC device located between the heat sink and the leadframe. The gate of the IC device is connected to the gate lead of the leadframe using a bond interconnect wire or a gate interconnect clip located and placed under the heat sink and in between the heat sink and main leadframe. Such a configuration provides both a simple design for the semiconductor package and a simple method of manufacturing. Other embodiments are described. | 10-06-2011 |
20110269271 | NANOTUBE BASED VAPOR CHAMBER FOR DIE LEVEL COOLING - The formation of electronic assemblies is described. In one embodiment, an electronic assembly includes a semiconductor die and a plurality of spaced apart nanotube structures on the semiconductor die. The electronic assembly also includes a fluid positioned between the spaced apart nanotube structures on the semiconductor die. The electronic assembly also includes a endcap covering the plurality of nanotube structures and the fluid, wherein the endcap is positioned to define a gap between the nanotube structures and an interior surface of the endcap. The endcap is also positioned to form a closed chamber including the working fluid, the nanotube structures, and the gap between the nanotube structures and the interior surface of the endcap. | 11-03-2011 |
20110275180 | METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE HEAT SPREADER WITH A THERMAL VIA - A method of making a semiconductor chip assembly includes providing a post, a base, a support layer and an underlayer, wherein the post extends above the base and the support layer is sandwiched between the base and the underlayer, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the post with an aperture in the conductive layer, then flowing the adhesive upward between the post and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal and a selected portion of the conductive layer, providing a heat spreader that includes the post, the base, the underlayer and a thermal via that extends from the base through the support layer to the underlayer, then mounting a semiconductor device on the post, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader. | 11-10-2011 |
20110287587 | METHOD FOR FABRICATING HEAT DISSIPATION PACKAGE STRUCTURE - A heat dissipation package structure and method for fabricating the same are disclosed, which includes mounting and electrically connecting a semiconductor chip to a chip carrier through its active surface; mounting a heat dissipation member having a heat dissipation section and a supporting section on the chip carrier such that the semiconductor chip can be received in the space formed by the heat dissipation section and the supporting section, wherein the heat dissipation section has an opening formed corresponding to the semiconductor chip; forming an encapsulant to encapsulate the semiconductor chip, and the heat dissipation member; and thinning the encapsulant to remove the encapsulant formed on the semiconductor chip to expose inactive surface of the semiconductor chip and the top surface of the heat dissipation section from the encapsulant. Therefore, the heat dissipation package structure is fabricated through simplified fabrication steps at low cost, and also the problem that the chip is easily damaged in a package molding process of the prior art is overcome. | 11-24-2011 |
20110287588 | METHOD FOR MANUFACTURING HEAT-DISSIPATING SEMICONDUCTOR PACKAGE STRUCTURE - A heat-dissipating semiconductor package structure and a method for manufacturing the same is disclosed. The method includes: disposing on and electrically connecting to a chip carrier at least a semiconductor chip and a package unit; disposing on the top surface of the package unit a heat-dissipating element having a flat portion and a supporting portion via the flat portion; receiving the package unit and semiconductor chip in a receiving space formed by the flat portion and supporting portion of the heat-dissipating element; and forming on the chip carrier encapsulant for encapsulating the package unit, semiconductor chip, and heat-dissipating element. The heat-dissipating element dissipates heat generated by the package unit, provides EMI shielding, prevents delamination between the package unit and the encapsulant, decreases thermal resistance, and prevents cracking. | 11-24-2011 |
20110300670 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The occurrence of a resin seal failure is suppressed. A molding step is carried out using a lead frame in which there are formed multiple air vent portions for discharging gas in each cavity formed in the upper die of a molding die to outside the cavity. The air vent portions are formed at positions overlapping with the other corner portions, arranged inside a gate portion of the cavity. Each of the air vent portions is led out from the other corner portions of the cavity to outside a clamp area and is extended along sides of the cavity, respectively, in the clamp area. | 12-08-2011 |
20110312133 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND UNDERFILL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a dispense port; attaching an integrated circuit to the package carrier and over the dispense port; placing a mold chase over the integrated circuit and on the package carrier, the mold chase having a hole; and forming an encapsulation through the dispense port or the hole, the encapsulation surrounding the integrated circuit including completely filled in a space between the integrated circuit and the package carrier, and in a portion of the hole, the encapsulation having an elevated portion or a removal surface resulting from the elevated portion detached. | 12-22-2011 |
20110318884 | PRODUCTION METHOD OF SEMICONDUCTOR MODULE WITH RESIN-MOLDED ASSEMBLY OF HEAT SPREADER AND SEMICONDUCTOR CHIP - A method of producing a semiconductor module which includes a resin molded package and a coolant passage is provided. The resin molded package is made up of a thermosetting resin-made mold and a thermoplastic resin-made mold. The resin molded package is formed by making the thermoplastic resin-made mold, placing the thermoplastic resin-made mold and a semiconductor sub-assembly made up of a power semiconductor chip, heat spreaders, terminals, etc., and then forming the thermosetting resin-made mold. Specifically, the thermosetting resin-made mold is made after the thermoplastic resin-made mold, thereby creating a high degree of adhesion of the thermosetting resin-made mold to the thermoplastic resin-made mold before the thermosetting resin-made mold is hardened completely, thereby forming firmly an adhered interface between the thermosetting resin-made mold and the thermoplastic resin-made mold. This minimizes the risk of occurrence of air gaps at the adhered interface and avoids the leakage of the coolant outside the resin molded package. | 12-29-2011 |
20120015485 | LOW NOISE HIGH THERMAL CONDUCTIVITY MIXED SIGNAL PACKAGE - An improved microelectronic assembly ( | 01-19-2012 |
20120021566 | CARBON NANOTUBE MICRO-CHIMNEY AND THERMO SIPHON DIE-LEVEL COOLING - A method, apparatus and system with a semiconductor package including a microchimney or thermosiphon using carbon nanotubes to modify the effective thermal conductivity of an integrated circuit die. | 01-26-2012 |
20120058606 | Method of Fabricating A Semiconductor Device Having A Resin With Warpage Compensated Structures - A semiconductor device including: a die pad, a die on the die pad, and resin encapsulating the die and forming an isolation thickness over the die pad, the resin including a mounting aperture and a major surface configured for mounting to an external device, the major surface having a non warpage compensation portion adjacent the die and a warpage compensation portion in a relatively thermally inactive zone with an approximate discontinuity and/or abrupt change in gradient between the non warpage compensation portion and the warpage compensation portion. | 03-08-2012 |
20120083071 | SEMICONDUCTOR DIE PACKAGE INCLUDING LOW STRESS CONFIGURATION - A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure. | 04-05-2012 |
20120122279 | SYSTEM FOR CLAMPING HEAT SINK - A system for clamping a heat sink that prevents excessive clamping force is provided. The system may include a heat sink, a semiconductor device, a printed circuit) board, and a cover. The semiconductor device may be mounted onto the circuit board and attached to the cover. The heat sink may be designed to interface with the semiconductor device to transfer heat away from the semiconductor device and dissipate the heat into the environment. Accordingly, the heat sink may be clamped into a tight mechanical connection with the semiconductor device to minimize thermal resistance between the semiconductor device and the heat sink. To prevent excessive clamping force from damaging the semiconductor device, loading columns may extend between the cover and the heat sink. | 05-17-2012 |
20120129300 | METHOD OF MAKING STACKABLE SEMICONDUCTOR ASSEMBLY WITH BUMP/BASE/FLANGE HEAT SPREADER AND BUILD-UP CIRCUITRY - A method of making a stackable semiconductor assembly that includes a semiconductor device, a heat spreader, an adhesive, a terminal, a plated through-hole and build-up circuitry is disclosed. The heat spreader includes a bump, a base and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the build-up circuitry and thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The build-up circuitry provides signal routing for the semiconductor device. The plated through-hole provides signal routing between the build-up circuitry and the terminal. The heat spreader provides heat dissipation for the semiconductor device. | 05-24-2012 |
20120178216 | DEVICE INCLUDING TWO MOUNTING SURFACES - A device including two mounting surfaces. One embodiment provides a power semiconductor chip and having a first electrode on a first surface and a second electrode on a second surface opposite to the first surface. A first external contact element and a second external contact element, are both electrically coupled to the first electrode of the semiconductor chip. A third external contact element and a fourth external contact element, both electrically coupled to the second electrode of the semiconductor chip. A first mounting surface is provided on which the first and third external contact elements are disposed. A second mounting surface is provided on which the second and fourth external contact elements are disposed. | 07-12-2012 |
20120214280 | HEAT SINK FOR INTEGRATED CIRCUIT DEVICES - A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor. | 08-23-2012 |
20120231584 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method for manufacturing a semiconductor device includes: a step of producing a semiconductor package intermediate by injecting a resin into a forming die in which electrodes, a heat dissipating pad, and a semiconductor element are disposed, providing a peel-off film on one side of the resin in the form of a still-uncured resin body opposite from the other side facing the heat dissipating pad and a rigid material on one side of the peel-off film, and curing the uncured resin body to form a sealant resin body; a step of forming a solder layer by reflow soldering between a substrate and the intermediate; and a step of removing the rigid material from the peel-off film, wherein the rigid material is integrated into the intermediate so as to make the thermal expansion coefficient and rigidity of the intermediate approximately equal to those of the substrate. | 09-13-2012 |
20120231585 | METHOD FOR PACKAGING A SEMICONDUCTOR STRUCTURE - The present application provides a method and semiconductor packaging structure comprising a conductive substrate having a first surface, a first lateral surface and a second lateral surface adjacent to the first surface. A first electrode line with two ends are provided on the first surface and the first lateral surface, and a second electrode line with two ends are provided on the first surface and a second lateral surface respectively. A semiconductor device is provided on the first surface of the conductive substrate which electrically connected to the first electrode line and the second electrode line, a protective plate with through holes covers the first surface, and a sheathing overlays the semiconductor device. | 09-13-2012 |
20120289002 | FLEXIBLE INTERCONNECT PATTERN ON SEMICONDUCTOR PACKAGE - An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered. | 11-15-2012 |
20120309132 | CURVILINEAR HEAT SPREADER/LID WITH IMPROVED HEAT DISSIPATION - A heat spreader or lid for a microelectronic package, in which the heat spreader has an underside surface that includes at least one curvilinear contour, in which the curvilinear contour is selected from at least one positive or protruding curvilinear feature, at least one negative or recessed curvilinear feature, and a combination thereof. A microelectronic package that includes the heat spreader/lid, in which there is improved heat dissipation or reduced mechanical stress in an interface between the heat spreader/lid and a circuit chip. | 12-06-2012 |
20130023089 | LESS EXPENSIVE HIGH POWER PLASTIC SURFACE MOUNT PACKAGE - A high power surface mount package including a thick bond line of solder interposed between the die and a heatsink, and between the die and a lead frame, wherein the lead frame has the same coefficient of thermal expansion as the heatsink. The heatsink and the lead frame preferably comprise the same material. The package can be assembled using standard automated equipment, and does not require a weight or clip to force the parts close together, which force typically reduces the solder bond line thickness. Advantageously, the thermal stresses on each side of the die are effectively balanced, allowing for a large surface area die to be packaged with conventional and less expensive materials. One type of die that benefits from the present invention can include a transient voltage suppressor, but could include other dies generating a significant amount of heat, such as those in excess of 0.200 inches square. | 01-24-2013 |
20130040427 | FABRICATION METHOD OF PACKAGING SUBSTRATE HAVING THROUGH-HOLED INTERPOSER EMBEDDED THEREIN - A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer. | 02-14-2013 |
20130045572 | FLEXIBLE ROUTING FOR HIGH CURRENT MODULE APPLICATION - In one aspect of the invention, an integrated circuit package is described. The integrated circuit package includes a substrate formed from a dielectric material that includes multiple electrical contacts and conductive paths. An upper lead frame is attached with and underlies the substrate. The upper lead frame is electrically connected with at least one of the contacts on the substrate. The active surface of an integrated circuit die is electrically and physically coupled to the upper lead frame through multiple electrical connectors. A lower lead frame may be attached with the back surface of the integrated circuit die. A passive device is positioned on and electrically connected with one of the contacts on the substrate and/or the upper lead frame. | 02-21-2013 |
20130122656 | FLEXIBLE INTERCONNECT PATTERN ON SEMICONDUCTOR PACKAGE - An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered. | 05-16-2013 |
20130137221 | MANUFACTURING METHOD OF PACKAGE CARRIER - In a manufacturing method of a package carrier, a substrate including a first metal layer, a second metal layer having a top surface and a bottom surface opposite to each other, and an insulating layer between the first and second metal layers is provided. The second metal layer has a greater thickness than the first metal layer. A first opening passing through the first metal layer and the insulating layer and exposing a portion of the top surface of the second metal layer is formed. The first metal layer is patterned to form a patterned conductive layer. Second openings are formed on the bottom surface of the second metal layer. The second metal layer is divided into thermal conductive blocks by the second openings that do not connect the first opening. A surface passivation layer is formed on the patterned conductive layer and the exposed portion of the top surface. | 05-30-2013 |
20130224912 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor. | 08-29-2013 |
20130252381 | Electrically Isolated Power Semiconductor Package With Optimized Layout - A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink. | 09-26-2013 |
20130273696 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A technology with which the reliability of a package making up a semiconductor device can be enhanced is provided. A feature of the technical idea of the invention is that: a heat sink unit and an outer lead unit are separated from each other; and the outer lead unit is provided with chip placement portions and each of the chip placement portions and each heat sink are joined together. As a result, when a sealing body is formed at a resin sealing step, tying portions function as a stopper for preventing resin leakage and the formation of resin burr in a package product can be thereby prevented. In addition, camber does not occur in the heat sink unit and cracking in a sealing body caused by winding (camber) can be suppressed. | 10-17-2013 |
20130273697 | FABRICATION METHOD OF A MIXED ALLOY LEAD FRAME FOR PACKAGING POWER SEMICONDUCTOR DEVICES - This invention discloses a mixed alloy lead frame for power semiconductor devices, which includes a plurality of heat sinks and a pin array; the heat sinks are made of the first material, with positioning holes on their upper parts and welding zones at the center of their lower parts, while the pin array is made of the second material, which is different from the first material, with a plurality of sets of terminals leading out from its upper end and lower end respectively. The heat sinks are positioned on the lead frame assembly welding plate, the pin is positioned in the area between the upper heat sinks and lower heat sinks on the lead frame assembly welding plate. The mixed alloy lead frame for power semiconductor devices in this invention improves the heat dissipation of lead frame, reduces the fabrication cost of lead frame, and enhances the flexibility of fabrication. | 10-17-2013 |
20130280864 | STACKED INTERCONNECT HEAT SINK - A heat spreader that is configured to be attached to an integrated circuit substrate. The heat spreader includes a thermally conductive core and a heat spreader via that passes through the thermally conductive core. A connection point of the thermally conductive core is configured to form a solder connection to an integrated circuit substrate plug. | 10-24-2013 |
20130337612 | HEAT DISSIPATION METHODS AND STRUCTURES FOR SEMICONDUCTOR DEVICE - A semiconductor device with efficient heat dissipating structures is disclosed. The semiconductor device includes a first semiconductor chip that is flip-chip mounted on a first substrate, a heat absorption portion that is formed between the first semiconductor chip and the first substrate, an outer connection portion that connects the first semiconductor chip to an external device and a heat conduction portion formed between the heat absorption portion and the outer connection portion to dissipate heat generated by the first semiconductor chip. | 12-19-2013 |
20130344659 | MICROELECTRONIC PACKAGE HAVING DIRECT CONTACT HEAT SPREADER AND METHOD OF MANUFACTURING SAME - A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die. | 12-26-2013 |
20140024176 | IN-SITU FOAM MATERIAL AS INTEGRATED HEAT SPREADER (IHS) SEALANT - Integrated heat spreader (IHS) lid over a semiconductor die connected to a substrate forms a cavity. A bead of foaming material may be placed within the INS cavity. During an IHS cure and reflow process the foaming material will expand and fill the IHS cavity and the foam's shape conforms to the various surface features present, encapsulating a thermal interface material (TIM) material, and increasing contact area of the foam sealant. | 01-23-2014 |
20140038361 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. | 02-06-2014 |
20140038362 | Self orienting micro plates of thermally conducting material as component in thermal paste or adhesive - The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite. | 02-06-2014 |
20140080262 | METHOD FOR PRODUCING THE SAME - A method for producing a semiconductor device includes solder-connecting a semiconductor chip, onto an insulating substrate including a ceramic board and having conductor layers on two surfaces thereof, with a lead-free solder; warping a radiating base such that a surface of the radiating base on a side opposite to the insulating substrate is convex; and solder-connecting the insulating substrate onto the warped radiating base with the lead-free solder so as to provide a substantially flat solder-connected radiating base. | 03-20-2014 |
20140134805 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package is provided, including: providing a heat dissipating structure having a heat dissipating portion, a deformable supporting portion coupled to the heat dissipating portion, and a coupling portion coupled to the supporting portion; coupling a carrier having a semiconductor element carried thereon to the coupling portion of the heat dissipating structure to form between the carrier and the heat dissipating portion a receiving space for the semiconductor element to be received therein; and forming in the receiving space an encapsulant that encapsulates the semiconductor element. The use of the supporting portion enhances the bonding between the heat dissipating structure and a mold used for packaging, thereby preventing the heat dissipating structure from having an overflow of encapsulant onto an external surface of the heat-dissipating portion. | 05-15-2014 |
20140206150 | APPARATUS AND METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT - The present invention relates to an apparatus for manufacturing an integrated circuit ( | 07-24-2014 |
20140235018 | DIAMOND PARTICLE MOLOLAYER HEAT SPREADERS AND ASSOCIATED METHODS - Thermally regulated semiconductor devices having reduced thermally induced defects are provided, including associated methods. Such a device can include a heat spreader having a monolayer of diamond particles within a thin metal matrix and a semiconductor material thermally coupled to the heat spreader. In one aspect, the coefficient of thermal expansion difference between the heat spreader and the semiconductor material is less than or equal to about 50%. | 08-21-2014 |
20140295622 | NOVEL BUILD-UP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME - A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body. | 10-02-2014 |
20140370660 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element. | 12-18-2014 |
20140377910 | LEADLESS SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE - A leadless semiconductor package includes a package body on a leadframe that includes a die paddle and a plurality of bond pads, none of which extend as far as a lateral face of the body. During manufacture of the package, molding compound is deposited over a face of the leadframe on which the die paddle and bond pads are positioned. After the molding compound is cured, a back side of the leadframe is etched to isolate the die paddle and bond pads, back surfaces of which remain exposed at a back face of the body. During manufacture of the leadframe, a parent substrate is etched to define the die paddle and a plurality of bond pads on one side of the substrate and a plurality of cavities on the opposite face. | 12-25-2014 |
20140377911 | PACKAGE CONFIGURATIONS FOR LOW EMI CIRCUITS - An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion. | 12-25-2014 |
20150024553 | POWER MODULE PACKAGE - An integrated power module includes a substantially planar insulated metal substrate having at least one cut-out region; at least one substantially planar ceramic substrate disposed within the cut-out region, wherein the ceramic substrate is framed on at least two sides by the insulated metal substrate, the ceramic substrate including a first metal layer on a first side and a second metal layer on a second side; at least one power semiconductor device coupled to the first side of the ceramic substrate; at least one control device coupled to a first surface of the insulated metal substrate; a power overlay electrically connecting the at least one semiconductor power device and the at least one control device; and a cooling fluid reservoir operatively connected to the second metal layer of the at least one ceramic substrate, wherein a plurality of cooling fluid passages are provided in the cooling fluid reservoir. | 01-22-2015 |
20150064848 | SEMICONDUCTOR DEVICE HAVING A DIAMOND SUBSTRATE HEAT SPREADER - In accordance with one or more embodiments, a semiconductor device comprises a semiconductor die having a heat region disposed on at least one portion of the semiconductor die, and a diamond substrate disposed proximate to the semiconductor die, wherein the diamond substrate is capable of dissipating heat from the diamond substrate via at least one or more bumps coupling the diamond substrate to the heat region of the semiconductor die. | 03-05-2015 |
20150087113 | ELECTRICALLY ISOLATED POWER SEMICONDUCTOR PACKAGE WITH OPTIMIZED LAYOUT - A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink. | 03-26-2015 |
20150093859 | ELECTRONIC MODULE ASSEMBLY WITH PATTERNED ADHESIVE ARRAY - An improved electronic module assembly and method of fabrication is disclosed. A patterned array of adhesive is deposited on a laminate, to which a chip is attached. Each region of adhesive is referred to as a lid tie. A lid is placed on the laminate, and is in contact with the lid ties. The lid ties serve to add stability to the laminate and reduce flexing during thermal processing and mechanical stress. | 04-02-2015 |
20150104907 | BUMPLESS BUILD-UP LAYER PACKAGE INCLUDING AN INTEGRATED HEAT SPREADER - An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface. | 04-16-2015 |
20150125998 | METAL BUMPS FOR COOLING DEVICE CONNECTION - A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate includes depositing a first-side UBM layer on a first surface of the substrate, and forming a plurality of first-side metal bumps on the first surface of the substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the substrate, and the first surface and the second surface are opposite of each other. The method includes forming a plurality of second-side metal bumps on the second surface of the substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps. | 05-07-2015 |
20150132894 | Heat spreading substrate with embedded interconnects - Heat spreading substrate with embedded interconnects. In an embodiment in accordance with the present invention, an apparatus includes a metal parallelepiped comprising a plurality of wires inside the metal parallelepiped. The plurality of wires have a different grain structure than the metal parallelepiped. The plurality of wires are electrically isolated from the metal parallelepiped. The plurality of wires may be electrically isolated from one another. | 05-14-2015 |
20150140740 | METHOD OF FABRICATION, DEVICE STRUCTURE AND SUBMOUNT COMPRISING DIAMOND ON METAL SUBSTRATE FOR THERMAL DISSIPATION - A method of fabrication, a device structure and a submount comprising high thermal conductivity (HTC) diamond on a HTC metal substrate, for thermal dissipation, are disclosed. The surface roughness of the diamond layer is controlled by depositing diamond on a sacrificial substrate, such as a polished silicon wafer, having a specific surface roughness. Following deposition of the diamond layer, an adhesion layer, e.g. comprising a refractory metal, such as tantalum, and at least one layer of HTC metal is provided. The HTC metal substrate is preferably copper or silver, and may be provided by electroforming metal onto a thin sputtered base layer, and optionally bonding another metal layer. The electrically non-conductive diamond layer has a smooth exposed surface, preferably ≦10 nm RMS, suitable for patterning of contact metallization and/or bonding to a semiconductor device. Methods are also disclosed for patterning the diamond on metal substrate to facilitate dicing. | 05-21-2015 |
20150357238 | METHOD OF MAKING INTEGRATED CIRCUIT - Methods of fabricating integrated circuits are disclosed herein. A die having a side is provided. A conductive stud extends from the side in a direction that is substantially normal to the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud pierces the first side of the first dielectric layer. A first via is formed through the first dielectric layer between the conductive stud and the second side. The first via is electrically connected to the conductive stud. | 12-10-2015 |
20160043016 | THERMAL INTERFACE MATERIAL ON PACKAGE - A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly. | 02-11-2016 |
20160079092 | POWER DEVICE HAVING REDUCED THICKNESS - An electronic device includes at least one chip and an insulating body embedding the chip. The electronic device further includes a heat-sink in contact with the chip. The heat-sink includes a plate having a first thickness. A recess is provided in the plate that defines a central portion of the plate having a second thickness less than the first thickness. The chip is mounted to the central region of the heat-sink within the recess. The insulating body includes a surface, such as a mounting surface, including an opening exposing at least a portion of the heat-sink. The device may further include a reophore extending through a side surface of the insulating body, that reophore being in contact with the heat sink. | 03-17-2016 |
20160111300 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes the steps of placing, on a heat sink made of a metal, a semiconductor element and a frame surrounding the semiconductor element, placing solder on an upper surface of the frame, placing a cap on the solder, and heating the solder while exerting on the cap a force to be applied toward the frame without scrubbing the cap on the frame. In the heating step a heat source is brought into contact with the heat sink and the solder is heated with the heat source. | 04-21-2016 |