Class / Patent application number | Description | Number of patent applications / Date published |
438119000 | Electrically conductive adhesive | 26 |
20080206927 | ELECTRONIC COMPONENT STRUCTURE AND METHOD OF MAKING - An external component, typically a surface mount passive, is attached to a semiconductor die. In some embodiments the passive is placed directly over exposed pads on the semiconductor die and attached using conductive tape or conductive epoxy. In some embodiments the passive is attached to the semiconductor die using non-conductive adhesive and wire bonded to bond pads on the semiconductor die and/or to pads on a substrate to which the semiconductor die is attached. | 08-28-2008 |
20080286904 | Method for manufacturing semiconductor package - Provided is a method for manufacturing a semiconductor package. In the method, a wafer for a cap substrate is provided. The wafer for the cap substrate includes a plurality of vias and via electrodes on a lower surface. A wafer for a device substrate is provided. The wafer for the device substrate includes a circuit unit and a connection electrode on an upper surface. The wafer for the cap substrate and the wafer for the device substrate are primarily bonded by a medium of a primary adhesive. A trench is formed to expose the upper surface of the wafer for the device substrate to an outside along an outer edge of the primary adhesive. A secondary bonding operation is performed by a medium of a secondary adhesive to electrically connect the via electrode and the connection electrode. The wafer for the device substrate is diced along a virtual cut line. | 11-20-2008 |
20080311704 | RADIO FREQUENCY IDENTIFICATION (RFID) TAG LAMINATION PROCESS USING LINER - A method of constructing an RFID unit can include using a protective layer to hold an integrated circuit chip module to a substrate layer with an antenna unit while a conductive adhesive has not yet fully set. | 12-18-2008 |
20090111219 | WAFER-LEVEL CHIP SCALE PACKAGE AND METHOD FOR FABRICATING AND USING THE SAME - A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e., interface) to the printed circuit board for any small die. | 04-30-2009 |
20090186451 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes providing an adhesive on a supporting board, the supporting board being where a semiconductor element is to be mounted; providing a member configured to block flow of the adhesive on a first main surface of the semiconductor element, the semiconductor element having a second main surface where an outside connection terminal is provided; mounting the semiconductor element on a part of the supporting board where the adhesive is provided by pressing the semiconductor element via the member. | 07-23-2009 |
20090191669 | METHOD OF ENCAPSULATING AN ELECTRONIC COMPONENT - A procedure of packaging an electronic component is provided, comprising the following steps: step A for mount at which a conductor and a chip are temporarily mounted on a carrier removable, and next step B for encapsulation at which the conductor and the chip are encapsulated with colloid and mounted and then removed from the carrier so that the chipset after modeled without any substrate may be mounted for decreasing the costs of substrate use and design and the probability of damage of the substrate an chip due to the thermal expansion and increasing the yield factor of a finished product. | 07-30-2009 |
20090269885 | PACKAGED SEMICONDUCTOR DEVICE WITH DUAL EXPOSED SURFACES AND METHOD OF MANUFACTURING - The invention claimed is a packaged semiconductor device with dual exposed surfaces and a method of manufacturing the device. A thermal clip and one or multiple source pads are exposed on opposite ends of the device through a nonconductive molding material used to package the device. The thermal clip and source pad can be either top or bottom-exposed. The gate, source and drain leads are exposed through the molding material, and all leads are coplanar with the bottom-exposed surface. The device can have multiple semiconductor dies or various sized dies while still having a single, constant footprint. The method of manufacturing requires attaching the semiconductor die to a thermal clip, and then attaching the die with the attached thermal clip to a lead frame. The resulting device is then molded, marked, trimmed and singulated, in this order, creating a packaged semiconductor device with dual exposed surfaces. | 10-29-2009 |
20100035383 | Methods and Apparatus for Improved Thermal Performance and Electromagnetic Interference (EMI) Shielding in Leadframe Integrated Circuit (IC) Packages - A method of assembling an IC device package is provided. A leadframe is formed. At least one IC die is attached to a die attach pad portion of the leadframe. Wire bonds are coupled between the IC die and the leadframe. A cap is attached to the leadframe. A second surface of the cap includes a cavity formed therein. The cap and leadframe form an enclosure structure that substantially encloses the at least one IC die. An encapsulating material is applied to encapsulate at least the IC die. A perimeter support ring portion of the leadframe is trimmed. | 02-11-2010 |
20100081236 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH EMBEDDED INTERPOSER - A method of manufacturing a semiconductor device includes forming printed circuit board (PCB) having an embedded interposer. A semiconductor chip or a semiconductor package is mounted onto the embedded interposer using a conductive adhesive agent. The embedded interposer has substantially the same coefficient of thermal expansion (CTE) as the semiconductor chip. The embedded interposer is formed using a semiconductor wafer. | 04-01-2010 |
20100291738 | Patterned Die Attach and Packaging Method Using the Same - A semiconductor die is attached to a packaging substrate by a patterned layer of conductive metal that includes voids. The voids provide a space into which the metal may expand when heated in order to avoid placing mechanical stress on the bonds caused by mismatches in the thermal coefficients of thermal expansion of the die, the conductive metal bond layer and the substrate. An additional coating of conductive metal may be flowed over the bond lines to reinforce the bonds. | 11-18-2010 |
20100304533 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND MOUNTING STRUCTURE OF SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, including the following steps, forming a resin layer on a surface of a semiconductor chip, the surface is provided with a bump formed thereon, the resin layer having photosensitivity and adhesiveness, exposing an upper surface of the bump by removing a part of the resin layer right above the bump by exposing and then developing the resin layer, and bonding the semiconductor chip provided with a resin film formed of the resin layer face-down to a substrate, the bump of the semiconductor chip and a conductive section of the substrate being electrically connected by the resin film functioning as an adhesive. | 12-02-2010 |
20110045640 | METHOD AND SYSTEM FOR BONDING ELECTRICAL DEVICES USING AN ELECTRICALLY CONDUCTIVE ADHESIVE - A system for bonding electrical devices using an electrically conductive adhesive to adhere the electrical devices together, the system comprising: an ultrasonic transducer to generate an ultrasonic vibration; and an ultrasonic to thermal energy apparatus operatively attached to and covering an operational end of the ultrasonic transducer, the ultrasonic to thermal energy apparatus damping the ultrasonic vibration to minimize ultrasonic vibration transmitted to a first electrical device and causing the conversion of the ultrasonic vibration to a heating pulse which is conducted through the first electrical device to the adhesive; wherein the adhesive is softened by the heating pulse to bond the electrical devices together. | 02-24-2011 |
20110177655 | Formation of Through Via before Contact Processing - The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads. | 07-21-2011 |
20110189824 | METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE - In a method for manufacturing an electronic device an integrated circuit ( | 08-04-2011 |
20110237031 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over the main surface and a drain electrode of a power MOSFET over the back side, and is bonded onto the die pad portion via an Ag paste. In the device, a source lead and the source pad are electrically coupled via an Al ribbon. Over the back surface of the silicon chip, an Ag nanoparticle coated film is formed, while another Ag nanoparticle coated film is formed over the die pad portion and lead (drain lead and source lead). | 09-29-2011 |
20120034741 | POWER DEVICE PACKAGE COMPRISING METAL TAB DIE ATTACH PADDLE (DAP) AND METHOD OF FABRICATING THE PACKAGE - A metal tab die attach paddle (DAP) disposed between the lead frame and a power device die in a power device package reduces the stress exerted on the semiconductor power device die caused by the different coefficients of thermal expansion (CTE) of the semiconductor power device die and the lead frame. In addition the power device package substantially prevents impurities from penetrating into the power device package by increasing the surface creepage distance of a sealant resulting from the metal tab DAP and an optional swaging of the lead frame. | 02-09-2012 |
20120164793 | Power Semiconductor Device Package Method - Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected. | 06-28-2012 |
20120202321 | IC Device Having Low Resistance TSV Comprising Ground Connection - A method of forming a semiconductor device includes an integrated circuit (IC) die which is provided with a substrate with surfaces. At least one through substrate via (TSV) is formed through the substrate to a protruding integral tip that includes sidewalls and a distal end. A metal layer is formed on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. Completing fabrication of at least one functional circuit including at least one ground pad on the top surface of the semiconductor, wherein the ground pad is coupled to said TSV. | 08-09-2012 |
20130017652 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE PACKAGE WITH A HEATSINK - Embodiments of the present invention relate to forming semiconductor device package with a heat sink. In one embodiment, a subassembly comprising a die attached to a lead frame is formed, a heat sink is provided in a molding cavity, and the subassembly is coupled to the heat sink while the heat sink is in the molding cavity. In certain embodiments, a second component of the lead frame can be substituted for the heat sink. Such techniques can simplify the manufacturing process for semiconductor packages having a heat sink or lead frame with a second component. | 01-17-2013 |
20130316500 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method includes the steps of: providing a lead frame, including providing a concaved part in an upper face of a joint part of a die-pad-support lead of a lead frame for setting down a die pad and a tie-bar; bonding a semiconductor chip to a first principal face of the die pad via an adhesive-member layer; then, setting the lead frame between first and second molding dies having first and second cavities respectively so that the first and second cavities are opposed to each other, and the second principal face of the die pad faces toward the second cavity; and forming first and second resin sealed bodies on the sides of the first and second principal faces of the die pad respectively by resin sealing with the first and second molding dies clamping the tie-bar and a part of the lead frame surrounding the tie-bar. | 11-28-2013 |
20140179065 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes attaching a curable film to a first connection member including a first circuit terminal, attaching a conductive film to a second connection member including a second circuit terminal, and thermally compressing the first connection member to the second connection member, with the first connection member and the second connection member placed such that the curable film and the conductive film face each other. | 06-26-2014 |
20140363925 | Method for Producing a Semiconductor Module by Using an Adhesion Carrier - A method for producing a semiconductor module includes providing an adhesion carrier and a plurality of circuit carriers. The adhesion carrier has an adhesive upper side and a lower side opposite the adhesive upper side. Each of the circuit carriers includes a ceramic carrier and an upper conductor layer applied to the ceramic carrier, and a circuit carrier lower side. By placing the circuit carriers onto the adhesive upper side, the circuit carrier lower side of the circuit carriers contacts and adheres to the adhesive upper side, so that a quasi-panel is formed, in which the circuit carriers are processed while preserving the quasi-panel and can then be removed from the adhesive upper side. | 12-11-2014 |
20150111344 | METHOD OF FABRICATING A CIRCUIT - Methods of fabricating integrated circuits are disclosed herein. In one embodiment of a method. A die having a side is provided. A conductive stud is connected to the side of the die, wherein the conductive stud has a first end that is connected to the die and an opposite second end. The die is encapsulated said die except for the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud enters the first side of the first dielectric layer. A conductive layer is affixed to the second side of the first dielectric layer. The second side of the conductive stud is affixed to the conductive layer using a conductive adhesive. | 04-23-2015 |
20150294951 | METHOD FOR BONDING BARE CHIP DIES - A method is provided for assembly of a micro-electronic component comprising the steps of: providing a conductive die bonding material comprising of a conductive thermosettable resin material or flux based solder and a dynamic release layer adjacent to the conductive thermoplastic material die bonding material layer; and impinging a laser beam on the dynamic release layer adjacent to the die bonding material layer; in such a way that the dynamic release layer is activated to direct conductive die bonding material matter towards the pad structure to be treated to cover a selected part of the pad structure with a transferred conductive die bonding material; and wherein the laser beam is restricted in timing and energy, in such a way that the die bonding material matter remains thermosetting. Accordingly adhesive matter can be transferred while preventing that the adhesive is rendered ineffective by thermal overexposure in the transferring process. | 10-15-2015 |
20160064312 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a semiconductor device that can achieve downsizing of the semiconductor device. Convex portions are pressed against side surfaces other than one side surface of one chip mounting portion, thereby fixing the chip mounting portion without forming a convex portion corresponding to the one side surface of the chip mounting portion. Likewise, convex portions are pressed against side surfaces other than one side surface of the other chip mounting portion, thereby fixing the other chip mounting portion without forming a convex portion corresponding to the one side surface of the other chip mounting portion. | 03-03-2016 |
20160155719 | CHIP BONDING APPARATUS AND CHIP BONDING METHOD | 06-02-2016 |