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Including adhesive bonding step

Subclass of:

438 - Semiconductor device manufacturing: process

438106000 - PACKAGING (E.G., WITH MOUNTING, ENCAPSULATING, ETC.) OR TREATMENT OF PACKAGED SEMICONDUCTOR

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
438119000 Electrically conductive adhesive 19
Entries
DocumentTitleDate
20110195546STACKING PACKAGE STRUCTURE WITH CHIP EMBEDDED INSIDE AND DIE HAVING THROUGH SILICON VIA AND METHOD OF THE SAME - The semiconductor device package structure includes a first die with a through silicon via (TSV) open from back side of the first die to expose bonding pads; a build up layer coupled between the bonding pads to terminal metal pads by the through silicon via (TSV); a substrate with a second die embedded inside and top circuit wiring and bottom circuit wiring on top and bottom side of the substrate respectively; and a conductive through hole structure coupled between the terminal metal pads to the top circuit wiring and the bottom circuit wiring.08-11-2011
20090053858METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE USING REDISTRIBUTION SUBSTRATE - An inexpensive method of manufacturing a semiconductor package using a redistribution substrate that is relatively thin. The method includes: attaching a semiconductor chip to a redistribution substrate; attaching the redistribution substrate to which the semiconductor chip is attached to a printed circuit board; removing a support substrate of the redistribution substrate; forming via holes to expose a bond pad of the semiconductor chip and a bond finger of the printed circuit board; and filling the via holes with a conductive material. Meanwhile, a redistribution substrate to which at least one other semiconductor chip may be mounted on the redistribution substrate.02-26-2009
20100075463Method and apparatus for fabricating self-assembling microstructures - A method and apparatus for assembling microstructures onto a substrate through fluid transport. The microstructures being shaped blocks self-align into recessed regions located on a substrate such that the microstructure becomes integral with the substrate. The improved method includes a step of transferring the shaped blocks into a fluid to create a slurry. Such slurry is then dispensed evenly or circulated over the top surface of a substrate having recessed regions thereon. The microstructure via the shape and fluid tumbles onto the surface of the substrate, self-aligns, and engages into a recessed region.03-25-2010
20130034935DICING DIE-BONDING FILM - Provide is a dicing die-bonding film that prevents the occurrence of reflow cracking and that is capable of manufacturing a semiconductor device having excellent reliability with good productivity. The dicing die-bonding film of the present invention comprises at least: a dicing film in which a pressure-sensitive adhesive layer is provided on a support base material; and a die-bonding film that is provided on the pressure-sensitive adhesive layer, wherein the dicing die-bonding film has a water absorption rate of 1.5% by weight or less calculated from the following formula (1).02-07-2013
20090068794MANUFACTURING PROCESS FOR A QUAD FLAT NON-LEADED CHIP PACKAGE STRUCTURE - A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A part of the conductive layer uncovered by the patterned solder resist layer is removed so as to form a patterned conductive layer. Chips are bonded onto the patterned conductive layer such that the patterned solder resist layer and the chips are at the same side of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. At least one molding compound is formed and the molding compound and the patterned conductive layer are separated.03-12-2009
20100144099METHOD FOR MANUFACTURING PASSIVE DEVICE AND SEMICONDUCTOR PACKAGE USING THIN METAL PIECE - A method for manufacturing passive devices and semiconductor packages using a thin metal piece is provided. According to the method, an adhesive layer is formed on a dummy substrate; a thin metal piece is bonded on the adhesive layer; a masking material is attached to the thin metal piece, a dielectric layer is formed; a masking material is attached to form metal pads; a metal pad is formed, and the formed device is attached to a lower substrate using the metal pads; the adhesive layer and the dummy substrate are removed, a masking material is attached on a surface exposed, a region where passive devices are to be formed is patterned, and the thin metal piece is etched at a predetermined depth; and solder bumps for surface mounting are formed.06-10-2010
20090186450IC PACKAGING PROCESS BY PHOTO-CURING ADHESIVE - A IC packaging process includes the steps of mounting at least one retaining member on a top side of a substrate, the retaining member defining a receiving space, a chip being mounted to the substrate and located in the receiving space; forming a photo-curing adhesive layer in the receiving space, the photo-curing adhesive layer being capable of shielding the chip completely; irradiating and developing the photo-curing adhesive layer to harden a part of the photo-curing adhesive layer to define a hardened portion thereof, the other part of the photo-curing adhesive layer defining a non-hardened portion corresponding to the chip; and removing the non-hardened portion to expose an active portion of the chip.07-23-2009
20120164792MODULAR LOW STRESS PACKAGE TECHNOLOGY - A method of manufacturing a modular semiconductor subassembly: providing at least one semiconductor subassembly having a modular sidewall element of modular dimensions and a semiconductor substrate base element coupled to the modular sidewall element that has at least one semiconductor element with a layout sized to be accommodated by modular dimensions of the modular sidewall element. If a modular package protective cover is to be used: providing the modular package protective cover configured to accommodate the semiconductor subassembly in accordance with a modular design; securing the semiconductor subassembly in the modular package protective cover to create a modular package assembly; and mounting the modular package assembly to a core, with a base side of the semiconductor substrate base element in contact with the core; otherwise: mounting the at semiconductor subassembly to the core, with the base side of the semiconductor substrate base element in contact with the core.06-28-2012
20130052776FORMING METAL FILLED DIE BACK-SIDE FILM FOR ELECTROMAGNETIC INTERFERENCE SHIELDING WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a carrier material, attaching a die in the cavity, wherein a backside of the die comprises a metal filled DBF, forming a dielectric material adjacent the die and on a bottom side of the carrier material, forming a coreless substrate by building up layers on the dielectric material, and removing the carrier material from the coreless substrate.02-28-2013
20130052775SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME - A semiconductor package including a package substrate having a chip mounting region and a peripheral region and including a ground layer formed in the peripheral region, first solder balls on the package substrate in the chip mounting region, second solder balls on the ground layer, at least one semiconductor chip stacked on the package substrate in the chip mounting region, and a package cap covering the semiconductor chip and contacting the package substrate in the peripheral region may be provided. The package cap is electrically connected to the second solder balls. Methods of fabricating the semiconductor package are also provided.02-28-2013
20110003436Placement Method of an Electronic Module on a Substrate - The aim the disclosed process is to ensure maximum precision both at the level of the manufacturing of an electronic assembly from a chip with small dimensions as well as the level of the placement of such an assembly on an insulating substrate. This aim is achieved by a placement process on a substrate, of at least one electronic assembly comprising a chip having at least one electric contact on one of its faces, said contact being intended to be electrically connected to a conductive track segment. The electronic assembly is built on a holding device which seizes and holds at least one conductive track segment previously formed and a chip. A placement device places this electronic assembly thus built at a predetermined position relative to the substrate and embeds or inserts said electronic assembly into the substrate.01-06-2011
20130059419METHODS OF FORMING SEMICONDUCTOR DEVICE PACKAGES INCLUDING A SEMICONDUCTOR DEVICE AND A REDISTRIBUTION ELEMENT, METHODS OF FORMING REDISTRIBUTION ELEMENTS AND METHODS FOR PACKAGING SEMICONDUCTOR DEVICES - A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane.03-07-2013
20130183799METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a semiconductor device, which includes: preparing a semiconductor wafer; and peeling off an adhesive layer from the semiconductor wafer. The prepared semiconductor wafer includes at least one semiconductor chip having a bump electrode group formed by arraying bump electrodes in a matrix, and the adhesive layer formed on one surface having the bump electrodes. The bump electrode group is formed by arraying the bump electrodes so that the number of bump electrodes in a second direction can be smaller than that in a first direction. To peel off the adhesive layer from the semiconductor wafer, the adhesive layer is peeled off from the semiconductor wafer along the first direction from one end side of the semiconductor wafer.07-18-2013
20110039373SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection. In the semiconductor device, the insulating layer is formed over a conductive layer serving as an antenna such that the value in the thickness ratio of the insulating layer in a portion not covering the conductive layer to the conductive layer is at least 1.2, and the value in the thickness ratio of the insulating layer formed over the conductive layer to the conductive layer is at least 0.2. Further, not the conductive layer but the insulating layer is exposed in the side face of the semiconductor device, and the insulating layer covers a TFT and the conductive layer. In addition, a substrate covering an element formation layer side is a substrate having a support on its surface is used in the manufacturing process.02-17-2011
20130065363METHOD FOR MANUFACTURING A CHIP PACKAGING STRUCTURE - A method for manufacturing a chip packaging structure is disclosed. The manufacturing method includes steps of: providing a protection layer; forming a conductive trace layer on the protection layer; forming an adhesion layer on the conductive trace layer; placing a chip on the adhesion layer; and electrically connecting the chip to the conductive trace layer. Via these arrangements, the chip packaging structure made by the manufacturing method can have a smaller thickness.03-14-2013
20130065364MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of components of the material constituting a wiring substrate.03-14-2013
20090011545CHIP PACKAGE PROCESS - The present invention further provides a chip package process, which includes providing a substrate, disposing a chip on the substrate and forming a buffering compound on the substrate and the chip, wherein the buffering compound covers the chip. The present invention further provides another chip package process, which includes providing a substrate, forming a buffering compound on the substrate and disposing a chip in the buffering compound.01-08-2009
20100248428MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A wiring circuit layer 09-30-2010
20110165734MANUFACTURING METHOD OF SEMI-CONDUCTOR CHIP PACKAGE - A manufacturing method of a semiconductor chip package includes molding a semiconductor chip and a number of passive devices after arranging on a film the semiconductor chip and the passive devices located in a vacant space around the periphery of the semiconductor chip; removing the film, forming an adhesive layer in a film-removed area, and attaching a conductive layer to the adhesive layer; etching a conductive layer to thereby form a conductive circuit pattern; and providing one or more conductive pads, which electrically connect the conductive circuit pattern to the semiconductor chip and to the passive devices.07-07-2011
20120100671Semiconductor Package And Method Of Manufacturing The Same - A semiconductor package includes a circuit substrate, a semiconductor chip on the circuit substrate, an inner solder ball between the circuit substrate and the semiconductor chip, and dummy solder filling a dummy opening in at least one of an substrate insulation layer of the circuit substrate and a chip insulation layer. The dummy solder does not electrically connect the semiconductor chip with the substrate. The circuit substrate may include a base substrate, a substrate connection terminal on the base substrate, and the substrate insulation layer covering the base substrate. The semiconductor chip may include a chip connection terminal and the chip insulation layer exposing the chip connection terminal. The inner solder ball may be interposed between the substrate connection terminal and the chip connection terminal to electrically connect the circuit substrate to the semiconductor chip.04-26-2012
20110281400NEAR CHIP SCALE SEMICONDUCTOR PACKAGES - Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die.11-17-2011
20110281401SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.11-17-2011
20120238059SACRIFICIAL SUBSTRATE FILM FOR BALL LAND PROTECTION - A method of forming solder balls on package substrates includes attaching a semiconductor die to a frontside of a package substrate that includes a film over a bottomside of the package substrate including over a plurality of ball land areas configured to receive solder balls thereon, followed by forming an encapsulating mold layer over the semiconductor die. The film blocks contamination such as mold debris from reaching the ball land areas during die attachment and molding. The film is then removed from the bottomside of the package substrate after molding to expose the plurality of exposed ball land areas. Solder balls are dispensed onto the plurality of exposed ball land areas.09-20-2012
20110129964STRUCTURE COMBINING AN IC INTEGRATED SUBSTRATE AND A CARRIER, AND METHOD OF MANUFACTURING SUCH STRUCTURE - The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The IC integrated substrate has a first dielectric layer attached to the carrier. The materials of the carrier and the first dielectric layer are selected to prevent the IC integrated substrate from peeling off the carrier during processing and to allow the IC integrated substrate to naturally separate from the carrier after being cut, through the adhesion between the carrier and the first dielectric layer. The present invention also provides a method of manufacturing the above structure and a method of manufacturing electrical devices using the above structure.06-02-2011
20100105172DIRECT DIE ATTACH UTILIZING HEATED BOND HEAD - A method is provided for bonding a die comprising a solder layer which has a melting point Tm. A bond head is heated to a bond head setting temperature T04-29-2010
20110111563ADHESIVE TAPE FOR RESIN-ENCAPSULATING AND METHOD OF MANUFACTURE OF RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE - An adhesive tape for resin-encapsulating used in a method of manufacture of a resin-encapsulated semiconductor device has a base material layer and an adhesive agent layer laminated on the base material layer, a total film thickness of the base material layer and the adhesive agent layer of 25 to 40 μm. According to the adhesive tape for resin encapsulating of the present invention, resin leakage can be efficiently prevented during the resin encapsulating operation.05-12-2011
20110318881SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a semiconductor device, which prevents waste generation from being caused peeling of films and prevents failure of peeling from being caused by waste due to peeling of films. A first semiconductor substrate is used which has a structure in which a peeling layer is not formed in a section subjected to a first dividing treatment, so that the peeling layer is not exposed at the end surface of a second semiconductor substrate when the second semiconductor substrate is cut out of the first semiconductor substrate. In addition, a supporting material is provided on a layer to be peeled of the second semiconductor substrate before the second semiconductor substrate is subjected to a second dividing treatment.12-29-2011
20120156831METHOD OF MANUFACTURING CARD - This IC card is provided with a module having an inlet, an adhesive layer covering the module, and a first base material and second base material sandwiching the module with interposition of the adhesive layer. The module is disposed on one face of the first base material with interposition of a viscous layer which has a thickness that varies according to the thickness at each area of the module, and its two ends are narrower than its other parts when viewed from the outer face side of the first base material or the outer face side of the second base material. According to this IC card, it is possible to offer the IC card with a flat surface, and without occurrence of strain in the embedded IC chip.06-21-2012
20110294265SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a semiconductor element, a supporting substrate where the semiconductor element is mounted, and a capacitor provided on the semiconductor element and coupled to the supporting substrate via an outside connection terminal. The capacitor includes a valve metal part, an anodic oxide film formed on a surface of the valve metal part, and a conductive part formed on the anodic oxide film and made of a conductive material.12-01-2011
20080248614WAFER LEVEL PACKAGE WITH GOOD CTE PERFORMANCE - The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the re-distribution built up layer. Terminal Conductive bumps are coupled to the UBM.10-09-2008
20100112757ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate.05-06-2010
20100112758CONNECTING MICROSIZED DEVICES USING ABLATIVE FILMS - A method of providing connectivity to a microsized device, the method includes the steps of providing an ablative base material having at least a top surface; providing a die having a first and second surface and having bonding pads at least upon the first surface; placing the die with the at least first surface of the die contacting the at least first surface of the ablative base material; and ablating a channel in the ablative material proximate to the die.05-06-2010
20120190153METHOD FOR CONNECTING SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for connecting substrates is provided. The method includes the steps of: preparing a first wiring substrate having a first substrate including a first region and a second region which are provided with a first metal wire, wherein an area ratio between the first region and the first metal wires in the first region is different from an area ratio between the second region and the first metal wire in the second region; heating the first wiring substrate to bend the first wiring substrate; and electrically connecting a third wiring on a third substrate to the first metal wire provided on the first wiring substrate, thereby mounting the first wiring substrate on the third substrate in a manner that the first surface of the first substrate is nonparallel to the first surface of the third substrate.07-26-2012
20100120204METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A chip is bonded onto a flat face of a first support through a first bonding layer with a terminal surface of the chip turned toward the flat face of the first support. A second support is bonded onto the chip through a second bonding layer. The first support is peeled from the chip to expose the terminal surface of the chip. An insulating layer from which the terminal surface of the chip is exposed is formed on the second support.05-13-2010
20090087951Method of manufacturing wafer level package - A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased.04-02-2009
20090275173METHODS FOR REDUCING STRESS IN MICROELECTRONIC DEVICES AND MICROELECTRONIC DEVICES FORMED USING SUCH METHODS - Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One such device can include a first support member, a second support member, and a microelectronic die positioned between the first support member and the second support member such that the second support member at least approximately completely covers a surface of the die. The die is in intimate contact with both the first support member and the second support member and electrically coupled to at least one of the first support member and the second support member. The device further includes a fill material between the first and second support members and at least partially encapsulating the die. The second support member has structural material characteristics that are closer to those of the first support member than to the structural material characteristics of the fill material.11-05-2009
20080305580BONDING OF STRUCTURES TOGETHER INCLUDING, BUT NOT LIMITED TO, BONDING A SEMICONDUCTOR WAFER TO A CARRIER - An expandable membrane (12-11-2008
20110171783METHOD FOR MAKING CONTACTLESS PORTABLE OBJECTS - The invention relates to a method for manufacturing contactless portable objects with an integrated circuit. The method of the invention is characterized in that it comprises the steps of: providing a silicon wafer (07-14-2011
20080242002Apparatus and Methods for Cooling Semiconductor Integrated Circuit Package Structures - The present invention relates generally to apparatus and methods for cooling semiconductor integrated circuit (IC) chip package structures. More specifically, the present invention relates to apparatus and methods for thermally coupling semiconductor chips to a heat conducting device (e.g., copper thermal hat or lid) using a compliant thermally conductive material (e.g., thermal paste), wherein a thermal interface is designed to prevent/inhibit the formation of voids in the compliant thermally conductive material due to the flow of such material in and out from between the chips and the heat conducting device due to thermal cycling.10-02-2008
20110201157METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE HEAT SPREADER AND A MULTILEVEL CONDUCTIVE TRACE - A method of making a semiconductor chip assembly includes providing a post and a base, mounting a second adhesive on the base, mounting a substrate with a conductive pattern on the second adhesive, mounting a first adhesive on the substrate and mounting a conductive layer on the first adhesive, then flowing the first adhesive upward between the post and the conductive layer and flowing the second adhesive upward between the post and the substrate, solidifying the adhesives, then providing a conductive trace that includes a pad, a terminal, the conductive pattern, first and second vias and a selected portion of the conductive layer, mounting a semiconductor device on the post, wherein a heat spreader includes the post and the base, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.08-18-2011
20090023251Method for manufacturing semiconductor device - An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is fixed to the upper surface of the element formation layer. The element formation layer is transformed through the support base material, and peeling is generated at an interface between the element formation layer and the release layer. Peeling is performed while the liquid is being supplied so that the element formation layer and the release layer which appear sequentially by peeling are wetted with the liquid such as pure water. Electric charge generated on the surfaces of the element formation layer and the release layer can be diffused by the liquid, and discharge by peeling electrification can be eliminated.01-22-2009
20090035892Component Bonding Method, Component Laminating Method And Bonded Component Structure - It is an object of the invention to provide a component bonding method and a component laminating method that can improve productivity in the heat pressing process.02-05-2009
20080305583Adhesive sheet, dicing tape integrated type adhesive sheet, and method of producing semiconductor device - The invention provides an adhesive sheet which can be stuck to a wafer at low temperatures of 100° C. or below, which is soft to the extent that it can be handled at room temperature, and which can be cut simultaneously with a wafer under usual cutting conditions; a dicing tape integrated type adhesive sheet formed by lamination of the adhesive sheet and a dicing tape; and a method of producing a semiconductor device using them. In order to achieve this object, the invention is characterized by specifying the breaking strength, breaking elongation, and elastic modulus of the adhesive sheet in particular numerical ranges.12-11-2008
20080305581Reducing stress in a flip chip assembly - In one embodiment, the present invention includes a method for depositing lead-free bumps on a package substrate, depositing an alloy material on the lead-free bumps, attaching a semiconductor die including conductive bumps to the package substrate so that the conductive bumps contact the alloy material, and heating attached components to reflow the alloy material to form a joint therebetween. Other embodiments are described and claimed.12-11-2008
20080242001Lid Attachment Mechanism - Apparatus and methods for assembling semiconductor chips packages are provided. In one aspect, a method of manufacturing is provided that includes placing a first set of semiconductor chip package substrates in a first group of receptacles of a first processing station. Each of the first set of semiconductor chip package substrates has a first footprint. The receptacles of the first group being dimensioned to accommodate the first footprint. A second set of semiconductor chip package substrates is placed in a second group of receptacles of the first processing station. Each of the second set of semiconductor chip package substrates has a second footprint larger than the first footprint. The receptacles of the second group being dimensioned to accommodate the second footprint. A first set of lids is placed on the first set of semiconductor chip package substrates and a second group of lids is placed on the second set of semiconductor chip package substrates.10-02-2008
20080213943THERMOSETTING DIE BONDING FILM - The thermosetting die bonding film of the invention is a thermosetting die bonding film used to produce a semiconductor device, which contains, as main components, 5 to 15% by weight of a thermoplastic resin component and 45 to 55% by weight of a thermosetting resin component, and has a melt viscosity of 400 Pa·s or more and 2500 Pa·s or less at 100° C. before the film is thermally set.09-04-2008
20100144100Method of Forming Quad Flat Package - A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.06-10-2010
20090280602DOUBLE WAFER CARRIER PROCESS FOR CREATING INTEGRATED CIRCUIT DIE WITH THROUGH-SILICON VIAS AND MICRO-ELECTRO-MECHANICAL SYSTEMS PROTECTED BY A HERMETIC CAVITY CREATED AT THE WAFER LEVEL - A TSV-MEMS packaging process is provided. The process includes forming TSVs in the front side of the product wafer, and attaching a first carrier to the front side of the product wafer, subsequent to forming TSVs. The process further includes thinning the back side of the product wafer to expose TSV tips, detaching the first carrier from the front side of the product wafer, and transferring the thinned wafer to a second carrier with back side adhered to the second wafer carrier. Semiconductor components are added to the front side of the product wafer, followed by forming a hermetic cavity over the added semiconductor components, and detaching the second carrier from the back side of the product wafer. Wafer level processing continues after detaching the second carrier.11-12-2009
20090004781METHOD OF FABRICATING A SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER - A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.01-01-2009
20090325347APPARATUSES AND METHODS TO ENHANCE PASSIVATION AND ILD RELIABILITY - Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices.12-31-2009
20080305582POWER SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE - A semiconductor chip packaging structure is fabricated by using a dielectric film with two surfaces, and a power semiconductor chip with an active surface having contact pads. An adhesive layer is used to connect the first surface of the dielectric film and the active surface of the power semiconductor chip. A patterned electrically conductive layer is formed adjacent to the second surface of the film, extending through holes in the film to the contact pads.12-11-2008
20090081830Semiconductor Device and Method of Laser-Marking Wafers with Tape Applied to its Active Surface - A method of laser-marking a semiconductor device involves providing a semiconductor wafer having a plurality of solder bumps formed on contact pads disposed on its active surface. The solder bumps have a diameter of about 250-280 μm. A backgrinding tape is applied over the solder bumps. The tape is translucent to optical images. A backside of the semiconductor wafer, opposite the active surface, undergoes grinding to reduce wafer thickness. The backside of the semiconductor wafer is laser-marked while the tape remains applied to the solder bumps. The laser-marking system including an optical recognition device, control system, and laser. The optical recognition device reads patterns on the active surface through the tape to control the laser. The tape reduces wafer warpage during laser-marking to about 0.3-0.5 mm. The tape is removed after laser-marking the backside of the semiconductor wafer.03-26-2009
20100003788METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE HEAT SPREADER AND VERTICAL SIGNAL ROUTING - The present invention provides a method of making a semiconductor chip assembly that includes providing a post and a base, mounting an adhesive on the base including inserting the post through an opening in the adhesive, mounting a substrate on the adhesive including inserting the post into an aperture in the substrate to form a gap in the aperture between the post and the substrate, then flowing the adhesive into and upward in the gap, solidifying the adhesive, then mounting a semiconductor device on a heat spreader that includes the post and the base, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader. The substrate includes first and second conductive layers and a dielectric layer therebetween, and the assembly provides the vertical signal routing between a pad at the first conductive layer and a terminal below the adhesive.01-07-2010
20130217188Structures and Formation Methods of Packages with Heat Sinks - A device includes a package component, and a die over and bonded to the package component. The die includes a substrate. A heat sink is disposed over and bonded to a back surface of the substrate through direct bonding.08-22-2013
20130217189METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING ELECTRONIC DEVICE - A method of manufacturing a semiconductor device, includes: providing a first adhesive layer on a support member; providing a film on the first adhesive layer; arranging a semiconductor element on the film; providing a resin layer on the film on which the semiconductor element is arranged, and forming a substrate including the semiconductor element and the resin layer on the film; and separating the film and the substrate from the first adhesive layer.08-22-2013
20090042338Capping Coating for 3D Integration Applications - A structure for a semiconductor component is provided having a bi-layer capping coating integrated and built on supporting layer to be transferred. The bi-layer capping protects the layer to be transferred from possible degradation resulting from the attachment and removal processes of the carrier assembly used for layer transfer. A wafer-level layer transfer process using this structure is enabled to create three-dimensional integrated circuits.02-12-2009
20100248427METHOD OF HANDLING A THIN WAFER - A method of handling a thin wafer includes forming a support structure at the edge of a thinned wafer that is encapsulated by a protection layer. The support structure can be an adhesive layer enclosing the protection layer, a dielectric-filled trench embedded in the thinned wafer and surrounding the protection layer, or a housing affixing the edge of the thinned wafer.09-30-2010
20080318364PROCESS APPLYING DIE ATTACH FILM TO SINGULATED DIE - Methods and systems of applying a plurality of pieces of die attach film to a plurality of singulated dice are provided. The method can involve making intervals between rows and columns of a plurality of pieces of die attach film. The interval can be made by expanding an underlaid expandable film on which the plurality of pieces of die attach film are placed or by removing portions of the die attach film between rows and columns of the plurality of pieces of die attach film. The method can further involve placing a plurality of singulated dice back side down on the plurality of pieces of die attach film.12-25-2008
20090246916Chip Package with Pin Stabilization Layer - Various methods and apparatus for semiconductor packing are disclosed. In one aspect, a method of manufacturing is provided that includes coupling first ends of plural conductor pins to a first surface of a semiconductor chip package substrate. A layer is formed on the first surface that engages and resists lateral movement of the conductor pins while leaving second ends of the conductor pins exposed.10-01-2009
20090253232Microwave Cure of Semiconductor Devices - A method for curing an adhesive is disclosed. A preferred embodiment comprises securing a cover onto a substrate to enclose a MEMs device using an adhesive. The adhesive is either partially or fully cured using microwave radiation. Another preferred embodiment utilizes the microwave radiation to cure an encapsulant placed to protect a semiconductor device.10-08-2009
20130011971FABRICATING METHOD OF SEMICONDUCTOR PACKAGE STRUCTURE - A fabricating method of a semiconductor package structure is provided. A dielectric layer having a first surface and a second surface is provided. A patterned metal layer has been formed on the first surface of the dielectric layer. An opening going through the first and the second surfaces is formed. A carrier having a third surface and a fourth surface is formed at the second surface. A portion of the third surface is exposed by the opening of the dielectric layer. A semiconductor die having a joining surface and a side-surface is joined in the opening. At least a through hole going through the third and the fourth surfaces is formed. A metal layer having at least a heat conductive post extending from the fourth surface of the carrier to the through hole and disposed in the through hole and a containing cavity is formed on the fourth surface.01-10-2013
20120196404Adhesive Compositions for a Semiconductor, an Adhesive Sheet for a Semiconductor and a Production Method of a Semiconductor Device - An adhesive composition for a semiconductor includes an acrylic polymer (A), an epoxy-based heat curable resin (B), a heat curing agent (C), a silane compound (D) having an organic functional group, molecular weight of 300 or more and an alkoxy equivalent of larger than 13 mmol/g, and a silane compound (E) having an organic functional group, molecular weight of 300 or less and an alkoxy equivalent of 13 mmol/g or less.08-02-2012
20100261315WAFER LEVEL PACKAGING METHOD - A wafer level packaging method is revealed. Firstly, a wafer with a plurality of bumps disposed on a surface is provided. Placing a dielectric tape on a mold plate is followed. Then, the wafer is laminated with the mold plate to make the dielectric tape be compliantly bonded to the surface of the wafer and to make the bumps be embedded in the dielectric tape. After removing the mold plate, flattening the dielectric tape to form a plurality of exposed surfaces of the bumps wherein the exposed surfaces and the flattened surface of the dielectric tape are coplanar. Therefore, the exposed surfaces of the bumps can be regarded as effective alignment points for easy pattern recognition of the wafer level packaged wafers during singulation process.10-14-2010
20100216282LOW COST BONDING TECHNIQUE FOR INTEGRATED CIRCUIT CHIPS AND PDMS STRUCTURES - Methods of bonding a structure fabricated in polydimethylsiloxane (PDMS) and an integrated circuit chip. The procedures for bonding include providing a substrate, affixing the integrated circuit to the substrate, as needed preparing the surface of the integrated circuit chip to permit bonding, aligning the PDMS structure and the features of the integrated circuit chip, and applying a bonding agent. The bonding agent is cured by exposure to a thermal regime for a suitable length of time. Depending on relative sizes, in some cases, a plural number of PDMS structures can be attached to one chip, or a single PDMS structure can be bonded to multiple chips. In some cases, the integrated circuit chip operates wirelessly. In other situations, the substrate provides electrical communication from the integrated circuit chip to electronic components.08-26-2010
20100184256RESIN SEALING METHOD OF SEMICONDUCTOR DEVICE - A resin sealing method of a semiconductor device includes: positioning semiconductor devices at predetermined positions of an adhesive layer formed on a support body and adhering the semiconductor devices thereto, sealing a part of each of the semiconductor devices with resin by curing a first seal resin in a fluidization state so as to fix the semiconductor devices adhered to the predetermined positions of the adhesive layer formed on the support body, setting the semiconductor devices fixed to the predetermined positions of the adhesive layer formed on the support body in a mold and sealing the exposure parts of the semiconductor devices exposed from the first seal resin with a second seal resin, and removing the support body and the adhesive layer from the semiconductor devices sealed with the resin.07-22-2010
20100151629MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES - A wiring circuit layer 06-17-2010
20090075429Sheet-Like Underfill Material and Semiconductor Device Manufacturing Method - A sheet-like underfill material includes a base and adhesive layer provided peelably on the base for use in a flip chip mounting process in the manufacture of a semiconductor device. The process includes laminating a sheet-like underfill material onto a circuit face of a semiconductor wafer having bumps on its circuit face and, simultaneously, allowing the bumps to pierce the adhesive layer and allowing the tops of the bumps to penetrate the base. The base has a storage elastic modulus of 1.0×1003-19-2009
20120142147WIRING BOARD WITH BUILT-IN ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME - A wiring board with a built-in electronic component includes a core substrate having a penetrating hole formed in the core substrate, an electronic component accommodated in the penetrating hole in the core substrate, a conductive pattern layer formed on a first surface of the core substrate and including a first conductive pattern and a second conductive pattern, and an interlayer insulation layer formed over the conductive pattern layer and the first surface of the core substrate. The second conductive pattern is formed adjacent to a periphery of the penetrating hole and contoured such that a sheet for positioning the electronic component in the penetrating hole is laminated horizontally with respect to the first surface of the core substrate over the penetrating hole.06-07-2012
20100197080ADHESIVE SHEET FOR MANUFACTURING SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING THE SHEET, AND SEMICONDUCTOR DEVICE OBTAINED BY THE METHOD - The adhesive sheet for manufacturing a semiconductor device is an adhesive sheet for manufacturing a semiconductor device used when a semiconductor element is adhered to an adherend and the semiconductor element is wire-bonded, and is a peelable adhesive sheet in which the 180 degree peeling adhesive strength against a silicon wafer is 5 (N/25 mm width) or less.08-05-2010
20110129965METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE SYSTEM WITH DIE SUPPORT PAD - A method for manufacturing a semiconductor package system includes: providing a leadframe, having an open center, with leads adjacent to a peripheral edge of the leadframe; making a die support pad, formed without tie bars, separately from the leadframe; providing a coverlay tape for positioning the support pad centered within the leadframe; attaching a semiconductor die to the die support pad through a die attach adhesive, the semiconductor die being spaced from the leads; and connecting a bonding pad on the semiconductor die to one of the leads using a bonding wire.06-02-2011
20110129963Clipless Integrated Heat Spreader Process and Materials - In one or more embodiments, a method comprising applying thermo compression to a package assembly including a lid, a die, and a package substrate to assemble the package assembly is disclosed. The method may include assembling the package assembly without coupling a biasing mechanism to the lid. Heat may be applied to a bond head coupled with a pick and place tool. Heat may be applied to a bond stage coupled to a carrier for holding the package assembly during processing. An adhesive applied to the lid or package substrate may be allowed to at least partially cure. The method may further include, in an oven, reflowing a thermal interface material (TIM) coupled to the lid and the die, curing the TIM, and/or curing the adhesive, without using clips.06-02-2011
20100297813Semiconductor package with position member - The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package.11-25-2010
20130143362ORGANIC ELECTRONIC DEVICES - A technique comprising: mounting a device substrate on a processing support, forming one or more electronic elements on the device substrate with the device substrate thus mounted on the processing support; wherein the device substrate comprises an organic support structure, and provides primary protection for the overlying electronic elements against the ingress of a degrading species from a side of the device substrate opposite to the one or more electronic elements.06-06-2013
20110045638HEAT RESISTANT MASKING TAPE AND USAGE THEREOF - The present invention provides a masking tape which can be easily released without leaving an adhesive residue. A heat resistant masking tape, comprising (1) a heat resistant backing film layer, and (2) a pressure-sensitive adhesive layer disposed on the heat resistant backing film layer, wherein the adhesive layer comprises a polymer having a solubility parameter (SP) value at 25° C. of 20 MPa02-24-2011
20110244631SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND WIRING BOARD - In a semiconductor device manufacturing method, a semiconductor chip is mounted on a support board so as to expose a side of the semiconductor chip on which a plurality of terminal electrodes are provided. An insulating layer is formed so as to cover the side of the semiconductor chip on which the terminal electrodes are provided. Through electrodes connecting to the terminal electrodes and piercing the insulating layer are formed. Metal wirings connecting to the through electrodes are formed on the insulating layer. External terminal electrodes connecting the metal wiring are formed. Second spacing, spacing between the adjacent external terminal electrodes, is larger than first spacing, spacing between the adjacent terminal electrodes.10-06-2011
20100003787METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE HEAT SPREADER AND HORIZONTAL SIGNAL ROUTING - The present invention provides a method of making a semiconductor chip assembly that includes providing a post and a base, mounting an adhesive on the base including inserting the post through an opening in the adhesive, mounting a substrate on the adhesive including inserting the post into an aperture in the substrate to form a gap in the aperture between the post and the substrate, then flowing the adhesive into and upward in the gap, solidifying the adhesive, then mounting a semiconductor device on a heat spreader that includes the post and the base, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader. The substrate includes first and second conductive layers and a dielectric layer therebetween and provides horizontal signal routing between a pad and a terminal at the first conductive layer.01-07-2010
20120244664REDUCING WARPAGE FOR FAN-OUT WAFER LEVEL PACKAGING - Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.09-27-2012
20100062569LAYER HAVING FUNCTIONALITY, METHOD FOR FORMING FLEXIBLE SUBSTRATE HAVING THE SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - It is an object of the present invention to provide a method for forming a layer having functionality including a conductive layer and a colored layer and a flexible substrate having a layer having functionality with a high yield. Further, it is an object of the present invention to provide a method for manufacturing a semiconductor device that is small-sized, thin, and lightweight. After coating a substrate having heat resistance with a silane coupling agent, a layer having functionality is formed. Then, after attaching an adhesive to the layer having functionality, the layer having functionality is peeled from the substrate. Further, after coating a substrate having heat resistance with a silane coupling agent, a layer having functionality is formed. Then, an adhesive is attached to the layer having functionality. Thereafter, the layer having functionality is peeled from the substrate, and a flexible substrate is attached to the layer having functionality.03-11-2010
20110059578METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE HEAT SPREADER, A SIGNAL POST AND A CAVITY - A method of making a semiconductor chip assembly includes providing a thermal post, a signal post and a base, mounting an adhesive on the base including inserting the thermal post into a first opening in the adhesive and the signal post into a second opening in the adhesive, mounting a conductive layer on the adhesive including aligning the thermal post with a first aperture in the conductive layer and the signal post with a second aperture in the conductive layer, then flowing the adhesive upward between the thermal post and the conductive layer and between the signal post and the conductive layer, solidifying the adhesive, providing a conductive trace that includes a pad, a terminal and the signal post, wherein the pad includes a selected portion of the conductive layer, mounting a semiconductor device on the thermal post, wherein a heat spreader includes the thermal post and the base and the semiconductor device extends into a cavity in the thermal post, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.03-10-2011
20090023250APPARATUS AND METHOD FOR PRODUCING SEMICONDUCTOR MODULES - An apparatus and method for producing semiconductor modules is disclosed. One embodiment provides for bonding at least one semiconductor die onto a carrier including a support film strip, the support film having applied an adhesive layer to one of its surfaces to attach the semiconductor die, and a pressure tool to press the semiconductor die and the support film strip onto the carrier to permanently contact the at least one semiconductor die to the carrier.01-22-2009
20110151625HEAT-RESISTANT ADHESIVE SHEET FOR SUBSTRATELESS SEMICONDUCTOR PACKAGE FABRICATION AND METHOD FOR FABRICATING SUBSTRATELESS SEMICONDUCTOR PACKAGE USING THE ADHESIVE SHEET - The present invention is intended to solve the following problems with a method for fabricating a substrateless semiconductor package using an adhesive sheet as a temporary fixing supporter. A chip can be displaced from a specified position by pressure during resin encapsulation because the chip is not properly held by the adhesive sheet. If such displacement occurs, the relative positional relationship between the chip and an interconnect to be connected to a specified position in a subsequent wiring step also changes by the displacement of the chip from the specified position. Another problem is that if adhesive deposits occur during peeling of the adhesive sheet and the surface of a package is contaminated with the adhesive deposits, adhesive components left on the surface of the chip can inhibit connection between the interconnect and the chip in a subsequent wiring step. To solve these problems, the present invention provides an adhesive sheet for semiconductor device fabrication that is attached to a substrateless semiconductor chip when the chip is encapsulated with resin. The adhesive sheet includes a base material layer and an adhesive layer. The adhesive layer has a specific adhesion strength and peel strength.06-23-2011
20110151626METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE/POST HEAT SPREADER AND ASYMMETRIC POSTS - A method of making a semiconductor chip assembly includes providing first and second posts, first and second adhesives and a base, wherein the first post extends from the base in a first vertical direction into a first opening in the first adhesive and is located within a periphery of the second post, the second post extends from the base in a second vertical direction into a second opening in the second adhesive and the base is sandwiched between and extends laterally from the posts, then flowing and solidifying the adhesives, then providing a conductive trace that includes a pad and a terminal, wherein the pad extends beyond the base in the first vertical direction and the terminal extends beyond the base in the second vertical direction, providing a heat spreader that includes the posts and the base, then mounting a semiconductor device on the first post, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.06-23-2011
20090253233METHOD OF FABRICATING BONDING STRUCTURE - A method of fabricating a bonding structure having compliant bumps includes first providing a first substrate and a second substrate. The first substrate includes first bonding pads. The second substrate is disposed on one side of the first substrate and includes second bonding pads and compliant bumps disposed thereon. The second bonding pads are opposite to the first bonding pads. Next, a non-conductive adhesive layer and ball-shaped spacers are formed between the first and the second substrates. Finally, the first substrate, the non-conductive adhesive layer, and the second substrate are compressed, such that the compliant bumps on the second bonding pads of the second substrate pass through the non-conductive adhesive layer and are electrically connected to the first bonding pads of the first substrate, respectively. The ball-shaped spacers are distributed in the non-conductive adhesive layer sandwiched between the first and the second substrates for maintaining the gap therebetween.10-08-2009
20110256669DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE - The present invention provides a dicing tape-integrated film for semiconductor back surface, including a film for flip chip type semiconductor back surface for protecting a back surface of a semiconductor element flip chip-connected onto an adherend, and a dicing tape, the dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material, the film for flip chip type semiconductor back surface being formed on the pressure-sensitive adhesive layer, in which the pressure-sensitive adhesive layer is a radiation-curable pressure-sensitive adhesive layer whose pressure-sensitive adhesive force toward the film for flip chip type semiconductor back surface is decreased by irradiation with a radiation ray.10-20-2011
20120064671METHOD FOR PRODUCING CHIP ELEMENTS EQUIPPED WITH WIRE INSERTION GROOVES - The invention relates to a method for producing chip elements provided with a groove, comprising the following steps: on an interconnect substrate, providing a conductive track arranged to connect a contact area of an active surface of a chip to an area corresponding to a first wall of the groove; growing a contact bump by electrodeposition on the conductive track at the level of the area corresponding to the first wall of the groove; assembling the chip on the substrate via its active surface so that a side wall of the chip forms the bottom of the groove; machining the chip via its rear surface in parallel to the substrate while measuring the distance between the rear surface of the chip and the contact bump; stopping machining when the measured distance reaches a required value; and assembling by bonding a plate to the rear surface of the chip so as to form a second wall of the groove.03-15-2012
20110086469MODULAR LOW STRESS PACKAGE TECHNOLOGY - A method of manufacturing a protected package assembly: providing a protective modular package cover in accordance with a modular design; selectively applying an adhesive to the cross member of each subassembly receiving section of the protective modular package cover that will receive a subassembly to form an adhesive layer of the protective modular package cover; encapsulating the one or more subassemblies in the subassembly receiving sections on the selectively applied adhesive layer to generate a protected package assembly; and controlling application of a distributed downward clamping force applied to the top surfaces of the subassemblies received by the protective modular package cover and useful for mounting the protected package assembly to a core through activation of fastener elements and cross members of the subassembly receiving sections.04-14-2011
20100330745PROCESS FOR PRODUCING A SEMICONDUCTOR DEVICE - The process for producing a semiconductor device of the invention is a process for producing a semiconductor device, comprising: a temporarily bonding step of bonding a semiconductor element temporarily on an adherend through an adhesive sheet, a semi-curing step of heating the adhesive sheet under predetermined conditions, thereby turning the sheet into a semi-cured state that the shearing adhering strength of the sheet to the adherend is 0.5 MPa or more, and a wire bonding step of causing the semiconductor element to undergo wire bonding in the state that the adhesive sheet is semi-cured.12-30-2010
20110076804POWER DEVICE PACKAGES AND METHODS OF FABRICATING THE SAME - Provided is a power device package including: a substrate including at least one first die attach region; at least one first power semiconductor chip and at least one second power semiconductor chip that are stacked in order on the first die attach region; at least one die attach paddle that is disposed between the at least one first power semiconductor chip and the at least one second power semiconductor chip, wherein the die attach paddle comprises an adhesive layer that is attached to a top surface of the first power semiconductor chip; a conductive pattern including a second die attach region, on which the second semiconductor chip is mounted, and a wire bonding region that is electrically connected to the second die attach region; and an interlayer member between the adhesive layer and the conductive pattern; and a plurality of firs leads electrically connected to at least one of the at least one first power semiconductor chip and the at least one second power semiconductor chip.03-31-2011
20090197374METHOD OF FABRICATING CHIP PACKAGE STRUCTURE - A chip package structure includes a chip, a lead frame, first and second bonding wires, an upper encapsulant, a first lower encapsulant, and a second lower encapsulant. The chip has an active surface, a back surface, and chip bonding pads disposed on the active surface. The lead frame having an upper surface and a lower surface includes a die pad, leads, and at least a bus bar. The back surface of the chip is adhered to the die pad. The leads surround the die pad. The bus bar is disposed between the die pad and the leads. The first bonding wires are connected to the chip bonding pads and the bus bar. The second bonding wires are connected to the bus bar and the leads. The upper encapsulant encapsulates the upper surface of the lead frame, the chip, the first bonding wires, and the second bonding wires.08-06-2009
20120309131SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a technique that can improve the data retention characteristic of an MRAM device by improving the resistance against an external magnetic field in a semiconductor device including the MRAM device.12-06-2012
20100190297METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE HEAT SPREADER AND A CAVITY IN THE POST - A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a substrate on the adhesive including aligning the post with an aperture in the substrate, then flowing the adhesive into and upward in a gap located in the aperture between the post and the substrate, solidifying the adhesive, then etching the post to form a cavity in the post, then mounting a semiconductor device on the post, wherein a heat spreader includes the post and the base and the semiconductor device extends into the cavity, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader.07-29-2010
20110263078METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include die bonding to bond a semiconductor element to a first position of a base member via a bonding layer provided on one surface of the semiconductor element. The method can include wire bonding to connect a terminal formed on the semiconductor element to a terminal formed on the base member by a bonding wire. In addition, the method can include sealing to seal the semiconductor element and the bonding wire. Viscosity of the bonding layer in the bonding is controlled not to exceed the viscosity of the bonding layer in the sealing.10-27-2011
20100029046INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONCAVE TERMINAL - An integrated circuit package system includes: connecting a concave terminal and an integrated circuit; and forming an encapsulation, having a bottom side, over the integrated circuit and the concave terminal with the concave terminal within the encapsulation.02-04-2010
20090239341IC PACKAGING PROCESS - An IC packaging process includes the steps of preparing a substrate having a chip-receiving place formed on a front side thereof; creating a dam layer on the front side of the substrate; coating an ultraviolet adhesive layer on the dam layer; removing a part of the ultraviolet adhesive layer that corresponds to the chip-receiving place; removing a part of the dam layer that corresponds to the chip-receiving place; mounting a chip to the chip-receiving place in the open chamber and bonding wires between the substrate and the chip for electrical connection of the chip and the substrate; and mounting a cover layer on the ultraviolet adhesive layer and then heating the ultraviolet adhesive layer to adhesively fasten the cover layer on the dam layer. Accordingly, the IC packaging process effectively reduces the adhesive squeeze-out to prevent it from damage to the chip.09-24-2009
20110117703FABRICATION OF ELECTRONIC DEVICES INCLUDING FLEXIBLE ELECTRICAL CIRCUITS - A packaged electronic device includes a die, a flexible circuit structure, and a barrier film disposed on the die. The die includes die circuitry and electrical contacts. The flexible circuit structure is bonded directly to the die, and includes electrical conductors encapsulated by structural layers. Each electrical conductor contacts a respective electrical contact. The electronic device is encapsulated by the barrier film and one or more of the structural layers.05-19-2011
20090081829METHOD OF ADHERING WIRE BOND LOOPS TO REDUCE LOOP HEIGHT - A method of reducing wire bond loop heights in wire bonds electrically connecting an integrated circuit die with a contact pad to a printed circuit board with a conductor, by mounting the integrated circuit die such that the contact pad is spaced from the conductor, positioning an adhesive surface between the contact pad and the conductor on the printed circuit board, attaching wire to one of the contact pad or the conductor, drawing the wire towards the other of the contact pad or the conductor, allowing the wire to contact the adhesive surface, and, attaching the wire to the other of the contact pad of the conductor to form a wire bond adhered to the adhesive surface and a point intermediate its ends.03-26-2009
20110306168INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - An integrated circuit package system and method of manufacture thereof includes: forming an area array substrate; mounting surface conductors on the area array substrate; and molding a molded package body, having a step surrounding a core section, on the area array substrate and the surface conductors, the step providing access to the surface conductors including providing a non-vertical slope from the core section to the step.12-15-2011
20130196471STRESS-ENGINEERED INTERCONNECT PACKAGES WITH ACTIVATOR-ASSISTED MOLDS - A method includes providing a pad chip having contact pads, providing a spring chip having micro-springs, applying a chemical activator to one of either the pad chip or the spring chip, applying an adhesive responsive to the chemical activator on the other of the pad chip or the spring chip, aligning the pad chip to the spring chip such that the micro-springs will contact the contact pads, and pressing the pad chip and the spring chip together such that the chemical activator at least partially cures the adhesive.08-01-2013
20090263936Insulating Liquid Die-Bonding Agent And Semiconductor Device - An insulating liquid die-bonding agent for bonding a semiconductor-chip-mounting member to an active surface of a semiconductor chip, said agent comprising: (A) a mixture of (a-1) an organopolysiloxane resin having alkenyl groups and (a-2) a linear-chain organopolysiloxane having in one molecule at least two alkenyl groups; (B) an organopolysiloxane having in one molecule at least two silicon-bonded hydrogen atoms; (C) an organic silicon compound having in one molecule at least one silicon-bonded alkoxy groups; (D) insulating spherical silicone rubber particles having an average diameter of 0.1 to 50 μm and having a type A durometer hardness according to JIS K 6253 equal to or below 80; and (E) a hydrosilylation-reaction catalyst, may not damage the active surface of the semiconductor chip, is well suited for screen printing, is resistant to the formation of voids on the interface between the semiconductor chip and the die-bonding agent, and does not lose its wire-bonding properties.10-22-2009
20090298235CLIPLESS INTEGRATED HEAT SPREADER PROCESS AND MATERIALS - In one or more embodiments, a method comprising applying thermo compression to a package assembly including a lid, a die, and a package substrate to assemble the package assembly is disclosed. The method may include assembling the package assembly without coupling a biasing mechanism to the lid. Heat may be applied to a bond head coupled with a pick and place tool. Heat may be applied to a bond stage coupled to a carrier for holding the package assembly during processing. An adhesive applied to the lid or package substrate may be allowed to at least partially cure. The method may further include, in an oven, reflowing a thermal interface material (TIM) coupled to the lid and the die, curing the TIM, and/or curing the adhesive, without using clips.12-03-2009
20120040498SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor device package includes a semiconductor chip including a conductive pad, a die pad on which the semiconductor chip is mounted and having a first thickness, a lead pattern including a first portion disposed adjacent to the edge of the die pad and having the first thickness and a second portion having a second thickness greater than the first thickness, a heat radiation member disposed on the die pad and the lead pattern and including a groove formed at its bottom surface, and a conductive line disposed to electrically connect the conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove.02-16-2012
20090053857SEMICONDUCTOR PACKAGING METHOD - The present invention relates to a semiconductor packaging method. The method comprises (S02-26-2009
20110318882METHOD OF RESTRICTING CHIP MOVEMENT UPON BONDING TO RIGID SUBSTRATE USING SPRAY COATABLE ADHESIVE - A method of bonding a chip to a wafer at precise alignment suitable for fabricating a heater chip in an ink jet printhead is provided. The method includes spray coating an adhesive composition on a surface of a substrate, aligning and tacking at least one chip to the substrate coated with the adhesive composition, exposing the substrate tacked with at least one chip coated with the adhesive composition to radiation and heat, and performing thermal compression bonding. The method uses a spray coatable adhesive composition comprising a thermally activated adhesive and a photoacid generator.12-29-2011
20090053859Non-random array anisotropic conductive film (ACF) and manufacturing process - The present invention discloses structures and manufacturing processes of an ACF of improved resolution and reliability of electrical connection using a non-random array of microcavities of predetermined configuration, shape and dimension. The manufacturing process includes the steps of (i) fluidic filling of conductive particles onto a substrate or carrier web comprising a predetermined array of microcavities, or (ii) selective metallization of the array followed by filling the array with a filler material and a second selective metallization on the filled microcavity array. The thus prepared filled conductive microcavity array is then over-coated or laminated with an adhesive film.02-26-2009
20090246915Adhesive Composition, Adhesive Sheet and Production Method of Semiconductor Device - The object of the present invention is to provide an adhesive composition that enables to produce conforming products with a high manufacturing yield and without breaking or chipping of the chips in the picking-up step and that enables to stably connect a wire without contaminating a wire pad part disposed at the circumference of a bonding surface during a wire bonding step that is performed after die bonding, even in the case of chips being reduced in a thickness.10-01-2009
20100055842THERMOSETTING DIE-BONDING FILM - The thermosetting die-bonding film of the present invention is used in manufacturing a semiconductor device, has at least an epoxy resin, a phenol resin, and an acrylic copolymer, and the ratio X/Y is 0.7 to 5 when X represents a total weight of the epoxy resin and the phenol resin and Y represents a weight of the acrylic copolymer.03-04-2010
20120003793METHOD FOR MANUFACTURING EMBEDDED SUBSTRATE - A method for manufacturing an embedded substrate is disclosed. The method for manufacturing an embedded substrate, which includes a core substrate formed with a pattern on both surfaces thereof and formed with a cavity penetrating from an upper part thereof to a lower part thereof, a chip embedded in the cavity, and a first insulator and a second insulator provided respectively on either surface of the core substrate so as to protect the pattern, includes: preparing the core substrate; laminating the first insulator on a lower surface of the core substrate so as to cover a lower side of the cavity; forming an adhesive layer on the first insulator that is exposed through the cavity; embedding the chip in the cavity by attaching the chip on the adhesive layer; and laminating the second insulator on an upper surface of the core substrate.01-05-2012
20130183800CIRCUIT BOARD STRUCTURE AND FABRICATION THEREOF - A circuit board structure and a fabrication method thereof are disclosed. The circuit board structure includes a carrying board having a first and an opposite second surface and having at least one through cavity formed therein; a semiconductor chip disposed in the through cavity of the carrying board; an adhesive material filling the gap between the through cavity of the carrying board and the semiconductor chip to fix the semiconductor chip in the through cavity; and a reinforcing layer disposed on the second surface of the carrying board and the inactive surface of the semiconductor chip, thereby increasing the strength of the carrying board as well as the reliability of the circuit board.07-18-2013
20120058605METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - When forming a conductive film by a method comprising sputtering after grinding the back surface of a semiconductor substrate, in order to avoid discharge from a part of an adhesive flown out at the outer periphery of the substrate, wherein the adhesive is used to fix the substrate to a support during grinding, at least the substrate end or the adhesive is removed after grinding the semiconductor substrate and before forming the conductive film, so that a gap between the substrate end and the adhesive may have a predetermined size.03-08-2012
20120058604MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE CARRIER AND MANUFACTURING METHOD FOR SEMICONDUCTOR PACKAGE USING THE SAME - A conductive carrier having a first surface and a second surface is provided. The conductive trace layer is formed on the second surface of the conductive carrier. A conductive stud layer is formed on the conductive trace layer. A dielectric layer is formed on the conductive layer to encapsulate the conductive trace layer and the conductive stud layer. The conductive stud layer is exposed. A plating conductive layer is formed to envelop the conductive carrier, the dielectric layer and the exposed end of the conductive stud layer. A cavity is formed on the conductive carrier, wherein the conductive trace layer and the dielectric layer are exposed in the cavity. A surface finishing is formed on at least an exposed portion of the conductive stud layer. The plating conductive layer is removed.03-08-2012
20120028419SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - There is provided a low-cost semiconductor device that commercial and quality-assured (inspected) chip size packages can be stacked and has a small co-planarity value and a high mounting reliability. A semiconductor device in which a flexible circuit substrate is adhered to at least a part of a lateral side of a semiconductor package, and the flexible circuit substrate, which is on a side facing solder balls of the semiconductor package, is folded at a region inside of an edge of the semiconductor package (FIG. 02-02-2012
20120064672METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE HEAT SPREADER AND A SUBSTRATE USING GRINDING - A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post through an opening in the adhesive, mounting a substrate on the adhesive including inserting the post into an aperture in the substrate, then flowing the adhesive between the post and the substrate in the aperture, solidifying the adhesive, then grinding the post and the adhesive, then mounting a semiconductor device on a heat spreader that includes the post and the base, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader.03-15-2012
20120208322SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A multilayer wiring substrate has an upper surface with multiple bonding leads and a lower surface with multiple lands. Multiple wiring layers and insulating layers are alternately formed on the upper surface side and on the lower surface side of the core material of the wiring substrate. The bonding leads are formed of part of the uppermost wiring layer and the lands are formed of part of the lowermost wiring layer. The insulating layers include second insulating layers containing fiber and resin and third insulating layers smaller in fiber content than the second insulating layers. The second insulating layers are formed on the upper and lower surface sides of the core material. The third insulating layers are formed on the upper and lower surface sides of the core material with the second insulating layers in-between. The uppermost and lowermost wiring layers are formed over the third insulating layers.08-16-2012
20110065241METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A BUMP/BASE HEAT SPREADER AND A DUAL-ANGLE CAVITY IN THE BUMP - A method of making a semiconductor chip assembly includes providing a bump and a ledge, wherein the bump includes first, second and third bent corners that shape a cavity, mounting an adhesive on the ledge including inserting the bump into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the bump with an aperture in the conductive layer, then flowing the adhesive between the bump and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal and a selected portion of the ledge, providing a heat spreader that includes the bump, then mounting a semiconductor device on the bump within the cavity, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.03-17-2011
20110104856METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE/POST HEAT SPREADER - A method of making a semiconductor chip assembly includes providing first and second posts, first and second adhesives and a base, wherein the first post extends from the base in a first vertical direction into a first opening in the first adhesive, the second post extends from the base in a second vertical direction into a second opening in the second adhesive and the base is sandwiched between and extends laterally from the posts, then flowing the first adhesive in the first vertical direction and the second adhesive in the second vertical direction, solidifying the adhesives, then providing a conductive trace that includes a pad and a terminal, wherein the pad extends beyond the base in the first vertical direction and the terminal extends beyond the base in the second vertical direction, providing a heat spreader that includes the posts and the base, then mounting a semiconductor device on the first post, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.05-05-2011
20110104855Method of making a semiconductor chip assembly with a post/base heat spreader with an ESD protection layer - A method of making a semiconductor chip assembly includes providing a post, a base, an ESD protection layer and a metal layer, wherein the post extends above the base and the ESD protection layer is sandwiched between the base and the metal layer, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the post with an aperture in the conductive layer, then flowing the adhesive upward between the post and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal and a selected portion of the conductive layer, providing a heat spreader that includes the post, the base, the ESD protection layer and an underlayer that includes at least a portion of the metal layer, then mounting a semiconductor device on the post, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.05-05-2011
20110183472METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE HEAT SPREADER AND A PLATED THROUGH-HOLE - A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the post with an aperture in the conductive layer, then flowing the adhesive upward between the post and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal, a plated through-hole and a selected portion of the conductive layer, mounting a semiconductor device on the post, wherein a heat spreader includes the post and the base, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.07-28-2011
20120129299METHOD OF MAKING THERMALLY ENHANCED SEMICONDUCTOR ASSEMBLY WITH BUMP/BASE/FLANGE HEAT SPREADER AND BUILD-UP CIRCUITRY - A method of making a semiconductor assembly that includes a semiconductor device, a heat spreader, an adhesive and a build-up circuitry is disclosed. The heat spreader includes a bump, a base and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the build-up circuitry and thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The build-up circuitry includes a dielectric layer and conductive traces on the semiconductor device and the flange. The conductive traces provide signal routing for the semiconductor device.05-24-2012
20120129298METHOD OF MAKING STACKABLE SEMICONDUCTOR ASSEMBLY WITH BUMP/FLANGE HEAT SPREADER AND DUAL BUILD-UP CIRCUITRY - A method of making a stackable semiconductor assembly that includes a semiconductor device, a heat spreader, an adhesive, a plated through-hole, first build-up circuitry and second build-up circuitry is disclosed. The heat spreader includes a bump and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the first build-up circuitry and thermally connected to the bump. The bump extends into an opening in the adhesive and the flange extends laterally from the bump at the cavity entrance. The first build-up circuitry and the second build-up circuitry extend beyond the semiconductor device in opposite vertical directions. The plated through-hole extends through the adhesive and provides signal routing between the first build-up circuitry and the second build-up circuitry. The heat spreader provides heat dissipation for the semiconductor device.05-24-2012
20120164791Substrate for semiconductor package and method for manufacturing the same - Disclosed herein are a substrate for a semiconductor package and a method for manufacturing the same. The substrate for the semiconductor package includes: a semiconductor chip forming region; and a hydrophobic film for controlling the flow of an adhesive for bonding a semiconductor chip in a portion of a solder resist layer. According to the present invention, a molecular film type of chemically treated hydrophobic film is formed to effectively control the flow of epoxy resin as an adhesive for bonding a semiconductor chip at a location where the epoxy resin meets the hydrophobic film. Also, a part to be controlled is bonded to a substrate through chemical bonding, thereby maintaining a very stable form.06-28-2012
20120178214ROUTABLE ARRAY METAL INTEGRATED CIRCUIT PACKAGE FABRICATED USING PARTIAL ETCHING PROCESS - An integrated circuit assembly is fabricated on a metal substrate strip in an array format that has raised circuitry pattern formed by photolithographic and metal etching processes. The circuitry pattern is formed on one side of the metal substrate only. The raised circuitry's etch depth extends partially through the metal substrate. Die attachment can be performed using a non-conductive material applied directly onto and around the raised circuitry features directly under the die. After wirebond and molding processes, the molded metal substrate strip assembly is processed through a metal etching process to remove the metal substrate portion that is exposed beyond the mold cap. A solder mask coating can be applied to protect the metal circuitry and to define the package pad opening to form Land-Grid-Array (LGA) packages. Solder balls can also be attached to form Ball-Grid-Array (BGA) packages.07-12-2012
20100009501Packaging structure, method for manufacturing the same, and method for using the same - A packaging structure applied for a surface mounting process, comprising: a chip module having a packaging surface; and a pre-cured layer formed on the packaging surface of the chip module. As above-mentioned, the structure is employed for protecting the external surface of the wafer. The pre-cured layer is formed on pre-curing a gluing material and the gluing material is uniformly filled with the space between the connecting protrusions on the packaging surface. The pre-cured later is post-curing in a connecting process for mounting the connecting protrusions to the substrate so that the connecting strength is improved. Moreover, the rate of the packaging process is increasing.01-14-2010
20090061565STRUCTURE COMBINING AN IC INTEGRATED SUBSTRATE AND A CARRIER, AND METHOD OF MANUFACTURING SUCH STRUCTURE - The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The interface between the IC integrated substrate and the carrier has a specific area at which the interface adhesion is different from that at the remaining area of the interface. The present invention also provides a method of manufacturing the above structure and a method of manufacturing electronic devices using the above structure.03-05-2009
20110003437METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE/FLANGE HEAT SPREADER AND A CAVITY IN THE FLANGE - A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a first conductive layer on the adhesive including aligning the post with an aperture in the first conductive layer, then flowing the adhesive between the post and the first conductive layer, solidifying the adhesive, then etching the post to form a first cavity in the adhesive above the post, depositing a second conductive layer into the first cavity to form a second cavity that extends into the first cavity, providing a conductive trace that includes a pad, a terminal and a selected portion of the first conductive layer, providing a heat spreader that includes the post, the base and a flange that includes a selected portion of the second conductive layer that defines the second cavity, mounting a semiconductor device on the flange in the second cavity, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.01-06-2011
20110039374METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A BUMP/BASE HEAT SPREADER AND A CAVITY IN THE BUMP - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a bump, a base and a flange. The conductive trace includes a pad and a terminal. The semiconductor device extends into a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal.02-17-2011
20100203679METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE HEAT SPREADER AND A CAVITY OVER THE POST - A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a substrate on the adhesive including aligning the post with an aperture in the substrate, then flowing the adhesive into and upward in a gap located in the aperture between the post and the substrate, solidifying the adhesive, then etching the post to form a cavity in the adhesive above the post, then mounting a semiconductor device on the post, wherein a heat spreader includes the post and the base and the semiconductor device extends into the cavity, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader.08-12-2010
20110045639PHOTOSENSITIVE ADHESIVE - A photosensitive adhesive capable of alkali development, the photosensitive adhesive exhibiting adhesion property for an adherend after it has been patterned by light exposure and development, the photosensitive adhesive being used in a method for producing a semiconductor device 02-24-2011
20120322209SEMICONDUCTOR DEVICE WITH HEAT SPREADER - A BGA type semiconductor device includes: a substrate having wirings and electrodes; a semiconductor element disposed on the substrate, having a rectangular plan shape, and a plurality of electrodes disposed along each side of the semiconductor element; a plurality of wires connecting the electrodes on the semiconductor element with the electrodes on the substrate; a heat dissipation member disposed on the substrate, covering the semiconductor element, and having openings formed in areas facing apex portions of the plurality of wires connected to the electrodes formed along each side of the semiconductor element; and a sealing resin member for covering and sealing the semiconductor element and heat dissipation member.12-20-2012
20130011970MANUFACTURING METHOD OF MOLDED PACKAGE - In a manufacturing method of a molded package, a lead frame including an island portion and a support portion is prepared. A circuit chip is mounted on the island portion, and the sensor chip is arranged such that a first end section having an electric connecting portion is adjacent to the circuit chip and a second end section having a sensing portion is supported by the support portion. The circuit chip and the electric connecting portion of the first end section is electrically connected through a connection member. The circuit chip, the island portion, the connection member and the first end section are sealed with a resin while maintaining the support state. After the sealing, the support portion is cut from the lead frame and separated from the second end section.01-10-2013
20120149155Electronic Assemblies Including Mechanically Secured Protruding Bonding Conductor Joints - A method for joining integrated circuit (IC) die. The includes pressing the IC die toward a workpiece so that a protruding bonding feature is inserted into a cavity of a receptacle through an opening. The pressing bends peripheral shelf regions downward into the cavity and towards sidewall portions of the receptacle to form bent peripheral shelf regions. A protruding bonding feature contacts the bent peripheral shelf regions along a contact area. The contact area being at least primarily along the sidewall surfaces of the protruding bonding feature.06-14-2012
20120149154PRE-BONDED SUBSTRATE FOR INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING THE SAME - A substrate and a method of making thereof are disclosed. The substrate comprises an electrically conductive leadframe, the leadframe having a plurality of lands on a first side of the leadframe with a first recessed portion between the lands, and a plurality of routing leads on an opposing second side of the leadframe with a second recessed portion between the routing leads. The substrate also comprises a first bonding compound filling the first recessed portion. In one embodiment, the substrate also comprises a support material attached to the first bonding compound for holding the leadframe together. In another embodiment, the substrate comprises a second bonding compound filling the second recessed portion.06-14-2012
20130017651METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGEAANM Standing; MartinAACI VillachAACO ATAAGP Standing; Martin Villach ATAANM Ganitzer; PaulAACI VillachAACO ATAAGP Ganitzer; Paul Villach AT - A method for manufacturing a semiconductor package, the method comprising providing a substrate having opposite first and second surfaces and having one or more through openings formed therethrough from the first to the second surfaces at predefined positions; providing at least one first die having first and second opposite surfaces and having one or more first contact terminals on the first surface of the at least one first die; placing the at least one first die with the first surface thereof on the first surface of the substrate, with an adhesive applied therebetween outside the one or more through openings, such that the one or more through openings are aligned to the one or more first contact terminals, whereby a die assembly having correspondingly opposite first and second surfaces is formed; providing the first surface of the die assembly with a first plating layer of an electrically conductive plating material to electrically contact the one or more first contact terminals, wherein the plating material of the first plating layer extends in the through openings to electrically contact the one or more first contact terminals therethrough.01-17-2013
20080233681Design of BEOL Patterns to Reduce the Stresses on Structures Below Chip Bondpads - A semiconductor structure comprising a substrate including a first layer comprising a first material having a first modulus of elasticity; a first structure comprising a conductor and formed within the substrate, the first structure having an upper surface; and a stress diverting structure proximate the first structure and within the first layer, the stress diverting structure providing a low mechanical stress region at the upper surface of the first structure when a physical load is applied to the first structure, wherein said low mechanical stress region comprises stress values below the stress values in areas not protected by the stress diverting structure. The stress diverting structure comprises a second material having a second modulus of elasticity less than the first modulus of elasticity, the second material selectively formed over the upper surface of the first structure for diverting mechanical stress created by the physical load applied to the first structure.09-25-2008
20080233680Semiconductor Die Collet and Method - Semiconductor device assembly die attach apparatus and methods are disclosed for improvements in attaching a semiconductor die to a die pad. Preferred methods of the invention include steps for positioning a semiconductor die on a bearing surface of a collet and retaining the die on the bearing surface of the collet using a vacuum force. A pushing force is also exerted on the die adjacent to the applied vacuum force. The pushing force opposes flexion of the die in the direction of the vacuum force. In further steps, the die is placed on a die pad, and die attach adhesive is interposed between the die and the die pad. A preferred method includes applying a pushing force to bow the central region of the die toward the die pad. In a preferred apparatus of the invention, a collet has a body including a bearing surface for receiving a die and a vacuum for holding it. A chamber encompassed by the bearing surface is adapted for applying the force of expelled gas against a die borne on the bearing surface. The collet is configured for holding a die surface against the bearing surface and for simultaneously pushing outward on the center region of the die so held.09-25-2008
20080220566Substrate process for an embedded component - A substrate process for an embedded component is disclosed. A mold having a surface and protruding components protruded from the surface is provided. A first dielectric layer is formed on the surface and covers the protruding components. At least one electronic component having an active surface, a back surface, and contacts formed on the active surface is disposed on the first dielectric layer. The active surface is faced to the first dielectric layer, and the contacts are corresponding to the protruding components. A second dielectric layer is formed on the first dielectric layer and a carrier is disposed on the back surface of the electronic component. Openings are formed on the first dielectric layer by the protruding components in an imprinting step. The openings are corresponding to the contacts. Finally, the mold is removed to form a substrate with an embedded component.09-11-2008
20130143363ADHESIVE COMPOSITION FOR SEMICONDUCTOR AND ADHESIVE FILM COMPRISING THE SAME - An adhesive film for a semiconductor may include about 60 wt % to about 80 wt % of a thermoplastic resin based on a total solid content of the adhesive film, a phenolic curing agent, and an amine curing agent, and the adhesive film may have a storage modulus of about 2 MPa or more and a reaction curing rate of about 50% or more when cured at 150° C. for 20 minutes.06-06-2013
20080213944STRUCTURE COMBINING AN IC INTEGRATED SUBSTRATE AND A CARRIER, AND METHOD OF MANUFACTURING SUCH STRUCTURE - The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The IC integrated substrate has a first dielectric layer attached to the carrier. The materials of the carrier and the first dielectric layer are selected to prevent the IC integrated substrate from peeling off the carrier during processing and to allow the IC integrated substrate to naturally separate from the carrier after being cut, through the adhesion between the carrier and the first dielectric layer. The present invention also provides a method of manufacturing the above structure and a method of manufacturing electrical devices using the above structure.09-04-2008
20130102113METHOD FOR ENCAPSULATING SEMICONDUCTOR AND STRUCTURE THEREOF - Embodiments of the present invention disclose a method for encapsulating a component with plastic and its encapsulation structure, which belong to the plastic encapsulation technology field. The method includes: processing, by using the surface mounting technology, a first surface of a part to be encapsulated with plastic and/or performing die bonding on the first surface; encapsulating, with plastic, the first surface of the part to be encapsulated with plastic a second surface of the part to be encapsulated with plastic the first surface and/or performing die bonding in the second face; and encapsulating, with plastic, the second surface of the part to be encapsulated with plastic. This encapsulation structure includes a substrate, where components are fixed on an upper surface and a lower surface of the substrate, and the components on the upper surface and lower surface are all encapsulated with plastic in seal.04-25-2013
20130102112Process for Forming Packages - A method includes loading a first package component on a concave boat, and placing a second package component over the first package component. A load clamp is placed over the second package component, wherein the load clamp is supported by a temperature-variable spacer of the concave boat. A reflow step is performed to bond the second package component to the first package component. During a temperature-elevation step of the reflow step, the temperature-variable spacer is softened in response to an increase in temperature, and a height of the softened temperature-variable spacer is reduced, until the load clamp is stopped by a rigid spacer of the concave boat.04-25-2013
20080199987MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF LEAD FRAME - Improvement in the reliability of a semiconductor device is aimed at. By heating a lead frame, after preparing a lead frame with a tape, until a resin molding is performed, at the temperature 160 to 300° C. (preferably 180 to 300° C.) for a total of more than 2 minutes in the atmosphere which has oxygen, crosslinkage density becoming high in resin of adhesives, a low molecular compound volatilizes and jumps out outside, therefore as a result, since a low molecular compound does not remain in resin of adhesives, the generation of copper migration can be prevented.08-21-2008
20080199986METHOD AND APPARATUS FOR MANUFACTURING ELECTRONIC INTEGRATED CIRCUIT CHIP - A method (and apparatus) of assembling a die on an electronic substrate, includes processing an assembly including a substrate and a die, and during the processing, introducing a pre-stress to the assembly during a cure process.08-21-2008
20090142885METHOD FOR PROTECTING POROUS LOW-K DIELECTRIC POST CHEMICAL MECHANICAL PLANARIZATION - A method of forming a semiconductor structure chemically-mechanically polishes (CMP) a semiconductor structure before applying a sealant layer over the porous low-k dielectric. The process of applying the sealant layer is a selective process that causes the sealant to adhere to or deposit onto the porous low-k dielectric and to not adhere to the copper conductors. After the sealant layer is formed, the cap is applied. The parylene layer seals the pores in the low-k dielectric which prevents the low-k dielectric layer from being damaged during the cap pre-cleaning process and also prevents the cap material from penetrating into the low-k dielectric.06-04-2009
20130149817FABRICATING METHODS OF SEMICONDUCTOR DEVICES AND PICK-UP APPARATUSES OF SEMICONDUCTOR DEVICES THEREIN - A fabricating method of a semiconductor device may include forming a semiconductor die on a supporting wafer, and picking up the die from the wafer by attaching to the die a transfer unit, the transfer unit including a head unit configured to enable twisting movement, and performing the twisting movement. A fabricating method of a semiconductor device may include forming a first semiconductor device on a supporting wafer; and picking up the first semiconductor device from the wafer, moving the first semiconductor device onto a second semiconductor device, and bonding the first semiconductor device to the second semiconductor device while maintaining the first semiconductor device oriented so that a surface faces upwardly. A fabricating method of a semiconductor device may include forming a first semiconductor device on a supporting wafer, attaching to the first semiconductor device a transfer unit configured to enable twisting movement, and performing the twisting movement.06-13-2013
20110275179PROTECTIVE TAPE JOINING METHOD AND PROTECTIVE TAPE USED THEREFOR - Provided is an improved method of joining a protective tape having one object to suppress generation of bending of a semiconductor wafer after a back-grinding process. The protective tape is supplied toward the semiconductor wafer suction-held on a chuck table, and an intermediate sheet is supplied along an upper side of the protective tape. Then, the intermediate sheet is interposed between a joining member and the protective tape along a surface of a base material in the protective tape so as to be movable. Under this state, the joining member and the semiconductor wafer move relative to each other in a horizontal direction, whereby the protective tape is joined to a surface of the semiconductor wafer.11-10-2011
20100317156METHOD FOR MANUFACTURING INTEGRATED CIRCUIT - A method for separating an integrated circuit formed by a thin film having a novel structure or a method for transferring the integrated circuit to another substrate, that is, so-called transposing method, has not been proposed. According to the present invention, in the case that an integrated circuit having a thin film having a novel structure formed over a substrate via a release layer is separated, the release layer is removed in the state that the thin film integrated circuit is fixated, the thin film integrated circuit is transposed to a supporting substrate having an adhesion surface, and the thin film integrated circuit is transposed to another substrate having an adhesion surface with higher strength of adhesion than that of the supporting substrate.12-16-2010
20130157416METHODS OF FORMING A SEMICONDUCTOR DEVICE - A method and structure for a semiconductor device, the device including a handle wafer, a diamond layer formed directly on a front side of the handle wafer, and a thick oxide layer formed directly on a back side of the handle wafer, the oxide of a thickness to counteract tensile stresses of the diamond layer. Nitride layers are formed on the outer surfaces of the diamond layer and thick oxide layer and a polysilicon is formed on outer surfaces of the nitride layers. A device wafer is bonded to the handle wafer to form the semiconductor device.06-20-2013
20130122654Package Substrate Having Die Pad with Outer Raised Portion and Interior Recessed Portion - A method of forming an electronic assembly includes dispensing a die attach material on a substrate into a recessed portion that includes an inner recessed portion of including a die pad. The die attach material is not dispensed on an outer raised flat portion of the die pad. A semiconductor die is attached directly on the outer raised flat portion and affixed to the die pad with said die attach material in said interior recessed portion but not on said outer raised flat portion.05-16-2013
20110312132METHOD FOR POSITIONING CHIPS DURING THE PRODUCTION OF A RECONSTITUTED WAFER - A process for fabricating a reconstituted wafer that includes chips having connection pads on a front side side of the chip, this process including positioning of the chips on an adhesive support, front side down on the support; deposition of a resin on the support in order to encapsulate the chips; and curing of the resin. Before deposition of the resin, the process includes bonding, onto the chips, a support wafer for positioning the chips, this support wafer having parts placed on one side of the chips.12-22-2011
20110312131Forming A Semiconductor Package Including A Thermal Interface Material - In one embodiment, the present invention includes a method for placing a thermal interface material (TIM) between a die including a backside metallic (BSM) layer including copper (Cu) and a heat spreader having a contact surface including Cu, where the TIM is formed of an alloy including indium (In) and tin (Sn), and bonding the TIM to the die and the heat spreader to form at least one quaternary intermetallic compound (IMC) layer. Other embodiments are described and claimed.12-22-2011
20120003794Thermally Enhanced Semiconductor Package - Disclosed are systems and methods for improving the thermal performance of integrated circuit packages. Aspects of the present invention include improved thermal package structures and methods for producing the same through the application of one or more thermal spreaders in the package. In embodiments, a thermal spreader is incorporated in a semiconductor chip package between a semiconductor die and its die pad. By including a thermal spreader in an IC package, the package can handle higher levels of power while maintaining approximately the same temperature of the package or can reduce the temperature of the package when operating at the same power level, as compared to a package without a thermal spreader.01-05-2012
20120015484POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a power semiconductor module. The module includes metal plates each having a first through hole, with an anodic oxidation layer formed on a surface of metal plates and an interior of the first through hole. A cooling member has a second through hole at a position corresponding to the first through hole, and the metal plates are attached to both sides of the cooling member. A circuit layer is formed on the anodic oxidation layer and performs an interlayer connection through a via formed in the first and second through holes. A power device is connected to the circuit layer. A resin encapsulant encloses the circuit layer and the power device. A housing is installed to each of the metal plates to form a sealing space for the resin encapsulant.01-19-2012
20130196472PRE-CUT WAFER APPLIED UNDERFILL FILM ON DICING TAPE - A method for preparing a semiconductor with preapplied underfill comprises (a) providing a thinned silicon semiconductor wafer having a plurality of metallic bumps on its active face and, optionally, through-silica-vias vertically through the silicon semiconductor wafer; (b) providing an underfill material on a dicing support tape, in which the underfill material is precut to the shape of the semiconductor wafer; (c) aligning the underfill material on the dicing support tape with the semiconductor wafer and laminating the underfill material to the semiconductor wafer.08-01-2013
20120295403FABRICATION METHOD OF EMBEDDED CHIP SUBSTRATE - An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.11-22-2012
20120094442METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A BUMP/BASE/LEDGE HEAT SPREADER, DUAL ADHESIVES AND A CAVITY IN THE BUMP - A method of making a semiconductor chip assembly includes providing a bump and a ledge, mounting a first adhesive on the ledge including inserting the bump into an opening in the first adhesive, mounting a conductive layer on the first adhesive including aligning the bump with an aperture in the conductive layer, then flowing the first adhesive between the bump and the conductive layer, solidifying the first adhesive, then providing a heat spreader that includes the bump, a base and the ledge, then mounting a second adhesive on the ledge, mounting a conductive trace that includes a pad and a terminal on the second adhesive, then mounting a semiconductor device on the bump in a cavity in the bump, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.04-19-2012
20120094441Semiconductor Chip Attach Configuration Having Improved Thermal Characteristics - An array of metal bodies are attached to a metal carrier by forming Metal bodies form metal inter-diffusions with carrier. The metal bodies are coined to form flattened body ends. A polymeric adhesive precursor is disposed onto the array and a semiconductor chip having a first surface including circuitry and an opposite second surface free of circuitry is attached to the adhesive precursor so that the second chip surface is in contact with the flattened ends of the arrayed metal bodies, which stop at the second surface.04-19-2012
20120094440METHOD OF DIE BONDING ONTO DISPENSED ADHESIVES - A method of bonding semiconductor dice onto a substrate first uses an optical assembly to perform pattern recognition of a die bonding section of the substrate in which multiple die pads are located so as to identify positions of the multiple die pads simultaneously during such pattern recognition step. After pattern recognition of the said die bonding section, an adhesive is dispensed with an adhesive dispenser onto at least one of the die pads located in the die bonding section. While the adhesive dispenser is dispensing the adhesive to further die pads located in the die bonding section, a pick-and-place arm concurrently bonds a die onto each die pad where the adhesive has already been dispensed.04-19-2012
20130210196SEMICONDUCTOR PACKAGE WITH INTEGRATED SUBSTRATE THERMAL SLUG - To reduce the thermal stresses that may be caused by a difference in thermal expansion coefficients between a molded casing and an active side of a semiconductor device embedded in the molded casing, and thus reduce the number of corresponding failures caused by the thermal stresses, the active side of the semiconductor device is arranged face-down, towards a substrate supporting the semiconductor device. The semiconductor device includes a through via that electrically connects the active side of the semiconductor device to a passive side of the semiconductor device. A wire bond electrically connects the passive side of the semiconductor device to the substrate. To increase the dissipation of heat generated in the semiconductor device, a thermally conductive slug may be disposed in the substrate, and the active side of the semiconductor device may be attached to the thermally conductive slug.08-15-2013

Patent applications in class Including adhesive bonding step

Patent applications in all subclasses Including adhesive bonding step