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Substrate dicing

Subclass of:

438 - Semiconductor device manufacturing: process

438106000 - PACKAGING (E.G., WITH MOUNTING, ENCAPSULATING, ETC.) OR TREATMENT OF PACKAGED SEMICONDUCTOR

438110000 - Making plural separate devices

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
438114000 Utilizing a coating to perfect the dicing 41
Entries
DocumentTitleDate
20110189822METHOD OF MANUFACTURING LAYERED CHIP PACKAGE - A layered chip package includes a main body and wiring. The main body includes a plurality of layer portions stacked. The wiring is disposed on at least one side surface of the main body. In the method of manufacturing the layered chip package, first, a plurality of substructures each of which includes an array of a plurality of preliminary layer portions are used to fabricate a layered substructure that includes a plurality of pre-separation main bodies arranged in rows. Next, the layered substructure is cut into a plurality of blocks each of which includes a row of a plurality of pre-separation main bodies, and the wiring is formed on the plurality of pre-separation main bodies included in each block simultaneously. The plurality of pre-separation main bodies are then separated from each other. Each of the plurality of blocks includes a row of three, four, or five pre-separation main bodies.08-04-2011
20110195545PACKAGE PROCESS - A package process is provided. The package process includes: disposing a semiconductor substrate on a carrier, wherein the semiconductor substrate has plural contacts at a side facing the carrier; thinning the semiconductor substrate from a back side of the semiconductor substrate and then forming plural through silicon vias in the thinned semiconductor substrate; forming plural first pads on the semiconductor substrate, wherein the first pads respectively connected to the through silicon vias; bonding plural chips to the semiconductor substrate, wherein the chips are electrically connected to the corresponding pads; forming a molding compound on the semiconductor substrate to cover the chips and the first pads; separating the semiconductor substrate and the carrier and then forming plural solder balls on the semiconductor substrate; and sawing the molding compound and the semiconductor substrate.08-11-2011
20120178213CHIP SCALE PACKAGE STRUCTURE WITH CAN ATTACHMENT - A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test.07-12-2012
20090311830SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor chip, semiconductor package including the same, and a method of manufacturing the semiconductor chip and semiconductor package to block up electrical contacts between bonding wires and the semiconductor chip by providing insulation over the edge of the semiconductor chip.12-17-2009
20130078768NEST MECHANISM WITH RECESSED WALL SEGMENTS - A nest mechanism includes a 2-dimensional grid of support positions for supporting singulated electronic units. The support positions each include an inner opening and an outer horizontal base around the inner opening having a support surface that supports units thereon. A segmented wall arrangement is on the outer horizontal base located beyond an area of the unit for preventing movement of the unit while on the support surface. The segmented wall arrangement includes (i) a plurality of raised wall segments that extend to a first height above the support surface, and (ii) at least one recessed segment between the plurality of raised wall segments that has a height less than the first height. The recessed segment(s) help liquid-based washing processes to remove residue material generated by a sawing process that can become stuck under the units while in the nest mechanism awaiting transfer.03-28-2013
20130078767METHODS FOR FABRICATING INTEGRATED CIRCUIT SYSTEMS INCLUDING HIGH RELIABILITY DIE UNDER-FILL - A method is provided for fabricating an integrated circuit system that includes fabricating a plurality of integrated circuits in and on a semiconductor substrate. Spaced apart solder bumps are attached to the plurality of integrated circuits, the solder bumps in electrical contact to components of the integrated circuits. A dicing tape having a layer of under-fill material thereon is provided and the semiconductor substrate is laminated to the dicing tape with the layer of under-fill material filling spaces between the solder bumps. The semiconductor substrate and layer of under-fill material are diced to singulate individual ones of the plurality of integrated circuits, and one of the individual ones of the plurality of integrated circuits is attached to a second substrate such as another integrated circuit chip or printed circuit board.03-28-2013
20130034934WAFER LEVEL PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a wafer level package is provided that enables suppressing the wearing of a cutter and extending the lifetime of the cutter, including forming insulating first resin over the top face of a substrate, which includes a groove for wiring to be formed; forming a film of first metal that is to serve as a portion of the wiring on the top face of the first resin using physical vapor deposition; forming a film of second metal that is to form a portion of the wiring on the top face of the first metal, with a lower hardness than the first metal; setting a cutter at a height corresponding to a place where the film of the first metal is not formed on a side face of the groove or the film thickness is low; and cutting at least the first resin by scanning the cutter.02-07-2013
20130040426MANUFACTURING METHOD USING MULTI-STEP ADHESIVE CURING FOR SEALED SEMICONDUCTOR DEVICE - A method for forming a sealing body without cracks in manufacture of a semiconductor device having an external terminal formed through the use of an electrolysis plating method. A front surface of a semiconductor wafer is placed over a front surface of a first support heated to a first temperature. An adhesive sheet is then bonded to a back surface of the semiconductor wafer, after which the semiconductor wafer is subjected to heat treatment at a second temperature higher than the first temperature. After the semiconductor wafer and the adhesive sheet are cut along cutting regions, a plurality of semiconductor chips each having an adhesive patch bonded thereto are obtained. A mother substrate is placed over a front surface of a second support heated to a third temperature and the semiconductor chips are fixed to an upper surface of the mother substrate via the adhesive patch.02-14-2013
20090176333METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To prevent semiconductor chips from adhering to the trays during transport, a method is employed which transports semiconductor chips in the following state. When trays provided with a plurality of accommodating portions having a recessed cross section for accommodating semiconductor chips on a main surface thereof are stacked in a plurality of stages, the semiconductor chips are accommodated in spaces defined by the accommodating portions formed over the main surface of the lower-stage tray and corresponding accommodating portions formed over the back surface of the upper-stage tray. Here, on bottom surfaces of the accommodating portions formed over the back surface of the upper-stage tray, isolated projections having a height which prevents the projections from coming into contact with the semiconductor chips are arranged in a scattered manner. In this way, it is possible to prevent the semiconductor chips from adhering to the back surface of the upper-stage tray.07-09-2009
20100041181HEAT DISSIPATING PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A heat dissipating package structure includes a chip carrier; a semiconductor chip mounted and electrically connected to the chip carrier; a heat spreader having a first surface, an opposed second surface and a hollow structure, the second surface of the heat spreader being mounted on the chip, wherein the chip is larger in size than the hollow structure such that the chip is partly exposed to the hollow structure; an encapsulant formed between the heat spreader and the chip carrier, for encapsulating the chip, wherein the first surface and sides of the heat spreader are exposed from the encapsulant to dissipate heat produced from the chip; and a plurality of conductive elements disposed on the chip carrier, for electrically connecting the chip to an external device. The present invention also provides a method for fabricating the heat dissipating package structure.02-18-2010
20100144098Method for Fabricating Flip-Attached and Underfilled Semiconductor Devices - A semiconductor device (06-10-2010
20080299706Wafer level package fabrication method - Provided is a wafer level package fabrication method. The method includes providing a device substrate wafer including one or more devices on an upper surface thereof, and a bonding pad electrically connected to the device, providing a bonding seal surrounding the device along the bonding pad, bonding a cap substrate wafer to the device substrate wafer through the bonding seal, the cap substrate wafer having a via formed in a region corresponding to the bonding pad, forming an external terminal on the cap substrate wafer, the external terminal being electrically connected to the bonding pad, and cutting the cap substrate wafer and the device substrate wafer along a cutting line to individually separate a plurality of wafer level packages. The method is conducive to reducing product size for miniaturization, is capable of performing a bonding process without wafer deformation or damage, and increases freedom in wafer material selection.12-04-2008
20130029457TCE Compensation for Package Substrates for Reduced Die Warpage Assembly - A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages.01-31-2013
20130045570METHOD AND SYSTEM FOR WAFER LEVEL SINGULATION - A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.02-21-2013
20130089954METHOD OF FABRICATING ELECTRONIC DEVICE HAVING FLEXIBLE DEVICE - There is provided a method of fabricating an electronic device having a flexible device, which is fabricated using a support substrate by Joule-heating induced film separation (JIFS). A method of fabricating an electronic device having a flexible device includes providing a support substrate, coating a conductive layer on one surface of the support substrate, forming a plastic substrate on the other surface of the support substrate, forming one or more thin-film transistors (TFTs) on the plastic substrate, forming an electronic device electrically connected to any one of the TFTs, and separating the plastic substrate from the conductive layer by generating Joule-heating through application of an electric field to the conductive layer. Accordingly, the flexible device can be separated from the support substrate without deformation of the support substrate and degradation of the electronic device. Since the separation time is short, it is easy to fabricate a large-area device, and the fabrication yield can be improved.04-11-2013
20110003434SEMICONDUCTOR CHIP PACKAGE STRUCTURE FOR ACHIEVING FACE-UP ELECTRICAL CONNECTION WITHOUT USING A WIRE-BONDING PROCESS AND METHOD FOR MAKING THE SAME - A semiconductor chip package structure for achieving face-up electrical connection without using a wire-bonding process includes a package unit, a semiconductor chip, a substrate unit, a first insulative unit, a first conductive unit, a second conductive unit, and a second insulative unit. The package unit has a central receiving groove and an outer receiving groove formed around the central receiving groove. The semiconductor chip has a plurality of conductive pads. The first insulative unit has a first insulative layer formed between the conductive pads. The first conductive unit has a plurality of first conductive layers. The second conductive unit has a plurality of second conductive layers formed on the first conductive layers. The second insulative unit is formed between the first conductive layers and between the second conductive layers.01-06-2011
20130071970MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention makes it possible to inhibit cutting burrs from forming in package dicing.03-21-2013
20130059418FABRICATION METHOD OF SEMICONDUCTOR PACKAGE DEVICE, AND FABRICATION METHOD OF SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.03-07-2013
20130065361CHIP PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor package structure is disclosed. In one embodiment, the method includes the steps of forming a plurality of conductive pastes on a matrix lead frame with a groove located within a predetermined distance from each conductive paste on the lead; partially curing the conductive pastes so that the conductive pastes are in a semi-cured state; preparing at least one chip with a plurality of bumps thereon; electrically connecting the chip and the lead by implanting the bumps into the semi-cured conductive pastes, wherein the groove on the lead of the matrix lead frame is configured to receive overflowed semi-cured conductive pastes; curing the semi-cured conductive pastes to completely secure the bumped chip; and forming an encapsulating material covering the lead frame and the chip. The method can also be applied in pre-molded lead frame package.03-14-2013
20130065362FLIP CHIP PACKAGE MANUFACTURING METHOD - A flip chip package manufacturing method is provided. A non-conductive film is pressed onto a wafer with multiple conductive bumps. The wafer is cut to multiple single chips. A carrier is provided, and a thermo-compression flip chip bonding process is executed to bond the non-conductive film onto the carrier. The carrier is transferred into a chamber with enclosed, pneumatic pressurized and heatingable characteristics to execute a de-void process to eliminate the bubbles and to execute a high-temperature soldering process to solder the single chip onto the carrier. The sequence of the de-void process and the high-temperature soldering process may exchange.03-14-2013
20120115280FILM FOR SEMICONDUCTOR AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A film for semiconductor includes a support film, a second adhesive layer, a first adhesive layer and a bonding layer which are laminated together in this order. This film for semiconductor is configured so that it supports a semiconductor wafer laminated on the bonding layer thereof when the semiconductor wafer is diced and the bonding layer is selectively peeled off from the first adhesive layer when a chip is picked up. This film for semiconductor is characterized in that in the case where peel strength at 23° C. of the chip is defined as “F05-10-2012
20090011542Structure and manufactruing method of chip scale package - A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.01-08-2009
20080305578METHOD OF MACHINING WAFER - A method of machining a wafer, wherein a wafer provided with devices each having a low dielectric constant insulating film (low-k film) stacked on the face side thereof is divided into the individual devices, the devices thus divided are mounted on a wiring board, and then a grindstone is brought into contact with each of the mounted devices from the side of a side surface of the devices, to grind the back side of the device by a desired amount. Since no vertical load is exerted on the low-k film, the low-k film can be prevented from being broken, and device quality is not lowered.12-11-2008
20080241998METHOD FOR FABRICATING A LOW COST INTEGRATED CIRCUIT (IC) PACKAGE - A method for fabricating a low cost integrated circuit package (10-02-2008
20110281398THIN QUAD FLAT PACKAGE WITH NO LEADS (QFN) FABRICATION METHODS - Embodiments of the present invention include a method of packaging semiconductor devices. The method comprises the steps of molding a surface of a wafer, sawing the wafer into individual devices, attaching the individual semiconductor device to an adhesive surface, molding the exposed surface, and sawing the wafer into individual semiconductor devices. The step of molding forms a continuous molded layer. The step of sawing results in each individual semiconductor having a molded layer. This molded layer corresponds to a portion of the continuous molded layer. The step of attaching includes attaching the molded layer of the individual semiconductor devices to the adhesive surface. The step of molding the exposed area includes molding an exposed area above the adhesive surface. This forms a solid expanse of material. The step of sawing the wafer into individual semiconductor devices includes sawing the solid expanse of material.11-17-2011
20110281399ADHESIVE BONDING SHEET, SEMICONDUCTOR DEVICE USING SAME, AND METHOD FOR MANUFACTURING SUCH SEMICONDUCTOR DEVICE - An adhesive bonding sheet having an optically transmitting supporting substrate and an adhesive bonding layer, and being used in both a dicing step and a semiconductor element adhesion step, wherein the adhesive bonding layer comprises: 11-17-2011
20090081828MEMS Fabrication Method - The present invention provides methods for singulating microelectromechanical systems (MEMS) die from a wafer. A plurality of MEMS devices are formed on the top surface of a wafer, and a plurality of intersecting scribe lanes are then formed, on the bottom surface of the wafer, to define a plurality of dies, each including at least one MEMS device. The intersecting scribe lanes penetrate the wafer to a depth of about 80%, and the wafer is cleaved along the scribe lanes to separate each of the plurality of dies from the wafer.03-26-2009
20120108012FILM FOR SEMICONDUCTOR AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A film for semiconductor includes a support film, a second adhesive layer, a first adhesive layer and a bonding layer which are laminated together in this order. This film for semiconductor is configured so that it supports a semiconductor wafer laminated on the bonding layer thereof when the semiconductor wafer is diced and the bonding layer is selectively peeled off from the first adhesive layer when the semiconductor elements obtained by the dicing are picked up. This film for semiconductor is characterized in that an average thickness of the second adhesive layer is in the range of 20 to 100 μm. This makes it possible to control cutting lines formed during the dicing so as to locate distal ends thereof within the first adhesive layer easily and reliably and to prevent defects which would be generated when the cutting lines come down to the support film.05-03-2012
20120108011METHOD OF FABRICATING A SEMICONDUCTOR DEVICE WITH A BACK ELECTRODE - A semiconductor device capable of stabilizing operations thereof is provided. This semiconductor device comprises a substrate provided with a region having concentrated dislocations at least on part of the back surface thereof, a semiconductor element layer formed on the front surface of the substrate, an insulator film formed on the region of the back surface of the substrate having concentrated dislocations and a back electrode formed to be in contact with a region of the back surface of the substrate other than the region having concentrated dislocations.05-03-2012
20110287585SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR ELEMENTS MOUNTED ON BASE PLATE - A method of manufacturing a semiconductor device and a semiconductor device including a first semiconductor element mounted on a first surface of a base plate, wherein solder balls are formed on a second opposite surface of the base plate—such that the second opposite surface includes an area without solder balls. At least one second semiconductor element is mounted to the base plate at the area of the second surface without solder balls. The at least one semiconductor element may be mounted to the base plate using low molecular adhesive, or in the alternative, high temperature solder.11-24-2011
20110287584SEMICONDUCTOR PACKAGE HAVING SIDE WALLS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a semiconductor chip having an upper surface, side surfaces connected with the upper surface, and bonding pads formed on the upper surface. A first insulation layer pattern is formed to cover the upper surface and the side surfaces of the semiconductor chip and expose the bonding pads. Re-distribution lines are placed on the first insulation layer pattern and include first re-distribution line parts and second re-distribution line parts. The first re-distribution line parts have an end connected with the bonding pads and correspond to the upper surface of the semiconductor chip and the second re-distribution line parts extend from the first re-distribution line parts beyond the side surfaces of the semiconductor chip. A second insulation layer pattern is formed over the semiconductor chip and exposes portions of the first re-distribution line parts and the second re-distribution line parts.11-24-2011
20110294262SEMICONDUCTOR PACKAGE PROCESS WITH IMPROVED DIE ATTACH METHOD FOR ULTRATHIN CHIPS - A semiconductor packaging process with improved die attach method for ultrathin chips package comprises the steps of providing a semiconductor wafer having a wafer frontside and a wafer backside with a plurality of integrated circuit chips (IC chips) formed on the wafer frontside; adhering a supporting substrate onto the wafer frontside through a bonding layer to form a wafer combo; grinding the wafer backside with the supporting substrate and the wafer bonded together; dicing the wafer combo into a plurality of die combos each comprising a substrate piece stacked on top of an IC chip bonded by a bonding layer piece; attaching a die combo onto a die pad of a lead frame with a bottom of the IC chip connected to the lead frame thereof; and removing the substrate piece with the bonding layer piece from the top surface of the IC chip.12-01-2011
20110294263Pattern verification method, program thereof, and manufacturing method of semiconductor device - A verification method of an integrated circuit pattern includes extracting a pattern which is not greater than a preset pattern size, extracting a pattern edge as a target of lithography simulation from the extracted pattern, and performing the lithography simulation on the extracted pattern edge to verify the integrated circuit pattern.12-01-2011
20080305577METHOD OF MINIMIZING KERF WIDTH ON A SEMICONDUCTOR SUBSTRATE PANEL - A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.12-11-2008
20100035382Methods of making compliant semiconductor chip packages - A method of making a semiconductor chip package is provided in which a compliant layer is provided over a contact bearing face of a semiconductor chip. The compliant layer can have a bottom surface adjacent to the chip face, a top surface facing away from the bottom surface, and at least one sloping surface between the top and bottom surfaces. The compliant layer can be disposed remote in a lateral direction along the contact bearing face from at least one contact adjacent to the sloping surface. Bond ribbons can be formed atop the compliant layer, wherein each bond ribbon electrically connects one of the contacts to an associated conductive terminal at the top surface of the compliant layer. The compliant layer can provide stress relief to the bond ribbons, such as during handling and affixing the assembly to an external substrate. A bond ribbon can include a strip extending along the sloping surface of the compliant layer, the strip having a substantially constant thickness in a direction extending away from the sloping surface.02-11-2010
20110217814METHOD FOR SINGULATING ELECTRONIC COMPONENTS FROM A SUBSTRATE - Methods for forming electronic assemblies are provided. A device substrate having a plurality of electronic components embedded therein is provided. The device substrate is attached to a carrier substrate using an adhesive material. A plurality of cuts are formed through the device substrate to divide the device substrate into a plurality of portions. Each of the plurality of portions includes at least one of the electronic components. A force is applied to each of the plurality of portions in a direction away from the carrier substrate to remove the plurality of portions from the carrier substrate.09-08-2011
20110217813METHOD OF FABRICATING MULTI-CHIP PACKAGE STRUCTURE - A method of fabricating a multi-chip package structure is provided. In the method, a number of cavities are formed on a predetermined cutting line of a first wafer by partly removing the first wafer and a first metal layer. Conductive walls of a first circuit layer are electrically connected to a cut cross-section of the first metal layer exposed by the cavities. In addition, conductive bumps of a second wafer or a chip are pressed into a cover layer and electrically connected to the first circuit layer. The first metal layer is then patterned to form a second circuit layer having a number of second pads. Next, the first wafer and the second wafer are cut along the predetermined cutting line to form a number of separated multi-chip package structures.09-08-2011
20090203171SEMICONDUCTOR DEVICE FABRICATING METHOD - A semiconductor device fabricating method includes forming a plurality of semiconductor devices that include one semiconductor chip and a metal plate having an opening portion that surrounds a region where the semiconductor chip is provided, by cutting, at regions where a frame portion exists, a plate-shaped member that includes: a wiring layer including a wiring portion and an insulating portion; a plurality of semiconductor chips disposed on one surface of the wiring layer; a metal plate disposed at a surface of the wiring layer at a side at which the semiconductor chips are provided, and having a plurality of opening portions that surround regions where the semiconductor chips are provided and the frame portion that forms the opening portions; and a sealing resin layer provided so as to seal at least gaps between the semiconductor chips and the metal plate.08-13-2009
20090017581Method for manufacturing a semiconductor device - A single-crystal semiconductor layer is provided in a large area over a large-sized glass substrate, whereby a large-scale SOI substrate is obtained. A single-crystal semiconductor substrate provided with an embrittlement layer and a dummy substrate are bonded to each other, and the single-crystal semiconductor substrate is separated at the embrittlement layer as a boundary by heat treatment to form a piece of single-crystal semiconductor over the dummy substrate. The dummy substrate is divided to form a piece of single-crystal semiconductor. The piece of single-crystal semiconductor is bonded to a supporting substrate, and the piece of single-crystal semiconductor is separated from the dummy substrate. Then, a plurality of pieces of single-crystal semiconductor are arranged and transferred to the large-sized glass substrate.01-15-2009
20090162975Method of forming a wafer level package - A method is provided for forming a microelectronic package at a wafer level. Such method can include providing a semiconductor wafer having a surface with a pattern of electrical contacts thereon. An interposer component can be provided which has a compliant dielectric layer bonded to a conductive layer. A pattern of holes can be formed through the compliant dielectric layer and the conductive layer which corresponds to the pattern of electrical contacts. The compliant dielectric layer can be contacted with the semiconductor wafer surface so that the pattern of holes is in an aligned position with the pattern of contacts and the compliant dielectric layer and the semiconductor wafer surface then bonded in the aligned position to unite the semiconductor wafer and the interposer component to form a wafer level semiconductor package. The wafer level semiconductor package can be diced to form individual semiconductor chip packages.06-25-2009
20100105171SEMICONDUCTOR CHIP, METHOD OF MANUFACTURING THE SEMICONDUCTOR CHIP AND SEMICONDUCTOR CHIP PACKAGE - In a semiconductor chip, a body has a top surface where a pattern is formed, an underside surface opposing the top surface and a plurality of side surfaces. A plurality of electrode pads are formed on the top surface of the body to connect to an external terminal. A shielding conductive film is formed on the surfaces excluding the top surface of the body where the pattern is formed. A conductive via is extended through the body to connect one of the electrode pads with the conductive film.04-29-2010
20090148984BULK GaN AND AlGaN SINGLE CRYSTALS - Bulk GaN and AlGaN single crystal boules, preferably fabricated using a modified HVPE process, are provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If desired, the bulk material can be doped during growth, for example to achieve n-, i-, or p-type conductivity.06-11-2009
20100267204PACKAGE STRUCTURE FOR INTEGRATED CIRCUIT DEVICE AND METHOD OF THE SAME - A package structure for packaging at least one of a plurality of intergraded circuit devices of a wafer is provided. The package structure includes an extension metal pad, a first conductive bump and an insulator layer. The extension metal pad electrically contacts the at least one of the plurality of intergraded circuit devices. The first conductive bump is located on the extension metal pad. The insulator layer is located over the at least one of the plurality of intergraded circuit devices and on a sidewall of it.10-21-2010
20100120202Method for Reducing Chip Warpage - A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.05-13-2010
20100120203SEMICONDUCTOR DEVICE AND MEMORY CARD USING THE SAME - A circuit board has a curved portion provided in at least one side of an external shape thereof. An external connecting terminal is provided on a first main surface of the circuit board. A semiconductor element is mounted on a second main surface of the circuit board. A first wiring network is provided in a region except the terminal region on the first main surface. A second wiring network is provided on the second main surface. Distance from the side including the curved portion to the first wiring network is larger than distance from at least one of the other sides to the first wiring networks, and distance from the side including the curved portion to the second wiring network is larger than distance from at least one of the other sides to the second wiring networks.05-13-2010
20100081235METHOD FOR MANUFACTURING RF POWDER - A method for manufacturing RF powder wherein the RF powder is composed of a large amount of particles and used as collective RF powder (a powdery entity); and a large amount of RF powder particles can be obtained from a wafer in a stable manner and at a high yield is provided.04-01-2010
20100093133ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - The electronic device comprises a first substrate 04-15-2010
20110201155MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of components of the material constituting a wiring substrate.08-18-2011
20110171780SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Of three chips (07-14-2011
20090093087METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In the method of manufacturing a semiconductor device that semiconductor chips are mounted facing-up on the printed wiring board on which a protective insulation film is formed by means of a film-like resist and a plurality of the semiconductor chips are collectively molded by a transfer mold technology, when transfer molding is performed, among the adsorption face of the printed wiring board and the lower die to make adsorb the printed wiring board, the through holes reaching the exterior space of the lower die from the vicinity of the end portion opposing the gate to pour mold resin of a mold cavity are formed as many as possible in order to prevent a short circuit and an open circuit by big deformation of a bonding wire connecting an electrode of the semiconductor chip and an conductor pattern of the printed wiring board.04-09-2009
20090286357METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE - A method of manufacturing a semiconductor structure. One embodiment produces a substrate having at least two semiconductor chips embedded in a molded body. A layer is applied over at least one main surface of the substrate by using a jet printing process.11-19-2009
20090291529METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.11-26-2009
20110171781METHOD OF FABRICATING A 3-D DEVICE - A method of fabricating a semiconductor device includes providing a semiconductor substrate having an active surface, thinning the substrate by removing material from a second surface of the substrate opposite the active surface, bonding a metal carrier to the second surface of the thinned substrate, forming a via opening in the thinned substrate, forming a conductive member in the via opening, and patterning the metal carrier bonded to the second surface of the thinned substrate to form a metal pattern.07-14-2011
20100279468LAMINATED FILM AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - The present invention provides a laminated film which includes a pressure-sensitive adhesive sheet including a pressure-sensitive adhesive layer, and a die-adhering layer laminated on the pressure-sensitive adhesive layer of the pressure-sensitive adhesive sheet, the laminated film being for use in a production step of a semiconductor device, in which the pressure-sensitive adhesive layer of the pressure-sensitive adhesive sheet contains a water-supporting body, and the pressure-sensitive adhesive layer has a gel fraction of 90% by weight or more.11-04-2010
20100279467METHODOLOGY FOR PROCESSING A PANEL DURING SEMICONDUCTOR DEVICE FABRICATION11-04-2010
20080241999SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device is manufactured by sealing a semiconductor chip, which is mounted on a prescribed support such as a lead frame, support bars, and a substrate connected with electrical wiring, in a package. Herein, individual information containing management information representing manufacturing conditions of semiconductor chips and test information representing results of testing of semiconductor chips is automatically recorded on a prescribed position of the prescribed support with respect to each of the semiconductor chips in synchronization with a die bonding process in response to the type of the package. That is, the individual information is recorded on exposed portions of outer leads, exposed portions of support bars, or the backside of the substrate, for example. This improves workability in reading and writing individual information without error, traceability to assure quality of semiconductor devices, and analysis of defects in semiconductor devices.10-02-2008
20080274592Process and apparatus for wafer-level flip-chip assembly - A method of forming an integrated circuit structure is provided. The method includes providing an interposer wafer; mounting the interposer wafer onto a handling wafer; thinning a backside of the interposer wafer; removing the handling wafer from the interposer wafer after the step of thinning; securing the interposer wafer on a fixture; and bonding a die on the interposer wafer.11-06-2008
20080274593Semiconductor device package with multi-chips and method of the same - The present invention provides a semiconductor device package with the multi-chips comprising a substrate with at least a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. At least a first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Then, a first bonding wire is formed to couple the first bonding pads and the first contact pads. Further, at least a second die having second bonding pads is placed on the first die. A second bonding wire is formed to couple to the second bonding pads and the first contact pads. A dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate.11-06-2008
20080286902METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.11-20-2008
20080286903Semiconductor device packaged into chip size and manufacturing method thereof - A semiconductor device includes a semiconductor substrate having an integrated circuit and at least one connection pad, and at least one external connection electrode electrically connected with the connection pad. A first sealing material is provided on the semiconductor substrate around the external connection electrode, each impurity concentration of an Na ion, a K ion, a Ca ion and Cl ion contained in the first sealing material being not greater than 10 ppm. A second sealing material is provided on at least one of a lower surface and a peripheral side surface of the semiconductor substrate, a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the second sealing material being not smaller than 100 ppm.11-20-2008
20080293187Substrate table and chip manufacturing method - A substrate table used for manufacturing a chip is provided. The substrate table includes a substrate stage, a substrate placement surface formed on the substrate stage, and on which a substrate is placed, and a guiding member that can project and retract from the substrate placement surface. The guiding member positions the substrate when the guiding member is at a projected position abutting an edge portion of the substrate placed on the substrate placement surface, and the guiding member retracts at a time of applying a tape to the substrate.11-27-2008
20090087950Wafer packaging method - A wafer packaging method is disclosed.04-02-2009
20080318362Manufacturing Method of Semiconductor Integrated Circuit Device - After performing rough grinding to the back surface of a semiconductor wafer using the first grinding material (for example, particle size of polish fine powder from #320 to #360) and making the thickness of the semiconductor wafer, for example less than 140 □m, less than 120 □m, or less than 100 □m, the back surface of the semiconductor wafer being performed fine finish grinding using the third grinding material (for example, particle size of polish fine powder from #3000 to #100000), the thickness of the semiconductor wafer becomes, for example less than 100 □m, less than 80 □m, or less than 60 □m, and the relatively thin second crush layer, for example the second crush layer of the thickness of less than 0.5 □m, less than 0.3 □m, or less than 0.1 □m is formed on the back surface of the semiconductor wafer. Thereby, without reducing the die strength of a chip, at the same time permeation of the pollution impurities from the back surface of the semiconductor wafer and further, diffusion of the pollution impurities to the circuit formation surface of the semiconductor wafer are prevented, and the poor characteristic of semiconductor elements is prevented.12-25-2008
20100136747METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - Provided is a method for manufacturing a semiconductor package. The method includes providing a first substrate having a first top surface on which a chip pad is formed and a first bottom surface opposite to the first top surface. The method additionally includes removing a portion of the first top surface to form a sawing groove, and forming a conductive pattern on the first substrate. Also, the method includes removing a portion of the first bottom surface to divide the first substrate into a plurality of semiconductor chips having a redistribution pattern formed of a portion of the conductive pattern, and mounting a selected one of the plurality of semiconductor chips on a second substrate having a second top surface on which a lead is formed. The method further includes forming an interconnector electrically connecting the lead to the redistribution pattern.06-03-2010
20120142146METHOD OF MANUFACTURING LAYERED CHIP PACKAGE - A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of stacked layer portions. A method of manufacturing the layered chip package includes the step of fabricating a layered substructure and the step of cutting the layered substructure. The layered substructure includes: a plurality of arrayed pre-separation main bodies; a plurality of accommodation parts disposed between two adjacent pre-separation main bodies; and a plurality of preliminary wires accommodated in the accommodation parts. The accommodation parts are formed in a photosensitive resin layer by photolithography. In the step of cutting the layered substructure, the plurality of pre-separation main bodies are separated from each other, and the wires are formed by the preliminary wires.06-07-2012
20110207263SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - The present invention relates to a method of manufacturing a semiconductor device including (1) forming a laminated structure on a major surface of a semiconductor substrate, the laminated structure comprising at least a first metal layer that forms a Schottky junction with the semiconductor substrate, a second metal layer primarily composed of aluminum, and a third metal layer primarily composed of molybdenum or titanium, (2) patterning the laminated structure into a predetermined configuration, (3) forming a solder bonding metal layer comprising at least nickel, ion or cobalt on the major surface of the semiconductor substrate having the patterned laminated structure formed thereon, (4) patterning the solder bonding metal layer into a pattern configuration identical to that of the laminated structure, (5) cutting the semiconductor substrate on which the laminated structure and the solder bonding metal layer are patterned to form a plurality of semiconductor chips, and (6) bonding the semiconductor chip to a first frame using at least one solder layer formed on the solder bonding metal layer on the major surface of the semiconductor substrate, and bonding a rear face of the semiconductor chip to a second frame.08-25-2011
20090298232METHOD OF FORMING A LEADED MOLDED ARRAY PACKAGE - In one embodiment, a method for forming a leaded molded array package includes placing a lead frame assembly into a molding apparatus having lead cavities. The method further includes forming seals between conductive leads within the lead frame assembly and the lead cavities, and encapsulating the lead frame assembly to form a molded array assembly. The molded array assembly is then separated into individual leaded molded packages.12-03-2009
20090298231Cmos process for fabrication of ultra small or non standard size or shape semiconductor die - A method for the singulation of integrated circuit die, the method including: etching a semiconductor layer disposed on a silicon oxide dielectric layer, thereby forming a trench defining a boundary of the die; depositing a silicon nitride layer in the trench; coating the semiconductor layer with an oxide layer such that the trench is filled; removing part of the oxide layer from the semiconductor layer such that the oxide layer only remains in the trench; mounting the semiconductor layer to a carrier; removing the silicon oxide dialectic layer, the nitride layer, and the oxide layer; and releasing the die from the carrier. The method is suitable for irregularly shaped or extremely small die and is compatible with traditional CMOS processes.12-03-2009
20110269269LASER ABLATION ALTERNATIVE TO LOW COST LEADFRAME PROCESS - The present inventions relate generally to methods for packaging integrated circuits using thin foils that form electrical interconnects for the package. The foil includes a base layer (such as copper) with an optional plating layer (such as silver) suitable for improving adhesion of the bonding wires (or other connectors) to the foil. The base layer (or the plated surface if the foil is preplated) of the foil is patterned by laser ablation to define components (e.g. contacts) of a device area. The patterning is arranged to ablate entirely through selected portions of the plating layer and part, but not all, of the way through corresponding underlying portions of the base layer. In some embodiments, the metallic foil is partially etched after the laser ablation in order to deepen the trenches that define the patterning of the foil. Multiple dice may then be attached to die attach pad areas of the plated foil and electrically coupled to electrical contacts. Some embodiments contemplate encapsulating the dice, bonding wires, and portions of the plated foil with a plastic molding material. Portions of the metallic foil may then be removed by etching, laser ablation, or grinding. The resulting structure may then be singulated to form individual integrated circuit packages.11-03-2011
20090186448Method for providing an LED chip with a peripheral protective film before cutting the same from a wafer - A method is disclosed to divide a wafer into chips. In the method, a substrate is provided. The substrate is made of an isolating material. An epitaxial laminate is provided on the substrate. At least one slit is made through the epitaxial laminate completely to form at least two chips connected to each other by the substrate only so that each of the chips includes a portion of the substrate and a portion of the epitaxial laminate. Positive and negative electrodes are formed in each of the chips. An upper protective film is provided to cover an upper side of each of the chips except the electrodes. A peripheral protective film is provided into the slit to cover the periphery of the portion of the epitaxial laminate of each of the chips. Finally, the chips are separated from each other.07-23-2009
20080318363Stack circuit member and method - A stack circuit member may include a first circuit member and a second circuit member. The first and the second circuit members may be electrically and mechanically connected together using a thermocompression bonding method. A photosensitive polymer layer may be interposed between the first circuit member and the second circuit member. A gap fill process and an electrical connection process may be performed at the same time.12-25-2008
20090004778Manufacturing Method of Light Emitting Diode - Disclosed is a manufacturing method of a light emitting diode. The manufacturing method comprises the steps of preparing a substrate and mounting light emitting chips on the substrate. An intermediate plate is positioned on the substrate. The intermediate plate has through-holes for receiving the light emitting chips and grooves for connecting the through-holes to one another on its upper surface. A transfer molding process is performed with a transparent molding material by using the grooves as runners to form first molding portions filling the through-holes. Thereafter, the intermediate plate is removed, and the substrate is separated into individual light emitting diodes. Accordingly, it is possible to provide a light emitting diode in which the first molding portion formed through a transfer molding process is positioned within a region encompassed by cut surfaces of the substrate. Since the first molding portion is positioned within the region encompassed by the cut surfaces of the substrate, second molding portions can be symmetrically formed on the side surfaces of the first molding portions in various manners.01-01-2009
20090029505SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS - A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode.01-29-2009
20090186449METHOD FOR FABRICATING PACKAGE STRUCTURES FOR OPTOELECTRONIC DEVICES - A package structure for an optoelectronic device. The package structure comprises a device chip reversely disposed on a first substrate, which comprises a second substrate and a first dielectric layer between the first and second substrates. The first dielectric layer comprises a pad formed in a corner of the first dielectric layer non-overlapping the second substrate, such that the surface and sidewall of the pad are exposed. A metal layer is formed directly on the exposed surface of the pad and covers the second substrate. A protective layer covers the metal layer, having an opening to expose a portion of the metal layer on the second substrate. A solder ball is disposed in the opening, electrically connecting to the metal layer. The invention also discloses a method for fabricating the same.07-23-2009
20090325346SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.12-31-2009
20130217185POWER DEVICE MANUFACTURE ON THE RECESSED SIDE OF A THINNED WAFER - A recess is formed into a first side of a wafer such that a thinned center portion of the wafer is formed, and such that the central portion is surrounded by a thicker peripheral edge support portion. The second side of the wafer remains substantially entirely planar. After formation of the thinned wafer, vertical power devices are formed into the first side of the central portion of the wafer. Formation of the devices involves forming a plurality of diffusion regions into the first side of the thinned central portion. Metal electrodes are formed on the first and second sides, the peripheral portion is cut from the wafer, and the thin central portion is diced to form separate power devices. In one example, a first commercial entity manufactures the thinned wafers, and a second commercial entity obtains the thinned wafers and performs subsequent processing to form the vertical power devices.08-22-2013
20100248426METHOD OF MAKING CHIP-ON-LEAD PACKAGE - A process for assembling a Chip-On-Lead packaged semiconductor device includes the steps of: mounting and sawing a wafer to provide individual semiconductor dies; performing a first molding operation on a lead frame; depositing epoxy on the lead frame via a screen printing process; attaching one of the singulated dies on the lead frame with the epoxy, where the die attach is done at room temperature; and curing the epoxy in an oven. Throughput improvements may be ascribed to not including a hot die attach process. An optional plasma cleaning step may be performed, which greatly improves wire bonding quality and a second molding quality. In addition, since a first molding operation is performed before the formation of epoxy to avoid the problem of the epoxy hanging in the air, the delamination risk between the epoxy and the die is avoided.09-30-2010
20100248425Chip-size-package semiconductor chip and manufacturing method - A method of manufacturing semiconductor chips includes preparing a semiconductor substrate having on its front side a plurality of chip forming areas; sticking a support to the front surface of the substrate via an adhesive sheet; forming through holes extending from the back surface of the substrate; forming a groove along each of boundaries between the chip forming areas, the groove extending from the back surface of the substrate through the adhesive sheet to the support to expose cross-sections of the adhesive sheet; forming an insulating film over the back surface so as to cover side walls of the through holes and the cross-sections of the adhesive sheet; and dicing the substrate along the grooves with the insulating film remaining.09-30-2010
20100003786CHIP-LEVEL UNDERFILL PROCESS AND STRUCTURES THEREOF - A process comprises forming a first electrical interconnect structure on a surface of a singulated semiconductor chip having an alignment pattern. The alignment pattern is scanned and stored in a scanning device prior to application of a curable underfill coating to the surface of the singulated semiconductor chip. This is followed by applying a curable underfill coating to the surface of the singulated semiconductor chip to produce a coated semiconductor chip. The process also includes a step of delivering the scanned and stored alignment pattern to an alignment and joining device positioned adjacent to and operatively associated with a substrate having a second electrical interconnect structure alignable to make electrical contact with the first electrical interconnect structure. The coated semiconductor chip is placed in the alignment and joining device so that when the scanned and stored alignment pattern is activated the alignment and joining device positions the coated semiconductor chip so that the first electrical interconnect structure is aligned to make electrical contact with the second electrical interconnect structure. This is followed by activating the alignment and joining device to join the coated semiconductor chip to the substrate so that the first electrical interconnect structure is in electrical contact with the second electrical interconnect structure. In one embodiment, the first electrical interconnect structure is placed on a surface of a semiconductor chip array in a wafer to produce the electrically connectable semiconductor structure which is followed by dicing to produce at least one of the singulated semiconductor chips. Another embodiment comprises aligning the fist and second electrical interconnect structures prior to applying the curable underfill coating.01-07-2010
20090053856SEMICONDUCTOR DEVICE COMPRISING LIGHT-EMITTING ELEMENT AND LIGHT-RECEIVING ELEMENT, AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes a substrate for transmitting light, a wiring layer provided on the substrate, a semiconductor chip formed on the wiring layer, a columnar electrode, a sealant, and an external connection terminal electrically connected to the semiconductor chip via the wiring layer and protruding electrode. The device includes a cut surface formed by dicing and constituted by only the substrate and the sealant. Since the cut surface has a single-layer structure as a result of forming the sealant in a single step, moisture cannot infiltrate through the sealant, hence a device resistant to corrosion and operational defects is provided.02-26-2009
20090209065METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND ULTRASONIC BONDING APPARATUS - An example of the invention is a method of manufacturing a semiconductor device including, pressing a part of the connection conductor having a plate-like shape or a belt-like shape against a lead terminal which is formed on a lead frame, is formed into a thin and long plate-like shape, and is supported only at one end in a longitudinal direction of the terminal, in such a manner that the part of the conductor is brought into contact with the lead terminal, and applying ultrasonic vibration substantially in the longitudinal direction in a plane perpendicular to the pressing direction to the connection conductor in the state where the part of the connection conductor is pressed against the lead terminal.08-20-2009
20090246913Adhesive Composition, Adhesive Sheet and Production Method of Semiconductor Device - The object of the present invention is to provide an adhesive composition that enables to produce conforming products with a high manufacturing yield and without breaking or chipping of the chips in the picking-up step and that enables to stably connect a wire without contaminating a wire pad part disposed at the circumference of a bonding surface during a wire bonding step that is performed after die bonding, even in the case of chips being reduced in a thickness.10-01-2009
20080261351WAFER SAWING METHOD - A wafer sawing method for sawing a wafer by using a cutting tool is provided. Sawing paths are formed on a surface of the wafer. In the wafer sawing method, a carrier on which strip-shaped adhesives or at least a fiducial mark is formed is firstly provided. The dimension of the carrier is greater than the dimension of the wafer. Next, the surface of the wafer is bonded to the carrier, and the strip-shaped adhesives or the fiducial mark is extended or located outside a bonding region between the wafer and the carrier. Here, the surface of the wafer faces the carrier. The cutting tool and the carrier are positioned according to the strip-shaped adhesives or the fiducial mark outside the bonding region. The wafer is then sawed by using the cutting tool. The wafer sawing method provides a precise and rapid sawing process and achieves superior productive yield.10-23-2008
20090246912METHOD OF PRODUCING SEMICONDUCTOR PACKAGES - Semiconductor chips are fixed to one of two opposite surfaces of a leadframe, and the leadframe is electrically connected to each semiconductor chip with wires. After having applied water-soluble masking ink to the other surface of the leadframe, a sealed structure is molded. Then, when the sealed structure is cut with cutting water into individual semiconductor packages, burrs of the mold resin formed on the other surface side of the leadframe are removed by the cutting water while the masking ink on the other surface of the leadframe is dissolved and removed by the cutting water.10-01-2009
20090246914Semiconductor package and method of manufacturing the same - A package may include a semiconductor chip mounted on a film substrate. A method of manufacturing the same may involve providing a semiconductor chip. The semiconductor chip may include recesses and bumps. A film substrate including a through hole may be provided. The semiconductor chip may be inserted into the through hole of the film substrate. Circuit wires may be formed on the film substrate to contact the bumps of the semiconductor chip.10-01-2009
20090253231ADHESIVE SHEET FOR LASER DICING AND ITS MANUFACTURING METHOD - An adhesive sheet for laser dicing is used for dicing a workpiece into individual chips by light absorption ablation of laser beam and has at least an adhesive layer on one side of a base material which has a surface opposite to the adhesive layer having no convex parts of width (W) of 20 mm or less and height (h) of 1 μm or more, or no concave parts of width (W) of 20 mm or less and depth (d) of 1 μm or more.10-08-2009
20100015760SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Of three chips (01-21-2010
20100178733Thin Quad Flat Package with No Leads (QFN) Fabrication Methods - Embodiments of the present invention include a method of packaging semiconductor devices. The method comprises the steps of molding a surface of a wafer, sawing the wafer into individual devices, attaching the individual semiconductor device to an adhesive surface, molding the exposed surface, and sawing the wafer into individual semiconductor devices. The step of molding forms a continuous molded layer. The step of sawing results in each individual semiconductor having a molded layer. This molded layer corresponds to a portion of the continuous molded layer. The step of attaching includes attaching the molded layer of the individual semiconductor devices to the adhesive surface. The step of molding the exposed area includes molding an exposed area above the adhesive surface. This forms a solid expanse of material. The step of sawing the wafer into individual semiconductor devices includes sawing the solid expanse of material.07-15-2010
20100151627FABRICATION METHOD OF THIN FILM DEVICE - A method for fabricating a thin film device includes the step of forming a sacrificial layer on a first substrate. A portion other than a region of the sacrificial layer is selectively removed. A material film is formed on the sacrificial layer to be connected to the first substrate via the selectively removed region. The material film portion filled in the selectively removed region is provided as an anchor. A thin film lamination is formed on the material film. The desired thin film device is formed by using a selective etching process. After removing the sacrificial layer, the thin film device floats over the first substrate with being supported by the anchor. A support body is temporarily attached on the thin film lamination. The thin film device is transferred to the support body onto a second substrate.06-17-2010
20100159644LOW-COST FLIP-CHIP INTERCONNECT WITH AN INTEGRATED WAFER-APPLIED PHOTO-SENSITIVE ADHESIVE AND METAL-LOADED EPOXY PASTE SYSTEM - Various exemplary embodiments provide materials and methods for flip-chip packaging technology. The disclosed flip-chip packaging technology can use a single B-stage wafer-applied photo-sensitive adhesive along with printed interconnects, which does not include conventional underfill materials and processes. In one embodiment, a photo-sensitive adhesive can be applied on a semiconductor die or a base substrate with conductive bumps printed in through-openings of the photo-sensitive adhesive. One or more semiconductor dies can be laterally packaged or vertically stacked on the base substrate using the printed conductive bumps as interconnects there-between.06-24-2010
20110111562Partially Patterned Lead Frames and Methods of Making and Using the Same in Semiconductor Packaging - A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.05-12-2011
20100184255MANUFACTURING METHOD FOR PACKAGE STRUCTURE - A manufacturing method for package structure is provided. The manufacturing method includes the follow steps. Firstly, a substrate is provided. Next, a number of chips are provided. Then, the chips are electrically connected with the substrate. After that, the chips are encapsulated with a sealant, so that the chips and the substrate form a package. Then, the package is adhered by a vacuum force. Afterwards, the adhered package is singulated to form many package structures along the portion between adjacent two of airways.07-22-2010
20100159645SEMICONDUCTOR APPARATUS AND PROCESS OF PRODUCTION THEREOF - A method of producing a semiconductor apparatus, the method including forming metal ball bumps in direct contact with a circuit pattern of a semiconductor device, forming a resin film to seal spaces between the metal ball bumps, cleaning the surfaces of the metal ball bumps projecting out from the resin film using plasma cleaning by removing components inviting a rise in a connection resistance and a decline in a joint strength, forming eutectic solder layers different in composition from the metal ball bumps on the surfaces of the metal ball bumps, cutting the semiconductor substrate into unit semiconductor chips, and mounting at least one of the chips on a mounting board from a bump forming surface side of the chip so as to connect the eutectic solder layers to the mounting board with the resin film directly contacting the chip and not directly contacting the mounting board.06-24-2010
20100151628MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - An improved manufacturing method for semiconductor devices is provided. This method can prevent chips and cracks from being generated when the rear face of the semiconductor substrate is polished. The manufacturing method includes preparing a semiconductor substrate having a front face and a rear face. The front face has an inner surface area and a peripheral surface area. Circuit elements are provided in the inner surface area of the semiconductor substrate. The manufacturing method also includes sealing the circuit elements with circuit sealing resin. The manufacturing method also includes providing cured resin in the peripheral surface area of the semiconductor substrate. The manufacturing method also includes polishing the rear face of the semiconductor substrate after the circuit sealing step. The manufacturing method also includes cutting the semiconductor substrate after the substrate polishing step so as to obtain semiconductor devices.06-17-2010
20100240176ELECTRONIC COMPONENT, SEMICONDUCTOR DEVICE, METHODS OF MANUFACTURING THE SAME, CIRCUIT BOARD, AND ELECTRONIC INSTRUMENT - The present invention is a method of manufacturing a semiconductor device, by forming a wiring on or above a wafer so that the wiring is electrically connected to a first electrode disposed on a first surface of the wafer, forming a first resin layer on or above the wafer such that the wiring is disposed between the wafer and the first resin layer, forming an opening in the first resin layer such that the opening overlaps the wiring, forming a conductive member in the opening such that the conductive member being electrically connected to the wiring, forming a second electrode on the conductive member such that the second electrode is electrically connected to the wiring via the conductive member, and separating the wafer into individual elements after the forming of the first resin layer.09-23-2010
20100144097METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE IN WHICH BOTTOM SURFACE AND SIDE SURFACE OF SEMICONDUCTOR SUBSTRATE ARE COVERED WITH RESIN PROTECTIVE FILM - First, a trench is formed in parts of a semiconductor wafer, a sealing film and other elements corresponding to a dicing street and both sides thereof. In this state, the semiconductor wafer is separated into silicon substrates by the formation of the trench. Then, a resin protective film is formed on the bottom surface of each silicon substrate including the inner part of the trench. In this case, the semiconductor wafer is separated into the silicon substrates. However, a support plate is affixed to the upper surfaces of the columnar electrode and the sealing film via an adhesive layer. Therefore, when the resin protective film is formed, it is possible to prevent the entire workpiece including the separated silicon substrates from being easily warped.06-10-2010
20100144096METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE IN WHICH BOTTOM SURFACE AND SIDE SURFACE OF SEMICONDUCTOR SUBSTRATE ARE COVERED WITH RESIN PROTECTIVE FILM - First, a trench is formed in parts of a semiconductor wafer, a sealing film and other elements corresponding to a dicing street and both sides thereof. In this state, the semiconductor wafer is separated into silicon substrates by the formation of the trench. Then, a resin protective film is formed on the bottom surface of each silicon substrate including the inner part of the trench. In this case, the semiconductor wafer is separated into the silicon substrates. However, a support plate is affixed to the upper surfaces of the columnar electrode and the sealing film via an adhesive layer. Therefore, when the resin protective film is formed, it is possible to prevent the entire workpiece including the separated silicon substrates from being easily warped.06-10-2010
20130217186METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING ELECTRONIC ASSEMBLY - A method of manufacturing a semiconductor device, includes: providing an adhesive layer on a support body; providing a semiconductor element on the adhesive layer; providing a resin layer on the adhesive layer, the semiconductor element being provided on the adhesive layer, and forming a substrate on the adhesive layer, the substrate including the semiconductor element and the resin layer; and removing the substrate from the adhesive layer, wherein an adhesive force of the adhesive layer in a direction in which the substrate is removed is less than an adhesive force of the adhesive layer in a planar direction in which the substrate is formed.08-22-2013
20100136746METHOD FOR PRODUCING A SET OF CHIPS MECHANICALLY INTERCONNECTED BY MEANS OF A FLEXIBLE CONNECTION - The method relates to production of a set of chips mechanically interconnected by means of a flexible connection. The chips, integrated on a substrate, each comprise a receiving area. The chips of the set are connected in series in the receiving areas by a connecting element. The chips are then released, the connecting element forming a flexible connection.06-03-2010
20080293188Reactive solder material - Reactive solder material. The reactive solder material may be soldered to semiconductor surfaces such as the backside of a die or wafer. The reactive solder material includes a base solder material alloyed with an active element material. The reactive solder material may also be applied to a portion of a thermal management device. The reactive solder material may be useful as a thermally conductive interface between a semiconductor surface and a thermal management device.11-27-2008
20100197078DICING FILM HAVING SHRINKAGE RELEASE FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME. - The present invention relates to a dicing film having an adhesive film for dicing a wafer and a die adhesive film, which are used for manufacturing a semiconductor package, and a method of manufacturing a semiconductor package using the same. More particularly, the present invention relates to a dicing film wherein a shrinkage release film is inserted between an adhesive film for dicing a wafer and a die adhesive film so that the die adhesive film and a die can be easily separated from the adhesive film for dicing a wafer when picking up a semiconductor die, and a method of manufacturing a semiconductor package using the same.08-05-2010
20100197079SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR ELEMENTS MOUNTED ON BASE PLATE - A method of manufacturing a semiconductor device and a semiconductor device including a first semiconductor element mounted on a first surface of a base plate, wherein solder balls are formed on a second opposite surface of the base plate-such that the second opposite surface includes an area without solder balls. At least one second semiconductor element is mounted to the base plate at the area of the second surface without solder balls. The at least one semiconductor element may be mounted to the base plate using low molecular adhesive, or in the alternative, high temperature solder.08-05-2010
20090023249Wire bonded wafer level cavity package - A microelectronic device includes a chip having a front surface and a rear surface, the front surface having an active region and a plurality of contacts exposed at the front surface outside of the active region. The device further includes a lid overlying the front surface. The lid has edges bounding the lid, at least one of the edges including one or more outer portions and one or more recesses extending laterally inwardly from the outer portions, with the contacts being aligned with the recesses and exposed through them.01-22-2009
20130130443METHOD FOR PACKAGING ULTRA-THIN CHIP WITH SOLDER BALL THERMO-COMPRESSION IN WAFER LEVEL PACKAGING PROCESS - The invention generally relates to a packaging method of an ultra-thin chip, more specifically, the invention relates to a method for packaging the ultra-thin chip with solder ball thermo-compression in wafer level packaging process. The method starts with disposing solder balls on metal pads arranged on the front surface of semiconductor chips that are formed at the front surface of a semiconductor wafer. The solder balls are soften by heating the wafer, a compression plate is applied with a pressure on the top ends of the solder balls thus forming a co-planar top surface at the top ends of the solder balls. A molding compound is deposited on the front surface of the wafer with the top ends of the solder balls exposed. The wafer is then ground from its back surface to reduce its thickness to achieve ultra-thin chip.05-23-2013
20130130444CHIP PACKAGE AND FABRICATION METHOD THEREOF - The invention is related to a chip package including: a semiconductor substrate having at least one bonding pad region and at least one device region, wherein the semiconductor substrate includes a plurality of heavily doped regions in the bonding pad region, and two of the heavily doped regions are insulatively isolated; a plurality of conductive pad structures disposed over the bonding pad region; at least one opening disposed at a sidewall of the chip package to expose the heavily doped regions; and a conductive pattern disposed in the opening to electrically contact with the heavily doped region.05-23-2013
20130137219METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - There is provided a method for producing a semiconductor device, which is capable of suppressing voids during mounting of a semiconductor element to produce a semiconductor device with high reliability. A method for producing a semiconductor device of the present invention includes the steps of: providing a sealing sheet having a base material and an under-fill material laminated on the base material; bonding the sealing sheet to a surface of a semiconductor wafer on which a connection member is formed; dicing the semiconductor wafer to form a semiconductor element with the under-fill material; retaining the semiconductor element with the under-fill material at 100 to 200° C. for 1 second or more; and electrically connecting the semiconductor element and the adherend through the connection member while filling a space between the adherend and the semiconductor element with the under-fill material.05-30-2013
20100311207Compounds Having A Diphenyl Oxide Backbone and Maleimide Functional Group - A compound having a diphenyl oxide backbone, and pendant from the backbone at least one hydrocarbon chain, the hydrocarbon chain containing an ester functionality and being terminated with a maleimide functional group is prepared from the reaction of diphenyl oxide, formaldehyde or paraformaldehyde, and a compound containing both carboxylic acid and maleimide functionality. Exemplary compounds include:12-09-2010
20110129961Process to form semiconductor packages with external leads - This invention discloses a process for packaging semiconductor device with external leads. The process includes comprises Step 1: providing a lead frame comprising a plurality of lead frame units connected by a plurality of metal beams, each lead frame unit comprising a die pad and a plurality of leads located on opposite sides of the die pad; adhering a semiconductor chip onto each of the die pad, and providing a plurality of metal connections for electrically connecting each chip to its corresponding leads; Step 2 providing a plastic molding material to enclose the plurality of the lead frame units, the metal beams, the chips, and at least portions of the metal connections; Step 3 removing a portion of the plastic molding material above the metal beams to expose the metal beams and portions of the leads in connection with the metal beams; and Step 4 separating each lead frame unit, forming a plurality of individual semiconductor plastic package components with external leads.06-02-2011
20110027942SEMICONDUCTOR PACKAGE - A semiconductor package is disclosed. One embodiment provides a semiconductor package singulated from a wafer includes a chip defining an active surface, a back side opposite the active surface, and peripheral sides extending between the active surface and the back side; a contact pad disposed on the active surface; and a metallization layer extending from the contact pad onto a portion of the peripheral sides of the chip.02-03-2011
20110014749Method for Packaging Semiconductor Dies Having Through-Silicon Vias - An integrated circuit structure is provided. The integrated circuit structure includes a die and an anisotropic conducing film (ACF) adjoining the back surface of the die. The die includes a front surface; a back surface on an opposite side of the die than the front surface; and a through-silicon via (TSV) exposed through the back surface of the die.01-20-2011
20110212574PROCESSING METHOD FOR PACKAGE SUBSTRATE - A processing method for a package substrate having a base substrate partitioned by a plurality of crossing division lines to form a plurality of chip forming areas where a plurality of semiconductor chips are respectively formed and molded with resin. The package substrate has a resin surface and an electrode surface opposite to the resin surface. The processing method includes a warp correcting step of cutting the package substrate from the resin surface or the electrode surface along the division lines by using a cutting blade to form a cut groove, thereby correcting a warp of the package substrate, and a grinding step of grinding the resin surface of the package substrate in the condition where the electrode surface of the package substrate is held on a holding table after performing the warp correcting step, thereby reducing the thickness of the package substrate to a predetermined thickness.09-01-2011
20110129962ENCAPSULATION METHOD FOR PACKAGING SEMICONDUCTOR COMPONENTS WITH EXTERNAL LEADS - This invention discloses a method for packaging a semiconductor device with leads extending outside its encapsulation. The method comprises the following steps: Step 1, providing a lead frame comprising a plurality of lead frame units arranged in two dimensional array, each lead frame unit comprising a die pad and a plurality of leads located along two opposite sides of the die pad, attaching a semiconductor chip onto the die pad and electrically connecting the electrodes on each chip to its corresponding leads; Step 2, Encapsulating the chips, the die pads, and the leads with molding material into a plurality of one dimensional plastic encapsulation bars with the leads of each lead frame unit extending out along two opposite sides of the plastic encapsulation bars connecting to a plurality of tie bars substantially parallel to the plastic encapsulation bars; Step 3, Trimming off the tie bars therefore cutting off the connections between the leads to the tie bars while preserving a portion of the leads extending out of the plastic encapsulation bars; and Step 4, Sawing through the plastic encapsulation bars to form a plurality of individual semiconductor components with leads extending outside its encapsulation.06-02-2011
20090221114PACKAGING AN INTEGRATED CIRCUIT DIE USING COMPRESSION MOLDING - A structure (09-03-2009
20110244630Method of Substrate Bonding with Bonding Material Having Rare Earth Metal - A microchip has a bonding material that bonds a first substrate to a second substrate. The bonding material has, among other things, a rare earth metal and other material.10-06-2011
20120244663SEMICONDUCTOR DEVICE CHIP MOUNTING METHOD - A semiconductor device chip has a plurality of projecting electrodes mounted on a wiring board or wafer having electrodes respectively corresponding to the projecting electrodes of the semiconductor device chip. An insulator is applied to the front side of the semiconductor device wafer where the projecting electrodes are formed, to fill any spaces between adjacent electrodes with the insulator. The front side of the wafer covered with the insulator is planarized to expose the end surfaces of the projecting electrodes, and the wafer is divided along division lines to obtain a plurality of individual semiconductor device chips. Each chip is mounted on the wiring board or the wafer with an anisotropic conductor interposed between the projecting electrodes of each chip and the electrodes of the wiring board or the wafer to thereby respectively connect the projecting electrodes and the electrodes through the anisotropic conductor.09-27-2012
20100055839METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device. One embodiment provides a carrier. A semiconductor chip is provided with a first face and a second face opposite to the first face. The semiconductor chip is placed over the carrier with the first face facing the carrier. A voltage is applied between the second face of the semiconductor chip and the carrier for attaching the semiconductor chip to the carrier.03-04-2010
20100055841SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A method of producing a semiconductor device includes the steps of: preparing a semiconductor wafer having an MEMS (Micro Electro Mechanical Systems) element formed on a surface thereof; forming a groove portion surrounding the MEMS element in the surface of the semiconductor wafer; preparing a sealing wafer having a recess portion formed in a surface thereof and a protruding portion surrounding the recess portion; filling an adhesive in the groove portion; arranging the semiconductor wafer so that the surface of the semiconductor wafer faces the surface of the sealing wafer; fitting the protruding portion into the groove portion so that the recess portion covers the MEMS element; hardening the adhesive to form an MEMS element mounting wafer; and cutting the MEMS element mounting wafer into pieces to obtain the semiconductor device. Further, the adhesive is formed of a silicone type resin.03-04-2010
20100055840Electronic packaging structure and a manufacturing method thereof - A packaging structure includes a main substrate having a plurality of circuit lines thereon, and an electronic module having at least one conductive pad at the bottom thereof and having a plurality of conductive lines on the sides thereof. The pad and the conductive circuits are connected electrically to the circuits on the main substrate when the electronic module is disposed on the main substrate. As above-mentioned, one electronic module can be stacked on top of another so that the integrity of the packaging structure is improved.03-04-2010
20100068853METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a substrate having first electrodes on a main surface thereof and a semiconductor chip having second electrodes on a first main surface thereof are arranged such that the main surface of the substrate and the first main surface of the semiconductor chip oppose to each other, and the first electrodes and the second electrodes are connected so as to electrically connect the substrate and the semiconductor chip. The semiconductor chip is made thin by grinding a second main surface opposing to the first main surface of the semiconductor chip which is connected with the substrate. Side surfaces and the second main surface of the semiconductor chip made thin are sealed with resin.03-18-2010
20110097851METHOD OF FABRICATING A PACKAGE STRUCTURE - A method fabricates a packaging structure, including cutting a complete panel of packaging substrates with a large area into a plurality of packaging substrate blocks each having a plurality of packaging substrate units; mounting a semiconductor chip on each of the packaging substrate units and securing the semiconductor chip to the packaging substrate unit with a molding material, to form a plurality of packaging structure blocks each having a plurality of packaging structure units; and cutting the packaging structure block into a plurality of packaging structure units. Accordingly, each of the packaging structure unit has a moderate area, the alignment difference between the packaging structure units in each of the packaging structure blocks can be reduced, and the semiconductor chips for all the packaging substrate units in each of the packaging substrate blocks can be packaged at one time. Therefore, the yield is increased and the overall cost is reduced.04-28-2011
20110097850METHOD OF FABRICATING A PACKAGING STRUCTURE - A method of fabricating a packaging structure includes cutting a panel of packaging substrate into a plurality of packaging substrate blocks each having a plurality of packaging substrate units; mounting and packaging a semiconductor chip on each of the packaging substrate unit to form package blocks each having multiple packaging structure units; and cutting package blocks to form a plurality of package units. In the method, the alignment difference between the packaging structure units in each package block is minimized by appropriately cutting and forming substrate blocks to achieve higher precision and better yield, and also packaging of semiconductor chips can be performed on all package units in the substrate blocks, thereby integrating fabrication with packaging at one time to improve production efficiency and reduce the overall costs as a result.04-28-2011
20110033981MODULAR DIE AND MASK FOR SEMICONDUCTOR PROCESSING - Modular dies and modular masks that can be used during the manufacture of semiconductor devices are described. The modular mask can be used repeatedly to make multiple, substantially-similar modular dies. The modular die contains a substrate with an integrated circuit as well as a conductive layer containing a source metal and a gate metal connected respectively to the source and gate of the integrated circuit. The gate metal of the conductive layer is located only in an outer portion of the modular die. The modular die can be made by providing the integrated circuit in a first and second portion of the substrate, providing the conductive layer on both the first and second portions, making a first modular die by patterning the conductive layer on the first portion using the modular mask; moving the modular mask to the second portion and using it to make a second modular die by patterning the conductive layer on the second portion. Thus, fewer mask sets need to be made, improving efficiency and reducing costs. Other embodiments are described.02-10-2011
20100304532Semiconductor Die Attachment Method Using Non-Conductive Screen Print and Dispense Adhesive - A uniform layer of non-conductive material, e.g., epoxy, is screen printed onto the backside of an integrated circuit wafer to a required thickness, and then heated until it is hard cured (C-stage). The integrated circuit wafer having the hard cured coating is then sawn apart to separate the individual integrated circuit dice. A non-conductive adhesive is dispensed onto mating faces of die attach paddles of leadframes. The dice are placed into the non-conductive adhesive and then the die and die attach paddle assembly are heated to hard cure the adhesive between the mating faces of the die and die attach paddle. This provides long term electrical isolation of the integrated circuit die from the die attach paddle, and effectively eliminates silver migration from the die attach paddle which causes conductive paths to form that increase unwanted leakage currents in the die and ultimately cause failure during operation thereof.12-02-2010
20110212575METHOD FOR MANUFACTURING THIN FILM INTEGRATED CIRCUIT, AND ELEMENT SUBSTRATE - Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. In view of the above described object, one feature of the invention is to provide the steps of forming a separation layer over an insulating substrate and forming a thin film integrated circuit having a semiconductor film as an active region over the separation layer, wherein the thin film integrated circuit is not separated. There is less limitation on the shape of a mother substrate in the case of using the insulating substrate, when compared with the case of taking a chip out of a circular silicon wafer. Accordingly, reduction in cost of an IC chip can be achieved.09-01-2011
20100112756INTEGRATED CIRCUIT PACKAGE FORMATION - Integrated circuit packages are formed from a panel where the panel is separated by laser cutting the panel. In some embodiments, the panel is attached to the carrier for the formation of interconnect layers on the panel. Afterwards, the panel is cut with a laser while on the carrier to separate the integrated circuit packages. A tape or other type of structure may be attached to the top of the packages after the laser cutting. The integrated circuit packages are removed from the carrier by releasing the adhesive and removing the integrated circuit packages with the tape. The packages are then removed from the tape.05-06-2010
20100105170Method for manufacturing a semiconductor device having a heat spreader - A method for manufacturing a semiconductor device includes cutting a resin sealing body into a plurality of pieces. The resin sealing body includes a plurality of semiconductor chips mounted on a wiring board, a heat spreader disposed above the plurality of the semiconductor chips, and sealing resin filled between the wiring board and the heat spreader. The cutting the resin sealing body includes shaving the resin sealing body from a side of the heat spreader and shaving the resin sealing body from a side of the wiring board. The method prevents the heat spreader from generation of burrs.04-29-2010
20110256666THERMOSETTING DIE BOND FILM, DICING DIE BOND FILM AND SEMICONDUCTOR DEVICE - The present invention provides a thermosetting type die bond film that can be preferably broken by tensile force. It is a thermosetting type die bond film used for a method of obtaining a semiconductor element from a semiconductor wafer by forming a reforming region by irradiating the semiconductor wafer with a laser beam and then breaking the semiconductor wafer in the reforming region or a method of obtaining a semiconductor element from a semiconductor wafer by forming grooves that do not reach the backside of the semiconductor wafer on a surface thereof and then exposing the grooves from the backside by grinding the backside of the semiconductor wafer, wherein the elongation rate at break at 25° C. before thermal curing is larger than 40% and 500% or less.10-20-2011
20110020984Method of Manufacturing A Semiconductor Device - A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.01-27-2011
20110053318FABRICATION METHOD OF PACKAGE STRUCTURE - Provided is a fabrication method of a package structure, including cutting a full-panel packaging substrate into a plurality of packaging substrate blocks, each of which has a plurality of packaging substrate units; mounting and packaging a semiconductor chip on each of the packaging substrate units and securing and protecting the semiconductor chips with an encapsulating material, thereby forming a plurality of packaging substrate blocks with packaging substrate units; and cutting the packaging substrate blocks to separate the packaging substrate units from each other. In the fabrication process, the alignment error between packaging substrate units in each packaging substrate block can be reduced by cutting the packaging substrate into packaging substrate blocks of appropriate size, thereby increasing the yield, and also the packaging of the semiconductor chips can be performed at the same time on all packaging substrate units in each substrate block so as to integrate fabrication of substrates with the packaging of semiconductor chips to simplify fabrication steps, thus increasing the productivity and reducing fabrication costs.03-03-2011
20100285636MANUFACTURING METHOD OF A PACKAGING STRUCTURE OF ELECTRONIC COMPONENTS - A manufacturing method of a packaging structure of electronic components includes the steps of: providing a substrate including a plurality of electronic components; covering the electronic components disposed on the substrate with a molding body; forming a plurality of pre-cut grooves on the molding body so as to define a plurality of molding units on the molding body; forming an electromagnet barrier layer covering the molding units on the molding units and the pre-cut grooves; and cutting along at least one of the pre-cut grooves deeply down to break the substrate so as to form separately a plurality of packaging structures of the electronic components.11-11-2010
20110256667STACKED WAFER MANUFACTURING METHOD - A manufacturing method for a stacked wafer configured by bonding a mother wafer having a plurality of first semiconductor device and a stacking wafer having a plurality of second semiconductor devices. The manufacturing method includes the steps of attaching a protective member to the front side of the stacking wafer to protect the second semiconductor devices, next grinding the back side of the stacking wafer, next bonding the front side of a reinforcing wafer through a bonding layer to the back side of the stacking wafer, next dividing the stacking wafer together with the reinforcing wafer into the plural second semiconductor devices, next bonding the front side of each second semiconductor device to the front side of the mother wafer to thereby connect the electrodes of each second semiconductor device to the electrodes of the corresponding first semiconductor device of the mother wafer, and finally grinding the reinforcing wafer bonded to the back side of each second semiconductor device to thereby remove the reinforcing wafer.10-20-2011
20090191668METHOD FOR MANUFACTURING IC TAG INLET - An IC tag inlet (07-30-2009
20100047969BACKGRINDING-UNDERFILL FILM, METHOD OF FORMING THE SAME, SEMICONDUCTOR PACKAGE USING THE BACKGRINDING-UNDERFILL FILM, AND METHOD OF FORMING THE SEMICONDUCTOR PACKAGE - A semiconductor package forming method includes mounting a backgrinding-underfill film which includes a laminated backgrinding film and a laminated underfill film on a semiconductor wafer so that the underfill film adheres to a front side of the semiconductor wafer; backgrinding a back side of the semiconductor wafer on which the backgrinding-underfill film has been mounted and removing the backgrinding film of the backgrinding-underfill film from the semiconductor wafer. The method further includes dicing the semiconductor wafer from which the backgrinding film has been removed, so that semiconductor chips are separated from the semiconductor wafer.02-25-2010
20120309130Method of Manufacturing a Semiconductor Device - In one embodiment a method for manufacturing a semiconductor device comprises arranging a wafer on a carrier, the wafer comprising singulated chips; bonding the singulated chips to a support wafer, and removing the carrier.12-06-2012
20100190296METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides a method of manufacturing a semiconductor device in which a thinned substrate of a semiconductor or semiconductor device is handled without cracks in the substrate and treated with heat to improve a contact between semiconductor back surface and metal in a high yield and a semiconductor device may be manufactured in a high yield. In the method of manufacturing a semiconductor device according to the present invention, a notched part is formed from a surface to a middle in a semiconductor substrate by dicing and the surface of the substrate is fixed to a support base. Next, a back surface of the substrate is ground to thin the semiconductor substrate and then a metal electrode and a carbon film that is a heat receiving layer are sequentially formed on the back surface of the substrate. Next, the carbon film is irradiated with light at a power density of 1 kW/cm07-29-2010
20110189823METHOD OF MAKING SEMICONDUCTOR PACKAGE WITH IMPROVED STANDOFF - A no-lead type semiconductor package is formed by attaching a die to a top surface of a flag of a lead frame and then taping a bottom surface of the flag and leads of the lead frame. Die bonding pads are connected to the leads with wires and then the assembly is put in a mold chase and encapsulated with a plastic material. The mold chase has protrusions between the flag and the leads of a lead frame, and between the leads themselves, which causes indentations to be formed between the leads and between the flag and the leads. The method is particularly useful for making quad flat no lead (QFN) devices and power-QFN type devices.08-04-2011
20100144095METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE IN WHICH BOTTOM SURFACE AND SIDE SURFACE OF SEMICONDUCTOR SUBSTRATE ARE COVERED WITH RESIN PROTECTIVE FILM - First, a trench formed in parts of a semiconductor wafer, a sealing film and others corresponding to a dicing street and both sides thereof. In this state, the semiconductor wafer is separated into silicon substrates by the formation of the trench. Then, a resin protective film is formed on the bottom surface of each silicon substrate including the inner part of the trench. In this case, the semiconductor wafer is separated into the silicon substrates. However, a support plate is affixed to the upper surfaces of the columnar electrode and the sealing film via an adhesive layer. Therefore, when the resin protective film is formed, it is possible to prevent the entirety including the separated silicon substrates from being easily warped.06-10-2010
20110070698Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method - This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size, shape and thickness of the adhesive material are applied according to different application requirements according to size and shapes of the contact zone of the semiconductor chip and the metal connector. Particularly, the adhesive zones are formed by pre-printing the adhesive material thus significantly enhance the quality and performance of semiconductor products, and improves the productivity.03-24-2011
20110117702APPARATUS AND METHOD FOR PROCESSING A SUBSTRATE - A method of processing a substrate that displays out-gassing when placed in a vacuum comprises placing the substrate in a vacuum and performing an out-gassing treatment by heating the substrate to a temperature T05-19-2011
20130196470CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad.08-01-2013
20120302008Packaging Jig and Process for Semiconductor Packaging - An embodiment is a method for semiconductor packaging. The method comprises attaching a chip to a carrier substrate through a first side of a jig, the chip being attached by bumps; applying balls to bond pads on the carrier substrate through a second side of the jig; and simultaneously reflowing the bumps and the balls. According to a further embodiment, a packaging jig comprises a cover, a base, and a connector. The cover has a first window through the cover. The base has a second window through the base. The first window exposes a first surface of a volume intermediate the cover and the base, and the second window exposes a second surface of the volume. The first surface is opposite the volume from the second surface. The connector aligns and couples the cover to the base.11-29-2012
20080268575Orientation-dependent etching of deposited AIN for structural use and sacrificial layers in MEMS - In accordance with the present invention, accurate and easily controlled sloped walls may be formed using. AlN and preferably a heated TMAH for such purpose as the fabrication of MEMS devices, wafer level packaging and fabrication of fluidic devices. Various embodiments are disclosed.10-30-2008
20100330744ULTRATHIN SEMICONDUCTOR CIRCUIT HAVING CONTACT BUMPS AND CORRESPONDING PRODUCTION METHOD - The invention relates to an ultrathin semiconductor circuit having contact bumps and to a corresponding production method. The semiconductor circuit includes a bump supporting layer having a supporting layer thickness and having a supporting layer opening for uncovering a contact layer element being formed on the surface of a semiconductor circuit. An electrode layer is situated on the surface of the contact layer element within the opening of the bump supporting layer, on which electrode layer is formed a bump metallization for realizing the contact bump. On account of the bump supporting layer, a thickness of the semiconductor circuit can be thinned to well below 300 micrometers, with the wafer reliably being prevented from breaking. Furthermore, the moisture barrier properties of the semiconductor circuit are thereby improved.12-30-2010
20110318878MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGES - Conductive core balls are joined to joint pads formed on an upper substrate. Core balls are joined to joint pads formed on an extending part of an upper-substrate substrate material. The joint pads formed on the extending part of the upper-substrate substrate material are joined to the joint pads formed on an extending part of a lower-substrate substrate material via the core balls. The joint pads formed in an area corresponding to the upper substrate of the upper-substrate substrate material are connected to the joint pads formed in an area corresponding to a lower substrate of the lower-substrate substrate material via the core balls and the conductive core balls. The upper-substrate substrate material is fixed to the lower-substrate substrate material by a mold resin supplied therebetween. The extending parts of the upper-substrate substrate material and the lower-substrate substrate material are removed, and the semiconductor packages are individualized.12-29-2011
20110318877DICING METHODS - The present invention provides a dicing method that achieves excellent dicing properties at low costs by removing a metal film through a metal processing operation with a diamond tool and then performing pulse laser beam irradiation. The dicing method is a method of dicing a substrate to be processed, devices being formed in the substrate to be processed, a metal film being formed on one surface of the substrate to be processed. The dicing method includes: placing the substrate to be processed onto a first stage; forming a groove portion by removing the metal film through a metal processing operation with a diamond tool; placing the substrate to be processed onto a second stage; generating a clock signal; emitting a pulse laser beam synchronized with the clock signal to the groove portion of the substrate to be processed; moving the substrate to be processed and the pulse laser beam relative to each other; switching the pulse laser beam between irradiation and non-irradiation of the substrate to be processed on a light pulse basis by controlling passing and blocking of the pulse laser beam with a pulse picker in synchronization with the clock signal; and forming cracks in the substrate to be processed, the cracks reaching the substrate surface.12-29-2011
20110318876SEMICONDUCTOR PACKAGE, ELECTRICAL AND ELECTRONIC APPARATUS INCLUDING THE SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring.12-29-2011
20120045870Method of Manufacturing Leadless Integrated Circuit Packages Having Electrically Routed Contacts - A method of manufacturing a leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The IC chip, the electrical contacts, and a portion of the metal leadframe are covered with an encapsulation compound, with portions of the electrical contacts exposed on a bottom surface of the encapsulation compound. The electrical contacts of the IC package having metal traces connecting bonding areas on a top surface thereof and contact areas on a bottom surface thereof, wherein at least some of the bonding areas are laterally disposed from the contact areas connected thereto.02-23-2012
20100029044CONDUCTIVE BUMP, METHOD FOR MANUFACTURING THE CONDUCTIVE BUMP, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - Conductive bump (02-04-2010
20120156830METHOD OF FORMING A RING-SHAPED METAL STRUCTURE - A method includes providing a first semiconductor chip comprising a ring-shaped metal structure extending along a contour of a first main surface of the semiconductor chip. The method includes encapsulating the first semiconductor chip with an encapsulation body thereby defining a second main surface and depositing a metal layer over the first semiconductor chip and the encapsulation body. A plurality of external contact pads are placed over the second main surface of the encapsulation body, the metal layer electrically coupling at least one external contact pad of the plurality of external contact pads to the ring-shaped metal structure. A seal ring is placed between the ring-shaped metal structure and the contour of the first main surface of the first semiconductor chip.06-21-2012
20120208320On-Chip RF Shields with Front Side Redistribution Lines - A system on chip comprising a RF shield is disclosed. In one embodiment, the system on chip includes a RF component disposed on a chip, first redistribution lines disposed above the system on chip, the first redistribution lines coupled to I/O connection nodes. The system on chip further includes second redistribution lines disposed above the RF component, the second redistribution lines coupled to ground potential nodes. The second redistribution lines include a first set of parallel metal lines coupled together by a second set of parallel metal lines.08-16-2012
20110104853METHOD OF FORMING SEMICONDUCTOR PACKAGE - A method of forming a semiconductor package includes providing a transfer film and placing electronic components on the transfer film with active sides of the electronic components facing the transfer film. The electronic components include a first assembled package and one or more of a second assembled package and a passive component. A molding operation is performed to encapsulate the electronic components and one side of the transfer film. The transfer film is then removed, which exposes the active sides of the electronic components. An electrical distribution layer is formed over the active sides of the electronic components and electrically connects the electronic components. Conductive bumps are then formed on the electrical distribution layer.05-05-2011
20110104854METHOD AND LEADFRAME FOR PACKAGING INTEGRATED CIRCUITS - A leadframe suitable for use in the packaging of at least two integrated circuit dice into a single integrated circuit package is described. The leadframe includes a plurality of leads. Each of a first set of the plurality of leads has a first side and a second side substantially opposite the first side of the lead. Additionally, each of the first and second sides of the first set of leads each include at least two solder pads. Each solder pad on a lead of the first set of leads is isolated from other solder pads on the same side of the lead with at least one recessed region adjacent the solder pad. In various embodiments, I/O pads from at least two dice are physically and electrically connected to the opposing sides of the leads.05-05-2011
20110183468Semiconductor device - There is provided a semiconductor device whose cost is low and whose case is restrained from breaking. In the semiconductor device having a semiconductor sensor chip, a signal processing circuit for processing signals output from the semiconductor sensor chip and a hollow case for mounting the semiconductor sensor chip and the signal processing circuit therein, the case is constructed by bonding a concave bottom member whose one end is opened with a plate-like lid member that covers the opening of the bottom member. Then, the bottom and lid members are both made of a semiconductor material and are bonded by means of anode bonding or metal bonding for example.07-28-2011
20110183469Integrated semiconductor substrate structure using incompatible processes - A plurality of FPGA dice is disposed upon a semiconductor substrate. In order both to connect thousands of signal interconnect lines between the plurality of FPGA dice and to supply the immense power required, it is desired that the substrate construction include two different portions, each manufactured using incompatible processes. The first portion is a signal interconnect structure containing a thin conductor layers portion characterized as having a plurality of thin, fine-pitch conductors. The second portion is a power connection structure that includes thick conductors and vertical through-holes. The through-holes contain conductive material and supply power to the FPGA dice from power bus bars located at the other side of the semiconductor substrate. The portions are joined at the wafer level by polishing the wafer surfaces within a few atoms of flatness and subsequent cleaning. The portions are then fusion bonded together or combined using an adhesive material.07-28-2011
20120129297METHOD OF MANUFACTURING WAFER LEVEL PACKAGE - A method of manufacturing a wafer level package including: separating chips by dicing a wafer; forming a removable resin layer in a space between the separated chips and at upper parts thereof; separating the chips by dicing the removable resin layer; mounting the chips separated in a state of being surrounded by the removable resin layer, on a carrier plate; forming a molding material on the carrier plate to cover the removable resin layer; separating the carrier plate from the chips; forming a dielectric layer having redistribution lines connected to the chips, on the chips exposed by separating the carrier plate; and forming a solder resist layer on the dielectric layer to expose portions of the redistribution lines.05-24-2012
20120164790DOUBLE-FACED ELECTRODE PACKAGE, AND ITS MANUFACTURING METHOD - A dual-face package has an LSI chip sealed with a mold resin, and electrodes for external connections on both of the front face and the back face. The LSI chip is bonded onto the die pad of a leadframe whose outer lead portions are exposed as back-face electrodes at at least the back face. The LSI chip and a plurality of inner lead portions of the leadframe are connected by wiring. At least some of the plurality of inner lead portions have front-face electrodes integrally formed by working a portion of the leadframe. Head faces of the front-face electrodes, or bump electrodes connected to the respective head faces of the front-face electrodes serve as electrodes for external connections to another substrate, element, or the like.06-28-2012
20120315728Saw Type Package without Exposed Pad - In one embodiment, a method for manufacturing a saw type pad is provided. The method includes performing a first molding process to form a first molded layer beneath a pad of a lead frame. A semiconductor device is placed on the pad. A second molding process is performed to form a second molded layer. The first molded layer and the second molded layer form an encapsulation to enclose the semiconductor device and the pad. The lead frame is singulated to form an individualized semiconductor package. The pad is not exposed from a bottom surface of the semiconductor package.12-13-2012
20120214279METHOD OF MANUFACTURING SEMICONDUCTOR CHIP STACK - A method of manufacturing a semiconductor chip stack includes providing a circuit layout of a function device, the circuit layout further comprising a first device layout and a second device layout, and an integration density of the first device layout is larger than an integration density of the second device layout; defining a plurality of first chip regions on a first wafer and forming the first device layout in each first chip region; defining a plurality of second chip regions on a second wafer and forming the second device layout in each second chip region; forming a plurality of first TSVs in each first wafer for electrically connecting the first device layout and the second device layout; and respectively cutting the first wafer and the second wafer to form a plurality of first chips and a plurality of second chips.08-23-2012
20120214278METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprises the steps of (a) applying a resin member onto a front surface of a semiconductor wafer having an uneven structure on the front surface thereof, and (b) flattening a surface of the resin member by heating the resin member, and in the method, the resin member is formed also on a side surface of the semiconductor wafer. The method further comprises the steps of (c) performing a thinning process for the semiconductor wafer on a back surface thereof after the step (b), and (d) removing the resin member from the semiconductor wafer after the step (c). By the method, it is possible to uniformize the thickness of a semiconductor wafer which is thinned and reduce the number of foreign matters remaining on a surface of the semiconductor wafer.08-23-2012
20100173455SEMICONDUCTOR DEVICE HAVING SEALING FILM AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a plurality of wiring lines which are provided on an upper side of a semiconductor substrate and which have connection pad portions, and columnar electrodes are provided on the connection pad portions of the wiring lines. A first sealing film is provided around the columnar electrodes on the upper side of the semiconductor substrate and on the wiring lines. A second sealing film is provided on the first sealing film. The first sealing film is made of a resin in which fillers are not mixed, and the second sealing film is made of a material in which fillers are mixed in a resin.07-08-2010
20100279469Low-Voiding Die Attach Film, Semiconductor Package, and Processes for Making and Using Same - This invention is a low-voiding adhesive film prepared from a composition. The composition comprises a toughening polymer, a curable resin, a curing agent for the curable resin, a void reduction compound, and a curing agent for the void reduction compound. The void reduction compound has at least two Si—O moieties contiguous with each other and at least one reactive functionality. Additional embodiments of this invention are described, including a process for producing the low-voiding die attach film, a method for reducing voids in a semiconductor package using the film of this invention, and a semiconductor package assembled with the film of this invention.11-04-2010
20090098682Method for Singulating a Group of Semiconductor Packages that Contain a Plastic Molded Body - A method for singulating a group of semiconductor packages containing a plastic molded body. The singulation of the semiconductor packages is effected along a predetermined separation area, wherein, in the predetermined separation area, a metallic layer extending over at least a partial section of the predetermined separation area has to be cut through in addition to a plastic layer formed of a material of the molded body. The method includes the steps of: making a groove into the predetermined separation area of the semiconductor packages by laser engraving, wherein at least a part of the metallic layer extending in the predetermined singulation area is removed, and subsequent separation of the semiconductor packages by mechanical sawing cut along the predetermined separation area.04-16-2009
20100273296Thermally Enhanced Wafer Level Package - A method of forming a package structure includes providing a plurality of dies; attaching the plurality of dies onto a heat-dissipating plate; and sawing the heat-dissipating plate into a plurality of packages, each including one of the plurality of dies and a piece of the heat-dissipating plate.10-28-2010
20100273295Surface-Decorated Polymeric Amphiphile Porogens for the Templation of Nanoporous Materials - A nanoparticle which includes a multi-armed core and surface decoration which is attached to the core is prepared. A multi-armed core is provided by any of a number of possible routes, exemplary preferred routes being living anionic polymerization that is initiated by a reactive, functionalized anionic initiator and ∈-caprolactone polymerization of a bis-MPA dendrimer. The multi-armed core is preferably functionalized on some or all arms. A coupling reaction is then employed to bond surface decoration to one or more arms of the multi-armed core. The surface decoration is a small molecule or oligomer with a degree of polymerization less than 50, a preferred decoration being a PEG oligomer with degree of polymerization between 2 and 24. The nanoparticles (particle size ≦10 nm) are employed as sacrificial templating porogens to form porous dielectrics. The porogens are mixed with matrix precursors (e.g., methyl silsesquioxane resin), the matrix vitrifies, and the porogens are removed via burnout. Greater porosity reduces the dielectric constant k of the resulting dielectrics. The porous dielectrics are incorporated into integrated circuits as lower k alternatives to silicon dioxide.10-28-2010
20100009500Aluminum Leadframes for Semiconductor QFN/SON Devices - A post-mold plated semiconductor device has an aluminum leadframe (01-14-2010
20120220080Method for Fabricating Flip-Attached and Underfilled Semiconductor Devices - A semiconductor device, which comprises a workpiece with an outline and a plurality of contact pads and further an external part with a plurality of terminal pads. This part is spaced from the workpiece and the terminal pads are aligned with the workpiece contact pads, respectively. A reflow element interconnects each of the contact pads with its respective terminal pad. Thermoplastic material fills the space between the workpiece and the part; this material adheres to the workpiece, the part and the reflow elements. Further, the material has an outline substantially in line with the outline of the workpiece, and fills the space substantially without voids. Due to the thermoplastic character of the filling material, the finished device can be reworked, when the temperature range for reflowing the reflow elements is reached.08-30-2012
20090061564METHOD OF PACKAGING AN INTEGRATED CIRCUIT DIE - A structure (03-05-2009
20120258572ADHESIVE SHEET AND PRODUCTION METHOD FOR ELECTRONIC COMPONENT - Disclosed is an adhesive sheet that has a base film and an ultraviolet curable adhesive layered upon the base film. The ultraviolet curable adhesive includes 100 parts by mass of an acrylic ester copolymer with a weight-average molecular weight of at least one million, 20 to 200 parts by mass of a photopolymerizable acrylate having at least three carbon-carbon double bonds, and 0.1 to 10 parts by mass of an isocyanate curing agent. From among the monomers used during the copolymerization of the acrylic ester copolymer, a monomer having one or both of a hydroxyl group and a carboxyl group is included at no more than 0.1 mass %.10-11-2012
20110124157METHOD FOR ENCAPSULATING ELECTRONIC COMPONENTS ON A WAFER - A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.05-26-2011
20120264258METHOD OF ASSEMBLING SEMICONDUCTOR DEVICE INCLUDING INSULATING SUBSTRATE AND HEAT SINK - Semiconductor dies are mounted on a heat sink array frame structure. The heat sink array frame structure and the semiconductor dies are assembled together with an insulating substrate that has a corresponding array of apertures on an adhesive tape. The semiconductor dies are connected electrically with electrical contacts on the insulating substrate. The semiconductor dies, heat sinks and electrical connections to the contacts are encapsulated with a mold compound and then the encapsulated array is de-taped and singulated.10-18-2012
20120264257MOLD ARRAY PROCESS METHOD TO PREVENT EXPOSURE OF SUBSTRATE PERIPHERIES - Disclosed is a mold array process (MAP) method to prevent exposure of peripheries of substrate units where the major characteristic is to implement two kinds of encapsulating materials in the MAP method in mass production. A first encapsulating material for encapsulating chips is formed on a substrate strip by molding to continuously encapsulate the substrate units and the scribe lines between adjacent substrate units. Prior to forming a second encapsulating material, a plurality of cut grooves are formed along the scribing lines by pre-cutting processes to penetrate through the substrate strip but without penetrating through the first encapsulating material and have such a width that a plurality of peripheries of the substrate units are exposed outside the scribing lines. Then, the second encapsulating material is filled into the cut grooves. Accordingly, the peripheries of the substrate units are still encapsulated with the remains of the second encapsulating material after singulation processes where the substrate units are singulated into individual semiconductor packages to prevent exposure of the peripheries of the substrate units.10-18-2012
20110003433MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A disclosed device includes a manufacturing method of semiconductor device including preparing a semiconductor substrate including semiconductor chip forming regions, scribing regions surrounding these regions, and cutting regions formed in the scribing regions and narrower than the scribing regions, forming check patterns and semiconductor chips, forming a resist film, forming through grooves narrower than the scribing regions and wider than the check patterns and the cutting regions, removing the check patterns with a wet blast process using the resist film and collectively forming grooves at portions of a protection film and the semiconductor substrate facing the through grooves, removing the resist film, forming internal connection terminals on the contacting faces, forming an insulating resin layer, forming a wiring forming face by removing until connecting faces are exposed, forming wiring patterns, and cutting the semiconductor substrate, the insulating resin layer, and a solder resist layer to separate into individual semiconductor devices.01-06-2011
20100203678SEMICONDUCTOR SUBSTRATE CUTTING METHOD - A semiconductor substrate cutting method which can efficiently cut a semiconductor substrate having a front face formed with a functional device together with a die bonding resin layer is provided.08-12-2010
20110045637Ultra Thin Bumped Wafer With Under-Film - A method of making a semiconductor device includes forming an under-film layer over bumps disposed on a surface of a wafer to completely cover the bumps, and forming an adhesive layer over the under-film layer. The method further includes attaching a support layer over the adhesive layer, removing a portion of a back surface of the wafer, and removing the support layer to expose the adhesive layer that remains disposed over the under-film layer. The method further includes removing the adhesive layer to expose the under-film layer while the bumps remain completely covered by the under-film layer, and singulating the wafer to form a semiconductor die. The method further includes pressing the bumps into contact with a substrate while the under-film layer provides an underfill between the semiconductor die and the substrate.02-24-2011
20100233855METHOD FOR FABRICATING CHIP SCALE PACKAGE STRUCTURE WITH METAL PADS EXPOSED FROM AN ENCAPSULANT - A chip scale package structure and a method for fabricating the same are disclosed. The method includes forming metal pads on a predetermined part of a carrier; mounting chips on the carrier, each of the chips having a plurality of conductive bumps soldered to the metal pads; forming an encapsulant on the carrier to encapsulate the chips and the conductive bumps; removing the carrier to expose the metal pads and even the metal pads with a surface of the encapsulant; forming on the encapsulant a plurality of first conductive traces electrically connected to the metal pads; applying a solder mask on the first conductive traces, and forming a plurality of openings on the solder mask to expose a predetermined part of the first conductive traces; forming a plurality of conductive elements on the predetermined part; and cutting the encapsulant to form a plurality of chip scale package structures.09-16-2010
20100233854METALLIC SOLDERABILITY PRESERVATION COATING ON METAL PART OF SEMICONDUCTOR PACKAGE TO PREVENT OXIDE - Embodiments of the present invention are directed to metallic solderability preservation coating on connectors of semiconductor package to prevent oxide. Singulated semiconductor packages can have contaminants, such as oxides, on exposed metal areas of the connectors. Oxidation typically occurs on the exposed metal areas when the semiconductor packages are not stored in appropriate environments. Copper oxides prevent the connectors from soldering well. An anti-tarnish solution of the present invention is used to coat the connectors during sawing, after sawing, or both of a semiconductor array to preserve metallic solderability. The anti-tarnish solution is a metallic solution, which advantageously allows the semiconductor packages to not need be assembled immediately after fabrication.09-16-2010
20120322208ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - A method for manufacturing an electronic device includes forming a resin film over a wafer, the wafer including a plurality of elements formed therein, each of the elements including a functional unit, patterning the resin film to form a plurality of frame members, each of the frame members being provided on each of the elements and surrounding the functional unit, dividing the wafer into the elements, and providing an encapsulation.12-20-2012
20120322207SEMICONDUCTOR PACKAGE WITH ADHESIVE MATERIAL PRE-PRINTED ON THE LEAD FRAME AND CHIP, AND ITS MANUFACTURING METHOD - This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size, shape and thickness of the adhesive material are applied according to different application requirements according to size and shapes of the contact zone of the semiconductor chip and the metal connector. Particularly, the adhesive zones are formed by pre-printing the adhesive material thus significantly enhance the quality and performance of semiconductor products, and improves the productivity.12-20-2012
20120088332Semiconductor Package and Method of Manufacturing the Same - A method of forming a semiconductor package includes attaching a semiconductor substrate on a support substrate, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region that separates respective ones of the semiconductor chips. A first cutting groove is formed that has a first kerf width between first and second ones of the plurality of first semiconductor chips. A plurality of second semiconductor chips is attached to the plurality of first semiconductor chips. A molding layer is formed so as to fill the first cutting groove and a second cutting groove having a second kerf width that is less than the first kerf width is formed in the molding layer so as to form individual molding layers covering one of the plurality of first semiconductor chips and one of the plurality of second semiconductor chips.04-12-2012
20110294264HEAT SPREADER AS MECHANICAL REINFORCEMENT FOR ULTRA-THIN DIE - A technique to fabricate a package. A thin wafer supported by a wafer support substrate (WSS) is formed. The WSS-supported thin wafer layer is diced into a plurality of WSS-supported thin dice. A WSS-supported thin die is bonded to a first heat spreader (HS) to form a HS-reinforced thin die.12-01-2011
20120329213FLEXIBLE ELECTRONIC DEVICE AND METHOD FOR THE FABRICATION OF SAME - A semiconductor device may have a thickness, such that the semiconductor devices are not flexible, and may be bonded and electrically coupled on a flexible substrate. After this bonding, the semiconductor device may be thinned so as to be rendered flexible.12-27-2012
20120288999METHOD FOR MANUFACTURING SEMICONDUCTOR MODULES - A method for fabricating a semiconductor module includes: bonding a semiconductor substrate onto a first insulating resin layer; dicing the semiconductor substrate into a plurality of individual semiconductor devices; widening the spacings between the adjacent semiconductor devices by expanding the first insulating resin layer in a biaxially stretched manner; fixing the plurality of semiconductor devices to a flat sheet, with a second insulating resin layer held between the plurality of semiconductor devices and the flat sheet, and removing the first insulating resin layer; stacking the plurality of semiconductor devices, a third insulating resin layer, and a metallic plate, in this order, so as to form a laminated body having electrodes by which to electrically connect the device electrodes to the metallic plate; forming a wiring layer by selectively removing the metallic plate and forming a plurality of semiconductor modules; and separating the semiconductor modules into individual units.11-15-2012
20120289000DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE, AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - The present invention relates to a dicing tape-integrated film for semiconductor back surface including: a dicing tape including a base material and a pressure-sensitive adhesive layer laminated in this order, and a film for semiconductor back surface provided on the pressure-sensitive adhesive layer of the dicing tape, where the pressure-sensitive adhesive layer has a thickness of from 20 μm to 40 μm.11-15-2012
20120288998WAFER LEVEL IC ASSEMBLY METHOD - A wafer level integrated circuit assembly method is conducted as follows. First, a mother device wafer with plural first posts is provided. The first posts are used for electrical connection and are made of copper according to an embodiment. Solder is sequentially formed on the first posts. The solder is preferably pre-formed on a wafer, and the locations of the solder correspond to the first posts of the mother device wafer. Consequently, the solder can be formed on or adhered to the first posts by placing the wafer having pre-formed solder onto the first posts. Plural dies having plural second posts corresponding to the first posts are placed onto the mother device wafer. Then, the solder is reflowed to bond the first and second posts, and the mother device wafer is diced.11-15-2012
20120289001Method for Making Solder-top Enhanced Semiconductor Device of Low Parasitic Packaging Impedance - A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.11-15-2012
20090197373Semiconductor Device Singulation Method - The objective of the invention is to provide a semiconductor device manufacturing method with which the generation of burrs can be suppressed while increasing the singulation speed of the package. In a manufacturing method of a QFN package of the present invention, a molding prepared by sealing a lead frame with plural semiconductor chips carried on it en bloc with a resin; the operation comprises the following processing steps: a first singulation processing step S08-06-2009
20120149152METHOD TO PREVENT METAL PAD DAMAGE IN WAFER LEVEL PACKAGE - The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a bonding pad on a first substrate; forming wiring pads on the first substrate; forming a protection material layer on the first substrate, on sidewalls and top surfaces of the wiring pads, and on sidewalls of the bonding pad, such that a top surface of the bonding pad is at least partially exposed; bonding the first substrate to a second substrate through the bonding pad; opening the second substrate to expose the wiring pads; and removing the protection material layer.06-14-2012
20110159642TAPE FOR HOLDING CHIP, METHOD OF HOLDING CHIP-SHAPED WORKPIECE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING TAPE FOR HOLDING CHIP, AND METHOD OF MANUFACTURING TAPE FOR HOLDING CHIP - The present invention aims to provide a tape for holding a chip that makes pasting and peeling of a chip-shaped workpiece easy. It is a tape for holding a chip having a configuration in which a pressure-sensitive adhesive layer is formed on a base material, wherein the pressure-sensitive adhesive layer has a chip-shaped workpiece pasting region onto which a chip-shaped workpiece is pasted and a frame pasting region onto which a mount frame is pasted, and that is used by pasting the mount frame to the frame pasting region, wherein the 180-degree peeling adhesive power of the pressure-sensitive adhesive layer to a silicon mirror wafer at the frame pasting region is 5 times or more the 180-degree peeling adhesive power of the pressure-sensitive adhesive layer to a silicon mirror wafer at the chip-shaped workpiece pasting region.06-30-2011
20080233678METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device having a substrate on which conductor wiring is disposed, electrodes provided to the conductor wiring, a semiconductor element connected to the electrodes, and a sealing member that covers the semiconductor element, comprises; mounting a plurality of semiconductor elements on the substrate in the X-axial direction and the Y-axial direction, forming marks in the X-axial direction, supplying the sealing material onto the substrate to continuously-covering the plurality of semiconductor elements arranged in the X-axial direction along the marks, dicing the sealing member and the substrate in the Y-axial direction to form cut planes of the sealing member and the substrate in substantially one plane and being a pair of cut planes opposite one another.09-25-2008
20080227240Method of Making Reliable Wafer Level Chip Scale Package Semiconductor Devices - The present invention relates to a method of making a robust wafer level chip scale package and, in particular, a method that prevents cracking of the passivation layer during solder flow and subsequent multiple thermal reflow steps. In one embodiment, a passivation layer that is formed using a highly compressive insulating material is used. In another aspect, another layer is applied over the passivation layer to assist with preventing cracking of the passivation layer.09-18-2008
20130178017METHOD FOR MANUFACTURING SEMICONDUCTOR CHIPS FROM A SEMICONDUCTOR WAFER - A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame.07-11-2013
20120202320WAFER-LEVEL CHIP SCALE PACKAGING OF METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT-TRANSISTORS (MOSFET'S) - Wafer-level chip scale packaging of metal-oxide-semiconductor-field-effect-transistors (MOSFET's) provides protection and good solder-ability to a die backside by fabricating a plurality of power MOSFET devices with die contacts on a wafer that can later be cut into individual die. A plurality of contact pads is included on the wafer to provide connectivity to the die contacts. A layer which includes aluminum (Al) or zinc (Zn) is electrolessly plated on a backside of the wafer to form a metalized backside. The plating tank used in this step is not contaminated. The contact pads and metalized backside are plated with a layer of electroless nickel (Ni) followed by a layer of gold (Au). Solder balls are formed on each of the contact pads after their plating with nickel (Ni) and gold (Au). The wafer is diced to yield MOSFET wafer level chip-scale packages which provide protection and good solder-ability to the die backside.08-09-2012
20130115736METHOD FOR SEPARATING A PLURALITY OF DIES AND A PROCESSING DEVICE FOR SEPARATING A PLURALITY OF DIES - A method for separating a plurality of dies is provided. The method may include: selectively removing one or more portions from a carrier including a plurality of dies, for separating the plurality of dies along the selectively removed one or more portions, wherein the one or more portions are located between the dies; and subsequently forming over a back side of the dies, at least one metallization layer for packaging the dies05-09-2013
20130095613FABRICATION METHOD OF SEMICONDUCTOR DEVICES AND FABRICATION SYSTEM OF SEMICONDUCTOR DEVICES - In aspects of the invention, a holding stage of a pick up system can include a first stage on which a semiconductor chip is mounted with an adhesive sheet put in between, a second stage supporting the first stage, and an evacuation pipe. The first stage can be provided with a plurality of grooves, projections each being formed with side walls of adjacent grooves, and air holes connected to the grooves. The semiconductor chip can be mounted on the first stage so that the whole end portion of the semiconductor chip does not position on one groove. Then, a closed space surrounded by the adhesive sheet and the first and second stages and can be evacuated to make the semiconductor chip held on the projections. Thereafter, the semiconductor chip can be picked up by a collet.04-18-2013
20130095612WAFER LEVEL PACKAGING METHOD OF ENCAPSULATING THE BOTTOM AND SIDE OF A SEMICONDUCTOR CHIP - A chip-scale packaging method, with bottom and side of a semiconductor chip encapsulated, includes the following steps: attaching backside of a thinned semiconductor wafer to a dicing tape; separating individual chips by cutting from front side of the wafer at scribe line but not cut through the dicing tape; flipping and attaching the wafer onto a top surface of a double-sided tape, then removing the dicing tape; attaching bottom surface of the double-sided tape on a supporting plate; filling the space between adjacent chips and covering the whole wafer backside with a molding material; flipping the whole structure and remove the supporting plate; placing solder balls at corresponding positions on electrodes of each chip and performing backflow treatment; finally separating individual chip packages by cutting through molding material at the space between adjacent chip packages with molding material encapsulating the bottom and side of each individual semiconductor chip.04-18-2013
20130095614WAFER LEVEL PACKAGING OF SEMICONDUCTOR CHIPS - A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a larger pads near the center of package and smaller UBM pads near the periphery. The method includes attaching a stiffener to an inactive surface of the wafer; forming under bump metallization pads; and forming solder bumps extending from the UBM pads.04-18-2013
20080199985LEADFRAME ENHANCEMENT AND METHOD OF PRODUCING A MULTI-ROW SEMICONDUCTOR PACKAGE - A semiconductor package includes a plurality of first leads, each with a top outer portion removed from the lead and an outer end, and a plurality of second leads, each with a bottom outer portion removed from the lead and an outer end. The first and second leads alternate with each other along an edge of the package. Also, the outer ends of the first leads form a first row along the edge of the package and the outer ends of the second leads form a second row along the edge of the package. In one embodiment, the first and second rows are parallel to each other and an encapsulant covers at least a portion of the first and second leads.08-21-2008
20130137218UNDER-FILL MATERIAL AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - The present invention provides an under-fill material with which a semiconductor device having a high connection reliability can be provided while securing a usable material by reducing a difference in thermal-responsive behavior between a semiconductor element and an adherend, and a method for producing a semiconductor device using the under-fill material. In the under-fill material of the present invention, a storage elastic modulus E′ [MPa] and a thermal expansion coefficient α [ppm/K] after carrying out a heat-curing treatment at 175° C. for an hour satisfy the following formula (1) at 25° C.:05-30-2013
20120258573FABRICATION METHOD OF SUBSTRATE - A fabricating method of a substrate board is provided. The substrate board includes a substrate having rigid areas and flexible areas, and at least an electronic component disposed on the substrate, wherein each of the rigid areas is thicker than the flexible areas. A patterned high-extensive material may be additionally disposed on the substrate to improve reliability thereof. The rigid areas and the flexible areas may be formed by molds or cutters. By using an above structure, the electronic component is less affected when the substrate is under stress, so that good characteristics are maintained.10-11-2012
20100311208METHOD AND APPARATUS FOR NO LEAD SEMICONDUCTOR PACKAGE - A leadframe for use in fabricating a no lead semiconductor package contains connecting bars between individual electrical contact pads. For embodiments having a die pad, the leadframe further includes connecting bars between the contact pads and the die pad. The lower surfaces of the connecting bars are coplanar with the lower surfaces of the contact pads and/or the die pad, and the upper surfaces of the connecting bars are recessed with respect to the upper surfaces of the contact pads and/or the die pad. The semiconductor package is fabricated by encapsulating the die and the leadframe in a molding compound and then removing the connecting bars. The leadframe is typically formed by half etching a metal sheet to form the connecting bars. The connecting bars are removed from the encapsulated package by a selected cutting, sawing, or etching means, based on a predetermined pattern.12-09-2010
20100317155MULTIFUNCTIONAL DIE ATTACHMENT FILM AND SEMICONDUCTOR PACKAGING USING THE SAME - A multifunctional die attachment film used in a semiconductor packaging process includes a first die attachment film attached to a surface of a wafer having fine circuit patterns and solder bump patterns and having a first adhesive strength; and a second die attachment film attached on the first die attachment film and having a second adhesive strength with a wafer, a die chip, PCB and a flexible board, and the multifunctional die attachment film serves as a backgrinding tape in a backgrinding process, and after the backgrinding process is completed, the multifunctional die attachment film is not removed, but is used to attach a die chip to a connection member. And, the present invention utilizes the die attachment film as a backgrinding tape in the backgrinding process and concurrently a wafer protection means in a wafer dicing process, thereby preventing sawing burr, scratches or cracks.12-16-2010
20130157414STACKED-DIE PACKAGE AND METHOD THEREFOR - Consistent with an example embodiment, there is a semiconductor device comprised of a combination of device die. The semiconductor device comprises a package substrate having groups of pad landings. A first device die is anchored to the package substrate, the first device die having been wire-bonded to a first group of pad landings. At least one subsequent device die is anchored to the first device die. The at least one subsequent device die has an underside profile with recesses defined therein, the recesses of a size are defined to accommodate wires bonded to the first device die; the at least one subsequent device is wire bonded to a second group of pad landings.06-20-2013
20130157415METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - There is provided a method for producing a semiconductor device, capable of suppressing generation of voids at an interface between a semiconductor element and an under-fill sheet to produce a semiconductor device with high reliability. The method includes providing a sealing sheet having a support and an under-fill material laminated on the support; thermally pressure-bonding a circuit surface of a semiconductor wafer, on which a connection member is formed, and the under-fill material of the sealing sheet under conditions of a reduced-pressure atmosphere of 10000 Pa or less, a bonding pressure of 0.2 MPa or more and a heat pressure-bonding temperature of 40° C. or higher; dicing the semiconductor wafer to form a semiconductor element with the under-fill material; and electrically connecting the semiconductor element and the adherend through the connection member while filling a space between the adherend and the semiconductor element using the under-fill material.06-20-2013
20130189814Method for Fabricating Array-Molded Package-on-Package - a An improved semiconductor device package is manufactured by attaching semiconductor chips (07-25-2013
20120015483Semiconductor Device Package and Method of Assembly Thereof - A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material.01-19-2012
20120028417SEMICONDUCTOR COMPONENT WITH CELL STRUCTURE AND METHOD FOR PRODUCING THE SAME - A semiconductor component comprises a semiconductor body comprising a first component electrode arranged on one of the surfaces of the semiconductor body, a second component electrode arranged on one of the surfaces of the semiconductor body, and a component control electrode arranged on one of the surfaces of the semiconductor body. In this case, active semiconductor element cells are arranged in a first active cell array of the semiconductor body, the semiconductor element cells comprising a first cell electrode, a second cell electrode and a cell control electrode and also a drift path between the cell electrodes. At least the component control electrode is arranged on a partial region of the semiconductor body and a second active cell array is additionally situated in the partial region of the semiconductor body below the component control electrode.02-02-2012
20120028416FILM FOR FLIP CHIP TYPE SEMICONDUCTOR BACK SURFACE AND ITS USE - The present invention relates to a film for flip chip type semiconductor back surface, which is to be disposed on a back surface of a semiconductor element flip chip-connected onto an adherend, the film for flip chip type semiconductor back surface including an adhesive layer and a protective layer laminated on the adhesive layer, in which the protective layer is constituted of a heat-resistant resin having a glass transition temperature of 200° C. or more or a metal.02-02-2012
20120028415DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE, AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - The present invention relates to a dicing tape-integrated film for semiconductor back surface including: a dicing tape including a base material and a pressure-sensitive adhesive layer laminated in this order, and a film for semiconductor back surface provided on the pressure-sensitive adhesive layer of the dicing tape, where the pressure-sensitive adhesive layer has a thickness of from 20 μm to 40 μm.02-02-2012
20120094439Method for Positioning Chips During the Production of a Reconstituted Wafer - A method for fabricating a re-built wafer which comprises chips having connection pads, comprising: fabricating a first wafer of chips, production on this wafer of a stack of at least one layer of redistribution of the pads of the chips on conductive tracks designed for the interconnection of the chips, this stack being designated the main RDL layer, cutting this wafer in order to obtain individual chips each furnished with their RDL layer, transferring the individual chips with their RDL layer to a sufficiently rigid support to remain flat during the following steps, which support is furnished with an adhesive layer, with the RDL layer on the adhesive layer, depositing a resin in order to encapsulate the chips, polymerizing the resin, removing the rigid support, depositing a single redistribution layer called a mini RDL in order to connect the conductive tracks of the main RDL layer up to interconnection contacts, through apertures made in the adhesive layer, the wafer comprising the polymerized resin, the chips with their RDL layer and the mini RDL being the re-built wafer.04-19-2012

Patent applications in class Substrate dicing

Patent applications in all subclasses Substrate dicing