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Assembly of plural semiconductive substrates each possessing electrical device

Subclass of:

438 - Semiconductor device manufacturing: process

438106000 - PACKAGING (E.G., WITH MOUNTING, ENCAPSULATING, ETC.) OR TREATMENT OF PACKAGED SEMICONDUCTOR

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
438109000 Stacked array (e.g., rectifier, etc.) 159
438108000 Flip-chip-type assembly 108
Entries
DocumentTitleDate
20130040424Fixing Semiconductor Die in Dry and Pressure Supported Assembly Processes - Semiconductor die are assembled on a substrate by providing the semiconductor die, substrate, and an elastically deformable foil fixture preformed with one or more sunken regions having sidewalls and a bottom, and placing the semiconductor die in the one or more sunken regions so that the foil fixture is populated with a first side of the semiconductor die facing the bottom of the one or more sunken regions and a second opposing side of the semiconductor die facing away from the bottom of the one or more sunken regions. The substrate is placed adjacent the second side of the semiconductor die with a joining material interposed between the substrate and the semiconductor die. The substrate and the populated foil fixture are pressed together at an elevated temperature and pressure via first and second pressing tool members so that the substrate is attached to the second side of the semiconductor die via the joining material.02-14-2013
20090311827Adhesive for electronic components, method and for manufacturing semiconductor chip laminate, and semiconductor device - It is an object of the present invention to provide: an adhesive for electronic parts that makes it possible to accurately maintain a distance between electronic parts upon joining electronic parts such as two or more semiconductor chips and also to obtain reliable electronic parts such as a semiconductor device; a method for producing a semiconductor chip laminated body using the adhesive for electronic parts; and a semiconductor device using the adhesive for electronic parts.12-17-2009
20100062565Substrate Bonding with Bonding Material Having Rare Earth Metal - A microchip has a bonding material that bonds a first substrate to a second substrate. The bonding material has, among other things, a rare earth metal and other material.03-11-2010
20100055838SENSITIVITY CAPACITIVE SENSOR - A method of creating an improved sensitivity capacitive fingerprint sensor involves forming vias from a first side of a sensor chip having an array of capacitive sensors, making the vias electrically conductive, and attaching a cover plate over the first side of the sensor chip spaced from the sensor chip by a distance of less than 25 μm. An improved sensitivity capacitive fingerprint sensor has a capacitive sensor array including multiple sensor cells and electrically conductive, through-chip vias extending from connection points for sensor cell circuitry to a back side of the capacitive sensor array, a chip including active detection circuitry and electrical connection points, the electrical connection points being respectively connected to corresponding ones of the sensor cell circuitry connection points, and a cover plate, disposed above the sensor cells at a spacing of less than 25 μm.03-04-2010
20100055836METHOD OF STACKING AND INTERCONNECTING SEMICONDUCTOR PACKAGES VIA ELECTRICAL CONNECTORS EXTENDING BETWEEN ADJOINING SEMICONDUCTOR PACKAGES - An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.03-04-2010
20120184068METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method includes the steps of: (a) fixing a front surface of a wafer (semiconductor wafer) having the front surface, a plurality of chip regions formed on the front surface, a dicing region formed between the chip regions, and a rear surface opposite to the front surface to the supporting member; (b) in a state of having the wafer fixed to the supporting member, grinding the rear surface of the wafer to expose the rear surface; (c) in a state of having the wafer fixed to the supporting member, dividing the wafer into the chip regions; (d) etching side surfaces of the chip regions to remove crushed layers formed in the step (c) on the side surfaces and obtain a plurality of semiconductor chips. After the steps (e) and (d), the plurality of divided chip regions are peeled off from the supporting member to obtain a plurality of semiconductor chips.07-19-2012
20100047963Through Silicon Via Bonding Structure - System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.02-25-2010
20120178211CO-PACKAGING APPROACH FOR POWER CONVERTERS BASED ON PLANAR DEVICES, STRUCTURE AND METHOD - A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a planar vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the power die.07-12-2012
20100075460Low Cost Die-To-Wafer Alignment/Bond For 3d IC Stacking - The cost associated with alignment in a stacked IC device can be reduced by aligning multiple die instead of a single die during the alignment step. In one embodiment, the alignment structures are placed in the scribe line instead of within the die itself. Aligning four die instead of one eliminates the need for as many alignment indicators and thus more silicon on the wafer can be used for active areas. In addition, this method allows for yield improvement through binning of dies having the same yield configuration.03-25-2010
20120244661Method of Fabricating Semiconductor Die with Through-Hole Via on Saw Streets and Through-Hole Via in Active Area of Die - A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. Metal vias are also formed through the contact pads on the active area of the die. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. Repassivation layers are formed between the RDL for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The vias through the saw streets and vias through the active area of the die, as well as the RDL, provide electrical interconnect to the adjacent die.09-27-2012
20130078765On-Chip Heat Spreader - A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.03-28-2013
20130078763MULTI-CHIP SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A first semiconductor chip having a first projection electrode formed on an upper surface thereof is prepared. A second semiconductor chip having a second projection electrode is mounted on the first semiconductor chip to expose the first projection electrode. An insulating film is formed between the first projection electrode and the second projection electrode. A groove is formed in the insulating film. An interconnection configured to fill an inside of the groove and connected to the first projection electrode and the second projection electrode is formed.03-28-2013
20130078764SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a flexible circuit board which includes a first external electrode provided on a first face and second and third external electrodes provided on a second face; a plurality of memory devices and passive components; a supporter which is provided with a groove on one face; and a computing processor device. The memory devices and the passive components are connected to the first external electrode, the one face of the supporter is bonded on the first face of the flexible circuit board so that the groove houses the memory devices and the passive components. The flexible circuit board is bent along a perimeter of the supporter to be wrapped around a side face and another face of the supporter. On the flexible circuit board, the second external electrode is provided on the second face which is opposite to the first external electrode, and the third external electrode is provided on the second face which is bent to the another face of the supporter. The computing processor device is connected to the second external electrode, and a bump is formed on the third external electrode.03-28-2013
20130137215Die Fixing Method and Apparatus - A die fixing method is disclosed which includes providing a substrate having a metallized surface, forming a joining material on the metallized surface and placing a die alignment member with a plurality of openings on the substrate so that portions of the joining material are exposed through the openings. The method further includes placing a plurality of dies in the openings of the die alignment member with a bottom side of each die in contact with part of the joining material and attaching the plurality of dies to the metallized surface of the substrate at an elevated temperature and pressure, the die alignment member withstanding the elevated temperature and pressure. The die alignment member is removed from the substrate after the plurality of dies are attached to the metallized surface of the substrate.05-30-2013
20130040423Method of Multi-Chip Wafer Level Packaging - A method of multi-chip wafer level packaging comprises forming a reconfigured wafer using a plurality of photo-sensitive material layers. A plurality of semiconductor chips and wafers are embedded in the photo-sensitive material layers. Furthermore, a variety of through assembly vias are formed in the photo-sensitive material layers. Each semiconductor chip embedded in the photo-sensitive material layers is connected to input/output pads through connection paths formed by the through assembly vias.02-14-2013
20090011539Flexible Structures for Interconnect Reliability Test - A method for forming an integrated circuit structure includes forming a test wafer. The step of forming the test wafer includes providing a first semiconductor substrate; and forming a first plurality of unit blocks over the first semiconductor substrate. Each of the first plurality of unit blocks includes a plurality of connection block cells arranged as an array. Each of the connection block cells includes two connection blocks, and a metal line connecting the two connection blocks. The method further includes forming a plurality of unit block boundary lines separating the first plurality of unit blocks from each other; and forming a first plurality of metal lines connecting a portion of the first plurality of unit blocks.01-08-2009
20100093131BONDING APPARATUS AND BONDING METHOD - A bonding apparatus (04-15-2010
20090124045Low Profile Stacking System and Method - The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.05-14-2009
20130045569METHOD AND APPARATUS FOR FABRICATING INTEGRATED CIRCUIT DEVICE USING SELF-ORGANIZING FUNCTION - In a method of fabricating an integrated circuit device having a three-dimensional stacked structured, the step of fixing many chip-shaped semiconductor circuits to a support substrate or a circuit layer with a predetermined layout can be performed easily and efficiently with a desired accuracy. Temporary adhesion portions 02-21-2013
20130089951Wafer Level Packaging Using a Lead-Frame - Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed.04-11-2013
20090004775METHODS FOR FORMING QUAD FLAT NO-LEAD (QFN) PACKAGES - Methods are provided for forming Quad Flat No-Lead (QFN) packages. An embodiment includes disposing an active side of a semiconductor chip on a plurality of leads, coupling a plurality of wire bonds to the active side of the semiconductor chip, coupling the plurality of wire bonds to the plurality of leads in a space between the active side and the plurality of leads, and encasing the semiconductor chip, at least a portion of each of the plurality of leads, and the plurality of wire bonds in a mold material to define a mounting side of the QFN package. The mounting side has a perimeter, the plurality of leads are oriented on and exposed on the mounting side within the perimeter, and the plurality of wire bonds are oriented between the active side and the mounting side within the mold material.01-01-2009
20090305462COMPACT MULTI-PORT CAM CELL IMPLEMENTED IN 3D VERTICAL INTEGRATION - A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array.12-10-2009
20130071969ELECTRONIC ASSEMBLY APPARATUS AND ASSOCIATED METHODS - A method of fabricating an electronic assembly includes fabricating first and second interconnects. The first interconnect is adapted to interconnect a first die to a substrate. The second interconnect is adapted to interconnect the first die to a second die. The method further includes assembling the first die, the second die, and the substrate together such that the first die is disposed above the substrate, and the second die is disposed below the first die.03-21-2013
20120309127METHOD FOR FABRICATING 3D INTEGRATED CIRCUIT DEVICE USING INTERFACE WAFER AS PERMANENT CARRIER - A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 12-06-2012
20110014747STACKABLE PACKAGES FOR THREE-DIMENSIONAL PACKAGING OF SEMICONDUCTOR DICE - An apparatus and a method for packaging semiconductor devices. The apparatus includes a substrate strip component of a leadless three-dimensional stackable semiconductor package having mounting contacts on, for example, four peripheral edges. The substrate strip may either be fabricated for mounting a single electrical component (e.g., an integrated circuit die) or a plurality of substrate strips may be laid out in an X-Y matrix pattern which may later be singulated into individual package strip for leadless packages. three-dimensional stacking is achieved by a bonding area on an uppermost portion of the sidewall. The sidewall of the strip is high enough to enclose an encapsulant covering a later mounted integrated circuit die and associated bonding wires.01-20-2011
20110014746Semiconductor Device and Method of Forming Conductive TSV in Peripheral Region of Die Prior to Wafer Singulaton - A semiconductor device is made by providing a semiconductor wafer having semiconductor die separated by a peripheral region. An opening is formed in the peripheral region having a depth less than a thickness of the wafer. A conductive material is deposited in the opening of the peripheral region of the wafer to form a conductive via extending partially through the wafer. The wafer is singulated through the conductive via in the peripheral region to provide a plurality of semiconductor die each having the conductive via. A semiconductor die is mounted on a sacrificial carrier. An encapsulant is deposited over the carrier around the semiconductor die. A portion of the encapsulant and semiconductor die is removed to expose the conductive via. A first and second interconnect structure are formed over the encapsulant and semiconductor die. The first and second interconnect structures are electrically connected to the conductive via.01-20-2011
20090269882ROTARY CHIP ATTACH - A rotary chip attach process and manufacturing approach takes chips (e.g., integrated circuits (ICs)) from a wafer in a rotary process. A chip wafer with a positioning unit is placed over the top of a sprocketed wheel that picks the ICs directly from the wafer and moves them in a semi-continuous in-step motion to a web that will accept the ICs. The sprocketed wheel includes chips that are preferably the same type as used in a typical pick-and-place robotic system, with vacuum heads adapted to pierce the wafer flat membrane (if needed), grab and IC and place and IC as desired. This positioning system keeps the IC's placement in an accurate position on the web, which can be made to move continuously with a plurality of sprocketed wheel placement units in place.10-29-2009
20120225523Method for Attaching Wide Bus Memory and Serial Memory to a Processor within a Chip Scale Package Footprint - A method for forming a semiconductor device includes physically attaching a first semiconductor die to front surface of a first substrate. The first die is electrically connected to routings on front surface of the first substrate. The routings are electrically connected with conductive pads on back surface of the first substrate. A second semiconductor die is physically attached to front surface of a second substrate. The die is electrically connected to routings on front surface of second substrate. These routings are electrically connected with conductive pads on front surface of the second substrate. A third semiconductor die is physically attached to the second die. The third die is electrically attached to the second die through a plurality of through substrate vias (TSVs) within the second die. The conductive pads on back surface of first substrate are electrically connected to the conductive pads on front surface of second substrate.09-06-2012
20120225522Package 3D Interconnection and Method of Making Same - A method of manufacturing an integrated circuit (IC) package is provided. The method includes stacking an interposer substrate and a device structure, the interposer substrate having a first plurality of contact members formed on a first surface of the interposer substrate and the device structure having a second plurality of contact members that are exposed at a surface of the device structure, and laminating the interposer substrate and the device structure such that the first plurality of contact members are physically and electrically coupled to the second plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the second plurality of contact members.09-06-2012
20130065360METHOD FOR PRODUCING CHIP STACKS, AND A CARRIER FOR CARRYING OUT THE METHOD - The invention relates to a method for producing chip stacks with the following method sequence: 03-14-2013
20110045634Semiconductor Device and Method of Forming Dual-Active Sided Semiconductor Die in Fan-Out Wafer Level Chip Scale Package - In a semiconductor device, a plurality of conductive pillars is formed over a temporary carrier. A dual-active sided semiconductor die is mounted over the carrier between the conductive pillars. The semiconductor die has first and second opposing active surfaces with first contact pads on the first active surface and second contact pads on the second active surface. An encapsulant is deposited over the semiconductor die and temporary carrier. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure is electrically connected to the conductive pillars and first contact pads of the dual-active sided semiconductor die. The temporary carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The second interconnect structure is electrically connected to the conductive pillars and second contact pads of the dual-active sided semiconductor die.02-24-2011
20090233400Rigid-flexible printed circuit board manufacturing method for package on package - A manufacturing method for rigid-flexible multi-layer printed circuit board including: a flexible substrate of which circuits are formed on both sides and which is bendable; a rigid substrate which is laminated on the flexible substrate and circuits are formed on both sides and a cavity within which a semiconductor chip is mounted is formed; and a bonding sheet adhering the flexible substrate and the rigid substrate and having a insulating property. When the same numbers of the semiconductor chips are mounted or the POP is embodied, the whole thickness of the package can be lower. Also, two more semiconductor chips can be mounted using the space as the thickness of the core layer, and the structure impossible when the number of semiconductor chip mounted on the bottom substrate becomes two from one in conventional technology can be embodied.09-17-2009
20120115278STACKED SEMICONDUCTOR PACKAGE WITHOUT REDUCTION IN DATA STORAGE CAPACITY AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package includes a semiconductor chip module including at least two semiconductor chips with a semiconductor chip body having an upper surface, a lower surface, side surfaces coupling the upper surface and the lower surface, and a circuit part. The semiconductor chips include pads coupled to the circuit part and disposed at an edge of the upper surface. A recess parts are concavely formed in the side surfaces corresponding to each pad. Conductive connection patterns cover the recess parts, and each conductive connection pattern is electrically connected to a corresponding bonding pad. The is semiconductor chip module is disposed on a substrate, and the contact pads of the semiconductor substrate are electrically connected to the conductive connection patterns. The stacked semiconductor package provides an improved structure that can contain a plurality of stacked semiconductor chips with no reduction in data storage capacity.05-10-2012
20120115277MULTI-CHIP STACKING METHOD TO REDUCE VOIDS BETWEEN STACKED CHIPS - A multi-chip stacking method to reduce voids between stacked chips is revealed. A first chip is disposed on a substrate, and a plurality of first bonding wires are formed by wire bonding to electrically connect the first chip and the substrate. A second chip is disposed on an active surface of the first chip where a FOW (film over wire) adhesive is formed on a back surface of the second chip. The FOW adhesive partially encapsulates the first bonding wires and adheres to the active surface of the first chip. Then, the substrate is placed in a pressure oven to provide a positive pressure greater than one atm during thermally curing the FOW adhesive with exerted pressures. Accordingly, voids can be reduced inside the FOW adhesive during the multi-chip stacked processes where issues of poor adhesion and popcorn between chips can be avoided.05-10-2012
20100087033METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - A resin layer is formed on a support substrate. An intermediate structure body is formed on the resin layer. The support substrate is fixed to a first unit configured to fix and heat. The intermediate structure body is fixed to a second unit configured to fix and heat. The support substrate and the intermediate structure body are heated by the first unit or the second unit, so as to soften the resin layer. The second unit is moved with respect to the first unit along each of a plurality of line segments or a curve, so as to enlarge a distance between a center of the support substrate and a center of the intermediate structure body as the second unit moves, while the support substrate and the intermediate structure body being kept in the horizontal state, and until the support substrate and the intermediate structure body are separated.04-08-2010
20100330741FABRICATION METHOD FOR SYSTEM-ON-CHIP (SOC) MODULE - A fabrication method for a system-on-chip (SoC) module is provided. The fabrication method includes the steps of providing at least two SoC sub-modules and connecting the SoC sub-modules. The SoC sub-modules are electrically connected with each other by connection interfaces of the SoC sub-modules so as to form the SoC module. As the SoC sub-modules have been verified in advance, the time required for verifying the resulting SoC module can be significantly reduced. As for application-specific SoC modules, they are fabricated by connecting with application-specific SoC sub-modules via the appropriate connection interfaces. Thus, the time and costs for developing SoC modules can both be minimized.12-30-2010
20130164889SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device, a first semiconductor element having a first terminal is embedded in a resin layer such that terminals thereof are exposed through a first surface of the resin layer. A wiring layer is formed in the first surface of the resin layer. A second semiconductor element includes second and third terminals. Regardless of the relationship between the plane size of the first semiconductor element and that of the second semiconductor element, the second terminal of the second semiconductor element is connected to the first terminal of the first semiconductor element exposed through the first surface of the resin layer, and the third terminal of the second semiconductor element is connected to the wiring layer formed in the resin layer.06-27-2013
20110165730METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method of stacking semiconductor chips in layers over a semiconductor substrate having, close to its main surface, semiconductor chips, connecting semiconductor chips in different layers to enable signal transmission, and singularizing the layered semiconductor chips into pieces. The method includes steps of forming an insulating layer on the main surface of the semiconductor substrate; stacking the semiconductor chips over the semiconductor chips of the semiconductor substrate in such a manner as to interpose the insulating layer between them and an opposite surface of each disposed semiconductor chip opposes the insulating layer, the opposite surface being opposite to the main surface; forming, in each of the disposed semiconductor chips, a via hole penetrating from the main to the opposite surface; and forming a connection which enables signal transmission between the disposed semiconductor chips and the corresponding semiconductor chips of the semiconductor substrate via the via holes.07-07-2011
20120100668METHOD OF MANUFACTURING A FLIP CHIP PACKAGE AND APPARATUS TO ATTACH A SEMICONDUCTOR CHIP USED IN THE METHOD - A method and apparatus to manufacture a flip chip package includes dotting a flux on a first preliminary bump of a package substrate, attaching a preliminary bump of a first semiconductor chip to the first preliminary bump of the package substrate via the flux, dotting a flux on a second preliminary bump of the package substrate, and attaching a preliminary bump of a second semiconductor chip to the second preliminary bump of the package substrate via the flux. Accordingly, an evaporation of the flux on the preliminary bump of the package substrate may be suppressed.04-26-2012
20080311700Plastic overmolded packages with mechancially decoupled lid attach attachment - The specification describes a lidded MCM IC plastic overmolded package with a chimney-type heat sink. The lid is mechanically decoupled from the chimneys by a compliant conductive polymer plug.12-18-2008
20110300669Method for Making Die Assemblies - The present invention relates to a method for making chip assemblies, including the following steps of: (a) providing a tested upper wafer and at least one tested lower wafer; (b) sawing the at least one tested lower wafer to form a plurality of lower dice, the lower dice including a plurality of know good lower dice; (c) picking up and rearranging the know good lower dice on a carrier according to the wafer map of the upper wafer; (d) bonding the upper wafer and the carrier; (e) removing the carrier; and (f) proceeding sawing step. Whereby, the dice of the die assembly are both known good dice, thus the yield loss caused by the different yields between the upper wafer and the lower wafer will not occur.12-08-2011
20110300668USE OF DEVICE ASSEMBLY FOR A GENERALIZATION OF THREE-DIMENSIONAL METAL INTERCONNECT TECHNOLOGIES - An assembly process properly positions and align a plurality of first die within a carrier substrate. The first die are positioned within cavities formed in the carrier substrate. The carrier substrate is then aligned with a second substrate having a plurality of second die fabricated therein. The first die and the second die are fabricated using different technologies. Aligning the carrier substrate and the second substrate aligns the first die with the second die. One or more first die can be aligned with each second die. Once aligned, a wafer bonding process is performed to bond the first die to the second die. In some cases, the carrier substrate is removed, leaving behind the first die bonded to the second die of the second substrate. In other cases, the carrier substrate is left in place as a cap. The second substrate is then cut to form die stacks.12-08-2011
20110281395SELF-ASSEMBLY OF MICRO-STRUCTURES - Embodiments of a method for assembling a multi-chip module (MCM) are described. During this method, a fluid that includes coupling elements is applied to a surface of a base plate in the MCM. Then, at least some of the coupling elements are positioned into negative features on the surface of the base plate using fluidic assembly. Note that a given coupling element selects a given negative feature using chemical-based selection and/or geometry-based selection. Next, the fluid and excess coupling elements (which reside in regions outside of the negative features on the surface) are removed.11-17-2011
20110281396Stacked electronic component and manufacturing method thereof - A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.11-17-2011
20120009733POWER SEMICONDUCTOR MODULE AND FABRICATION METHOD - A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.01-12-2012
20110287582METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of funning a semiconductor device includes filling a gap of a semiconductor chip stack while carrying out a first heating process which heats the semiconductor chip stack from upper and lower portions of the semiconductor chip stack.11-24-2011
20110287581SEMICONDUCTOR WORKPIECE CARRIERS AND METHODS FOR PROCESSING SEMICONDUCTOR WORKPIECES - Semiconductor workpiece carriers and methods for processing semiconductor workpieces are disclosed herein. In one embodiment, a semiconductor workpiece carrier assembly includes (a) a support structure having an opening sized to receive at least a portion of a semiconductor workpiece, and (b) a replaceable carrier positioned at the opening. The replaceable carrier includes a base and an adhesive layer on the base. The base has a surface, and the adhesive layer covers only a section of the surface of the base. The adhesive layer releasably attaches the replaceable carrier to the support structure.11-24-2011
20120108009ELECTRICALLY CONDUCTIVE INTERCONNECT SYSTEM AND METHOD - An electrically conductive interconnect system has a post, extending above a supporting surface, the post including a rigid material, a coating on the rigid material, wherein the post and has a first width at the supporting surface and a second width at a distance removed from the supporting surface, and the post narrows from the first width to the second width. A method of electrically connecting a portion of a first supporting surface to a portion of a second supporting surface involves bringing a post on the first supporting surface into contact with an electrically conductive material located on the second supporting surface, softening the electrically conductive material, causing a separation distance between the first supporting surface and the second supporting distance to decrease so that a portion of the post will be surrounded by the electrically conductive material, and allowing the temperature of the electrically conductive material to decrease.05-03-2012
20100099220ELECTRONIC DEVICE WITH UNIQUE ENCODING - An electronic device comprising a thin film transistor (TFT) array and manufacturing methods thereof according to various embodiments. Jet-printed material is deposited on selected partially formed transistors to form completed transistors. Thus, a selected number of the TFTs are connected into the circuit while the remainder of the TFTs are not connected. An electronic read-out of the array identifies the specific array by distinguishing the connected TFTs from the unconnected ones. For a TFT array with n elements there are 204-22-2010
20100273293SUBSTRATE FOR A MICROELECTRONIC PACKAGE AND METHOD OF FABRICATING THEREOF - Substrates having molded dielectric layers and methods of fabricating such substrates are disclosed. The substrates may advantageously be used in microelectronic assemblies having high routing density.10-28-2010
20100035380Method for fabricating package structure of stacked chips - The invention relates to a method for fabricating a package structure of stacked chips, comprising the following steps: firstly, providing a substrate; attaching a first chip and a second chip on the upper surface of the substrate, in which the second chip is stacked on the upper side of the first chip; then connecting a first bonding wire between a second solder pad of the second chip and a first region of a first solder pad of the first chip; and connecting a second bonding wire between a second region of the first solder pad of the first chip and the metal contact of the substrate, whereby the invention is capable of tremendously reducing the volume as a whole, effectively solving the problem of having much bonding wire circuit, and reducing the volume and quantity occupied by the solder pads on the substrate, thereby reducing complexity of the circuit layout on the substrate.02-11-2010
20110263076Stacked semiconductor device - A stacked semiconductor device includes a first semiconductor element bonded on a circuit base. The first semiconductor element is electrically connected to a connection part of the circuit base via a first bonding wire. A second semiconductor element is bonded on the first semiconductor element via a second adhesive layer with a thickness of 50 μm or more. The second adhesive layer is formed of an insulating resin layer whose glass transition temperature is 135° C. or higher and whose coefficient of linear expansion at a temperature equal to or lower than the glass transition temperature is 100 ppm or less.10-27-2011
20100112753SEMICONDUCTOR MEMORY DEVICE - A method includes forming a switching device which includes a vertical channel spaced apart from a semiconductor substrate, and forming a storage device which is positioned on opposed sides of the switching device. The storage device includes a cylindrically shaped storage node, a plate electrode coupled to the storage node, and a dielectric film which is formed between the storage node and plate electrode, the storage nodes being electrically connected to the switching device.05-06-2010
20100267202METHOD OF FABRICATING STACKED SEMICONDUCTOR STRUCTURE - A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.10-21-2010
20100267201Method and System for Providing a Low-Profile Semiconductor Assembly - A semiconductor assembly is provided that includes a substrate that has a first surface. A chip is coupled to the substrate. The chip has a second surface that faces the first surface of the substrate. The chip is spaced apart from the substrate forming a gap. At least a portion of the substrate is coupled to the chip by solder bumps. The solder bumps include a deformable material, such that as a height of the gap between the chip and the substrate increases, the solder bumps deform into a stretched state. An underfill material is applied between the substrate and the chip. The underfill material substantially fills the gap between the chip and the substrate and surrounds the solder bumps in the stretched state. Barricades comprising non-conductive protrusions are disposed between the first surface of the substrate and the second surface of the chip. The barricades confine the solder bumps in a compressed state.10-21-2010
20100267200SEMICONDUCTOR DIE PACKAGES USING THIN DIES AND METAL SUBSTRATES - A semiconductor die package is disclosed. The semiconductor die package comprises a metal substrate, and a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, and at least one aperture. The metal substrate is attached to the second surface. A plurality of conductive structures is on the semiconductor die, and includes at least one conductive structure disposed in the at least one aperture. Other conductive structures may be disposed on the first surface of the semiconductor die.10-21-2010
20100267199METHOD FOR PRODUCING SEMICONDUCTOR CHIP WITH ADHESIVE FILM, ADHESIVE FILM FOR SEMICONDUCTOR USED IN THE METHOD, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - The method for producing a semiconductor chip with an adhesive film of the present invention comprises steps of: preparing a laminate in which a semiconductor wafer, an adhesive film for a semiconductor and a dicing tape are laminated in that order, the adhesive film for a semiconductor having a thickness in the range of 1 to 15 μm and a tensile elongation at break of less than 5%, and the tensile elongation at break being less than 110% of the elongation at a maximum load, and the semiconductor wafer having a reformed section for dividing the semiconductor wafer into the plurality of semiconductor chips, which is formed by irradiating with laser light; dividing the semiconductor wafer into the plurality of semiconductor chips without dividing the adhesive film for a semiconductor by expanding the dicing tape in a direction in which the plurality of semiconductor chips are each separated; and dividing the adhesive film for a semiconductor by picking up the plurality of semiconductor chips in a laminating direction of the laminate, thereby preparing a semiconductor chip with an adhesive film.10-21-2010
20090311828APPARATUS AND METHODS FOR CONSTRUCTING SEMICONDUCTOR CHIP PACKAGES WITH SILICON SPACE TRANSFORMER CARRIERS - Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.12-17-2009
20080280393METHODS FOR FORMING PACKAGE STRUCTURES - A method for forming a semiconductor structure includes forming a first connector over at least one pad of a first substrate, the first connector having at least one curved sidewall. An encapsulation layer is formed at least partially over the first connector so as to partially expose a top surface of the first connector. A solder structure is formed, contacting the first connector.11-13-2008
20120100669METHOD OF MANUFACTURING TMV PACKAGE-ON-PACKAGE DEVICE - A method of manufacturing a Through Mold Via (TMV) package-on-package device while preventing a bad solder joint from occurring in the TMV package-on-package device is provided. The method includes coating exposed portions of a lower semiconductor package with an organic soldering preservative, and stacking a top semiconductor package on the lower semiconductor package and connecting lower solder balls of the top semiconductor package with the top solder balls of the lower semiconductor package. According to the method, a bad solder joint may be prevented from occurring when a top semiconductor package is bonded to a lower semiconductor package.04-26-2012
20120034740PRE-ENCAPSULATED CAVITY INTERPOSER - Methods of forming pre-encapsulated frames comprise flowing a dielectric encapsulation material around at least one conductive trace. A cavity configured to receive at least one semiconductor device at least partially in the cavity is formed in the encapsulation material. A first connection area of the at least one trace is exposed within the cavity. At least another connection area of the at least one trace is exposed laterally adjacent to the cavity. The dielectric encapsulation material is hardened to form a pre-encapsulated frame.02-09-2012
20120034739CHIP CAPACITIVE COUPLING - A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.02-09-2012
20100081232LAYER TRANSFER PROCESS AND FUNCTIONALLY ENHANCED INTEGRATED CIRCUITS PRODUCED THEREBY - A structure for a semiconductor components is provided having a device layer sandwiched on both sides by other active, passive, and interconnecting components. A wafer-level layer transfer process is used to create this planar (2D) IC structure with added functional enhancements.04-01-2010
20110201153INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit having an active side and a non-active side; forming a channel through the integrated circuit; forming an indent, having a flange and an indent side, from a peripheral region of the non-active side; and forming a conformal interconnect, having an offset segment, a sloped segment, and a flange segment, under the indent.08-18-2011
20110201152SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device is provided that includes a semiconductor chip and a resin section that molds the semiconductor chip and has a first through-hole. A through electrode that is electrically coupled to the semiconductor chip, extends through the resin section, and extends between a top edge and a bottom edge of an inner surface of the first through-hole. A cavity which extends between planes corresponding to an upper surface and a lower surface of the resin section is formed inside the first through-hole.08-18-2011
20110201151METHODS FOR FORMING A BONDED SEMICONDUCTOR SUBSTRATE INCLUDING A COOLING MECHANISM - Bottom sides of two semiconductor substrates are brought together with at least one bonding material layer therebetween and bonded to form a bonded substrate. A cavity with two openings and a contiguous path therebetween is provided within the at least one bonding layer. At least one through substrate via and other metal interconnect structures are formed within the bonded substrate. The cavity is employed as a cooling channel through which a cooling fluid flows to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate. Alternatively, a conductive cooling fin with two end portions and a contiguous path therebetween is formed within the at least one bonding layer. The two end portions of the conductive cooling fin are connected to heat sinks to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate.08-18-2011
20090170242System-in-Package Having Integrated Passive Devices and Method Therefor - A method of manufacturing a semiconductor device involves providing a substrate, forming a first passivation layer over the substrate, and forming an integrated passive circuit over the substrate. The integrated passive circuit can include inductors, capacitors, and resistors. A second passivation layer is formed over the integrated passive circuit. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive circuit. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive circuit. A metal layer can be formed over the molding compound or first passivation layer for shielding.07-02-2009
20110171778METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like.07-14-2011
20110171777METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Chip cracking that occurs when a dicing step using a blade is carried out to acquire semiconductor chips with the reduced thickness of a semiconductor wafer is suppressed. When the semiconductor wafer is cut at the dicing step for the semiconductor wafer, a blade is advanced as follows: in dicing in a first direction (Y-direction in FIG. 07-14-2011
20090142883Leaded Stacked Packages Having Elevated Die Paddle - A semiconductor package includes a leadframe, an elevated die paddle disposed above the leadframe, a first die attached to a lower surface of the elevated die paddle to support the first die within the semiconductor package, and a second die attached to the first die. A method of manufacturing a semiconductor package includes providing a leadframe having a lower lead and an elevated die paddle structure, attaching a first die to the elevated die paddle structure with a die adhesive (DA) for supporting the first die within the semiconductor package, and wire bonding the first die to the lower lead.06-04-2009
20090137084Method and apparatus for manufacturing semiconductor module - Disclosed herewith is a semiconductor module manufacturing apparatus capable of reducing occurrence of warping of the wiring substrate, etc., as well as occurrence of failures of bonding between the wiring substrate and semiconductor chips, etc. without lowering the productivity. The semiconductor module manufacturing apparatus employs a batch reflowing process that heats one, two, or more wiring substrates and at least two or more semiconductor chips or semiconductor devices simultaneously. After the heating process, the semiconductor chips or semiconductor devices are heated and bonded on the wiring substrate. The apparatus includes at least a stage for chucking the wiring substrate fixedly; a heat source for heating the semiconductor chips or semiconductor devices out of contact therewith; and a controller for controlling the heating value of the heat source.05-28-2009
20090286354SEMICONDUCTOR CHIP HAVING GETTERING LAYER, AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor chip A wherein an element layer 11-19-2009
20110269268SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME - The degree of freedom of the chip layout in a semiconductor device is improved, and improvement in packaging density is aimed at.11-03-2011
20100279465SEMICONDUCTOR MANUFACTURING METHOD OF DIE PICK-UP FROM WAFER - A manufacturing method of a semiconductor device comprising the steps of: affixing a die attach film and a dicing film to a back surface of a semiconductor wafer: thereafter dicing the semiconductor wafer and the die attach film to divide the semiconductor wafer into a plurality of semiconductor chips: thereafter pulling the dicing film from the center toward the outer periphery of the dicing film with a first tensile force to cut the die attach film chip by chip; and thereafter picking up the semiconductor chips together with the die attach film while pulling the dicing film from the center toward the outer periphery of the dicing film with a second tensile force smaller than the first tensile force.11-04-2010
20100279463METHOD OF FORMING STACKED-DIE PACKAGES - A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure covers a central portion of the first surface of the wafer and leaves an edge portion of the wafer exposed. A protective material is formed over the first surface of the edge portion of the wafer.11-04-2010
20090170241Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier - A semiconductor device is made by forming contact pads on a sacrificial carrier. The contact pads may be formed on a pillar. A semiconductor die is mounted to electrically connect to the contact pads with solder bumps or wire bonds. The semiconductor die is encapsulated with molding compound. The sacrificial carrier is removed. A backside interconnect structure has a first conductive layer formed over the molding compound to electrically connect to the contact pads. A first insulating layer is formed over the first conductive layer. A portion of the first insulating layer is removed to expose the first conductive layer. Solder material is deposited in electrical contact with the first conductive layer. The solder material is reflowed to form a solder bump. A wire bond electrically connects to a contact pad. A front-side interconnect structure can be formed through the molding compound to the contact pads.07-02-2009
20100221870SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An IC card is more expensive than a magnetic card, and an electronic tag is also more expensive as a substitute for bar codes. Therefore, the present invention provides an extremely thin integrated circuit that can be mass-produced at low cost unlike a chip of a conventional silicon wafer, and a manufacturing method thereof. One feature of the present invention is that a thin integrated circuit is formed by a formation method that can form a pattern selectively, on a glass substrate, a quartz substrate, a stainless substrate, a substrate made of synthetic resin having flexibility, such as acryl, or the like except for a bulk substrate. Further, another feature of the present invention is that an ID chip in which a thin film integrated circuit and an antenna according to the present invention are mounted is formed.09-02-2010
20080274588Semiconductor device and method of fabricating the same, circuit board, and electronic instrument - A method of fabricating a semiconductor device, including: preparing a wiring board on which is mounted a first semiconductor chip having a plurality of first pads; electrically connecting each of the first pads to an interconnecting pattern of the first semiconductor chip by a wire; providing resin paste on the first semiconductor chip; mounting a second semiconductor chip having a plurality of second pads on the first semiconductor chip with the resin paste interposed therebetween; and forming a spacer by hardening the resin paste to fix the first and second semiconductor chips together, wherein the spacer is formed to extend under the second pads and further outward; and wherein the highest portion of the wire is disposed on the outer side of the first semiconductor chip.11-06-2008
20090170243Stacked Integrated Circuit Module - The present invention provides an improvement on the use of flexible circuit connectors for electrically coupling IC devices to one another in a stacked configuration by use of the flexible circuit to provide the connection of the stacked IC module to other circuits. Use of the flexible circuit as the connection of the IC module allows the flexible circuit to provide strain relief and allows stacked IC modules to be assembled with a lower profile than with previous methods. The IC module can be connected to external circuits through the flexible circuit connectors by a variety of means, including solder pads, edge connector pads, and socket connectors. This allows for IC devices to occupy less space then with previous methods, which is beneficial in modules such as memory modules with multiple, stacked memory devices.07-02-2009
20080293184Method of Bonding Aluminum Electrodes of Two Semiconductor Substrates - A method of bonding aluminum (Al) electrodes formed on two semiconductor substrates at a low temperature that does not affect circuits formed on the two semiconductor substrates is provided. The method includes: (a) forming aluminum (Al) electrodes on the two semiconductor substrates, respectively, and depositing a metal alloy that comprises aluminum (Al) and copper (Cu) onto the aluminum (Al) electrodes; (b) arranging the aluminum (Al) electrodes of the two semiconductor substrates to face with each other; and (c) heating the aluminum (Al) electrodes at a temperature lower than the melting point of the deposited metal alloy, and applying a specific pressure onto the two semiconductor substrates. Accordingly, bonding can be carried out at a temperature lower than the melting point of an Al11-27-2008
20080293185SEMICONDUCTOR SUBSTRATES HAVING USEFUL AND TRANSFER LAYERS - A method of fabricating composite substrates by associating a transfer layer with an intermediate support to form an intermediate substrate of predetermined thickness with the transfer layer having a free surface; providing a sample carrier having a surface and a recess that has a depth that is approximate the same as the predetermined thickness of the intermediate substrate so that the transfer layer free surface is positioned flush with the sample carrier surface; providing a support layer both on the transfer layer free surface and on a portion of the sample carrier surface surrounding the recess; removing the portion of the support layer that extends beyond the intermediate substrate; and detaching the transfer layer and support layer from its intermediate support to form the composite substrate. The support layer is made of a deposited material that has a lower quality than that of the intermediate support. A bonding layer may be included on one of the intermediate support or the useful layer, or both, to facilitate bonding of the layers. The final substrates are useful in optic, electronic, or optoelectronic applications.11-27-2008
20080305576METHOD OF REDUCING WARPAGE IN SEMICONDUCTOR MOLDED PANEL - A panel is disclosed on which a plurality of integrated circuit package outlines may be fabricated within a plurality of process tools. The panel includes recessed portions in the exposed surfaces of the molding compound and/or the substrate. The recesses relieve stress resulting from disparate coefficients of expansion between the substrate and molding compound applied to the substrate around the integrated circuits. In embodiments, the recesses may be formed as lines scored into the surface of the molding compound or substrate. Alternatively, the recesses may be formed in the solder mask on the substrate during a process for applying the solder mask, or the recesses may be formed in the molding compound during the encapsulation process.12-11-2008
20120295400METHOD FOR PRODUCING SEMICONDUCTOR CHIP WITH ADHESIVE FILM, ADHESIVE FILM FOR SEMICONDUCTOR USED IN THE METHOD, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - The method for producing a semiconductor chip with an adhesive film includes preparing a laminate of a divided semiconductor wafer, an adhesive film and a dicing tape, the adhesive film having a thickness in the range of 1 to 15 μm and a tensile elongation at break of less than 5%, and the tensile elongation at break being less than 110% of the elongation at a maximum load; and dividing the adhesive film for a semiconductor by picking up the plurality of semiconductor chips in a laminating direction of the laminate. The divided semiconductor wafer has been obtained by cutting the semiconductor wafer in a thickness less than that of the semiconductor wafer and by grinding the other side of the semiconductor wafer on which no cut is formed to reach the cut.11-22-2012
20100279464FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.11-04-2010
20080286899METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SYSTEM-IN-PACKAGE USING THE SAME - A method for manufacturing a semiconductor device and a method for manufacturing a system-in-package using the same, which are capable of enhancing reliability and the step coverage for a trench having a high aspect ratio. The semiconductor manufacturing method includes forming a first insulating film over a substrate; and then forming first and second metal patterns over the first insulating film; and then forming a second insulating film over the first insulating film including the first and second metal patterns; and then forming a trench extending through the first and second insulating films and into the substrate thereby exposing the substrate; and then sequentially forming first and second oxide films over the second insulating film and in the trench; and then forming a via hole exposing the first metal pattern; and then sequentially forming first and second barrier metal films over a resultant surface of the substrate including the second oxide film; and then forming a copper layer over the second barrier metal film and in the trench and the via hole; and then planarizing the copper layer exposing a portion of the second barrier metal film; and then forming a copper pad by recessing predetermined portions of the second barrier metal film, the first barrier metal film, the second oxide film and the first oxide film exposing the second insulating film at opposite sides of the copper pad.11-20-2008
20100144092Semiconductor device and fabrication method thereof - A semiconductor device and a fabrication method thereof are provided. A semiconductor device which is packaged as it includes a semiconductor in which an electronic circuit is disposed, the semiconductor device including: a substrate; a semiconductor chip which has a semiconductor main body having the electronic circuit formed thereon, a pad electrode formed on the semiconductor main body and a projected electrode that is connected to the pad electrode and projected from a surface of the semiconductor main body, wherein the semiconductor chip is mounted on the substrate from the back side of the surface to form the projected electrode thereon; and an insulating layer which is formed as the semiconductor chip buried therein and is polished from a top surface of the insulating layer to a height at which a top of the projected electrode is exposed.06-10-2010
20100144091Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device includes forming an interconnect member, mounting a first semiconductor chip having a semiconductor substrate in a face-down manner on the interconnect member, forming a resin layer on the interconnect member to cover a side surface of the first semiconductor chip, thinning the first semiconductor chip and the resin layer, forming an inorganic insulating layer on a back surface of the first semiconductor chip so as to be in contact with the back surface and to extend over the resin layer, and forming a through electrode so as to penetrate the inorganic insulating layer and the semiconductor substrate.06-10-2010
20120142144Wafer Level Structures and Methods for Fabricating and Packaging MEMS - Methods of fabricating a Micro-Electromechanical System (MEMS) in a hermetically sealed cavity formed at a substrate level are provided. Generally, the method comprises: (i) forming a number of first open cavities in a surface of a first substrate and a number of second open cavities in a surface of a second substrate corresponding to the first open cavities; (ii) forming an actuator/sensor layer including a number of MEMS devices with electrically conductive regions therein; (iii) bonding the first substrate and the second substrate to the actuator/sensor layer so that at least one of the number of the first and second open cavities align with at least one of the number of MEMS devices to form a sealed cavity around the MEMS; and (iv) electrically connecting the electrically conductive regions of the MEMS device to a pad outside of the sealed cavity through an electrical interconnect. Other embodiments are also described.06-07-2012
20090004774METHOD OF MULTI-CHIP PACKAGING IN A TSOP PACKAGE - A method of fabricating a semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package may include a leadframe having one or more semiconductor die and one or more passive components affixed thereon. The one or more passive components may be affixed by soldering with a solder material. In embodiments, in order to prevent bleeding of the solder material during a solder reflow process, barricades are formed on the surface of the leadframe, at least partially surrounding the one or more passive components.01-01-2009
20090186446Semiconductor device packages and methods of fabricating the same - Provided are semiconductor device packages and methods for fabricating the same. In some embodiments, the method includes providing a semiconductor chip on a substrate with through electrodes formed in the substrate, and providing a capping layer on the substrate to receive the semiconductor chip in a recess formed in the capping layer. The capping layer is coupled to the substrate by a bonding layer formed on the substrate, and the capping layer covers the semiconductor chip provided on the substrate. The processing of the substrate and the capping layer can be separately performed, thus allowing the material for the capping layer and/or the substrate to be selected to reduce (e.g., to minimize) a difference between the thermal expansion coefficients of the capping layer material and the substrate material.07-23-2009
20110223717PIN-TYPE CHIP TOOLING - An apparatus for use with multiple chips having multiple posts as to engage at least a portion of a surface of one of the multiple chips, a frame configured to releasably constrain each of the posts so that, when unconstrained, each individual post can contact an individual chip and, when constrained, will allow a uniform vertical force to be applied to the chips.09-15-2011
20090325343BONDED SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A method of forming a bonded semiconductor structure circuit includes providing a support substrate which carries a first semiconductor circuit and providing a first interconnect region carried by the support substrate. The method includes providing a bonded semiconductor substrate which is bonded to the first interconnect region through a bonding interface and forming a second semiconductor circuit which is carried by the first bonded semiconductor substrate.12-31-2009
20090023243METHOD AND APPARATUS FOR FABRICATING INTEGRATED CIRCUIT DEVICE USING SELF-ORGANIZING FUNCTION - In a method of fabricating an integrated circuit device having a three-dimensional stacked structured, the step of fixing many chip-shaped semiconductor circuits to a support substrate or a circuit layer with a predetermined layout can be performed easily and efficiently with a desired accuracy. Temporary adhesion portions 01-22-2009
20130217181METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A method of manufacturing a semiconductor package, the method including: disposing a plurality of semiconductor chips; forming a sealing part sealing the plurality of semiconductor chips; forming a substrate part on at least one surface of the sealing part; and forming an antenna part on the sealing part or the substrate part.08-22-2013
20090042336Fabrication method of an organic substrate having embedded active-chips - The fabrication method of an organic substrate having embedded active-chips such as semiconductor chips is disclosed. The present invention previously applies the conductive adhesives in a wafer state, makes them in a B-stage state, obtains individual semiconductor chips through dicing, and positions the individual semiconductor chips previously applied with the conductive adhesives in the cavities, making it possible to simultaneously obtain an electrical connection and a physical adhesion of the substrate and the semiconductor chips by means of a method of applying heat and pressure and stack the copper clad laminates on the upper portion of the substrate to which the semiconductor chips are connected. The present invention has advantages in processes such as a lead-free process, an environmental-friendly fluxless process, a low temperature process, ultra-fine pitch applications, etc., by mounting the active-chips through the flip chip interconnection using the non-solder bumps and the conductive adhesives.02-12-2009
20090087946STRUCTURE AND METHOD FOR THIN SINGLE OR MULTICHIP SEMICONDUCTOR QFN PACKAGES - A semiconductor device (04-02-2009
20090124044Method for removing bubbles from adhesive layer of semiconductor chip package - In a method for removing bubbles from adhesive layer of semiconductor chip package, one or more semiconductor chips are attached to or stacked on a base plate using an adhesive material. The base plate is selected from a substrate, a lead frame, and other carrier for carrying the semiconductor chips thereon. Before the adhesive material starts curing or becomes fully cured, the base plate with the semiconductor chips is placed in a processing tank which is preset to heat at a predetermined heating rising rate to a predetermined temperature and to apply a predetermined pressure for a predetermined period of time, so that bubbles presented in the adhesive material, at an interface between the adhesive material and the base, and at an interface between the adhesive material and the semiconductor chip are expelled from the adhesive material under the temperature and pressure in the processing tank.05-14-2009
20090203168Manufacturing Method for a Secure-Digital (SD) Flash Card with Slanted Asymmetric Circuit Board - A flash-memory device has a printed-circuit board assembly (PCBA) with a PCB with a flash-memory chip and a controller chip. The controller chip includes an input/output interface circuit to an external computer over a Secure-Digital (SD) interface, and a processing unit to read blocks of data from the flash-memory chip. The PCBA is encased inside an upper case and a lower case, with SD contact pads on the PCB that fit through contact openings in the upper case. Supporting end ribs under each of the SD contact pads and middle ribs support the PCB at a slanted angle to the centerline of the device. The PCB slants upward at the far end to allow more thickness for the chips mounted to the bottom surface of the PCB, and slants downward at the insertion end to position the SD contact pads near the centerline.08-13-2009
20090191665Electronic Device and Method of Manufacturing Same - This application relates to a method of manufacturing an electronic device comprising placing a first chip on a carrier; applying an insulating layer over the first chip and the carrier; applying a metal ions containing solution to the insulating layer for producing a first metal layer of a first thickness; and producing a second metal layer of a second thickness on the insulating layer wherein at least one of the first metal layer and the second metal layer comprises at least a portion that is laterally spaced apart from the respective other metal layer.07-30-2009
20110230011FABRICATION METHOD FOR INTEGRATED CIRCUIT CHIP COMPONENT,MULTI-CHIP MODULE, AND THEIR INTEGRATION STRUCTURE - A multi-chip module and an integrated structure of the present invention including: at least one of either a terminal unit formation area expanded type integrated circuit chip, or a terminal unit formation area identical type integrated circuit chip; terminal unit formation areas of these integrated circuits that are covered with protective layers, and expanded wiring units and terminal units formed in the protective layers; one or a plurality of the terminal unit formation area expanded type and the terminal unit formation area identical type integrated circuit chip components that are two-dimensionally or three-dimensionally aligned in further protective layers; a horizontal or a vertical wiring formed for arbitrarily connecting the plurality of the integrated circuit chip components in the further protective layers.09-22-2011
20090053854MEMORY CIRCUIT ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF - A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.02-26-2009
20090017580SYSTEMS AND METHODS FOR VERTICALLY INTEGRATING SEMICONDUCTOR DEVICES - Systems and methods for vertically integrating semiconductor devices are described. In one embodiment, a method comprises providing an interposer, aligning and bonding a plurality of die to a first surface of the interposer, aligning and bonding a backplate to the plurality of die, and reducing at least one portion of the interposer to create a reconstituted wafer. In another embodiment, an apparatus comprises an interposer operable to receive at least one donor semiconductor device disposed on a first surface of the interposer and aligned therewith, and at least one host semiconductor device disposed on a second surface of the interposer and aligned therewith; where the interposer allows the at least one donor and host semiconductor devices to become vertically integrated.01-15-2009
20090209061METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - Provided is a semiconductor package and method of manufacturing same. The method includes: forming a plurality of semiconductor chips which have the same pattern direction on a semiconductor substrate, each of which includes a memory cell region, a peripheral region and a pad region, and in each of which the pad region is disposed in an edge region; separating the semiconductor chips, which are formed on the semiconductor substrate, from one another; and disposing semiconductor chips, which are selected from the separated semiconductor chips, on a package substrate by changing the pattern directions of the selected semiconductor chips and arranging pad regions of the selected semiconductor chips in a center region of the package substrate.08-20-2009
20090239337MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.09-24-2009
20080274587Method of Assembling Electronic Components of an Electronic System, and System Thus Obtained - An electronic system comprising: an electronic system support substrate for the attachment of components of the electronic system, the electronic system support substrate including electric signal propagation paths for the propagation of electric signals between the system components; at least a first and a second electronic components, wherein at least the first electronic component is part of a module in mechanical and electrical connection with the electronic system support substrate, the module comprising a module substrate to which the first electronic component is at least mechanically connected, and an electric coupling between the first and the second electronic components, for the electric coupling allowing the first and the second electronic components exchange of electric signals. The electric coupling comprises a direct electric connection, particularly formed by a flexible electrical interconnection member, between the first and the second electronic components, the electric connection being independent of the electronic system support substrate.11-06-2008
20090246910Semiconductor device manufacturing method - A semiconductor device manufacturing method includes the steps of preparing a semiconductor element having a first electrode, a second electrode, and a third electrode facing the first electrode and second electrode, the first electrode and second electrode being electrically separated by an insulating layer; arranging a first conductive bonding material on a first metal foil and placing the semiconductor element on the first conductive bonding material; supporting a sheet-shape second conductive bonding material by the insulating layer; arranging a first post electrode and a second post electrode above the first and second electrodes respectively with the second conductive bonding material intervening therebetween; and forming a first conductive bonding layer for bonding the first electrode and the first post electrode, a second conductive bonding layer for bonding the second electrode and the second post electrode, and a third conductive bonding layer for bonding the third electrode and the first metal foil.10-01-2009
20090239336Semiconductor packages and methods of fabricating the same - A semiconductor package and module, and methods of fabricating the same are provided. A method of fabricating a semiconductor package may include bonding rear surfaces of first and second semiconductor chips to each other, each of the semiconductor chips having chip pads exposed on front surfaces. The method may also include forming an encapsulation portion configured to encapsulate side surfaces of the bonded semiconductor chips, forming via plugs configured to pass through the encapsulation portion, forming an insulating layer configured to expose surfaces of the chip pads and the via plugs on the exposed surfaces of the two semiconductor chips and surfaces of the encapsulation portion, and forming package pads on the exposed surfaces of the chip pads and the surfaces of the via plugs.09-24-2009
20090253230METHOD FOR MANUFACTURING STACK CHIP PACKAGE STRUCTURE - A method for manufacturing a stack chip package structure is disclosed. The method comprises: providing a first substrate; disposing a first chip on the first substrate; disposing a second chip and at least one second substrate on the first chip, wherein the second substrate is electrically connected to the first chip; bonding at least one first connecting wire connected between the second chip and the second substrate; bonding at least one second connecting wire connected between the first substrate and the second substrate; and forming a package body on the first substrate to encapsulate the first chip, the second chip, the second substrate, the first connecting wire and the second connecting wire.10-08-2009
20090258458DFN semiconductor package having reduced electrical resistance - A dual flat non-leaded semiconductor package is disclosed. A method of making a dual flat non-leaded semiconductor package includes forming a leadframe having a die bonding area with an integral drain lead, a gate lead bonding area and a source lead bonding area, the gate lead bonding area and a source lead bonding area being of increased area; bonding a die to the die bonding area; coupling a die source bonding area to the source lead bonding area; coupling a die gate bonding area to the gate lead bonding area; and partially encapsulating the die, the drain lead, the gate lead and the source lead to form the dual flat non-leaded semiconductor package.10-15-2009
20090258459Packaged System of Semiconductor Chips Having a Semiconductor Interposer - A semiconductor system (10-15-2009
20130011965DISTRIBUTING POWER WITH THROUGH-SILICON-VIAS - An integrated circuit with distributed power using through-silicon-vias (TSVs) is presented. The integrated circuit has conducting pads for providing power and ground located within the peripheral region of the top surface. A number of through-silicon-vias are distributed within the peripheral region and a set of TSVs are formed within the non-peripheral region of the integrated circuit. Conducting lines on the bottom surface are coupled between each peripheral through-silicon-via and a corresponding non-peripheral through-silicon-via. Power is distributed from the conducting pads to the TSVs within the non-peripheral region through the TSVs within the peripheral region, thus supplying power and ground to circuits located within the non-peripheral region of the integrated circuit chip.01-10-2013
20110111559INTEGRATED-CIRCUIT PACKAGE FOR PROXIMITY COMMUNICATION - Embodiments of a multi-chip module (MCM) are described. This MCM includes a first semiconductor die and a second semiconductor die, where a given semiconductor die, which can be the first semiconductor die or the second semiconductor die, includes proximity connectors proximate to a surface of the given semiconductor die. Moreover, the given semiconductor die is configured to communicate signals with the other semiconductor die via proximity communication through one or more of the proximity connectors. Furthermore, the MCM includes an alignment plate and a top plate coupled to the alignment plate. This alignment plate includes a first negative feature configured to accommodate the first semiconductor die and a second negative feature configured to accommodate the second semiconductor die, and the top plate includes a positive feature. Note that the positive feature is coupled to the first semiconductor die, and the positive feature facilitates mechanical positioning of the first semiconductor die.05-12-2011
20100261309METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device in which a second semiconductor chip is bonded to a surface of a first semiconductor chip. The method includes: a back side grinding step for grinding the back side of a wafer including a device area where a plurality of first semiconductor chips are formed, the grinding applied to an area corresponding to the device area, so as to reduce the thickness of the wafer in the device area to a predetermined finished thickness; a chip bonding step for bonding the second semiconductor chip to a predetermined position of the surface of each of the first semiconductor chips formed on the face-side surface of the wafer; and a wafer dividing step for dividing the wafer along streets to separate the device area of the wafer into individual semiconductor devices in each of which the second semiconductor chip is bonded to the surface of the first semiconductor chip.10-14-2010
20100261310Via First Plus Via Last Technique for IC Interconnect - A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. The first set of vias are produced prior to circuitry on the die, and the second set of vias are produced after circuitry on the die. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias.10-14-2010
20100216281Semiconductor Device and Method of Forming Through Vias with Reflowed Conductive Material - A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die.08-26-2010
20120196402IMPLEMENTING MULTIPLE DIFFERENT TYPES OF DIES FOR MEMORY STACKING - A method and structure are provided for implementing multiple different types of dies for memory stacking. A common wafer is provided with a predefined reticle type. The reticle type includes a plurality of arrays, and a plurality of periphery segments. A plurality of through-silicon-vias (TSVs) is placed at boundaries between array and periphery segments. Multiple different types of dies for memory stacking are obtained based upon selected scribing of the dies from the common wafer.08-02-2012
20100216280INTEGRATED CIRCUIT MICRO-MODULE - Various methods for forming an integrated circuit micro-module are described. In one aspect of the invention, layers of an epoxy are sequentially deposited over a substrate to form planarized layers of epoxy over the substrate. The epoxy layers are deposited using spin coating. At least some of the layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. Openings are formed in at least some of the patterned epoxy layers after they are patterned and before the next epoxy layer is deposited. An integrated circuit is placed within one of the openings. At least one of the epoxy layers is deposited after the placement of the integrated circuit to cover the integrated circuit. At least one conductive interconnect layer is formed over an associated epoxy layer. Multiple external package contacts are formed. The integrated circuit is electrically connected with the external package contacts at least in part through one or more of the conductive interconnect layers.08-26-2010
20100151624FABRICATING PROCESS OF A CHIP PACKAGE STRUCTURE - A fabricating process of a chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provided, wherein bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the second substrate and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first and second B-staged adhesive layer such that the bumps pierce through the second B-staged adhesive layer and are electrically connected to the second bonding pads, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.06-17-2010
20100240174Via Using Zn or Zn Alloys and Its Making Method, 3D Chip Stack Packages Using Thereof - Disclosed are via, a method for formation of via using zinc and zinc alloys, and a process for fabrication of three-dimensional multiple chip stack packages by using the same. In lamination of three-dimensional chips, the chips with reduced defects are rapidly formed by the steps of: punching each of the chips to form a via hole used for a circuit wiring between the chips; depositing a seed layer on an inside of the via hole; forming a plated layer inside the via hole by using Zn and Zn alloys through an electroplating process; removing oxide film from surface of the plated layer; and heat treating the via hole at a temperature of more than melting point of the Zn and Zn alloys. Particularly, the chip having Zn via formed according to the present invention has an advantage of simultaneously overcoming problems in establishment of processing parameters caused by Cu via (e.g., plating mode, current density, influence of additives, pore formation, etc.), problems in successive processes caused by Sn (and other low melting point metals) via (e.g., soldering, chip stack, etc.) and difficulty in mechanical reliability of the process. Additionally, when stacking multiple chips with various functions in the three-dimensional chip stack package, the package can be simply fabricated by controlling contents of constitutional elements in Zn alloy via which has specific thermal properties (such as melting point, thermal expansion coefficient, etc.) suitable for processing temperature of each of the chips.09-23-2010
20130217182PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES - Packaged microelectronic devices and methods of manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a stand-off layer over a plurality of microelectronic dies on a semiconductor workpiece, and removing selected portions of the stand-off layer to form a plurality of stand-offs with the individual stand-offs positioned on a backside of a corresponding die. The method further includes cutting the semiconductor workpiece to singulate the dies, and attaching the stand-off on a first singulated die to a second die.08-22-2013
20090075423METHOD OF BONDING CHIPS ON A STRAINED SUBSTRATE AND METHOD OF PLACING UNDER STRAIN A SEMICONDUCTOR READING CIRCUIT - The invention concerns a method of collective bonding of individual chips on a strained substrate (03-19-2009
20090075424Process for making microelectronic element chips - Apparatus including a chip substrate having a first chip surface facing away from a second chip surface; an array of microelectronic elements on the first chip surface; and an array of conductors each in communication with one of the microelectronic elements, the conductors passing through the chip substrate and fully spanning a distance between the first and second chip surfaces. Process including: providing an apparatus including a chip substrate having a first chip surface facing away from a second chip surface, an array of microelectronic elements being on the first chip surface, an array of conductors each being in communication with one of the microelectronic elements and partially spanning an average distance between the first and second chip surfaces; bonding a temporary support carrier onto the array of microelectronic elements; removing a portion of the chip substrate, thereby reducing the average distance between the first and second chip surfaces; and forming an under bump metallization pad at the second chip surface in electrical communication with a conductor.03-19-2009
20120142145SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, a semiconductor device manufacturing method includes producing a first substrate with an electrode, producing a second substrate with a through hole, stacking the second substrate on the first substrate, with an insulating layer intervening between the first substrate and the second substrate, making a hole reaching the electrode in the insulating layer under the through hole by etching the insulating layer with the second substrate as a mask, and filling the through hole and the hole with conductive substance.06-07-2012
20090280601METHOD AND APPARATUS FOR FACILITATING PROXIMITY COMMUNICATION AND POWER DELIVERY - The described embodiments provide a system that facilitates inter-chip alignment for proximity communication and power delivery. The system includes a first integrated circuit chip and a second integrated circuit chip, both of which whose surfaces have corresponding etch pit wells configured to align with each other. A shaped structure is placed in an etch pit well of the first integrated circuit chip such that when the corresponding etch pit well of the second integrated circuit chip is substantially aligned with the etch pit well of the first integrated circuit chip, the shaped structure mates with both the etch pit well of the first integrated circuit chip and with the corresponding etch pit well of the second integrated circuit chip, thereby aligning the first integrated circuit chip with the second integrated circuit chip. In some embodiments the etch pit wells include conductive structures for routing power through a conductive shaped structure.11-12-2009
20100197077SEMICONDUCTOR PACKAGE ADAPTED FOR HIGH-SPEED DATA PROCESSING AND DAMAGE PREVENTION OF CHIPS PACKAGED THEREIN AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes a semiconductor chip provided with a first surface having a bonding pad, a second surface opposing to the first surface and side surfaces; a first redistribution pattern connected with the bonding pad and extending along the first surface from the bonding pad to an end portion of the side surface which meets with the second surface; and a second redistribution pattern disposed over the first redistribution pattern and extending from the side surfaces to the to first surface. In an embodiment of the present invention, in which the first redistribution pattern connected with the bonding pad is formed over the semiconductor chip and the second redistribution pattern is formed over the first redistribution pattern, it is capable of reducing a length for signal transfer since the second redistribution pattern is used as an external connection terminal. It is also capable of processing data with high speed, as well as protecting the semiconductor chip having weak brittleness, since the semiconductor package is connected to the substrate without a separate solder ball.08-05-2010
20100221871Multi-Surface IC Packaging Structures and Methods for their Manufacture - An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.09-02-2010
20090186447PROCESS FOR SEALING AND CONNECTING PARTS OF ELECTROMECHANICAL, FLUID AND OPTICAL MICROSYSTEMS AND DEVICE OBTAINED THEREBY - A process for connecting two bodies forming parts of an electromechanical, fluid and optical microsystem, wherein a welding region is formed on a first body; an electrically conductive region and a spacing region are formed on a second body; the spacing region extends near the electrically conductive region and has a height smaller than the electrically conductive region. One of the first and second bodies is turned upside down on the other, and the two bodies are welded together by causing the electrically conductive region to melt so that it adheres to the welding region and collapses until its height becomes equal to that of the spacing region. Thereby it is possible to seal active parts or micromechanical structures with respect to the outside world, self-align the two bodies during bonding, obtain an electrical connection between the two bodies, and optically align two optical structures formed on the two bodies.07-23-2009
20090023244Etching/bonding chamber for encapsulated devices and method of use - A method for activating a getter at low temperature for encapsulation in a device cavity containing a microdevice comprises etching a passivation layer off the getter material while the device wafer and lid wafer are enclosed in a bonding chamber. A plasma etching process may be used, wherein by applying a large negative voltage to the lid wafer, a plasma is formed in the low pressure environment within the bonding chamber. The plasma then etches the passivation layer from the getter material, which is directly thereafter sealed within the device cavity of the microdevice, all within the etching/bonding chamber.01-22-2009
20130130440METHOD OF FABRICATING AND TRANSFERRING A MICRO DEVICE AND AN ARRAY OF MICRO DEVICES UTILIZING AN INTERMEDIATE ELECTRICALLY CONDUCTIVE BONDING LAYER - A method of fabricating and transferring a micro device and an array of micro devices to a receiving substrate are described. In an embodiment, an electrically insulating layer is utilized as an etch stop layer during etching of a p-n diode layer to form a plurality of micro p-n diodes. In an embodiment, an electrically conductive intermediate bonding layer is utilized during the formation and transfer of the micro devices to the receiving substrate.05-23-2013
20130130441CHIP-SCALE SEMICONDUCTOR DIE PACKAGING METHOD - A method of packaging one or more semiconductor dies includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame; attaching a lid to the chip-scale frame to form a substantially airtight chamber around the first die.05-23-2013
20100297811SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 11-25-2010
20100311205SEMICONDUCTOR DEVICE - The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved.12-09-2010
20100311206Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die - A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die.12-09-2010
20130143359SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME - A semiconductor device having a structure in which the structure is laminated in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the binding material of liquid state to the back surface of a semiconductor wafer by a spin coating method, this is dried and a solid-like adhesive layer is formed. Then, a semiconductor wafer is divided into each semiconductor chip by making the above-mentioned reforming area into a division origin. By pasting up this semiconductor chip on the main surface of the other semiconductor chip by the adhesive layer of the back surface, a semiconductor device having a structure in which the semiconductor device is laminated in many stages is manufactured.06-06-2013
20090068789MANUFACTURING PROCESS FOR A CHIP PACKAGE STRUCTURE - A manufacturing process for a chip package structure is provided. First, a patterned conductive layer and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned conductive layer such that the chips and the patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. A molding compound is formed to encapsulate the patterned conductive layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.03-12-2009
20090137083ASSEMBLING OF DOUBLED-SIDE STACKING PULRAL CHIPS - Disclosed is a method for assembling a semiconductor device, especially to dispose a plurality of chips on double sides of a chip carrier, such as a lead frame. At least a first chip is disposed on one surface of the chip carrier. Then, a protecting spacer is disposed on the active surface of the first chip. Then, the chip carrier is flipped over and placed on a hot plate where the protecting spacer keeps the active surface of the first chip away from direct contact with the hot plate. After the flipping and placing step, at least a second chip is disposed on another surface of the chip carrier and then is electrically connected to the chip carrier by a plurality of bonding wires. Therefore, any damages to the active surface of the first chip are avoided during disposition and electrical connections of the second chip.05-28-2009
20110008932METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - Provided is a semiconductor package and method of manufacturing same. The method includes: forming a plurality of semiconductor chips which have the same pattern direction on a semiconductor substrate, each of which includes a memory cell region, a peripheral region and a pad region, and in each of which the pad region is disposed in an edge region; separating the semiconductor chips, which are formed on the semiconductor substrate, from one another; and disposing semiconductor chips, which are selected from the separated semiconductor chips, on a package substrate by changing the pattern directions of the selected semiconductor chips and arranging pad regions of the selected semiconductor chips in a center region of the package substrate.01-13-2011
20110033975Semiconductor device and method for manufacturing the same - A semiconductor device includes: a semiconductor element having first and second surfaces, wherein the semiconductor element includes at least one electrode, which is disposed on one of the first and second surfaces; and first and second metallic layers, wherein the first metallic layer is disposed on the first surface of the semiconductor element, and wherein the second metallic layer is disposed on the second surface of the semiconductor element. The one electrode is electrically coupled with one of the first and second metallic layers, which is disposed on the one of the first and second surfaces. The one electrode is coupled with an external circuit through the one of the first and second metallic layers.02-10-2011
20110250721STACKED AND SHIELDED PACKAGES WITH INTERCONNECTS - Embodiments include methods for forming a stacked die package with a first die, first active circuitry on an upper surface of the first die, and a first conductive pattern on the first active circuitry. The stacked die package further includes a second die stacked over the first die, where the first die is wider than the second die in a cross-section of the stacked die package, and second active circuitry is present on an upper surface of the second die. The stacked die package further includes a mold compound disposed on the first die, where the mold compound encapsulates the second die. Electrical connections are formed from the top surface of the mold compound to the first conductive pattern and the second active circuitry, and a conductive pattern on the top surface of the mold compound provides a continuous electrical connection between upper ends of the electrical connections.10-13-2011
20110151621MICROFEATURE WORKPIECES HAVING INTERCONNECTS AND CONDUCTIVE BACKPLANES, AND ASSOCIATED SYSTEMS AND METHODS - Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a semiconductor substrate having integrated circuitry and terminals electrically coupled to the integrated circuitry. The device also includes electrically conductive interconnects extending through at least a portion of the semiconductor substrate and electrically coupled to corresponding terminals. The device further includes a conductive backplane assembly having a conductive layer at a back side of the semiconductor substrate. One or more of the interconnects are electrically coupled to the conductive layer at the back side of the semiconductor substrate.06-23-2011
20100062566Method of manufacturing stack-type semiconductor device and method of manufacturing stack-type electronic component - A first semiconductor element is bonded on a substrate. A complex film formed of integrated dicing film and adhesive film is affixed on a rear surface of a semiconductor wafer which is to be second semiconductor elements, the dicing film having a thickness within a range of not less than 50 μm nor more than 140 μm and a room temperature elastic modulus within a range of not less than 30 MPa nor more than 120 MPa, and the adhesive film having a thickness of 30 μm or more and a room temperature elastic modulus before curing within a range of not less than 500 MPa nor more than 1200 MPa. The semiconductor wafer together with the adhesive film is divided into the second semiconductor elements. The second semiconductor element is picked up from the dicing film to be bonded on the first semiconductor element.03-11-2010
20100062567Multi Layer Low Cost Cavity Substrate Fabrication for POP Packages - In a method and system for fabricating a semiconductor device (03-11-2010
20100055834SEMICONDUCTOR DEVICE MANUFACTURING METHOD - An improved method of manufacturing a semiconductor device. The resulting semiconductor device operates properly even when a plurality of semiconductor chips is mounted. One or more semiconductor chips are mounted on the bottom surface of a mounting substrate, the semiconductor chips are fixed to a supporting substrate with adhesive, and then the semiconductor chips are sealed with resin. Subsequently, another semiconductor chips are mounted on the top surface of the mounting substrate.03-04-2010
20100055837MULTI-CHIP MODULE AND METHODS - A substrate includes first and second regions over which first and second semiconductor devices are to be respectively positioned. The first region is located at least partially within the second region. Contact areas are located external to the first region but within the second region. In one embodiment, in which semiconductor devices are to be stacked over and secured to the substrate in a flip-chip type arrangement, the contact areas correspond to bond pads of an upper, second semiconductor device, while other contact areas located within the first region correspond to bond pads of a lower, first semiconductor device. In another embodiment, the contact areas correspond to bond pads of the first semiconductor device, which are electrically connected thereto by way of laterally extending discrete conductive elements, while other contact areas that are located external to the second region correspond to bond pads of the upper, second semiconductor device.03-04-2010
20110097847MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a microelectronic device includes a microelectronic die, a plurality of electrical couplers projecting from the die, and a flowable material disposed on the die. The die includes an integrated circuit and a plurality of terminals operably coupled to the integrated circuit. The electrical couplers are attached to corresponding terminals on the die. The flowable material includes a plurality of spacer elements sized to space the die apart from another component. The flowable material may be a no-flow underfill, a flux compound, or other suitable material.04-28-2011
20110097848Method for Connecting a Die Assembly to a Substrate in an Integrated Circuit and a Semiconductor Device Comprising a Die Assembly - A semiconductor device includes a substrate, a die assembly attachable to the substrate and a flexible strip extending over the substrate and the die assembly. The flexible strip has one or more routing circuits carried thereon. The die assembly and the substrate are arranged to be electrically connected through the one or more routing circuits carried on the flexible strip.04-28-2011
20110097846SEMICONDUCTOR CHIP, WAFER STACK PACKAGE USING THE SAME, AND METHODS OF MANUFACTURING THE SAME - A semiconductor chip comprises a substrate including a front surface and a rear surface, the substrate having a first via hole formed in the front surface and a second via hole formed in the rear surface, a first conductive plug formed on the substrate, the first conductive plug including a first portion formed in the first via hole and a second portion protruding from the front surface of the substrate, and a second conductive plug formed on the first conductive plug, the second conductive plug having a smaller cross-sectional area than the first conductive plug.04-28-2011
20100136744METHOD FOR MAKING SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING DIE AND INVERTED LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE - A method for making a multipackage module that has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.06-03-2010
20110250720THRU SILICON ENABLED DIE STACKING SCHEME - A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die.10-13-2011
20110097849MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED DEVICE - In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.04-28-2011
20100330742METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A first conductive member made of metal is provided over a first wiring substrate, which is a mounting substrate in the lower tier, a through hole is provided in a second wiring substrate, which is a mounting substrate in the upper tier, at a position corresponding to the first conductive member in a plan view, and a wiring is exposed at the sidewall of the through hole. The first conductive member is inserted into the through hole on the corresponding first wiring substrate side and the first wiring substrate and the second wiring substrate are electrically coupled by filling the through hole with a second conductive member. an electrode pad that is electrically coupled to the second conductive member and over which a semiconductor member in the upper tier is mounted is formed on the main surface side of the second wiring substrate.12-30-2010
20100297810Power Semiconductor Device and Method for Its Production - A power semiconductor device and a method for its production. The power semiconductor device has at least one power semiconductor chip, which has on its top side and on its back side large-area electrodes. The electrodes are electrically in connection with external contacts by means of connecting elements, the power semiconductor chip and the connecting elements being embedded in a plastic package. This plastic package has a number of layers of plastic, which are pressed one on top of the other and have plane-parallel upper sides. The connecting elements are arranged on at least one of the plane-parallel upper sides, between the layers of plastic pressed one on top of the other, as a patterned metal layer and are electrically in connection with the external contacts by means of contact vias through at least one of the layers of plastic.11-25-2010
20100112754METHODS FOR SECURING SEMICONDUCTOR DEVICES USING ELONGATED FASTENERS - Semiconductor device assemblies include elements such as electronic components and substrates secured together by a fastener that includes an elongated portion extending continuously through an aperture in two or more such elements. Computer systems include such semiconductor device assemblies. Fasteners for securing together such elements include an elongated portion, a first end piece, and a second end piece. Methods of securing together a plurality of semiconductor devices include inserting an elongated portion of a fastener through an aperture in a first semiconductor device and an aperture in at least one additional semiconductor device. Circuit boards include a plurality of apertures disposed in an array corresponding to an array of apertures in a semiconductor device assembly. Each aperture is sized and configured to receive a fastener for maintaining an assembled relationship between the semiconductor device assembly and the circuit board.05-06-2010
20100105168MICROELECRONIC ASSEMBLY AND METHOD FOR FORMING THE SAME - A microelectronic assembly and a method for forming a microelectronic assembly are provided. First and second substrates (04-29-2010
20100105167MEMS DEVICES AND METHODS OF ASSEMBLING MICRO ELECTROMECHANICAL SYSTEMS (MEMS) - A Micro ElectroMechanical Systems device according to an embodiment of the present invention is formed by dicing a MEMS wafer and attaching individual MEMS dies to a substrate. The MEMS die includes a MEMS component attached to a glass layer, which is attached to a patterned metallic layer, which in turn is attached to a number of bumps. Specifically, the MEMS component on the glass layer is aligned to one or more bumps using windows that are selectively created or formed in the metallic layer. One or more reference features are located on or in the glass layer and are optically detectable. The reference features may be seen from the front surface of the glass layer and used to align the MEMS components and may be seen through the windows and used to align the bumps. As an end result, the MEMS component may be precisely aligned with the bumps via optical detection of the reference features in the glass layer.04-29-2010
20100055833METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE IN WHICH FUNCTIONAL PORTION OF ELEMENT IS EXPOSED - A method of manufacturing a semiconductor device includes: forming a first resin layer on a wafer having a light receiving portion; patterning the first resin layer into a predetermined shape and forming a first resin film on the light receiving portion; dividing the wafer into light receiving elements; mounting the light receiving elements on an upper surface of a lead frame; a sealing step of forming a sealing resin layer around the first resin film; and removing the first resin film such that a portion of the light receiving element is exposed to the outside, and in the sealing step, the upper surface of the first resin film is flush with the upper surface of the sealing resin layer, or the upper surface of the first resin film is higher than the upper surface of the sealing resin layer.03-04-2010
20090317944MOLDED RECONFIGURED WAFER, STACK PACKAGE USING THE SAME, AND METHOD FOR MANUFACTURING THE STACK PACKAGE - A stack package includes at least two stacked package units. Each package unit comprises semiconductor chips having bonding pads on upper surfaces thereof; a molding part formed to surround side surfaces of the semiconductor chips; through-electrodes formed in the molding part; and re-distribution lines formed to connect the through-electrodes and adjacent bonding pads with each other.12-24-2009
20090215228WAFER LEVER FIXTURE AND METHOD FOR PACKAGING MICRO-ELECTRO-MECHANICAL-SYSTEM DEVICES - A fixture for packaging MEMS devices includes a base, a first material layer, an insulating layer and a second material layer. The base defines units, each including a notch. The first material layer is disposed on the base and the notches. The insulating layer is disposed on a part of the first material layer and exposes the other part of the first material layer located on the notches. The second material layer is disposed on the other part of the first material layer and formed with caps, whereby the caps are physically connected to the MEMS devices, and the MEMS devices are corresponding to the units of the base, wherein there is a first connecting force between the first and second material layers, there is a second connecting force between the caps and the MEMS devices, and the second connecting force is greater than the first connecting force.08-27-2009
20090148983Method of Manufacturing Flexible Semiconductor Assemblies - A method for producing flexible semiconductor assemblies is described. For example, an integrated circuit package consisting of an X-Y axes sensor die and a Z-axis sensor die disposed at 90 degrees to each other may be formed by applying a flexible dielectric membrane to a semiconductor wafer, creating bending gaps between the sensor dice, singulating the IC package from the wafer, and bending the flexible dielectric membrane so that the sensor dice are disposed orthogonally to each other. This method eliminates the need to precisely position previously singulated sensor dice relative to each other in order to apply a flexible dielectric membrane for purposes of interconnecting the dice.06-11-2009
20110177654Wafer-Level Semiconductor Device Packages with Three-Dimensional Fan-Out and Manufacturing Methods Thereof - In one embodiment, a method of forming a semiconductor device package includes: (07-21-2011
20120276690SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a method for manufacturing a semiconductor device, by which a transistor including an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating film therebetween is provided; an impurity is added to a part of a first region overlapped with the gate electrode with the gate insulating film therebetween in the active layer and a second region but the first region in the active layer by adding the impurity to the active layer from one oblique direction; and the second region is situated in the one direction relative to the first region.11-01-2012
20080268570FABRICATING PROCESS OF A CHIP PACKAGE STRUCTURE - A fabricating process of a chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the second substrate and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.10-30-2008
20110020982METHOD FOR BONDING OF CHIPS ON WAFERS - Method for bonding a plurality of chips onto a base wafer.01-27-2011
20110256662CHIP EMBEDDED SUBSTRATE AND METHOD OF PRODUCING THE SAME - A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.10-20-2011
20110136297INTEGRATED CIRCUIT CHIP THAT SUPPORTS THROUGH-CHIP ELECTROMAGNETIC COMMUNICATION - One embodiment of the present invention provides an integrated circuit chip, including an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The integrated circuit chip additionally comprises an electromagnetic via that facilitates communication between signal pads on the integrated circuit chip and signal pads on a second integrated circuit chip. The electromagnetic via couples a signal pad on the active face of the integrated circuit chip to the back face of the integrated circuit chip so that the integrated circuit chip can communicate with the second integrated circuit chip while the back face of the integrated circuit chip is adjacent to the active face of the second integrated circuit chip. Moreover, the electromagnetic via operates by facilitating non-conductive signaling through the integrated circuit chip.06-09-2011
20110076800MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The reliability of a semiconductor device is improved. A sealing resin (sealed body) is formed between a sub-substrate (first base member) and a base substrate (second base member) that are provided individually and distinctly to be integrated therewith, and then, the sub-substrate is electrically coupled to the second base member. As a means for electrically coupling the sub-substrate to the base substrate, lands (first lands) formed on the sub-substrate and lands (second lands) formed on the base substrate are disposed such that the respective positions thereof are aligned. After through holes are formed from the lands of the sub-substrate toward the lands of the base substrate, a solder member (conductive member) is formed in each of the through holes.03-31-2011
20090176331METHOD FOR PROCESSING A BASE - The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 07-09-2009
20090197369Multilayer substrate manufacturing method - A method for producing a multilayer substrate includes stacking a first substrate, the first substrate having a circuit pattern; stacking a connector, the connector coupling onto said first substrate, the connector having a ring structure, the ring structure having a plurality of holes separated a predetermined distance from one another; and stacking a second substrate, the second substrate coupling onto said first substrate by inserting said connector, the second substrate having a circuit pattern, the circuit pattern being electrically connected to a circuit pattern formed on said first substrate, the circuit pattern being electrically connected using the plurality of holes formed on said connector. The method of producing a multilayer substrate can shield the EMI generated by a high-speed switching element.08-06-2009
20120309128DISABLING ELECTRICAL CONNECTIONS USING PASS-THROUGH 3D INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS - Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.12-06-2012
20110189820METHOD OF MANUFACTURING LAYERED CHIP PACKAGE - In a method of manufacturing a layered chip package, a layered substructure is fabricated and used to produce a plurality of layered chip packages. The layered substructure includes first to fourth substructures stacked, each of the substructures including an array of a plurality of preliminary layer portions. In the step of fabricating the layered substructure, initially fabricated are first to fourth pre-polishing substructures each having first and second surfaces. Next, the first and second pre-polishing substructures are bonded to each other with the first surfaces facing each other, and then the second surface of the second pre-polishing substructure is polished to form a first stack. Similarly, the third and fourth pre-polishing substructures are bonded to each other and the second surface of the third pre-polishing substructure is polished to form a second stack. Then, the first and second stacks are bonded to each other.08-04-2011
20110189821SEMICONDUCTOR DEVICE - A semiconductor device and method is disclosed. One embodiment provides a method comprising placing a first semiconductor chip on a carrier. After placing the first semiconductor chip on the carrier, an electrically insulating layer is deposited on the carrier. A second semiconductor chip is placed on the electrically insulating layer.08-04-2011
20100029043PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member and at least one die in a stacked configuration attached to the support member. The support member may include a leadframe disposed longitudinally between first and second ends and latitudinally between first and second sides. The leadframe includes a lead extending between the first end and the first side.02-04-2010
20110070696FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.03-24-2011
20110070695METHOD OF FABRICATING A HIGH-TEMPERATURE COMPATIBLE POWER SEMICONDUCTOR MODULE - The invention relates to a method for fabricating a high-temperature compatible power semiconductor module in which a power semiconductor chip is bonded by means of a diffusion solder layer to a substrate and said substrate is bonded by means of silver sintered layer to a base plate, after which a bonding element is bonded to the top chip metallization. To prevent oxidation of the predefined bond area when producing the diffusion solder layer and the sintered silver layer 03-24-2011
20120302006DISTRIBUTED SEMICONDUCTOR DEVICE METHODS, APPARATUS, AND SYSTEMS - Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.11-29-2012
20120040497PANELIZED BACKSIDE PROCESSING FOR THIN SEMICONDUCTORS - A semiconductor manufacturing method includes attaching a first die to a substrate panel. The method also includes applying a mold compound after attaching the first die to the substrate panel to the first die and the substrate panel. The method further includes thinning the first die and the mold compound after applying the mold compound. Attaching the die to the substrate panel before thinning eliminates usage of a carrier wafer when processing thin semiconductors.02-16-2012
20100105169SEMICONDUCTOR CHIP HAVING VIA ELECTRODES AND STACKED SEMICONDUCTOR CHIPS INTERCONNECTED BY THE VIA ELECTRODES - A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.04-29-2010
20120045869FLIP CHIP BONDER HEAD FOR FORMING A UNIFORM FILLET - A low thermal conductivity material layer covers a peripheral portion of the bottom surface of the conductive plate of a chip bonder head. The center portion of the conductive plate is exposed or covered with another conductive plate laterally surrounded by the low thermal conductivity material layer. During bonding, the chip bonder head holds a first substrate upside down and heats the first substrate through the conductive plate. Heating of a fillet, i.e., the laterally extruding portion, of a pre-applied underfill material is reduced because the temperature at the exposed surfaces of the low thermal conductivity material layer is lower than the temperature at the bottom surface of the conductive plate. The longer curing time and the more uniform shape of the fillet in the bonded structure enhance the structural reliability of the bonded substrates.02-23-2012
20120003792STACKED DIE PACKAGE - The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed.01-05-2012
20120009735METHOD FOR PACKAGING SEMICONDUCTORS AT WAFER LEVEL - A method for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: lithographically forming, in a first lithographically processable material disposed on the surface portion of the semiconductor wafer, device exposing openings to expose the devices and electrical contact pad openings to expose electrical contact pads for devices; and mounting a support having a rigid dielectric layer formed on a selected portion of the support, such rigid dielectric layer comprising a second lithographically processable material, such rigid material being suspended over the device exposing openings and removed from portions of the support disposed over the electrical contacts pads openings in the first lithographically processable material. The support is released and removed from the second lithographically processable material, leaving the second photolithographically processable material bonded to the first photolithographically processable material.01-12-2012
20120009734SEMICONDUCTOR DEVICE ASSEMBLY AND METHOD THEREOF - A semiconductor device assembly includes a first semiconductor die, a second semiconductor die, at least one semiconductor package component or another semiconductor die, a first conductive element and a second conductive element. The first semiconductor die includes at least one bonding pad. The second semiconductor die includes a bonding pad module. The first conductive element is coupled between the bonding pad module of the second semiconductor die and the bonding pad of the first semiconductor die, and the second conductive element is coupled between the bonding pad module of the second semiconductor die and the semiconductor package component or the another semiconductor die, wherein the first semiconductor die is coupled to the semiconductor package component or the another semiconductor die via the bonding pad and the bonding pad module and the first and second conductive elements.01-12-2012
20120009732SYSTEM-IN-A-PACKAGE BASED FLASH MEMORY CARD - A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.01-12-2012
20110165731Method for Fabricating Array-Molded Package-on-Package - An improved semiconductor device package is manufactured by attaching semiconductor chips (07-07-2011
20110165729METHOD OF PACKAGING SEMICONDUCTOR DEVICE - Quad Flat No-Lead packaged devices are manufactured using two singulation operations with two different saw blades of varying widths with the first singulation operation using a wider saw blade than the second singulation operation. Between singulation operations, the exposed portions of the leads are plated with a solderable metal. By performing the second singulation operation within the first cut made by the first singulation, at least half of the exposed metal of the leads remains plated. Thus, better solder joints may be formed, which allows for simpler visual inspection.07-07-2011
20120021562METHOD FOR FORMING TERMINAL OF STACKED PACKAGE ELEMENT AND METHOD FOR FORMING STACKED PACKAGE - A semiconductor chip module having high degree of freedom in assignment of a circuit to each semiconductor chip and in position of a connection terminal of each semiconductor chip is provided. The present invention relates to a semiconductor chip module in which a plurality of semiconductor chips, each provided on the side face thereof with a part of a connection terminal coupled with a circuit pattern formed on the front face, have been stacked and bonded. Connection terminal portions on the side faces of the respective semiconductor chips are interconnected by a wiring pattern. The connection terminal on the semiconductor chip is led from the front face to the side face and formed by applying spraying of a conductive material in a mist state.01-26-2012
20120058603FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.03-08-2012
20120064667SEMICONDUCTOR DIE PACKAGE INCLUDING MULTIPLE DIES AND A COMMON NODE STRUCTURE - A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.03-15-2012
20120208319Packaged Semiconductor Device with Encapsulant Embedding Semiconductor Chip that Includes Contact Pads - A method of manufacturing a semiconductor package includes embedding a semiconductor chip in an encapsulant. First contact pads are formed on a first main face of the semiconductor package and second contact pads are formed on a second main face of the semiconductor package opposite the first main face. A diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d≧(8/25)x+142 μm, where x is a pitch of the second contact pads in micrometers.08-16-2012
20120108008ELECTRODE CONNECTION STRUCTURE OF SEMICONDUCTOR CHIP, CONDUCTIVE MEMBER, AND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.05-03-2012
20110065239METHOD OF FABRICATING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PRODUCTION EQUIPMENT - A present embodiment provides a method of fabricating a semiconductor device includes tentatively compressing a second electrode formed on a second semiconductor chip in a substrate to a first electrode on a first semiconductor chip, at least one of the first electrode and the second electrode being constituted with a metal protrusion, and fixedly compressing between the first electrode and the second electrode.03-17-2011
20110065238PROTECTION LAYER FOR ADHESIVE MATERIAL AT WAFER EDGE - A wafer is attached to a carrier by using an adhesive layer, and a portion of the adhesive layer is exposed adjacent to an edge of the wafer. After thinning the wafer, a protection layer is provided to cover the exposed portion of the adhesive layer. A plurality of dies is bonded onto the thinned wafer, and then the thinned wafer and the dies are encapsulated with a molding compound.03-17-2011
20120252165METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for forming a semiconductor device includes the following processes. A first semiconductor chip and a second semiconductor chip are stacked to form a stacked structure. A gap between the first and second semiconductor chips of the stacked structure is filled with a filler. A temperature of the stacked first and second semiconductor chips is kept more than room temperature from the stacking to the filing.10-04-2012
20120252164METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a semiconductor device which includes: providing a plurality of semiconductor substrates formed with through holes which penetrate between main surfaces of the substrates and are filled with porous conductors; stacking the plurality of semiconductor substrates while aligning the porous conductors filled in the through holes; introducing conductive ink containing particle-like conductors into the porous conductors of the plurality of stacked semiconductor substrates; and sintering the plurality of stacked semiconductor substrates.10-04-2012
20120252162METHODS FOR BONDING SEMICONDUCTOR STRUCTURES INVOLVING ANNEALING PROCESSES, AND BONDED SEMICONDUCTOR STRUCTURES FORMED USING SUCH METHODS - Methods of bonding together semiconductor structures include annealing a first metal feature on a first semiconductor structure, bonding the first metal feature to a second metal feature of a second semiconductor structure to form a bonded metal structure that comprises the first metal feature and the second metal feature, and annealing the bonded metal structure. Annealing the first metal feature may comprise subjecting the first metal feature to a pre-bonding thermal budget, and annealing the bonded metal structure may comprise subjecting the bonded metal structure to a post-bonding thermal budget that is less than the pre-bonding thermal budget. Bonded semiconductor structures are fabricated using such methods.10-04-2012
20120252163STACKED PACKAGE, METHOD OF FABRICATING STACKED PACKAGE, AND METHOD OF MOUNTING STACKED PACKAGE FABRICATED BY THE METHOD - Provided are a stacked package, method of fabricating a stacked package, and method of mounting a stacked package. A method includes providing an upper semiconductor package including an upper package substrate, upper semiconductor chips formed on a top surface of the upper package substrate, and first solders formed on a bottom surface of the upper package substrate and having a first melting temperature, providing a lower semiconductor package including a lower package substrate, lower semiconductor chips formed on a top surface of the lower package substrate, and solder paste nodes formed on the top surface of the lower package substrate and having a second melting temperature lower than the first melting temperature, and forming inter-package bonding units by attaching respective first solders and solder paste nodes to each other by performing annealing at a temperature higher than the second melting temperature and lower than the first melting temperature.10-04-2012
20110104852SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.05-05-2011
20120122278Method Of Manufacturing Semiconductor Package Board - Disclosed herein is a method of method of manufacturing a semiconductor package board, including: providing a substrate including a connection part formed on one side thereof, the connection part being provided thereon with a solder layer; disposing a conductive heat generator equipped with current wiring on the solder layer; applying current to the current wiring and thus heating the solder layer to attach a semiconductor chip to the connection part; and removing the current wiring from the conductive heat generator. The method is advantageous in that the semiconductor chip is attached to the substrate by applying current to the current wiring of the conductive heat generator to locally heat only the solder layer, thus reducing thermal stress and preventing the deformation of the substrate.05-17-2012
20090130798Process for Making a Semiconductor System - Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device.05-21-2009
20120214277SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is disclosed. One embodiment includes placing multiple semiconductor chips onto a carrier, each of the semiconductor chips having a first face and a second face opposite to the first face. An encapsulation material is applied over the multiple semiconductor chips and the carrier to form an encapsulating body having a first face facing the carrier and a second face opposite to the first face. A redistribution layer is applied over the multiple semiconductor chips and the first face of the encapsulating body. An array of external contact elements are applied to the second face of the encapsulating body.08-23-2012
20100210071METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device. The method includes providing a metal carrier, attaching chips to the carrier, and applying a metal layer over the chips and the metal carrier to electrically couple the chips to the metal carrier. The metal carrier is segmented, after applying the metal layer, to obtain metal contact elements.08-19-2010
20120135566Monolithic Integration Of Photonics And Electronics In CMOS Processes - Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices with at least a portion of each of the wafers bonded together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.05-31-2012
20120135565METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING FILLING GAP BETWEEN SUBSTRATES WITH MOLD RESIN - A method of manufacturing a semiconductor device in one exemplary embodiment includes preparing a first substrate and a second substrate, the first substrate including a bump electrode group formed of bump electrodes arrayed with a certain pitch, the number of bump electrodes along a first direction being larger than the number of bump electrodes along a second direction perpendicular to the first direction; joining the first substrate and the second substrate to each other through the bump electrodes so that a gap is formed between the first substrate and the second substrate; and filling the gap with a mold resin by causing the mold resin to flow in the gap from an edge of the first substrate along the second direction of the bump electrode group.05-31-2012
20100178731SEMICONDUCTOR DEVICE HAVING A PLURALITY OF SEMICONDUCTOR CONSTRUCTS - A semiconductor device includes a plurality of semiconductor constructs, each of the semiconductor constructs including a semiconductor substrate and external connection electrodes provided on an upper surface of the semiconductor substrate. The semiconductor substrates of the semiconductor constructs are different in a planar-size. The plurality of semiconductor constructs are stacked from bottom to top in descending order of planar-sizes of the semiconductor substrates included in the plurality of semiconductor constructs. An insulating film at least is provided around one semiconductor construct disposed on the top of the plurality of semiconductor constructs and on another semiconductor construct disposed under the one semiconductor construct. Each of the upper surfaces of the plurality of external connection electrodes is exposed from the one semiconductor construct and from the insulating film.07-15-2010
20120171817SINGLE DIE OUTPUT POWER STAGE USING TRENCH-GATE LOW-SIDE AND LDMOS HIGH-SIDE MOSFETS, STRUCTURE AND METHOD - A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit.07-05-2012
20120171816INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME - An integrated circuit package includes a first dielectric layer comprising a dielectric film having a first side and a second side, the first side having a plurality of contact locations and a plurality of non-contact locations. The package includes a plurality of components, each component having a first surface and a second surface, wherein the first surface of each of the plurality of components is affixed to a corresponding one of the plurality of contact locations of the dielectric film absent a layer of adhesive therebetween that is distinct from a material of the dielectric film.07-05-2012
20120171815CVD APPARATUS AND METHOD OF FORMING SEMICONDUCTOR SUPERLATTICE STRUCTURE USING THE SAME - Provided is a chemical vapor deposition (CVD) apparatus, including: a reaction chamber including an inner pipe having an internal space, and an external pipe configured to cover the inner pipe so as to maintain a sealing state thereof; a wafer holder disposed within the inner pipe and receiving a plurality of wafers stacked therein; and a gas supplier including at least one stem pipe disposed at the outside of the reaction chamber so as to supply a reactive gas thereto, a plurality of branch pipes connected to the stem pipe to introduce the reactive gas from the outside of the reaction chamber into the reaction chamber, and a plurality of spray nozzles provided with the branch pipes to spray the reactive gas to the plurality of respective wafers.07-05-2012
20120171818HYBRID BONDING INTERFACE FOR 3-DIMENSIONAL CHIP INTEGRATION - Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.07-05-2012
20120077311SEMICONDUCTOR PACKAGE HAVING BURIED POST IN ENCAPSULANT AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body. The semiconductor package includes a post within the first insulating body and adjacent to a side of the first semiconductor chip.03-29-2012
20120171814SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME - Provided are a semiconductor package and a method of fabricating the same. In one embodiment, to fabricate a semiconductor package, a wafer having semiconductor chips fabricated therein is provided. A heat sink layer is formed over the wafer. The heat sink layer contacts top surfaces of the semiconductor chips. Thereafter, the plurality of semiconductor chips are singulated from the wafer.07-05-2012
20120220079METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a method for manufacturing a semiconductor device, an opening formed in a semiconductor substrate by using a mask and covering an inner side face of the opening with a sidewall protective film. The mask is removed, while a part of the sidewall protective film remains.08-30-2012
201000479643D INTEGRATED CIRCUIT DEVICE FABRICATION USING INTERFACE WAFER AS PERMANENT CARRIER - A method is provided for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer. Also provided is a tangible computer readable medium encoded with a program that comprises instructions for performing such a method.02-25-2010
20100047965FABRICATING METHOD OF PACKAGING STRUCTURE - A fabricating method of packaging structure is provided. First, a capacitive element is formed. Then, a first dielectric layer is formed on a first electronic component by performing a build-up process, an interconnection is formed in the first dielectric layer, and a plurality of contacts are formed on the upper and lower surfaces of the first dielectric layer, wherein the capacitive element is embedded in the first dielectric layer during the fabrication of the interconnection and the capacitive element is electrically connected to the corresponding contacts through the interconnection. A second electronic component is disposed on the first dielectric layer, wherein the second electronic component is electrically connected to the corresponding contacts.02-25-2010
20100047962MULTI-CHIP PRINTHEAD ASSEMBLER - The invention relates to an assembler for assembling printhead integrated circuitry on a carrier. The assembler includes a support assembly, a wafer positioning assembly arranged on the support assembly and configured to retain and position a wafer defining a plurality of die to be picked from the wafer; and a die picking assembly arranged on the support assembly and configured to pick a pre-selected dice from the wafer. The assembler also includes a die placement assembly arranged on the support assembly and configured to receive the pre-selected dice and to place the dice on the carrier, and a die conveyance mechanism arranged on the support assembly and configured to convey the dice from the die picking assembly to the die placement assembly. Further included is a control system operatively engaged with the wafer positioning, die picking, die placement and die conveyance assemblies to control operation thereof.02-25-2010
20100273294Compact Co-packaged Semiconductor Dies with Elevation-adaptive Interconnection Plates - A semiconductor package is disclosed for packaging two adjacent semiconductor dies atop a circuit substrate. The dies are separated from each other along their longitudinal edges with an inter-die distance. An elevation-adaptive electrical connection connects a top metalized contact of die two to the bottom surface of die one while accommodating for elevation difference between the surfaces. The elevation-adaptive electrical connection includes: 10-28-2010
20090093084Die offset die to bonding - A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge of the die extends beyond the second edge of the spacer. Furthermore, a first semiconductor die has a plurality of bond pads thereon, a second semiconductor die has a plurality of bond pads thereon, and a substrate has a plurality of bond pads thereon. Each of a first plurality of wires connects a bond pad on the first semiconductor die with a bond pad on the second semiconductor die, and each of a second plurality of wires connects a bond pad on the second semiconductor die with a bond pad on the substrate.04-09-2009
20100009498PLANAR INTERCONNECT STRUCTURE FOR HYBRID CIRCUITS - Described herein is an electronic device in which one or more planar interconnect structure are interposed between two substrates each incorporating a hybrid circuit. The planar interconnect structure has a plurality of conductive traces formed on one of its faces for electrically connecting sets of interconnection points of each of the hybrid circuits.01-14-2010
20120238057Approach for Bonding Dies onto Interposers - A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.09-20-2012
20120238056MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The formation of a void is suppressed in the assembly of a semiconductor device. An MCU chip and an AFE chip are mounted over a die pad formed of a quadrangle having a pair of first sides and a pair of second sides. After wire bonding is carried out on the MCU chip and the AFE chip, resin is supplied from the side of one second side of the two second sides to the side of the other second side. The resin is thereby passed through the opening between a first pad group and a second pad group over the MCU chip to fill the area between the chips and thus the formation of a void is suppressed in the area between the chips.09-20-2012
20100291734Semiconductor Device with an Improved Solder Joint - A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA of the Periodic Table of the Elements. The solder joint system also includes, between the pads and the solder, layers of intermetallic compounds, which include grains of copper and tin compounds and copper, silver, and tin compounds. The compounds contain the transition metals. The inclusion of the transition metals in the compound grains reduce the compound grains size and prevent grain size increases after the solder joint undergoes repeated solid/liquid/solid cycles.11-18-2010
20100291733SEMICONDUCTOR PACKAGE WITH IMPROVED SIZE, RELIABILITY, WARPAGE PREVENTION, AND HEAT DISSIPATION AND METHOD FOR MANUFACTURING THE SAME - The semiconductor package includes a semiconductor package module with circuit patterns formed on an insulation substrate, at least two semiconductor chips electrically connected to each of the circuit patterns using bumps, and an insulation member filled in any open space in the semiconductor module. A cover plate is formed on the upper portion of the semiconductor package module, and a penetration electrode penetrates the semiconductor package. The penetration electrode is electrically connected to the circuit patterns. The described semiconductor package improves upon important characteristics such as size, reliability, warpage prevention, and heat dissipation.11-18-2010
20100291736STACKING MULTIPLE DEVICES USING SINGLE-PIECE INTERCONNECTING ELEMENT - An embodiment of the present invention is a technique to stack multiple devices using an interconnecting element. A board has a periphery and top and bottom surfaces. The top surface has top contact pads to attach to a first device. The bottom surface is milled down to form a cavity confined by vertical walls around the periphery. The cavity fits a second device. Bottom contact pads are formed on bottom side of the vertical walls. The bottom contact pads are raised with respect to the bottom side of the vertical walls. Traces internal to the board connect the bottom contact pads to the top contact pads.11-18-2010
20100291732Manufacturing method for electronic devices - A manufacturing method for an electronic device joining a first metallic bond part formed on a first electronic component and a second metallic bond part formed on a second electronic component includes a first process for placing the first metallic bond part directly against the second metallic bond part, applying pressure to the first electronic component and the second electronic component, joining the first metallic bond part to the second metallic bond part with solid-phase diffusion, and releasing the applied pressure, and a second process for heating the first electronic component and the second electronic component at a predetermined temperature such that the first metallic bond part and the second metallic bond part are joined together by melting the first metallic bond part and the second metallic bond part.11-18-2010
20120258571METHOD FOR FABRICATING A SEMICONDUCTOR AND SEMICONDUCTOR PACKAGE - A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.10-11-2012
20110124156Method of Fabricating Semiconductor Die with Through-Hole Via on Saw Streets and Through-Hole Via in Active Area of Die - A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. Metal vias are also formed through the contact pads on the active area of the die. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. Repassivation layers are formed between the RDL for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The vias through the saw streets and vias through the active area of the die, as well as the RDL, provide electrical interconnect to the adjacent die.05-26-2011
20110124155HYBRID STRUCTURE OF MULTI-LAYER SUBSTRATES AND MANUFACTURE METHOD THEREOF - A hybrid structure of multi-layer substrates comprises a first multi-layer substrate and a second multi-layer substrate. The first multi-layer substrate stacks up first metal layers, first dielectric layers alternately and has VIAs. A border district of a first metal layer connects with a border district of the corresponding first dielectric layer. The border districts are separated from adjacent first metal layers and adjacent first dielectric layers. The second multi-layer substrate stacks up second metal layers and second dielectric layers alternately. A border district of a second metal layer connects with a border district of the corresponding second dielectric layer. The border districts are separated from adjacent second metal layers and adjacent second dielectric layers. The VIAs are located at the border districts of the first dielectric layers and each VIA has electric conductor therein to connect one first metal layer with one second metal layer.05-26-2011
20110124154HYBRID STRUCTURE OF MULTI-LAYER SUBSTRATES AND MANUFACTURE METHOD THEREOF - A hybrid structure of multi-layer substrates comprises a first multi-layer substrate and a second multi-layer substrate. The first multi-layer substrate stacks up first metal layers, first dielectric layers alternately and has VIAs. A border district of a first metal layer connects with a border district of the corresponding first dielectric layer. The border districts are separated from adjacent first metal layers and adjacent first dielectric layers. The second multi-layer substrate stacks up second metal layers and second dielectric layers alternately. A border district of a second metal layer connects with a border district of the corresponding second dielectric layer. The border districts are separated from adjacent second metal layers and adjacent second dielectric layers. The VIAs are located at the border districts of the first dielectric layers and each VIA has electric conductor therein to connect one first metal layer with one second metal layer.05-26-2011
20120231582DEVICE INCLUDING A SEMICONDUCTOR CHIP - A device including a semiconductor chip and method. One embodiment provides a method of manufacturing a module, including providing a first device having a first semiconductor chip and a plurality of first external contact elements electrically coupled to the first semiconductor chip. The method further includes providing a second device having a second semiconductor chip, a plurality of second external contact elements and a metal layer including a first face and a second face opposite to the first face, the first face of the metal layer facing the second semiconductor chip and the second face of the metal layer facing the plurality of second external contact elements. The first external contact elements are soldered to the first face of the metal layer.09-13-2012
20080299704INTEGRATED CIRCUIT DIE WITH LOGICALLY EQUIVALENT BONDING PADS - An integrated circuit (IC) die includes two bonding pads, that share a common logical function, such as signal input or signal output, separated by the width of the die, and preferably on opposite sides of the die. System-in-package devices are produced by steps including directly electrically connecting one or the other bonding pad to bonding pads of other, functionally different IC dies, with the bonding pads of the other IC dies, to which are connected bonding pads of common logical function of the IC dies of the present invention, being functionally identical but geometrically different. Multchip package devices are produced by stacking the IC dies of the present invention with other IC dies and directly electrically connecting one or the other bonding pad to different bonding pads of the other IC dies.12-04-2008
20120264256METHOD AND SYSTEM FOR TEMPLATE ASSISTED WAFER BONDING - A method of fabricating a composite semiconductor structure includes providing a substrate including a plurality of devices and providing a compound semiconductor substrate including a plurality of photonic devices. The method also includes dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method further includes providing an assembly substrate, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, aligning the substrate and the assembly substrate, joining the substrate and the assembly substrate to form a composite substrate structure, and removing at least a portion of the assembly substrate from the composite substrate structure.10-18-2012
20110003431METHOD OF DIE REARRANGEMENT PACKAGE STRUCTURE HAVING PATTERNED UNDER BUMP METALLURGIC LAYER CONNECTING METAL LEAD - A die rearrangement package structure is provided and includes a die; an encapsulated structure is covered around the four sides of the die to expose the active surface and the reverse side of the die; a patterned protective layer is formed on the encapsulated structure and the active surface of the die, and the pads is to be exposed; one end of fan-out patterned metal layer is electrically connected the pads and other end is extended to cover the patterned protective layer; patterned second protective layer is provided to cover the patterned metal layer to expose the portions surface of the patterned metal layer; patterned UBM layer is formed on the exposed surface of the patterned metal layer; and a conductive component is formed on the patterned UBM layer, and electrically connected the patterned metal layer.01-06-2011
20110033976SELF-ASSEMBLY OF CHIPS ON A SUBSTRATE - A method of forming, on a surface of a substrate, at least one hydrophilic attachment area for the purpose of self-assembling a component or a chip, in which a hydrophobic area, which delimits the hydrophilic attachment area, is produced.02-10-2011
20120270367Component Stacking for Integrated Circuit Electronic Package - Component stacking for increasing packing density in integrated circuit packages. In one aspect of the invention, an integrated circuit package includes a substrate, and a plurality of discrete components connected to the substrate and approximately forming a component layer parallel to and aligned with a surface area of the substrate. An integrated circuit die is positioned adjacent to the component layer such that a face of the die is substantially parallel to the surface area of the substrate. The face of the die is aligned with at least a portion of the component layer, and terminals of the die are connected to the substrate.10-25-2012
20120322202SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device includes a supporting board, a first semiconductor element mounted on a main surface of the supporting board; and an electronic component provided between the supporting board and the first semiconductor element; wherein the supporting board includes a concave part formed in a direction separated from the first semiconductor element; and at least a part of the electronic component is accommodated in the concave part.12-20-2012
20120322203METHOD TO CONSTRUCT SYSTEMS - A method to construct first and second configurable systems including: providing a first configurable system including a first die and a second die, where the first die is diced from a first wafer and the second die is diced from a second wafer and the first die is connected to the second die using at least one through-silicon-via (TSV); providing a second configurable system including a third die and a fourth die, where the third die is diced from a third wafer and the fourth die is diced from a fourth wafer and the third die is connected to the fourth die using at least one through-silicon-via (TSV); where processing the first wafer and the third wafer utilizes a majority of masks that are substantially same; and where the first die is larger than the third die.12-20-2012
20110129960Method of manufacturing stacked wafer level package - A method of manufacturing a stacked wafer level package includes: preparing a substrate; forming a conductive layer on the substrate; forming chip connection pads and internal connection pads on the conductive layer; forming solder balls connected to the internal connection pads; mounting a semiconductor chip on the conductive layer to be connected to the chip connection pads; forming a sealing member to seal the solder balls and the semiconductor chip; separating the substrate from the conductive layer; forming a rearrangement wiring layer by etching the conductive layer; forming an external connection on the rearrangement wiring layer; forming contact holes in the sealing member to expose the solder balls; and stacking an electronic component to be electrically connected to the solder balls exposed through the contact holes.06-02-2011
20110237026METHOD OF FORMING A MULTI-CHIP STACKED STRUCTURE INCLUDING A THIN INTERPOSER CHIP HAVING A FACE-TO-BACK BONDING WITH ANOTHER CHIP - A temporary substrate having an array of first solder pads is bonded to the front side of a first substrate by reflowing an array of first solder balls. The first substrate is thinned by removing the back side, and an array of second solder pads is formed on the back side surface of the first substrate. The assembly of the first substrate and the temporary substrate is diced to form a plurality of stacks, each including an assembly of a first semiconductor chip and a handle portion. A second semiconductor chip is bonded to an assembly through an array of the second solder balls. The handle portion is removed from each assembly by reflowing the array of the first solder balls, while the array of the second solder balls does not reflow. The assembly is subsequently mounted on a packaging substrate employing the array of the first solder balls.09-29-2011
20120094435METHOD OF FABRICATION OF AI/GE BONDING IN A WAFER PACKAGING ENVIRONMENT AND A PRODUCT PRODUCED THEREFROM - A method of bonding of germanium to aluminum between two substrates to create a robust electrical and mechanical contact is disclosed. An aluminum-germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between two substrates; (3) it can be patterned so that this conduction path is localized; (4) the bond can be made with the aluminum that is available as standard foundry CMOS process. This has the significant advantage of allowing for wafer-level bonding or packaging without the addition of any additional process layers to the CMOS wafer.04-19-2012
20100233850Method for Bonding Wafers to Produce Stacked Integrated Circuits - A basic building block for wafer scale stacked integrated circuits is disclosed. The building block includes an integrated circuit device having an integrated circuit substrate having a circuit layer sandwiched between a buffer layer and a dielectric layer. The dielectric layer has a top side and a bottom side, the bottom side being in contact with the circuit layer. The top surface of the dielectric layer includes a plurality of pads. Each pad extends above the top surface by a predetermined distance. The pads have dimensions that reduce irregularities in the top surface of the pads. In addition, the pads are arranged in a manner to promote planarization of the surface of the wafer via CMP.09-16-2010
20120322204SEMICONDUCTOR ELEMENT AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes preparing a semiconductor element including a main surface over which a wiring layer is formed, forming a seed layer over the main surface, forming a resist layer over the main surface such that the resist layer covers the seed layer, removing a part of the resist layer by exposing and developing the resist layer, in which a part of the wiring layer is exposed from the removed part of the resist layer, forming a plurality of conductive posts electrically connected to the wiring layer at the removed part of the resist layer, forming a solder layer at each top of the plurality of conductive posts, removing a residual resist layer over the main surface, removing an area other than an area which overlaps with the seed layer, and melting the solder layer and forming a surface shape.12-20-2012
20120322201STACKED SEMICONDUCTOR PACKAGE AND STACKING METHOD THEREOF - A stacked semiconductor package technique applicable to semiconductor chips having pins short enough that the semiconductor chips cannot be directly bonded together is provided. A printed circuit board (PCB) is inserted into a space between pins of an upper semiconductor chip and the exterior of bodies of stacked semiconductor chips. The PCB includes a plurality of conductive patterns at locations corresponding to the respective pins. The respective conductive patterns and the corresponding respective pins of the upper and lower semiconductor chips are bonded together. The PCB includes a plurality of recess patterns on one side, the recess patterns having the same pitch as the pins of the semiconductor chips. The PCB is disposed across the pins of the lower semiconductor chip, and thereby easily arranged with the stacked semiconductor chips.12-20-2012
20120329211FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.12-27-2012
20120288995Semiconductor Wafer Bonding Incorporating Electrical and Optical Interconnects - Methods for bonding semiconductor wafers requiring the transfer of electrical and optical signals between the bonded wafers and across the bonding interface. The methods incorporate the formation of both electrical and optical interconnect vias within the wafer bonding interface to transfer electrical and optical signals between the bonded wafers. The electrical vias are formed across the bonding surface using multiplicity of metal posts that are interfused across the bonding surface. The optical vias are formed across the bonding surface using multiplicity of optical waveguides each comprised of a dielectric material that interfuses across the bonding interface and having an index of refraction that is higher than the index of refraction of the dielectric intermediary bonding layer between the bonded wafers. The electrical and optical vias are interspersed across the bonding surface between the bonded wafers to enable uniform transfer of both electrical and optical signals between the bonded wafers.11-15-2012
20100167465MULTIPHASE SYNCHRONOUS BUCK CONVERTER - Disclosed in this specification is a multiphase buck converter package and process for forming such package. The package includes at least four dies and at least nine parallel leads. The dies are electrically connected through a plurality of die attach pads, thus eliminating the need for wirebonding.07-01-2010
20130011964THERMAL ENHANCED PACKAGE - A method of manufacturing an integrated circuit package. The method includes attaching a first surface of a semiconductor die to a thermally and/or electrically conductive substrate, forming a plurality of die connectors on a second surface of the semiconductor die, and encapsulating the semiconductor die and the plurality of die connectors in an encapsulant material. The method also includes removing a portion of the encapsulant material to expose one or more of the plurality of die connectors, thereby forming a routing surface. The method further includes forming a plurality of conductive traces on the routing surface. Each of the plurality of conductive traces is characterized by a first portion in electrical communication with one of the plurality of die connectors and a second portion in electrical communication with a package connector.01-10-2013
20130011966STACKABLE SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING SUCH ASSEMBLIES - Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die.01-10-2013
20130011967SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.01-10-2013
20100129960METHOD FOR BONDING SEMICONDUCTOR WAFERS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a method for bonding semiconductor wafers of the present invention, a bonding layer containing a flux-active curing agent and a thermosetting resin is interposed between a first semiconductor wafer and a second semiconductor wafer, thereby producing a semiconductor wafer stacked body in which the first and second semiconductor wafers are stacked together, and then the semiconductor wafer stacked body is compressed in a thickness direction thereof while heating it so that the first and second semiconductor wafers are fixed together by melting and solidifying solder bumps while curing the thermosetting resin, thereby producing a semiconductor wafer bonded body in which first connector portions and second connector portions are electrically connected together through solidified products obtained by melting and solidifying the solder bumps.05-27-2010
20120149149FOUR MOSFET FULL BRIDGE MODULE - A molded, leadless packaged semiconductor multichip module includes 06-14-2012
20120149148METHOD AND SYSTEM FOR TEMPLATE ASSISTED WAFER BONDING - A method of fabricating a composite semiconductor structure includes providing an SOI substrate including a plurality of silicon-based devices and providing a compound semiconductor substrate including a plurality of photonic devices. The method also includes dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method further includes providing an assembly substrate, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, aligning the SOI substrate and the assembly substrate, joining the SOI substrate and the assembly substrate to form a composite substrate structure, and removing at least a portion of the assembly substrate from the composite substrate structure.06-14-2012
20130023088METHODS OF FORMING FULLY EMBEDDED BUMPLESS BUILD-UP LAYER PACKAGES AND STRUCTURES FORMED THEREBY - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands.01-24-2013
20130171773BONDED STRUCTURE EMPLOYING METAL SEMICONDUCTOR ALLOY BONDING - Vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with vertical stacks of a metal portion and a semiconductor portion formed on a second substrate. Alternately, vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with metal portions formed on a second substrate. The assembly of the first and second substrates is subjected to an anneal at a temperature that induces formation of a metal semiconductor alloy derived from the semiconductor portions and the metal portions. The first substrate and the second substrate are bonded through metal semiconductor alloy portions that adhere to the first and second substrates.07-04-2013
20080220563MODULE HAVING STACKED CHIP SCALE SEMICONDUCTOR PACKAGES - Stacked CSP (chip scale package) modules include a molded first (“top”) chip scale package having a molding side and a substrate side, and a second (“bottom”) package affixed to the substrate side of the top chip scale package, the second package being electrically connected to the first package by wire bonding between the first and second package substrates.09-11-2008
20120252161DIE BONDING METHOD UTILIZING ROTARY WAFER TABLE - An array of semiconductor components, comprising a first plurality of semiconductor components and a second plurality of semiconductor components held on a carrier, is bonded onto one or more substrates. The first plurality of semiconductor components is first located for pick-up by a transfer device, and each semiconductor component comprised in the first plurality of semiconductor components is picked up with the transfer device and is bonded onto a respective bonding position on the one or more substrates. After the first plurality of semiconductor components have been picked up and bonded, the carrier is rotated and the second plurality of semiconductor components is located for pick-up by the transfer device. Thereafter, each semiconductor component comprised in the second plurality of semiconductor components is picked up with the transfer device and is bonded onto a respective bonding position on the one or more substrates.10-04-2012
20130171772THROUGH-SILICON VIA STRUCTURE FORMATION PROCESS - In a process, an opening is formed to extend from a front surface of a semiconductor substrate through a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A block layer is formed on only a portion of the metal seed layer. A metal layer is formed on the block layer and the metal seed layer to fill the opening.07-04-2013
20130095608Methods for Forming 3DIC Package - A method includes dispensing an underfill between a first package component and a second package component, wherein the first package component is placed on a lower jig, and the second package component is over and bonded to the first package component. A through-opening is in the lower jig and under the first package component. The underfill is cured, wherein during the step of curing the underfill, a force is applied to flatten the first package component. The force is applied by performing an action selected from the group consisting of vacuuming and air blowing through the through-opening.04-18-2013
20130203216PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE - A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.08-08-2013
20110212573RIGID-BACKED, MEMBRANE-BASED CHIP TOOLING - An apparatus for use with multiple individual chips having a rigid plate, and a deformable membrane located on the plate, the deformable membrane having a thickness sufficient to allow the deformable membrane to peripherally conform to each of the individual multiple chips irrespective of any difference in height among the multiple individual chips and to prevent each of the multiple individual chips from moving in a lateral direction, the deformable membrane being configured to uniformly transfer a vertical force, applied to the rigid plate, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded during a connect and release cycle without causing damage to the individual chips or bonding surface.09-01-2011
20110237027Method Of Forming Package-On-Package And Device Related Thereto - Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.09-29-2011
20110256663High Speed, High Density, Low Power Die Interconnect System - A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may include active and passive elements. In one embodiment there is at least one interconnect coupling at least one conducting layer on a side of one die to at least one conducting layer on a side of the other die. Another interconnect embodiment is a slug having conducting and dielectric layers disposed between two or more die to interconnect between the die. Other interconnect techniques include direct coupling such as rod, ball, dual balls, bar, cylinder, bump, slug, and carbon nanotube, as well as indirect coupling such as inductive coupling, capacitive coupling, and wireless communications. The die may have features to facilitate placement of the interconnects such as dogleg cuts, grooves, notches, enlarged contact pads, tapered side edges and stepped vias.10-20-2011
20100055835METHOD OF STACKING AND INTERCONNECTING SEMICONDUCTOR PACKAGES VIA ELECTRICAL CONNECTORS EXTENDING BETWEEN ADJOINING SEMICONDUCTOR PACKAGES - An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.03-04-2010
20100285634INDUCTIVELY COUPLED INTEGRATED CIRCUIT WITH MAGNETIC COMMUNICATION PATH AND METHODS FOR USE THEREWITH - An integrated circuit includes a first integrated circuit die having a first circuit and a first inductive interface and a second integrated circuit die having a second circuit and a second inductive interface. A substrate is coupled to support the first integrated circuit die and the second integrated circuit die, the substrate including a magnetic communication path aligned with the first inductive interface and the second inductive interface, to magnetically communicate signals between the first circuit and the second circuit.11-11-2010
20100291735STACKABLE SEMICONDUCTOR CHIP LAYER COMPRISING PREFABRICATED TRENCH INTERCONNECT VIAS - A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.11-18-2010
20100317151WARPAGE RESISTANT SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package and a method for manufacturing the same is provided for minimizing or preventing warpage and twisting of semiconductor chip bodies as a result of thinning them during gringing. The semiconductor package includes a semiconductor chip body and a substrate. The semiconductor chip body has a first surface, a second surface facing away from the first surface, through-electrodes which pass through the semiconductor chip body and project from the second surface, and a warpage prevention part which projects in the shape of a fence along an edge of the second surface. The substrate has a substrate body and connection pads which are formed on an upper surface of the substrate body, facing the second surface, and which are connected with the projecting through-electrodes.12-16-2010
20130203215Packaging Methods for Semiconductor Devices - Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated.08-08-2013
20130157412CHIP ON WAFER BONDER - The present disclosure provides a bonding apparatus. The bonding apparatus includes a cleaning module designed for cleaning chips; and a chip-to-wafer bonding chamber configured to receive the chips from the cleaning module and designed for bonding the chips to a wafer.06-20-2013
20130122652Methods for Performing Reflow in Bonding Processes - A method includes placing a cover over a lower package component, wherein the cover comprises an opening aligned to the lower package component. An upper package component is placed over the lower package component. The upper package component is aligned to the opening, and a solder region is dispose between the upper package component and the lower package component. The cover and the upper package component are exposed to a radiation to reflow the solder region.05-16-2013
20110312130STACKED PACKAGE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, the stacked package includes a first chip disposed over a package substrate. The first chip has at least one first chip dummy pad, and the first chip dummy pad is not electrically connected to circuits of the first chip. A first dummy bonding wire is connected to the first chip dummy pad and the package substrate. A second chip is disposed over at least a portion of the first chip, and the second chip has at least one second chip bonding pad. A first bonding wire is electrically connected to the second chip bonding pad and the first dummy bonding wire.12-22-2011
20110312129INTERCONNECTION IN MULTI-CHIP WITH INTERPOSERS AND BRIDGES - A structure formation method. The method may include: attaching a substrate, a first interposer, a second interposer, and a first bridge together such that the first interposer is on and electrically connected to the substrate, the second interposer is on and electrically connected to the substrate, the first interposer comprises at least a first transistor, and the second interposer comprises at least a second transistor. The method may alternatively include: disposing both a first and second interposer on a substrate, wherein the first and second interposer are each electrically connected to the substrate; and electrically connecting a first bridge to the first and second interposers, wherein (i) the first bridge is in direct physical contact with the substrate or (ii) a bottom surface of the first bridge is within the substrate and below a top surface of the substrate.12-22-2011
20110312128STACK PACKAGE HAVING REDUCED ELECTRICAL CONNECTION LENGTH SUITABLE FOR HIGH SPEED OPERATIONS AND METHOD OF MANUFACTURING THE SAME - A stack package includes an upper semiconductor chip having a plurality of first bonding pads which are formed on an upper surface of the upper semiconductor chip and via-holes which are defined in the upper semiconductor chip under the respective first bonding pads; and a lower semiconductor chip attached to a lower surface of the upper semiconductor chip and having a plurality of second bonding pads which are formed on an upper surface of the lower semiconductor chip and bumps which are formed on the respective second bonding pads and are inserted into the respective via-holes to be come into the respective first bonding pads.12-22-2011
20120015480SYSTEM AND METHOD FOR MULTI-CHIP MODULE DIE EXTRACTION AND REPLACEMENT - A system and method are provided in which a first chip in a stacked multi-chip module configuration is affixed via one or more adhesion layers to a first portion of a partitioned interposer unit. Planar partitions of the interposer are physically bonded via multiple solder “bumps,” which possess high tensile strength but low resistance to horizontal shear force or torque. A second chip is affixed via one or more adhesion layers to the second portion of the partitioned interposer. The chips may thus be separated by horizontally and oppositely shearing or twisting the first and second portions of the partitioned interposer away from one another.01-19-2012
20120015479Semiconductor Package with a Mold Material Encapsulating a Chip and a Portion of a Lead Frame - Various exemplary embodiments provide components, devices, and methods of semiconductor packaging. The disclosed packaging component can include a mold material disposed around a lead frame and at least an integrated circuit (IC), wherein the IC is electrically connected with one side of the lead frame. The opposite side of the lead frame including, for example, lead segments, can be exposed from the mold material. A variety of other components, devices, and packages can then be assembled, e.g., over the disclosed packaging component, through the exposed regions so as to improve packaging densities.01-19-2012
20120015478Integrated Circuit Stacked Package Precursors and Stacked Packaged Devices and Systems Therefrom - A package-on-package (POP) package precursor and packaged devices and systems therefrom includes an electronic substrate including electrically conductive layers and a top surface. A first portion of the top surface has an IC die attached thereon. A second portion of the top surface has a plurality of first attach pads on opposing sides of the IC die for electrically coupling to a first electronic device on top of the IC die. At least a third portion of the top surface is positioned laterally with respect to the first and second portion. The third portion includes a plurality of second attach pads for electrically coupling to at least a second electronic device. At least one of the electrically conductive layers includes a coupling trace that couples at least one of the plurality of second attach pads to the IC die and/or one or more of the plurality of first attach pads.01-19-2012
20120015477STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.01-19-2012
20120021563METHOD AND APPARATUS FOR MANUFACTURING THREE-DIMENSIONAL INTEGRATED CIRCUIT - There is provided a three-dimensional integrated circuit manufacturing method for temporarily attaching a chip to a transcription substrate, and securely detaching the chip from the transcription substrate when the chip is transferred to a supporting substrate. When a chip is temporarily attached to a transcription substrate, by evaporating a liquid existing between the chip and the transcription substrate, the solids of the chip and the transcription substrate can be attached to each other. Accordingly, the chip can be temporarily attached to the transcription substrate so as not to be deviated from its own position. Further, by setting adhesive strength between the chip and a supporting substrate to be higher than that between the chip and the transcription substrate, the chip can be securely detached from the transcription substrate when the chip is transferred from the transcription substrate to the supporting substrate.01-26-2012
20120028413METHOD FOR MANUFACTURING BALL GRID ARRAY PACKAGE STACKING SYSTEM - A method for manufacturing a ball grid array package stacking system includes: providing a base substrate; coupling an integrated circuit to the base substrate; coupling a stacking substrate over the base substrate; mounting a heat spreader, having an access port, around the base substrate and the stacking substrate; and coupling a stacked integrated circuit to the stacking substrate through the access port.02-02-2012
20120028412SEMICONDUCTOR APPARATUS, METHOD OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface.02-02-2012
20120028411Embedded Wafer-Level Bonding Approaches - A method includes providing a carrier with an adhesive layer disposed thereon; and providing a die including a first surface, a second surface opposite the first surface. The die further includes a plurality of bond pads adjacent the second surface; and a dielectric layer over the plurality of bond pads. The method further includes placing the die on the adhesive layer with the first surface facing toward the adhesive layer and dielectric layer facing away from the adhesive layer; forming a molding compound to cover the die, wherein the molding compound surrounds the die; removing a portion of the molding compound directly over the die to expose the dielectric layer; and forming a redistribution line above the molding compound and electrically coupled to one of the plurality of bond pads through the dielectric layer.02-02-2012
20120295401METHODS FOR FORMING ASSEMBLIES AND MULTI CHIP MODULES INCLUDING STACKED SEMICONDUCTOR DICE - An assembly method that includes providing a first semiconductor device and positioning a second semiconductor device at least partially over the first semiconductor device is disclosed. Spacers space the active surface of the first semiconductor device substantially a predetermined distance apart from the back side of the second semiconductor device. Discrete conductive elements are extended between the active surface of the first semiconductor device and the substrate prior to positioning of the second semiconductor device. Intermediate portions of the discrete conductive elements pass through an aperture formed between the active surface of the first semiconductor device, the back side of the second semiconductor device, and two of the spacers positioned therebetween. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed.11-22-2012
20130095609Device and Method for Manufacturing a Device - A device includes a first semiconductor chip and a first encapsulant that encapsulates the first semiconductor chip and that includes a cavity. A carrier and an electrical component are mounted on the carrier. The carrier is arranged such that the electrical component is enclosed by the cavity.04-18-2013
20120088330AIRGAP MICRO-SPRING INTERCONNECT WITH BONDED UNDERFILL SEAL - A method of assembling a package includes aligning a pad chip with a spring chip to form at least one interconnect in an interconnect area, adhering the pad chip to the spring chip so that there is a gap between the pad chip and the spring chip, dispensing underfill material into the gap to seal the interconnect area from an environment external to the package, and curing the underfill material to form a solid mold.04-12-2012
20120088329SEMICONDUCTOR MULTI-PROJECT OR MULTI-PRODUCT WAFER PROCESS - The embodiment provides a semiconductor MP wafer process including processing a plurality of MP wafers in a lot or batch with a first process step. The plurality of the MP wafers is split into an MP wafer group-04-12-2012
20130210194METHOD OF TRANSFERRING AND BONDING AN ARRAY OF MICRO DEVICES - Electrostatic transfer head array assemblies and methods of transferring and bonding an array of micro devices to a receiving substrate are described. In an embodiment, a method includes picking up an array of micro devices from a carrier substrate with an electrostatic transfer head assembly supporting an array of electrostatic transfer heads, contacting a receiving substrate with the array of micro devices, transferring energy from the electrostatic transfer head assembly to bond the array of micro devices to the receiving substrate, and releasing the array of micro devices onto the receiving substrate.08-15-2013

Patent applications in class Assembly of plural semiconductive substrates each possessing electrical device

Patent applications in all subclasses Assembly of plural semiconductive substrates each possessing electrical device