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Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor

Subclass of:

438 - Semiconductor device manufacturing: process

438014000 - WITH MEASURING OR TESTING

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DocumentTitleDate
20090325325Laser Optical Path Detection in Integrated Circuit Packaging - A method is provided for detecting laser optical paths in integrated circuit (IC) packages. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. Power is supplied to the IC. The IC is scanned with a laser. Typically, a laser wavelength is used that is minimally absorbed by the glass spheres in the epoxy compound of the IC package, and changes in current to the IC are detected. A detected current change is cross-referenced against a scanned IC package surface region. This process identifies an optical pathway underlying the scanned IC package surface region. In some aspects, this process leads to the identification of a glass sphere-collecting package structure underlying the optical pathway. Examples of a glass sphere-collecting structure might include an inner lead wire, lead frame edge, or die edge.12-31-2009
20100022034Manufacture of devices including solder bumps - Typical testing of solder joints, (e.g. joints at printed circuit board pads) has not proven totally predictive of the ultimate performance of such joints. It has been found that this lack of reliability is, at least in part, due to the tendency during testing for these pads to lose adhesion to, or delaminate from, the underlying substrate. In contrast, such occurrence is not typical of phenomena induced during typical device usage. To remove this source of unreliability, a test structure is made together with the manufacturing device lot. The same pad processing is used and the pad size is substantially enlarged in the test structure. The test structure is employed to predict performance of devices in the lot and then the lot is processed accordingly.01-28-2010
20110195530SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A method including forming an intermediate product, the intermediate product being configured to include a wiring substrate including a plurality of first electrodes, a plurality of second electrodes and a plurality of test electrodes, a first semiconductor chip mounted over the wiring substrate and including a plurality of first pads electrically connected respectively to the first electrodes, and a second semiconductor chip stacked over the first semiconductor chip and including a plurality of second pads electrically connected respectively to the second electrodes; encapsulating the first and second semiconductor chips; and performing electrical tests on the first and second semiconductor chips by use of the test electrodes, after the encapsulating of the first and second semiconductor chips.08-11-2011
20110195529Rule-Based Semiconductor Die Stacking And Bonding Within A Multi-Die Package - A rule-based method of optimizing wire bonding jumps is disclosed which minimizes the amount of wire used for wire bonds and/or minimizes a number of power and ground pads on a substrate to support all wired connections.08-11-2011
20130078745Production Flow and Reusable Testing Method - An embodiment is a method. The method comprises providing a substrate comprising a die area. The die area comprises sections of pad patterns, and first sections of the sections each comprise a first uniform pad pattern. The method further comprises probing a first one of the first sections with a first probe card; stepping the first probe card to a second one of the first sections; and probing the second one of the first sections with the first probe card.03-28-2013
20130084661METHOD FOR MANUFACTURING OPTICAL DEFLECTOR FOR FORMING DICING STREET WITH DOUBLE ETCHING - A wafer-level optical deflector assembly is formed on a front surface side of a wafer. Then, the front surface side of the wafer is etched by using elements of the wafer-level optical deflector assembly, to form a front-side dicing street. Then, a transparent substrate with an inside cavity is adhered to the front surface side of the wafer. Then, a second etching mask is formed on a back surface side of the wafer. Then, the back surface side of the wafer is etched to create a back-side dicing street. Then, an adhesive sheet with a ring-shaped rim is adhered to the back surface side of the wafer. Then, the transparent substrate is removed. Finally, the ring-shaped rim is expanded to widen the front-side dicing street and the back-side dicing street to pick up optical deflectors one by one from the wafer.04-04-2013
20130052761METHOD AND DEVICE FOR RESIN COATING - A device for resin coating is used for producing an LED package including an LED element covered with resin containing phosphor. In a state in which a trial coating material 02-28-2013
20130052760METHOD OF INSPECTING AND MANUFACTURING A STACK CHIP PACKAGE - In an exemplary method of inspecting a stack chip package, a first chip is prepared. The first chip includes a through-silicon via, first pad electrodes connected to the through-silicon via and probe pad electrodes connected to the through-silicon via. A testing chip is prepared. The testing chip includes second pad electrodes that are arranged to correspond with the first pad electrodes. The testing chip is temporarily adhered to the first chip such that the second pad electrodes are electrically connected to the first pad electrode respectively, to form a stack structure wherein the probe pad electrodes are exposed to for testing. An electrical signal is applied to the exposed probe pad electrodes to test the through-silicon via included in the first chip.02-28-2013
20130071956Die Bonder and Bonding Method - With a die bonder or a bonding method, the die is adsorbed by the collet, the dicing tape to which the die is adsorbed is thrust up, the die adsorbed by the collet, and thrust up is peeled from the dicing tape, and the peeled die is bonded to the substrate. When the decrease in the air leak flow rate through the gap between the collet and the die upon the thrust up is smaller than the decrease in the normal peel by a predetermined amount, it is judged that a deflection occurs in the die.03-21-2013
20130059402Method and A System for Producing a Semi-Conductor Module - In a method for producing a semi-conductor module (03-07-2013
20110020962TEST CIRCUIT UNDER PAD - Aspects of the present invention relate to the arrangement of points of interconnection of integrated circuit die to the package in which they are enclosed. More specifically, aspects of the present invention pertain to an arrangement of bond pads over the active circuitry of an integrated circuit die, in order to permit a reduction in size of the die. An embodiment of the present invention may place a first bond pad over the active area of an integrated circuit, wherein the first bond pad is electrically coupled to a second bond pad outside of the active area of the integrated circuit. Production and delivery of the integrated circuit may proceed using the second bond pad during packaging, in parallel with the testing of packaging using the first bond pad. When processes related to the use of the first bond pad have been proven successful and sustainable, the second bond pad may be eliminated, resulting in a reduction of the size of the integrated circuit device. This approach may be employed to save die area, increasing the number of devices that may be produced on a silicon wafer, resulting in a reduction in device cost. The approach of the present invention works well whether the chip is pad or core limited. Although reference has been made to the used of this technique on a silicon wafer, an embodiment of the present invention may be employed in the fabrication of integrated circuit device using other materials as well, without departing from the spirit and scope of the present invention.01-27-2011
20110020961METHOD FOR MANUFACTURING LIGHT EMITTING DIODE ASSEMBLY - A method for manufacturing a light emitting diode (LED) assembly comprises the steps of: preparing a chip carrier comprising a carrier substrate, a P type electrode and an N type electrode, and arranging an LED chip onto the carrier substrate to electrically connect the LED chip with the P type electrode and the N type electrode; packaging the LED chip with a light-transmissible packaging gel and making the P type electrode and the N type electrode exposed to form a molded LED chip cell; preparing an arrangement carrier comprising a arrangement carrier substrate, a P type electrode plate and an N type electrode plate; forming an arrangement recess on the arrangement carrier substrate; and arranging the molded LED chip cell into the arrangement recess to make the P type electrode and the N type electrode electrically connect to the P type electrode plate and the N type electrode plate respectively.01-27-2011
20130164865METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE AND APPARATUS FOR MANUFACTURING LIGHT-EMITTING DEVICE - A method of manufacturing a light-emitting device which includes a light-emitting source by applying, onto the light-emitting source, a fluorescent resin which includes fluorescent particles and is stored in and discharged from an applicator, the method includes: measuring a first concentration which is a concentration of the fluorescent particles included in the fluorescent resin discharged from the applicator; and applying, onto the light-emitting source, the fluorescent resin in an application amount determined based on the first concentration which has been measured and reference data which indicates a relationship between a concentration of the fluorescent particles and an application amount of the fluorescent resin that enables the light-emitting device to have constant chromaticity.06-27-2013
20080293168Method and system of tape automated bonding - A tape automated bonding (TAB) structure which includes a flex tape having a conductive lead pattern formed thereon. The conductive lead pattern includes a plurality of leads configured to form an inner lead bond (ILB) portion of the TAB structure. At least one of the plurality of leads is internally routed and has a contact exposed interior to the ILB portion of the TAB structure.11-27-2008
20090098666CHIP PACKAGE ASSEMBLY USING CHIP HEAT TO CURE AND VERIFY - Methods of assembling a chip package are disclosed that employ heat from test pattern operation of the chip to cure a thermal interface material. The methods may also simultaneously verify thermal performance of the package using the heat from test pattern operation. Further, the heat may be used to cure the sealing material and/or underfill material, where they are used.04-16-2009
20110287560IN-SITU MELT AND REFLOW PROCESS FOR FORMING FLIP-CHIP INTERCONNECTIONS AND SYSTEMS THEREOF - A method for fabricating a flip-chip semiconductor package. The method comprises processing a semiconductor device, for example a semiconductor chip and processing a device carrier, for example a substrate. The semiconductor device comprises bump structures formed on a surface thereof. The substrate comprises bond pads formed on a surface thereof. Processing of the semiconductor chip results in heating of the semiconductor chip to a chip process temperature. The chip process temperature melts solder portions on the bump structures Processing of the substrate results in heating of the substrate to a substrate process temperature. The method comprises spatially aligning the semiconductor chip in relation to the substrate to correspondingly align the bump structures in relation to the bump pads. The semiconductor chip is then displaced towards the substrate for abutting the bump structures of the semiconductor chip with the bond pads of the substrate to thereby form bonds therebetween. A system for performing the above method is also disclosed.11-24-2011
20110294238SEMICONDUCTOR WAFER WITH ELECTRICALLY CONNECTED CONTACT AND TEST AREAS - The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.12-01-2011
20110294237PACKAGING METHOD OF SEMICONDUCTOR DEVICE - In a packaging method of semiconductor device, firstly, a wafer including a number of dies is provided. The wafer has an active surface and a back surface. The active surface adheres to a carrier. Subsequently, a number of openings are formed in each of the dies. Then, an insulating layer is formed on the back surface and on the side walls of the openings. A metal layer is formed to cover the insulating layer and the bottoms of the openings. A pattern protective layer is formed to cover the metal layer and to expose the metal layer outside the openings. Afterwards, the carrier is removed and the wafer is sawed. Later, a transparent substrate having a number of package units is provided. A spacer is formed at peripheral of each of the package units. A number of good dies are choose from the dies and disposed on the spacer.12-01-2011
20090148966METHOD OF MANUFACTURING A SYSTEM IN PACKAGE - A system in package (06-11-2009
20090098667Method For Picking Up Semiconductor Chips From A Wafer Table And Method For Mounting Semiconductor Chips On A Substrate - The invention relates to a method for picking up semiconductor chips from a wafer table and, optionally, their mounting on a substrate by means of a pick-and-place system. The position and orientation of the semiconductor chip to be mounted next are determined by means of a first camera and made available in the form of positional data relating to a first system of coordinates. The position and orientation of the substrate place on which the semiconductor chip will be mounted are determined by means of a second camera and made available in the form of positional data relating to a second system of coordinates. The conversion of coordinates of the first or second system of coordinates into coordinates of motion of the pick-and-place system occurs by means of two fixed mapping functions and two changeable correction vectors. The correction vectors are readjusted on the occurrence of a predetermined event.04-16-2009
20110263051INTERLEAF FOR LEADFRAME IDENTIFICATION - A method of making an IC device includes providing a stack of leadframe sheets each including a plurality of leadframes and an interleaf member interposed between adjacent ones of the leadframe sheets. The interleaf members include indicia that identifies the leadframes sheets. The stack of leadframe sheets is loaded onto an assembly machine. A first interleaf member is removed from the first leadframe sheet. The first leadframe sheet is transferred onto a mounting surface of the assembly machine. Semiconductor die are attached to leadframes on the first leadframe sheet. The method can include reading the indicia from the first interleaf member to determine a part number and lead finish for the first leadframe sheet, verifying the part number for the first leadframe sheet by comparing to a build list, and transferring the first leadframe sheet onto a mounting surface of the assembly machine only if the part number is verified.10-27-2011
20110201137Method of manufacturing layered chip package - A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body. Each substructure is fabricated through the steps of: fabricating a pre-substructure wafer including a plurality of pre-semiconductor-chip portions aligned; distinguishing between a normally functioning pre-semiconductor-chip portion and a malfunctioning pre-semiconductor-chip portion among the plurality of pre-semiconductor-chip portions included in the pre-substructure wafer; and forming electrodes connected to the normally functioning pre-semiconductor-chip portion and having respective end faces located in the side surface of the main body on which the wiring is disposed, without forming any electrode connected to the malfunctioning pre-semiconductor-chip portion.08-18-2011
20090093072ELECTRONIC ASSEMBLIES WITH HOT SPOT COOLING AND METHODS RELATING THERETO - A composite of two or more thermal interface materials (“TIMs”) is placed between a die and a heat spreader to improve cooling of the die in an integrated circuit package. The two or more TIMs vary in heat-dissipation capability depending upon the locations of die hot spots. In an embodiment, a more thermally conductive material may be positioned over one or more die hot spots, and a less thermally conductive material may be positioned abutting and/or surrounding the more thermally conductive material. The two or more TIMs may comprise a solder and a polymer. The composite TIM may be preformed as one unit or as a plurality of units. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.04-09-2009
20090286335METHODS OF FABRICATING LIGHT EMITTING DEVICES BY SELECTIVE DEPOSITION OF LIGHT CONVERSION MATERIALS BASED ON MEASURED EMISSION CHARACTERISTICS - A method of fabricating a light emitting device (LED) includes measuring emission characteristics for a plurality of LED chips configured to emit light of a first color. The plurality of LED chips are sorted based on the measured emission characteristics to provide a plurality of groups respectively including ones of the plurality of LED chips having similar measured emission characteristics. A respective light conversion material is selected for each of the plurality of groups based on the measured emission characteristics of the ones of the plurality of LED chips included therein and a desired color point. The selected light conversion material is configured to absorb at least some of the light of the first color and responsively emit light of a second color. For each of the plurality of groups, the respective selected light conversion material is deposited on the ones of the LED chips included therein to provide a plurality of packaged LEDs including the plurality of LED chips and respectively configured to emit light having the desired color point. Related apparatus is also discussed.11-19-2009
20080261336Semiconductor device and manufacturing method thereof - A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.10-23-2008
20080286886Monitoring Cool-Down Stress in a Flip Chip Process Using Monitor Solder Bump Structures - A semiconductor chip and methods for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.11-20-2008
20080293167FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.11-27-2008
20080305565Fabrication method for semiconductor device - A semiconductor device fabrication method can improve yield of semiconductor devices and decrease (or prevent) waste of non-defective semiconductor chips. This fabrication method has a step of performing characteristic inspection after packaging a semiconductor chip every time a semiconductor chip layer is formed. The fabrication method makes another semiconductor chip layer on this semiconductor chip layer only when the inspection indicates that the semiconductor chip is a non-defective product.12-11-2008
20080318349Wafer level hermetic bond using metal alloy - Systems and methods for forming an encapsulated MEMS device include a hermetic seal which seals an insulating gas between two substrates, one of which supports the MEMS device. The hermetic seal may be formed by heating at least two metal materials, in order to melt at least one of the metal materials. The first melted metal material flows into and forms an alloy with a second metal material, forming a hermetic seal which encapsulates the MEMS device.12-25-2008
20100144068High Throughput Die-to-Wafer Bonding Using Pre-Alignment - A method of forming integrated circuits includes providing a wafer that includes a plurality of dies; aligning a first top die to a first bottom die in the wafer; recording a first destination position of the first top die after the first top die is aligned to the first bottom die; bonding the first top die onto the first bottom die; calculating a second destination position of a second top die using the first destination position; moving the second top die to the second destination position; and bonding the second top die onto a second bottom die without any additional alignment action.06-10-2010
20100151598TEMPORARY PACKAGE FOR AT-SPEED FUNCTIONAL TEST OF SEMICONDUCTOR CHIP - In some embodiments, a temporary package for at-speed functional test of semiconductor chip, including high power chips, is presented. In this regard, a method is introduced including placing an integrated circuit die on a contactor layer, the contactor layer to electrically couple contacts on the integrated circuit die with contacts on a multi-layer substrate designed to be permanently attached with the integrated circuit die, placing an integrated heat spreader over the integrated circuit die, and bonding the integrated heat spreader with the substrate, the integrated heat spreader holding the integrated circuit die in place to form a temporary package. Other embodiments are also disclosed and claimed.06-17-2010
20080318348Method of constructing a stacked-die semiconductor structure - In constructing a multi-die semiconductor device, a plurality of semiconductor die are provided. Each die is probe tested when it is part of a wafer. Flat contacts are connected to each die when it is part of a wafer. After wafer sawing, each die is tested in a test socket, using the contacts connected thereto. The die are then packaged in stacked relation to form the multi-die semiconductor device.12-25-2008
20110223695Electronic assembly with detachable components - The present invention provides systems and methods for assembling an electronic assembly using an anisotropic conducting membrane (ACM) as a component interconnect and a substrate embossed with placement cavities or a positional fixture to facilitate component placement on the substrate in the electronic assembly. The fixture may comprise multiple layers of interconnects to improve routing density for the electronic assembly enclosed in a housing. An alignment chain may be used to monitor positional and contact integrity of the ACM interfaced components in a complex assembly. The systems and methods allow components to be detached for reuse. Interconnection elements or conduction pathways at the components can be used to interconnect a plurality of neighboring substrates over the ACM layers into a stacked electronic assembly.09-15-2011
20100248400Methods of fabricating a light-emitting device - Methods of fabricating of a light-emitting device are provided, the methods include forming a plurality of light-emitting units on a substrate, measuring light characteristics of the plurality of light-emitting units, respectively, depositing a phosphor layer on the plurality of light-emitting units using a printing method, and cutting the substrate to separate the plurality of light-emitting units into unit by unit. The phosphor layer is adjustably deposited according to the measured light characteristics of the plurality of light-emitting units.09-30-2010
20100248399METHOD FOR MANUFACTURING HYBRID IMAGE SENSORS - A method for wafer-to-wafer bonding of a sensor readout circuitry separately fabricated with a silicon substrate to a photodiode device made of non-silicon materials grown from a separate substrate. In preferred embodiments the non-silicon materials are epitaxially grown on a silicon wafer. The bonding technique of preferred embodiments of the present invention utilizes lithographically pre-fabricated metallic interconnects to connect each of a number of pixel circuits on a readout circuit wafer to each of a corresponding number of pixel photodiodes on a photodiode wafer. The metallic interconnects are extremely small (with widths of about 2 to 4 microns) compared to prior art bump bonds with the solder balls of diameter typically larger than 20 microns. The present invention also provides alignment techniques to assure proper alignment of the interconnects during the bonding step.09-30-2010
20090081818METHOD OF WIRE BOND ENCAPSULATION PROFILING - A method for profiling a bead of encapsulant extending along an edge of a die mounted to a supporting structure, by depositing a bead of encapsulant onto wire bonds along the edge of the die, positioning a profiling surface over the die at a predetermined spacing from the die, moving the profiling surface across the bead before the bead of encapsulant has cured to reshape the bead profile and, curing the bead of encapsulant. The invention has found that the encapsulant can be effectively shaped by a profiling surface without stripping the encapsulant from the wire bonds. The normally convex-shaped upper surface of the encapsulant bead can be pushed to one side of the bead with the profiling surface. With a lower encapsulant bead, the active surface can be brought into closer proximity with another surface without making contact. For example, the nozzle array on a printhead IC can be 300 microns to 400 microns from the paper path. By collapsing or flattening the wire bond arcs before applying and profiling a bead of encapsulant, the nozzle array on the printhead IC can be less than 100 microns from the paper path.03-26-2009
20100003771PRODUCTION METHOD OF SEMICONDUCTOR DEVICE AND BONDING FILM - To provide a method of manufacturing semiconductor devices, the method being capable of efficiently obtaining a singulated semiconductor chip upon which an adhesive is adhered and also capable of excellently bonding a semiconductor chip to a wiring substrate, and provide an adhesive film. A layered product 01-07-2010
20090075406INTEGRATION MANUFACTURING PROCESS FOR MEMS DEVICE - A method for manufacturing an MEMS device is provided. The method includes steps of a) providing a first substrate having a concavity located thereon, b) providing a second substrate having a connecting area and an actuating area respectively located thereon, c) forming plural microstructures in the actuating area, d) mounting a conducting element in the connecting area and the actuating area, e) forming an insulating layer on the conducting element and f) connecting the first substrate to the connecting area to form the MEMS device. The concavity contains the plural microstructures.03-19-2009
20090137069Chip packaging process including simpification and mergence of burn-in test and high temperature test - A chip packaging process integrates a burn-in test or a high temperature test to simplify overall packaging and testing process flow. One or more chips are disposed on one or more units of a substrate strip where the substrate strip has a plurality of electrical open sections at the plating lines to electrically isolate the external pads between different units. After electrical connection and encapsulation, a burn-in test is executed at the same time of a post mold curing step, with a high-temperature testing if necessary. Therefore, the chips on the substrate strip has been gone through the burn-in test during the encapsulant is completely cured at the post mold curing step and the burn-in test is finished before the singulation step to reduce the overall testing time.05-28-2009
20090209052PROCESS FOR THE COLLECTIVE FABRICATION OF 3D ELECTRONIC MODULES - The invention relates to the collective fabrication of n 3D module. It comprises a step of fabricating a batch of n dies i at one and the same thin plane wafer (08-20-2009
20090221104METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device involves the steps of: forming a plurality of product formation areas each having a circuit and a plurality of first electrode pads over a main surface of a semiconductor wafer; arranging a plurality of second electrode pads with larger pitches than the first electrode pads in each of the product formation areas; segmenting the semiconductor wafer to separate the plural product formation areas and provide a plurality of semiconductor devices each having the circuit, the plural first electrode pads and the plural second electrode pads on a first surface; and cleaning foreign matter off the first surface of the semiconductor device after the step of segmenting the semiconductor devices.09-03-2009
20090246892SENSOR, METHOD, AND DESIGN STRUCTURE FOR A LOW-K DELAMINATION SENSOR - The invention generally relates to a design structure of a circuit design, and more particularly to a design structure of a delamination sensor for use with low-k materials. A delamination sensor includes at least one first sensor formed in a layered semiconductor structure and a second sensor formed in the layered semiconductor structure. The at least one first sensor is structured and arranged to detect a defect, and the second sensor is structured and arranged to identify an interface where the defect exists.10-01-2009
20100015734Formation of Through-Wafer Electrical Interconnections and Other Structures Using a Thin Dielectric Membrane - Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a preexisting semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing the other side of the wafer, and depositing metallization over the other side of the wafer so as to contact the previously deposited metallization. Techniques also are disclosed for providing capacitive and other structures using thin metal membranes.01-21-2010
20110111534METHOD FOR PRODUCING A CONTACT FOR SOLAR CELLS - The invention relates to a method for producing a contact for solar cells (05-12-2011
20090075405IMAGING APPARATUS, RADIATION IMAGING APPARATUS, AND MANUFACTURING METHODS THEREFOR - An imaging apparatus is provided in which a plurality of pixels, each having a conversion element and a thin-film transistor, are arranged in a two-dimensional fashion on an insulating substrate; the photoelectric conversion element is arranged over the thin-film transistor, with an insulating film, which serves as an interlayer insulating film, inserted between the conversion element and the thin-film transistor; and by way of a contact hole portion provided in the insulating film, the source electrode or the drain electrode of the thin-film transistor and the photoelectric conversion element are connected with each other. The imaging apparatus has a pixel in which the contact hole portion is removed through a laser-beam irradiation so that the connection portion between the conversion element and a conductive layer, which serves as the source electrode or the drain electrode of the thin-film transistor, is discontinued.03-19-2009
20080286887Method for adjusting a transistor model for increased circuit simulation accuracy - According to one exemplary embodiment, a method for adjusting a transistor model for increased circuit simulation accuracy includes determining a first gate CD offset by matching a C-V test structure having a normalized channel current to an I-V test structure having the normalized channel current. The method further includes utilizing the first gate CD offset to adjust the transistor model for increased circuit simulation. The method also includes determining a second gate CD offset by varying I-V and C-V gate length parameters in the transistor model to cause simulated data from a test circuit to be approximately equal to measured data from the test circuit. The method further includes utilizing the second gate CD offset to adjust the transistor model.11-20-2008
20100311191Metallic electrode forming method and semiconductor device having metallic electrode - A metallic electrode forming method includes: forming a bed electrode on a substrate; forming a protective film with an opening on the bed electrode to expose the bed electrode from the opening; forming a metallic film covering the protective film and the opening; mounting the substrate on an adsorption stage, and measuring a surface shape of the metallic film by a surface shape measuring means; deforming the substrate by a deforming means so that a difference between the principal surface and a cutting surface is within a predetermined range; measuring a surface shape of the principal surface, and determining whether the difference is within a predetermined range; and cutting the substrate along with the cutting surface so that the metallic film is patterned to be a metallic electrode.12-09-2010
20090142861Method of Manufacturing Flash Memory Device - Disclosed are methods of manufacturing a flash memory device. The method can include performing a first test on memory banks of chips on a wafer to record an availability of the banks; performing an inking process on each of the chips according to a number of available banks in the chip; performing a sawing process to divide the chips mounted on the wafer; packaging the divided chips according to the number of available banks in the chip; and performing a verification test on the packaged chips.06-04-2009
20120244648MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To improve the reliability in an electric inspection of a semiconductor device. When a movable pedestal 09-27-2012
20120244647Pick-Up Method of Die Bonder and Die Bonder - The present invention provides a die bonder capable of stripping a die without fail, or a highly reliable die bonder or pick-up method using the die bonder.09-27-2012
20090215204FABRICATION METHOD OF SEMICONDUCTOR DEVICE - A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an opposite end of the lens barrel, and an image of a main surface of a chip is photographed through the objective lens. A surface-emitting lighting unit, a diffusing plate and a half mirror are internally provided between the lens barrel and the chip. Further, another lens barrel having a coaxial drop lighting function of radiating light to the main surface of the chip along the same optical axis as that of the camera is disposed.08-27-2009
20110151595Fabrication method for semiconductor device - A semiconductor device fabrication method can improve yield of semiconductor devices and decrease (or prevent) waste of non-defective semiconductor chips. This fabrication method has a step of performing characteristic inspection after packaging a semiconductor chip every time a semiconductor chip layer is formed. The fabrication method makes another semiconductor chip layer on this semiconductor chip layer only when the inspection indicates that the semiconductor chip is a non-defective product.06-23-2011
20110212549Apparatus and method for predetermined component placement to a target platform - The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and structures to detect and improve the component placement accuracy on a target platform by incorporating alignment marks on component and reference marks on target platform under various probing techniques. A set of sensors grouped in any array to form a multiple-sensor probe can detect the deviation of displaced components in assembly.09-01-2011
20110053295RESIN APPLICATION APPARATUS, OPTICAL PROPERTY CORRECTION APPARATUS AND METHOD, AND METHOD FOR MANUFACTURING LED PACKAGE - A resin application apparatus includes: an optical property measurement unit measuring an optical property of light emitted from a light emitting diode (LED) chip which is mounted on a package body and to which transparent resin is not applied; and a resin application unit applying light conversion material-containing transparent resin to the LED chip in accordance with a resin application amount which is decided depending on the optical property measured by the optical measurement unit.03-03-2011
20120122250APPARATUS AND METHOD FOR MANUFACTURING LED PACKAGE - An apparatus for manufacturing an light emitting diode (LED) package, includes: a heating unit heating an LED package array in a lead frame state in which a plurality of LED packages are installed to be set in an array on a lead frame; a testing unit testing an operational state of each of the LED packages in the LED package array by applying a voltage or a current to the LED package array heated by the heating unit; and a cutting unit cutting only an LED package determined to be a functional product or an LED package determined to be a defective product from the lead frame to remove the same according to the testing results of the testing unit.05-17-2012
20110136271Method of Producing Semiconductor Components - A method is provided for producing a semiconductor component (06-09-2011
20110097826DEVICE AND METHOD FOR DETECTING STRESS MIGRATION PROPERTIES - A device and method are provided for detecting stress migration properties of a semiconductor module mounted in a housing. A stress migration test (SMT) structure is formed in the semiconductor module. An integrated heating (IH) device is formed within or in direct proximity to the SMT structure. The SMT structure includes a first interconnect region in a first interconnect layer, a second interconnect region in a second interconnect layer, and a connecting region electrically connecting the interconnect regions through a first insulating layer. The IH device includes a heating interconnect region through which a heating current flows. The heating interconnect region is within or outside the first or second interconnect region or connecting region. When the heating current is applied, a measurement voltage is applied to the SMT structure, and a current through the SMT structure is measured to detect stress migration properties of the semiconductor module.04-28-2011
20110177627ASSEMBLY LINE FOR PHOTOVOLTAIC DEVICES - The present application provides a method for the production of photovoltaic devices, preferably tandem solar cells. The method comprises the steps of: Providing at least one substrate comprising a front contact; and depositing at least a first semiconductor stack onto the substrate to produce a photo-voltaic device; and comprises at least two of the steps of: applying a back contact to the photovoltaic device; contacting of the photovoltaic device; removal of unnecessary material from the edge regions of the photovoltaic device; encapsulation; cross-contacting; and/or framing of the photovoltaic device, wherein the substrate is continuously or semi-continuously moved from one step of the method to the next step of the method. The present application furthermore provides a system to carry out the method of the invention.07-21-2011
20120309118SILICON WAFER ALIGNMENT METHOD USED IN THROUGH-SILICON-VIA INTERCONNECTION - A method of silicon wafer alignment used in through-silicon-via interconnection for use in the field of high-integrity packaging technology is disclosed. In one aspect, the method includes aligning and calibrating the upper and lower silicon wafers, stacked and interconnected electrically, so as to improve alignment accuracy of silicon wafers and reduce interconnection resistances. In some embodiments, the integrated circuit chip made by the method improves speed and energy performance.12-06-2012
20100261297REMOTE CHIP ATTACHMENT - A method of attaching a pair of chips, each having primary contacts that can be mated to each other, involves forming one or more secondary contacts on each of the two chips of a shape sufficient to prevent an initial attachment material from contacting any of the primary contacts during a preliminary attachment operation, the secondary contacts further having a height that will prevent the primary contacts from touching when the secondary contacts are brought into contact with each other, bringing the secondary contacts into closer and closer aligned proximity to each other at least until the primary contacts touch in a first phase, and heating the primary contacts until material between each of corresponding primary contacts on each of the chips in the pair forms an electrical connection.10-14-2010
20100029023CONTROLLING EDGE EMISSION IN PACKAGE-FREE LED DIE - Light emitting diode (LED) structures are fabricated in wafer scale by mounting singulated LED dies on a carrier wafer or a stretch film, separating the LED dies to create spaces between the LED dies, applying a reflective coating over the LED dies and in the spaces between the LED dies, and separating or breaking the reflective coating in the spaces between the LED dies such that some reflective coating remains on the lateral sides of the LED die. Portions of the reflective coating on the lateral sides of the LED dies may help to control edge emission.02-04-2010
20100029022METHOD FOR IMPROVED UTILIZATION OF SEMICONDUCTOR MATERIAL - In a method for producing semiconductor components, in which chips are structured, tested, and isolated into dies on a wafer, in the event of a wafer being broken during the method, undamaged chips of a fragment of the wafer delimited by at least one edge section and at least one fracture contour are processed further as usual. The method has the result that the yield of usable chips is significantly increased in relation to the discarding and disposal of broken wafers provided in the prior art. The average production costs of electronic components and the loss of valuable semiconductor materials and the costs for the disposal of the fragments viewed as discards up to this point are thus significantly reduced.02-04-2010
20100022035Electronic apparatus and manufacturing method thereof - There are provided a plurality of semiconductor apparatuses judged as good items in electrical and functional inspections while having internal connection terminals disposed on electrode pads of semiconductor chips, resin layers which are disposed on surfaces of the semiconductor chips in which the electrode pads are formed and expose the internal connection terminals, and wiring patterns which are disposed on the resin layers and are connected to the internal connection terminals, a wiring substrate on which the plurality of semiconductor apparatuses are stepwise stacked, the wiring substrate electrically connected to the plurality of semiconductor apparatuses, and a sealing resin with which the plurality of semiconductor apparatuses are sealed.01-28-2010
20120231563OPERATING METHOD OF HARDWIRED SWITCH - An operating method of a hardwired switch is provided. First, a first die is provided. The first die is configured as the first die in the hardwired switch. Next, a function of the first die is inspected to obtain an inspected result. Upon the inspected result, whether a second TSV is selectively disposed between the first landing pad and the fifth landing pad, between the second landing pad and the sixth landing pad, between the third landing pad and the seventh landing pad, or between the fourth landing pad and the eighth landing pad or not is determined. The first die is stacked above a second die, so that the second surface is located between the first die and the second die.09-13-2012
20120040477AI EPOXY ADJUSTMENT - A method and apparatus for dispensing a volume of die attach adhesive onto a surface can include an optical system which images the dispensed volume of die attach adhesive. A two-dimensional area covered by the die attach adhesive and a die attach dispense pressure can be used as a comparison with a reference value to determine whether the volume of die attach adhesive dispensed is sufficient. The reference value can take into account viscosity changes of the die attach adhesive, so that the volume of die attach adhesive dispensed during production can be determined. The volume dispensed can be automatically adjusted in situ during production using a computer system.02-16-2012
20100178718METHODS FOR IMPROVING PERFORMANCE VARIATION OF A SOLAR CELL MANUFACTURING PROCESS - A method for optimizing a solar cell manufacturing process is described. The method includes determining a reference finger spacing value and a reference bulk lifetime for the solar cell manufacturing process. The method also includes measuring an actual bulk lifetime of a wafer with an in-line measurement tool. The method further includes calculating an optimal finger spacing value with a computer coupled to the in-line measurement tool, the optimal finger spacing value being the product of the reference finger spacing value and a square root of the actual bulk lifetime divided by the square root of the reference bulk lifetime. The method further includes forming a junction on the wafer, and depositing a set of busbars and a set of fingers on the wafer with a metal deposition device, wherein a distance between a first finger and a second finger of the set of fingers is about the optimal finger spacing value.07-15-2010
20100105154METHOD AND APPARATUS FOR PROCESSING SUBSTRATE - A substrate processing method can securely form a metal film by electroless plating on an exposed surface of a base metal, such as interconnects, with increased throughput and without the formation of voids in the base metal. The substrate processing method includes: cleaning a surface of a substrate having a base metal formed in the surface with a cleaning solution comprising an aqueous solution of a carboxyl group-containing organic acid or its salt and a surfactant as an additive; bringing the surface of the substrate after the cleaning into contact with a processing solution comprising a mixture of the cleaning solution and a solution containing a catalyst metal ion, thereby applying the catalyst to the surface of the substrate; and forming a metal film by electroless plating on the catalyst-applied surface of the substrate.04-29-2010
20110318850MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURING SAME - A microelectronic package includes a first substrate (12-29-2011
20120064642METHOD TO REMOVE SAPPHIRE SUBSTRATE - A Light-Emitting Diode (LED) is formed on a sapphire substrate that is removed from the LED by grinding and then etching the sapphire substrate. The sapphire substrate is ground first to a first specified thickness using a single abrasive or multiple abrasives. The remaining sapphire substrate is removed by dry etching or wet etching.03-15-2012
20130011941BOND LINE THICKNESS CONTROL FOR DIE ATTACHMENT - A semiconductor die is attached onto a substrate on a process platform during manufacturing of a semiconductor package. A dispenser dispenses an adhesive onto the substrate, and the semiconductor die is bonded onto the adhesive which has been dispensed onto the substrate with a bonding tool. Thereafter, a bond line thickness between a bottom surface of the semiconductor die and a top surface of the substrate on the process platform is measured using a measuring device.01-10-2013
20110092000METHOD FOR MANUFACTURING AND TESTING AN INTEGRATED ELECTRONIC CIRCUIT - A method for manufacturing and for testing an integrated circuit, including the steps of forming, on the upper portion of the integrated circuit, a passivation layer including openings at the level of metal tracks of the last interconnect stack of the integrated circuit; forming, in the openings, first pads connected to second pads formed on the passivation layer by conductive track sections, the first pads being intended for the connection of the integrated circuit; testing the integrated circuit by bringing test tips in contact with the second pads; and eliminating at least a portion of at least one of the conductive track sections.04-21-2011
20110091999Adapter board and method for manufacturing same, probe card, method for inspecting semiconductor wafer, and method for manufacturing semiconductor device - A method of manufacturing a semiconductor device includes preparing two package substrates, electrically coupling a semiconductor wafer to a measuring apparatus, inspecting the wafer, dicing the semiconductor wafer into semiconductor elements and packaging the semiconductor element over the prepared package substrates.04-21-2011
20110065215WAFER LEVEL INTEGRATION MODULE WITH INTERCONNECTS - A method and apparatus for manufacturing an integrated circuit (IC) device (03-17-2011
201100652143D MULTIPLE DIE STACKING - A process of forming three-dimensional (3D) die. A plurality of wafers are tested for die that pass (good die) or fail (bad die) predetermined test criteria. Two tested wafers are placed in proximity to each other. The wafers are aligned in such a manner so as to maximize the number of good die aligned between the two wafers. The two wafers are then bonded together and diced into individual stacks of bonded good die.03-17-2011
20120122251STACKED TYPE SEMICONDUCTOR MEMORY DEVICE AND CHIP SELECTION CIRCUIT - A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.05-17-2012
20110183447METHOD OF MANUFACTURING STACKED SEMICONDUCTOR PACKAGE - A method of manufacturing a stacked semiconductor package in which a plurality of semiconductor chips are stacked includes preparing a first semiconductor chip including a first semiconductor device, a first penetration electrode, and a first connection unit electrically connected to the first semiconductor device or the first penetration electrode, attaching the first semiconductor chip to a base substrate with the first connection unit interposed therebetween, forming a first rewiring pattern and a first protection layer on the first semiconductor chip by using a printing method, wherein the first rewiring pattern is electrically connected to the first penetration electrode and the first protection layer partially covers the first rewiring pattern and exposes other portions of the first rewiring pattern, and attaching a second semiconductor chip including a second semiconductor device to the first semiconductor chip to electrically connect the second semiconductor device to the first rewiring pattern.07-28-2011
20120164762Active matrix organic electroluminescent device and method of manufacture thereof - An active matrix organic electroluminescent device includes a thin-film transistor, an organic electroluminescent device, and a spacer layer deposited between the thin-film transistor and the organic electroluminescent device, wherein the spacer layer is made of adhesive for a dual curing system selected from the group consisting of ultraviolet curing-thermal curing, ultraviolet curing-microwave curing, ultraviolet curing-anaerobic curing, and ultraviolet curing-electron beam curing system. The present invention solves the poor adhesiveness between the thin-film transistor and the organic electroluminescent device, and improves the moisture and oxygen proof ability. The preparation method is simple, effective, and able to lower the cost and difficulty, and greatly improve the yield rate of the device.06-28-2012
20120164761METHOD FOR MANUFACTURING LIGHTING DEVICE - An object is to provide a method for manufacturing a lighting device, in which a problem of a short circuit between an upper electrode and a lower electrode of a light-emitting element is solved without reducing a light-emitting property of a normal portion of the light-emitting element to the utmost. In a light-emitting element including an upper electrode, an electroluminescent layer, and a lower electrode, a short-circuited portion that is undesirably formed between the upper electrode and the lower electrode is irradiated with a laser beam, whereby a region where the short-circuited portion is removed is formed, and then the region is filled with an insulating resin having a light-transmitting property. Thus, the problem of the short circuit between the upper electrode and the lower electrode is solved and yield of a lighting device is improved.06-28-2012
20100210042METHOD OF MANUFACTURING SEMICONDUCTOR MODULE - A method of manufacturing a semiconductor module is provided. A semiconductor package is formed, having one or more plate units which are bent by heat. The semiconductor package is aligned on a module substrate, and connection members are disposed between the semiconductor package and the module substrate. Heat is applied to the plate units and the connection members to extend a distance between the module substrate and the semiconductor package, and connection patterns are formed. The height of the connection patterns is larger than that of the connection members.08-19-2010
20120214262Embedded Semiconductor Device Including Phase Changeable Random Access Memory Element and Method of Fabricating the Same - Disclosed are an embedded semiconductor device including a phase changeable random access memory element and a method of fabricating the same. A semiconductor chip including a main memory element and a supplementary memory element is integrated on a substrate, intrinsic chip data are obtained by electrically testing the semiconductor chip, and the semiconductor chip is packaged. The intrinsic chip data are written into the supplementary memory element before the packaging of the semiconductor chip, and a memory layer of the supplementary memory element is formed of a material exhibiting an improved data retention property under thermal environmental conditions as compared with a memory layer of the main memory element.08-23-2012
20120214261TEST APPARATUS, TEST METHOD AND MANUFACTURING METHOD - Provided is a test apparatus for testing a device under test, comprising a dicing section that dices a wafer on which a plurality of devices under test are formed to separate each of the devices under test; a test packaging section that packages each of the devices under test resulting from the dicing by the dicing section in an individual test package; a testing section that tests the devices under test packaged in the test packages; a removing section that removes the devices under test that have been tested from the test packages; and a commercial packaging section that packages the devices under test removed from the test packages in commercial packages.08-23-2012
20120135548SEMICONDUCTOR DEVICE - A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.05-31-2012
20120252142Singulation and Strip Testing of No-Lead Integrated Circuit Packages Without Tape Frame - Strip testing is applied to a plurality of integrated circuit dies that are each encapsulated in an encapsulant, that each have a set of externally accessible leads connected thereto, and that are electrically isolated from one another. Provision is made for the strip testing to be performed without mounting the encapsulated integrated circuit dies on a support tape.10-04-2012
20100047934Method For Fabricating Semiconductor Component Having Encapsulated Through Wire Interconnect (TWI) - A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate.02-25-2010
20100009471Adapter board and method for manufacturing same, probe card, method for inspecting semiconductor wafer, and method for manufacturing semiconductor device - An adapter board includes a package substrate having a first surface and a second surface and further including a board having wirings formed therein, pads disposed in the device side, and the pads disposed in the bump side, an insulating resin layer joined to the first surface, through holes formed in the positions corresponding to the pads in the insulating resin layer, vias formed in the through holes, and pads covering the through holes, wherein the pads are electrically coupled to the pads through the wirings, and the pads are electrically coupled to the pads through the vias.01-14-2010
20120264240SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Of three chips (10-18-2012
20120264239LIGHT-TUNING METHOD - A light-tuning method is provided. In the method, a filter material is first selected for filtering out unwanted light of a specific wavelength to obtain a transmittance spectrum. The transmittance spectrum is multiplied by an eye sensitivity function to obtain a filtered spectrum. The filtered spectrum has a wavelength range between 450 nm and 650 nm. According to a full width at half maximum (FWHM) wavelength range of the filtered eye sensitivity function, a phosphor is selected and a light-emitting spectrum of the phosphor is determined so that between the light-emitting spectrum of the phosphor and the filtered eye sensitivity function is an optimal matching degree.10-18-2012
20110124135Solar Cell Module and Method for Assembling a Solar Cell Module - The invention relates to a method for assembly of solar cell modules by arranging a multitude pre-manufactured, individualized solar cells for forming a matrix of solar cells for the solar cell module; depositing a metallization layer at least partially on at least one surface of the matrix of solar cells for forming the solar cell module; testing electrical function at least of the solar cell module; depositing a passivation layer on a surface of the solar cell module. In another aspect the invention relates to a manufacturing system for a solar cell module and a solar cell module (05-26-2011
20080299685One piece method for integrated circuit (IC) assembly - In a method and system for assembling a semiconductor device, a tray is configured to provide an array of bins arranged in m rows and n columns, where m and n are integers. The tray containing defect free singulated substrates is received from a substrate supplier for assembly. Each one of the defect free singulated substrates, which is disposed in a corresponding bin of the tray, is accessible in a concurrent or sequential manner, thereby enabling concurrent or sequential assembly of m*n ones of the defect free singulated substrate. The assembly process for the semiconductor device starting from the defect free singulated substrate includes die attach, wire bonding, mold press, laser marking, solder ball attach, and testing operations. Assembly of the defect free singulated substrates avoids material loss and increases manufacturing efficiency.12-04-2008
20120322174CHIP FIXING APPARATUS AND CHIP TESTING METHOD USING THE SAME - A chip testing method includes cutting a wafer into chip packages, re-arranging the chip packages on a chip tray, and testing the re-arranged chip packages. The wafer includes a plurality of substrates vertically stacked thereon, and each of the plurality of substrates has a plurality of chips mounted thereon.12-20-2012
20100203654Method of Testing an Integrated Circuit Die, and an Integrated Circuit Die - In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.08-12-2010
20110237003METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE BY USING COMPRESSION MOLDING - A method of manufacturing a semiconductor device comprises: determining whether or not the viscosity of a sealing resin at a first temperature lower than the melting temperature of the sealing resin is less than or equal to a first reference value which prevents poor sealing from occurring at the first temperature, for each lot in which the corresponding sealing resin is manufactured; selecting the sealing resin of the lot when the viscosity of the sealing resin at the first temperature is less than or equal to the first reference value; introducing the sealing resin selected in selecting the sealing resin into a mold of a compression molding apparatus; and sealing a semiconductor chip mounted over a substrate with the sealing resin by compression molding using the mold heated at a second temperature higher than the first temperature after introducing the sealing resin.09-29-2011
20100233831RECONFIGURED WAFER ALIGNMENT - A method of manufacturing semiconductor device comprises placing multiple chips onto a carrier. An encapsulation material is applied to the multiple chips and the carrier for forming an encapsulation workpiece. The encapsulation workpiece having a first main face facing the carrier and a second main face opposite to the first main face. Further, marking elements are applied to the encapsulation workpiece relative to the multiple chips, the marking elements being detectable on the first main face and on the second main face.09-16-2010
20100167430APPARATUS AND METHOD FOR TESTING A TRANSDUCER AND/OR ELECTRONIC CIRCUITRY ASSOCIATED WITH A TRANSDUCER - A method and apparatus for applying a test signal to a node of a signal path of an integrated circuit using a parasitic capacitance of the integrated circuit associated with the node. For example, a parasitic capacitance associated with a bond pad may be used to apply a test signal to a signal path. Alternatively, a parasitic capacitance associated with a shielding element may be used to apply a test signal to the signal path.07-01-2010
20120149136FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In the fabrication of a semiconductor integrated circuit device, a 2D-3D inspection technique for solder printed on a substrate is provided which permits easy preparation of data and easy visual confirmation of a defective portion. In a substrate inspecting step, first, a 3D inspection is performed, followed by execution of 2D inspection, whereby a 2D picked-up image of the portion of a pad determined to be defective can be displayed on a larger scale simultaneously with the end of inspection, thereby providing an environment for efficient visual confirmation of the defect. Further, by subjecting a raw substrate to measurement at the time of preparing inspection data, a relation between an original height measurement reference generated automatically by the inspection system and the height of a pad upper surface is checked, whereby it is possible to measure the height and volume of printed solder based on the pad upper surface.06-14-2012
20130023068MANUFACTURE OF PHOTOVOLTAIC MODULE COMPRISING CELL ASSEMBLY - The present invention relates to the manufacture of a photovoltaic cell panel, said manufacture comprising the steps of: a) obtaining photovoltaic (PV) films that are each intended for a cell and are placed onto a front surface of a metal substrate; b) applying at least one conductive film (CG, CND) onto each front surface of a photovoltaic film; c) cutting up the substrate (SUB) so as to isolate the cells from each other; and d) encapsulating (ENC) the cells on a common mounting. According to the invention, steps d) and c) are reversed, so step d) relates to encapsulating the front surface of the substrate before step c), cutting the substrate up by the rear surface thereof. Additionally,—in step b), an area of the conductive film is extended over the substrate so that the conductive film simultaneously makes contact with the front surface of the photovoltaic film and the front surface of the substrate, and—in step c), the substrate is cut up so as to avoid short-circuiting between the photovoltaic cells, at least under the above-mentioned area of the conductive film and over a substrate width less than the width of the area.01-24-2013
20130171749PACKAGE METHOD FOR ELECTRONIC COMPONENTS BY THIN SUBSTRATE - Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.07-04-2013
20130171750PACKAGE METHOD FOR ELECTRONIC COMPONENTS BY THIN SUBSTRATE - Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.07-04-2013
20130171751PACKAGE METHOD FOR ELECTRONIC COMPONENTS BY THIN SUBSTRATE - Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.07-04-2013
20130171752Method for Collective Fabrication of 3D Electronic Modules Comprising Only Validated PCBs - A method for collective fabrication of 3D electronic modules comprises: the fabrication of a stack of reconstructed wafers, comprising validated active components, this stack including a redistribution layer; the fabrication of a panel of validated passive printed circuits which comprises: fabrication of a panel of printed circuits, electrical testing of each printed circuit, fitting of the validated printed circuits to an adhesive substrate, moulding of the mounted circuits in an electrically insulating resin, called coating resin and polymerization of the resin, removal of the adhesive substrate, a panel comprising only validated printed circuits being thus obtained; bonding the panel with a stack (of reconstructed wafers); cutting the “stack of panel” assembly for the purpose of obtaining the 3D electronic modules.07-04-2013
20130143334METHOD OF ENHANCING COLOR RENDERING INDEX OF A WHITE LED - The present invention discloses a method of enhancing color rendering index (CRI) of a white light emitting diode (LED), and particularly discloses a method of enhancing CRI of a white LED by adding a blue-green (or aquamarine) phosphor which can emit a light having wavelength of 485 nm to 519 nm.06-06-2013
20130177998METHOD OF MANUFACTURING LIGHT EMITTING DEVICE AND PHOSPHOR-CONTAINING FLUID RESIN DISPENSING APPARATUS - There is provided a method of manufacturing a light emitting diode (LED) package, including discharging a predetermined discharge amount of a phosphor-containing fluid resin to at least one LED package, and measuring color coordinates of white light emitted from the at least one LED package. The method also includes adjusting a discharge amount of the phosphor-containing fluid resin, based on a deviation between the measured color coordinates and target color coordinates, so as to obtain the target color coordinates. The method further includes discharging the adjusted discharge amount of the phosphor-containing fluid resin to another LED package;, and curing the phosphor-containing fluid resin dispensed to the another LED package.07-11-2013
20130102093METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device which solves a problem with a burn-in process where current and voltage are applied to finished semiconductor devices at high-temperature. The method uses an organic multilayer wiring substrate for a burn-in board in which power supply/grounding wiring is formed with microscopic openings formed at least almost all over the areas around sockets over the front or back surface of the substrate. For increasing the supply voltage and reference voltage for the burn-in board and other purposes, whenever possible, signal wires are disposed in inner wiring layers of the board. The related-art burn-in board which has a solid or blanket-type conductor pattern in an outermost layer as wiring for supply or reference voltage may cause an insulating protective film over the metal wiring to peel due to weak adhesion between the wiring and film when thermal cycles are repeated. The method solves the problem.04-25-2013
20130115722METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The manufacturing efficiency of semiconductor devices is improved. A plurality of external terminals (leads) electrically coupled with a semiconductor chip, and contact regions of a plurality of terminals (test terminals) are brought into contact with each other, respectively. This establishes an electrical coupling between the semiconductor chip and a test circuit. Thus, an electrical test is performed. Herein, the terminals are to be repeatedly used in the electrical test of a plurality of semiconductor devices. Whereas, the contact region of the terminal includes a core material formed of a first alloy, and a metal film covering the core material. Further, the metal film is formed of a second alloy higher in hardness than the first alloy.05-09-2013
20130130411Interleaf for Leadframe Identification - A method of making an IC device includes providing a stack of leadframe sheets each including a plurality of leadframes and an interleaf member interposed between adjacent ones of the leadframe sheets. The interleaf members include indicia that identifies the leadframes sheets. The stack of leadframe sheets is loaded onto an assembly machine. A first interleaf member is removed from the first leadframe sheet. The first leadframe sheet is transferred onto a mounting surface of the assembly machine. Semiconductor die are attached to leadframes on the first leadframe sheet. The method can include reading the indicia from the first interleaf member to determine a part number and lead finish for the first leadframe sheet, verifying the part number for the first leadframe sheet by comparing to a build list, and transferring the first leadframe sheet onto a mounting surface of the assembly machine only if the part number is verified.05-23-2013
20100279439AUTOMATED SUBSTRATE HANDLING AND FILM QUALITY INSPECTION IN SOLAR CELL PROCESSING - The present invention generally provides an apparatus and a method for automatically calibrating the placement of fragile substrates into a substrate carrier. Embodiments of the present invention also provide an apparatus and a method for inspecting the fragile substrates prior to processing to prevent damaged substrates from being further processed or broken in subsequent transferring steps. Embodiments of the invention also generally provide an apparatus and a method for determining the alignment and orientation substrates that are to be delivered into or removed from a substrate carrier. Embodiments of the invention further provide an apparatus and method for accurately positioning the substrate carrier for substrate loading. The substrate carriers are generally used to support a batch of substrates that are to be processed in a batch processing chamber.11-04-2010
20080206904METHOD OF MAKING PCB CIRCUIT MODIFICATION FROM MULTIPLE TO INDIVIDUAL CHIP ENABLE SIGNALS - A semiconductor package is disclosed having a single CE signal during electrical test and a plurality of CE signals during normal operation thereafter. After electrical testing of the memory die during fabrication, the electrical traces carrying the single CE signal from the memory test pad matrix to each of the memory die may be severed. Severing the electrical traces from the memory test pad matrix electrically isolates the multiple electrical traces between the controller die and memory die, and allows separate and individual CE signals between the controller die and memory die during normal usage of the memory die.08-28-2008
20080199979SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Method of manufacturing a semiconductor device, including: preparing a TAB tape featuring an insulating tape having a device hole and a plurality of holes, a plurality of leads formed on a surface of the tape and extending at one end into the device hole and at the other end into the holes, slits provided inside arrangements of columns of holes, and a warp prevention reinforcement insulating film to hold the leads between it and the tape; connecting front ends of the leads to the electrodes of the chip; forming an encapsulant to enclose the chip, the leads and a portion of the tape; forming thick bump electrodes on that surface side of the leads running through the holes to which the semiconductor chip is connected; performing an electric characteristic test, using the bump electrodes as measuring terminals; and cutting the TAB tape to a predetermined shape.08-21-2008
20110237004CHIPSTACK PACKAGE AND MANUFACTURING METHOD THEREOF - A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.09-29-2011
20110312108SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - Various embodiments of the present invention include a semiconductor device and a fabrication method therefor, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefor, in which downsizing and cost reduction can be realized.12-22-2011
20120015458MOUNTING APPARATUS AND MOUNTING METHOD - Provided is a mounting apparatus which mounts a chip component on a circuit pattern on a circuit board having a plurality of circuit patterns formed thereon. The mounting apparatus is provided with a plurality of bonding tools each of which mounts the chip component on each of the circuit patterns on the circuit board. Each bonding tool is provided with, within a region on the circuit board where the chip component is to be mounted, an exclusive mounting region where only each bonding tool can mount the chip component, and a common mounting region where both the bonding tool and the adjacent bonding tool can mount the chip component. A mounting method is also provided. The mounting tact time of the chip components can be shortened even in case where a plurality of circuit patterns are formed on the circuit board and a failure circuit pattern is included among the circuit patterns which have been formed.01-19-2012
20120015457PCB-MOUNTED INTEGRATED CIRCUITS - A method and apparatus (01-19-2012
20120015456SYSTEM AND METHOD FOR PROVIDING ACCESS TO AN ENCAPSULATED DEVICE - A method for providing access to a feature on a device wafer, and located outside an encapsulation region is described. The method includes forming a cavity in the lid wafer, aligning the lid wafer with the device wafer so that the cavity is located substantially above the feature, and removing material substantially uniformly from the bottom surface of the lid wafer, until an aperture is formed at the cavity, over the feature on the device wafer. By removing material from the lid wafer in a substantially uniform manner, difficulties with the prior art procedure of saw cutting, such as alignment and debris generation, are avoided.01-19-2012
20120028380DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE AND METHOD FOR PRODUCING THE FILM, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - The present invention relates to a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material having an asperities-formed surface, and a pressure-sensitive adhesive layer laminated on the base material, and a film for semiconductor back surface laminated on the pressure-sensitive adhesive layer of the dicing tape, in which the dicing tape has a haze of at most 45%.02-02-2012
20120045853SER Testing for an IC Chip Using Hot Underfill - A method for detecting soft errors in an integrated circuit (IC) due to transient-particle emission, the IC comprising at least one chip and a substrate includes mixing an epoxy with a radioactive source to form a hot underfill (HUF); underfilling the chip with the HUF; sealing the underfilled chip; measuring a radioactivity of the HUF at an edge of the chip; measuring the radioactivity of the HUF on a test coupon; testing the IC for soft errors by determining a current radioactivity of the HUF at the time of testing based on the measured radioactivity; and after the expiration of a radioactive decay period of the radioactive source, using the IC in a computing device by a user.02-23-2012
20120083053METHOD FOR ALIGNING WAFER STACK - A method for aligning a wafer stack includes providing a wafer stack including a top wafer with a top mark and a bottom wafer with a bottom mark in particular the top mark and the bottom mark capable of corresponding to each other; adjusting a relative position between the top wafer and the bottom wafer so that the top mark and the bottom mark are in contact with each other; applying an electrical signal on the top mark to obtain an electrical reading and optimizing the electrical reading to substantially align the wafer stack.04-05-2012
20130210174RESIN COATING DEVICE AND RESIN COATING METHOD - In a resin coating used for manufacturing an LED package including an LED element coated with resin containing phosphor, a light-transmitting member test-coated with resin for an emission characteristic measurement on a light-transmitting member placing section including a light source unit, a deviation between a measurement result of an emission characteristic of light emitted from the resin coated on the light-transmitting member measured by an emission characteristic measurement unit by irradiating the resin with excitation light emitted from the light source unit and a prescribed emission characteristic is obtained, and an appropriate resin coating amount of the resin to be coated on the LED element for an actual production is derived based on the deviation.08-15-2013

Patent applications in class Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor