Class / Patent application number | Description | Number of patent applications / Date published |
438012000 | And removal of defect | 6 |
20130115721 | EPITAXIAL FILM GROWTH IN RETROGRADE WELLS FOR SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device. A substrate is provided and includes a dielectric layer and a mask layer, which is patterned and developed. A plurality of trenches is created within the dielectric material by a retrograde etching process. The plurality of trenches is subsequently overfilled with a material by heteroepitaxial growth with aspect ratio trapping. The material includes at least one of germanium, a Group III-V compound, or a combination of two or more thereof. The overfilled plurality of trenches is then planarized. | 05-09-2013 |
20130295697 | Tj TEMPERATURE CALIBRATION, MEASUREMENT AND CONTROL OF SEMICONDUCTOR DEVICES - A semiconductor device, such as a semiconductor die, is disclosed including embedded temperature sensors for scanning the junction temperature, Tj, at one or more locations of the semiconductor die while the die is operating. Once a temperature of a hot spot is detected that is above a temperature specified for the die or package containing the die, the die/package may be discarded. Alternatively, the functionality of the die may be altered in a way that reduces the temperature of the hot spots. | 11-07-2013 |
20150311162 | Dicing Structures for Semiconductor Substrates and Methods of Fabrication Thereof - Dicing structures for semiconductor substrates and methods of fabrication thereof are described. In one embodiment, a semiconductor wafer includes a first chip disposed in a substrate, a second chip disposed adjacent the first chip and disposed in the substrate, and a dicing street disposed between the first and the second chip. A first and a second metal level are disposed over the dicing street, wherein the second metal level is disposed above the first metal level. A first alignment mark is disposed in the first metal level above a first portion of the dicing street, and first metal features disposed in the second metal level above the first portion of the dicing street. | 10-29-2015 |
20160042979 | MULTI-CHIP MODULE WITH REWORK CAPABILITY - Multi-chip underfills and methods for multi-chip module fabrication include connecting one or more chips to a substrate with one or more electrical connections; partially curing an underfill material such that the underfill provides structural support to the electrical connections; electrically testing the one or more chips to identify one or more defective chips; and replacing the one or more defective chips. | 02-11-2016 |
20160379898 | IMPLEMENTING RESISTANCE DEFECT PERFORMANCE MITIGATION USING TEST SIGNATURE DIRECTED SELF HEATING AND INCREASED VOLTAGE - A method and system are provided for implementing resistive defect performance mitigation for integrated circuits. A test is generated for identifying resistive defects. A first self heating repair process is performed for repairing resistive defects. Testing is performed to identify a mitigated resistive defect and a functional integrated circuit. Responsive to identifying a resistive defect not being mitigated and a functional integrated circuit, a second repair process is performed, then testing is performed again. | 12-29-2016 |
20160379899 | IMPLEMENTING RESISTANCE DEFECT PERFORMANCE MITIGATION USING TEST SIGNATURE DIRECTED SELF HEATING AND INCREASED VOLTAGE - A method and system are provided for implementing resistive defect performance mitigation for integrated circuits. A test is generated for identifying resistive defects. A first self heating repair process is performed for repairing resistive defects. Testing is performed to identify a mitigated resistive defect and a functional integrated circuit. Responsive to identifying a resistive defect not being mitigated and a functional integrated circuit, a second repair process is performed, then testing is performed again. | 12-29-2016 |