| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438010000 | Electrical characteristic sensed | 47 |
| 20130084656 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - An automatic analyzer detects voltage applied across electrodes, and judges whether voltage value falls within set voltage range. When the detected voltage value is lower than minimum value of set voltage range, the analyzer calculates the deficient amount of base solution based on the detected voltage value, controls a valve to supply the deficient amount of base solution, then, performs operation control of the valve so as to keep the prescribed amount of plating solution in plating solution tank, and discharges plating solution. When the detected voltage value is higher than maximum value of set voltage range, the analyzer calculates the excess amount of base solution based on the detected voltage value, controls a valve, and supplies pure water into the tank so that the base solution concentration falls within prescribed range to dilute plating solution, then controls a valve, and discharges plating solution so as to keep prescribed amount. | 04-04-2013 |
| 20100093113 | SEMICONDUCTOR MANUFACTURING APPARATUS - A semiconductor manufacturing apparatus includes: an ion source and a beam line for introducing an ion beam into a target film which is formed over a wafer with an insulating film interposed therebetween; a flood gun for supplying the target film with electrons for neutralizing charges contained in the ion beam; a rotating disk for subjecting the target film to mechanical scanning of the ion beam in two directions composed of r-θ directions; a rear Faraday cage for measuring the current density produced by the ion beam; a disk-rotational-speed controller and a disk-scanning-speed controller for changing the scanning speed of the target film; and a beam current/current density measuring instrument for controlling, according to the current density, the scanning speed of the target film. | 04-15-2010 |
| 20090325323 | AQUEOUS DISPERSION FOR CHEMICAL MECHANICAL POLISHING, PRODUCTION METHOD THEREOF, AND CHEMICAL MECHANICAL POLISHING METHOD - There is provided an aqueous dispersion for chemical mechanical polishing that comprises abrasives comprising:
| 12-31-2009 |
| 20090042321 | APPARATUS AND METHOD FOR PLASMA DOPING - Gas supplied to gas flow passages of a top plate from a gas supply device by gas supply lines forms flow along a vertical direction along a central axis of a substrate, so that the gas blown from gas blow holes can be made to be uniform, and a sheet resistance distribution is rotationally symmetric around a substrate center. | 02-12-2009 |
| 20100151596 | METHOD FOR ALIGNING OPTICAL PACKAGES - A method is given for aligning an optical package comprising a laser, a wavelength conversion device, at least one adjustable optical component and at least one actuator. The adjustable optical component may be moved to a command position by applying a pulse width modulated signal to the actuator. The command position represents an optimized alignment of the laser and wavelength conversion device. The actual position of the adjustable may be measured by measuring an output of a position measuring circuit, which may measure the voltage amplitude of an oscillation in a resonator tank circuit during an “off” period of the pulse-width modulated signal. The resonator tank circuit may comprise a capacitive element electrically coupled to the electrically conductive coil. The pulse-width modulated signal may then be adjusted to compensate for any difference in the actual position and the command position of the adjustable optical component. Additional embodiments are disclosed and claimed. | 06-17-2010 |
| 20110281377 | METHOD FOR SEPARATING AND TRANSFERRING IC CHIPS - [Problems] There are provided a chip separation method and a chip transfer method using features of dry etching. | 11-17-2011 |
| 20090053836 | Method of wafer level transient sensing, threshold comparison and arc flag generation/deactivation - A method for processing a semiconductor wafer in a plasma reactor comprises sensing transient voltages or currents on a conductor coupled to the wafer and providing a first comparator for comparing the transient voltages or currents with a threshold level stored in the comparator. The method further includes transmitting from the comparator an arc flag signal whenever a transient voltage or current is sensed that exceeds the threshold level, and deactivating the power generator in response to the arc flag signal. | 02-26-2009 |
| 20090142860 | SYSTEM AND METHOD FOR ENHANCED CONTROL OF COPPER TRENCH SHEET RESISTANCE UNIFORMITY - A method is disclosed for controlling the sheet resistance of copper trenches formed on semiconductor wafers. The method includes forming a plurality of copper-filled trenches on a wafer, measuring the sheet resistance of each of the plurality of copper-filled trenches, and comparing the measured sheet resistance values to a predetermined sheet resistance value. Photolithography steps performed on subsequent wafers are adjusted according to a difference between the measured sheet resistance values and the predetermined value. In one embodiment, this adjustment takes the form of adjusting a photolithographic extension exposure energy to thereby adjust the cross-section of the resulting trenches. | 06-04-2009 |
| 20090162953 | PREDICTING DOSE REPEATABILITY IN AN ION IMPLANTATION - An approach for predicting dose repeatability in an ion implantation is described. In one embodiment, an ion source is tuned to generate an ion beam with desired beam current. Beam current measurements are obtained from the tuned ion beam. The dose repeatability is predicted for the ion implantation as a function of the beam current measurements. | 06-25-2009 |
| 20090081816 | LIGHT EMITTING DEVICE AND PRODUCTION SYSTEM OF THE SAME - To provide a light emitting device without nonuniformity of luminance, a correcting circuit for correcting a video signal supplied to each pixel to a light emitting device. The correcting circuit is stored with data of a dispersion of a characteristic of a driving TFT among pixels and data of a change over time of luminance of a light emitting element. Further, by correcting a video signal inputted to the light emitting device in conformity with a characteristic of the driving TFT of each pixel and a degree of a deterioration of the light emitting element based on the over-described two data, nonuniformity of luminance caused by a deterioration of an electroluminescent layer and nonuniformity of luminance caused by dispersion of a characteristic of the driving TFT are restrained. | 03-26-2009 |
| 20090068769 | Method and Apparatus for Plasma Processing - An object of the invention is to provide a method and an apparatus for plasma processing which can accurately monitor an ion current applied to the surface of a sample. | 03-12-2009 |
| 20100227420 | INDUCTIVELY COUPLED PLASMA REACTOR HAVING RF PHASE CONTROL AND METHODS OF USE THEREOF - Embodiments of the present invention generally provide an inductively coupled plasma (ICP) reactor having a substrate RF bias that is capable of control of the RF phase difference between the ICP source (a first RF source) and the substrate bias (a second RF source) for plasma processing reactors used in the semiconductor industry. Control of the RF phase difference provides a powerful knob for fine process tuning. For example, control of the RF phase difference may be used to control one or more of average etch rate, etch rate uniformity, etch rate skew, critical dimension (CD) uniformity, and CD skew, CD range, self DC bias control, and chamber matching. | 09-09-2010 |
| 20100178717 | METHOD OF MANUFACTURING MEMS DEVICE - A method of manufacturing an MEMS device includes: forming a covering structure having an MEMS structure and a hollow portion, which is located on a periphery of the MEMS structure and is opened to an outside, on a substrate; and performing surface etching for the MEMS structure in a gas phase by supplying an etching gas to the periphery of the MEMS structure from the outside. | 07-15-2010 |
| 20120196386 | METHOD OF MANUFACTURING SEMICONDUCTOR MODULE - A method of manufacturing a semiconductor module is provided. The method includes forming semiconductor chips on a bare substrate, performing a burn-in process on the bare substrate including the semiconductor chips, sorting semiconductor chips that exceed a predetermined level of operability determined by testing electrical driving in the semiconductor chips on the burned-in bare substrate, separating the semiconductor chips from one another by cutting the bare substrate, and directly mounting the module semiconductor chips on a module substrate. | 08-02-2012 |
| 20080227226 | Semiconductor substrate, manufacturing method of a semiconductor device and testing method of a semiconductor device - A semiconductor substrate eliminates a restriction caused by a width of scribe lines so as to increase a number of semiconductor elements formed on the semiconductor substrate. A plurality of semiconductor element areas are formed by forming a plurality of unit exposed and printed areas, each of which contains the semiconductor element areas. A first scribe line extends between the semiconductor element areas formed within the unit exposed and printed area. A second scribe line extends between the unit exposed and printed areas. A width of the first scribe line is different from a width of the second scribe line. | 09-18-2008 |
| 20100216260 | PLASMA ETCHING METHOD AND APPARATUS, AND METHOD OF MANUFACTURING LIQUID EJECTION HEAD - The plasma etching method includes: an etching step of placing, on a stage in a chamber, a substrate in which a prescribed mask pattern is formed by a protective film on a surface of a material to be etched, generating a plasma in the chamber while supplying processing gas to the chamber, and etching a portion of the material corresponding to an opening portion in the mask pattern; a voltage measurement step of, during the etching in the etching step, measuring a voltage at the surface of the material on a side where the mask pattern is formed, through a conductive member that is placed in contact with the surface of the material on the side where the mask pattern is formed; and a control step of controlling an etching condition in the etching step in accordance with a measurement result obtained in the voltage measurement step. | 08-26-2010 |
| 20120244645 | ELECTROSTATIC POST EXPOSURE BAKE APPARATUS AND METHOD - An Electrostatic Post Exposure Bake (EPEB) subsystem comprising an Electrostatic Bake Plate (EBP) configured in a processing chamber in an EPEB subsystem, wherein the EPEB wafer comprises an exposed masking layer having unexposed regions and exposed regions therein and the EPEB wafer is developed using the EBP. | 09-27-2012 |
| 20090215202 | CONTROLLED EDGE RESISTIVITY IN A SILICON WAFER - An epitaxial silicon wafer is produced with a resistivity in the area adjacent the edge that is greater or less than the resistivity adjacent the center. The wafer may be manufactured by a method wherein one or more process parameters are adjusted during deposition of epitaxial layer to control the edge resistivity. Such process parameters may include using a non-homogeneous temperature and/or a process reactant gas flow across the front surface of the wafer. | 08-27-2009 |
| 20080248599 | Rapid Thermal Anneal Equipment and Method Using Sichrome Film - A method of determining the degree of calibration of an RTP chamber ( | 10-09-2008 |
| 20110136270 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, the semiconductor device including an integrated circuit having plural connection terminals arranged on a predetermined local region of the integrated circuit, plural metal bumps, and a wiring layer connected to at least a portion of the connection terminals via the plural metal bumps, the method includes the steps of a) measuring an impedance value of the predetermined local region of the integrated circuit, b) determining whether the measured impedance value matches a predetermined impedance value, c) determining positions of the plural metal bumps in accordance with the determination result of step b), d) forming the plural metal bumps on the positions determined in step c), and e) forming the wiring layer on the plural metal bumps. | 06-09-2011 |
| 20120309117 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device wherein a semiconductor element is sealed with mold resin, a MOS structure is on an upper side of the semiconductor chip, and a PN junction region is on a back side of the semiconductor chip, comprises: obtaining an in-plane distribution of impurity concentration of the PN junction region in the semiconductor chip before encapsulation so that an in-plane distribution of breakdown voltage and leakage current of the semiconductor chip become uniform after encapsulation; forming the PN junction region having the obtained in-plane distribution of impurity concentration on the back side of the semiconductor chip; and sealing the semiconductor chip with the resin after forming the PN junction region. | 12-06-2012 |
| 20110117682 | APPARATUS AND METHOD FOR PLASMA PROCESSING - Disclosed is an apparatus and method for plasma processing, which facilitates to constantly control a RF voltage supplied to a substrate supporting member by precisely detecting an inductive RF voltage induced to the substrate supporting member for a plasma, the apparatus comprising: a substrate supporting member for supporting a substrate, installed in a reaction room of a processing chamber; a RF generator for supplying a RF voltage to the substrate supporting member so as to form plasma in the reaction room; and a matching device for matching impedance of the RF voltage to be supplied to the substrate supporting member from the RF generator, wherein the matching device comprises: a matching unit for matching the impedance of RF voltage; and an inductive RF detecting unit which an inductive RF detecting voltage by removing noise frequency elements except a waveform of the RF voltage from a waveform of an inductive RF voltage induced to the substrate supporting member, and supplies the detected inductive RF detecting voltage to the RF generator so as to control the RF voltage. | 05-19-2011 |
| 20110306153 | METHOD OF MANUFACTURING MEMS DEVICE - A method of manufacturing an MEMS device includes: forming a covering structure having an MEMS structure and a hollow portion, which is located on a periphery of the MEMS structure and is opened to an outside, on a substrate; and performing surface etching for the MEMS structure in a gas phase by supplying an etching gas to the periphery of the MEMS structure from the outside. | 12-15-2011 |
| 20090325322 | Non-Destructive Laser Optical Integrated Circuit Package Marking - A method is provided for laser optically marking integrated circuit (IC) packages in a non-destructive manner. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. An acute angle is defined between a laser optical path and an IC package planar surface. The IC package surface is scanned with a laser, and in response to ablating the IC package surface, a legible mark on the planar surface. | 12-31-2009 |
| 20120003760 | GLITCH CONTROL DURING IMPLANTATION - An ion implantation system and method are disclosed in which glitches in voltage are minimized by modifications to the power system of the implanter. These power supply modifications include faster response time, output filtering, improved glitch detection and removal of voltage blanking. By minimizing glitches, it is possible to produce solar cells with acceptable dose uniformity without having to pause the scan each time a voltage glitch is detected. For example, by shortening the duration of a voltage to about 20-40 milliseconds, dose uniformity within about 3% can be maintained. | 01-05-2012 |
| 20120009691 | METHOD OF MANUFACTURING AN ORGANIC LIGHT EMITTING DISPLAY - A pixel includes an organic light emitting diode, a first transistor having a source coupled to a first power source, a control gate coupled to a first node, and a drain coupled to a second node, wherein the first transistor includes a floating gate and an insulating layer between the floating gate and the control gate, a second transistor having a source coupled to a data line, a drain coupled to the first node, and a gate coupled to a scan line, a third transistor having a source coupled to the second node, a drain coupled to the organic light emitting diode, and a gate coupled to one of a light emitting control line and the scan line, and a capacitor coupled between the first power source and the first node. | 01-12-2012 |
| 20120129277 | METHODS AND APPARATUSES FOR DETERMINING THICKNESS OF A CONDUCTIVE LAYER - Methods and apparatuses for calibrating eddy current sensors. A calibration curve is formed relating thickness of a conductive layer in a magnetic field to a value measured by the eddy current sensors or a value derived from such measurement, such as argument of impedance. The calibration curve may be an analytic function having infinite number terms, such as trigonometric, hyperbolic, and logarithmic, or a continuous plurality of functions, such as lines. High accuracy allows the omission of optical sensors, and use of eddy current sensors for endpoint detection, transition call detection, and closed loop control in which a process parameter is changed based on the measured magnetic flux density change in one or more processing zones. | 05-24-2012 |
| 20120115257 | FILM FORMING METHOD AND FILM FORMING APPARATUS - A film forming process is performed on a substrate in a deposition chamber. A first electrode is provided in the deposition chamber and is grounded. A second electrode is provided in the deposition chamber to face the first electrode. A radio frequency power supply supplies radio frequency power to the second electrode. A DC power supply supplies a DC bias voltage to the second electrode. A control unit adjusts a bias voltage to be less than the potential of the second electrode when the radio frequency power is supplied, but the bias voltage is not supplied. In this way, it is possible to improve film quality while preventing a reduction in the deposition rate of a film during deposition. | 05-10-2012 |
| 20090130783 | METHOD OF FABRICATING AN ULTRA-SMALL CONDENSER MICROPHONE - In the present invention, a semiconductor substrate wherein a plurality of MEMS microphones is formed is disposed opposed to a discharge electrode in a state of being stuck on a sheet. Electretization of a dielectric film provided in the MEMS microphone is performed by irradiating the dielectric film between a fixed electrode and a vibration film provided in the MEMS microphone with ions resulting from a corona discharge of the discharge electrode in a state that a predetermined potential difference is applied to the fixed electrode and the vibration film and fixing charges based on the ions to the dielectric film. The electretization is successively performed to each MEMS microphone on the semiconductor substrate by relatively moving the semiconductor substrate and the discharge electrode. Therefore, electretization of the dielectric film in the MEMS microphone chip is realized using a low-cost and simple fabricating equipment and productivity can be enhanced. | 05-21-2009 |
| 20120315711 | Adjusting Capacitance of Capacitors without Affecting Die Area - According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor. | 12-13-2012 |
| 20100190273 | METHOD FOR MANUFACTURING HIGH-FREQUENCY SIGNAL TRANSMISSION CIRCUIT AND HIGH-FREQUENCY SIGNAL TRANSMISSION CIRCUIT DEVICE - A method for manufacturing a high-frequency signal transmission circuit includes the steps of forming a groove to surround a first region on a semiconductor substrate, filling the groove with a stopper material, forming a high-frequency transmission line on the semiconductor substrate so that the transmission line extends over the first region, and etching the first region of the semiconductor substrate using the stopper material as an etching stopper to form a recess in the first region. | 07-29-2010 |
| 20090061542 | Method and apparatus for diagnosing status of parts in real time in plasma processing equipment - Apparatus and methods for diagnosing status of a consumable part of a plasma reaction chamber, the consumable part including at least one conductive element embedded therein. The method includes the steps of: coupling the conductive element to a power supply so that a bias potential relative to the ground is applied to the conductive element; exposing the consumable part to plasma erosion until the conductive element draws a current from the plasma upon exposure of the conductive element to the plasma; measuring the current; and evaluating a degree of erosion of the consumable part due to the plasma based on the measured current. | 03-05-2009 |
| 20090061541 | SEMICONDUCTOR FABRICATION SYSTEM, AND FLOW RATE CORRECTION METHOD AND PROGRAM FOR SEMICONDUCTOR FABRICATION SYSTEM - Zero point shift based on thermal siphon effect occurring actually when a substrate is processed is detected accurately and corrected suitably. The semiconductor fabrication system comprises a gas supply passage ( | 03-05-2009 |
| 20120083052 | Flexible Packaging for Chip-on-Chip and Package-on-Package Technologies - In one embodiment, a packaging solution for an application integrated circuit (IC) and one or more other ICs is provided. The packaging solution may support both chip-on-chip packaging of the application IC (in flip-chip connection to a package substrate) and other ICs (in non-flip chip orientation), and package-on-package packaging of the application IC and the other ICs. The package substrate may include a first set of pads proximate to the application IC to support chip-on-chip connection to the other ICs. The pads may be connected to conductors that extend underneath the application IC, to connect to the application IC. A second set of pads may be connected to package pins for package-on-package solutions. If the chip-on-chip solution proves reliable, support for the package-on-package solution may be eliminated and the package substrate may be reduced in size. | 04-05-2012 |
| 20120083051 | APPARATUS AND METHODS FOR ELECTRICAL MEASUREMENTS IN A PLASMA ETCHER - Apparatus and methods for plasma etching are disclosed. In one embodiment, an apparatus for etching a plurality of features on a wafer comprises a chamber, a feature plate disposed in the chamber for holding the wafer, a gas channel configured to receive a plasma source gas, an anode disposed above the feature plate, a cathode disposed below the feature plate, a radio frequency power source configured to provide a radio frequency voltage between the anode and the cathode so as to generate plasma ions from the plasma source gas, a pump configured to remove gases and etch particulates from the chamber, and a clamp configured to clamp the wafer against the feature plate. The clamp includes at least one measurement hole for passing a portion of the plasma ions to measure a DC bias of the feature plate. | 04-05-2012 |
| 20120276661 | HIGH SENSITIVITY EDDY CURRENT MONITORING SYSTEM - A method of chemical mechanical polishing a substrate includes polishing a metal layer on the substrate at a polishing station, monitoring thickness of the metal layer during polishing at the polishing station with an eddy current monitoring system, and controlling pressures applied by a carrier head to the substrate during polishing of the metal layer at the polishing station based on thickness measurements of the metal layer from the eddy current monitoring system to reduce differences between an expected thickness profile of the metal layer and a target profile, wherein the metal layer has a resistivity greater than 700 ohm Angstroms. | 11-01-2012 |
| 20120276662 | EDDY CURRENT MONITORING OF METAL FEATURES - A method of chemical mechanical polishing a substrate includes polishing a plurality of discrete separated metal features of a layer on the substrate at a polishing station, using an eddy current monitoring system to monitor thickness of the metal features in the layer, and controlling pressures applied by a carrier head to the substrate during polishing of the layer at the polishing station based on thickness measurements of the metal features from the eddy current monitoring system to reduce differences between an expected thickness profile of the metal feature and a target profile. | 11-01-2012 |
| 20120329179 | Capacitance modification without affecting die area - According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor. | 12-27-2012 |
| 438011000 | Utilizing integral test element | 4 |
| 20080220544 | METHOD FOR UTILIZING HEAVILY DOPED SILICON FEEDSTOCK TO PRODUCE SUBSTRATES FOR PHOTOVOLTAIC APPLICATIONS BY DOPANT COMPENSATION DURING CRYSTAL GROWTH - A method for using relatively low-cost silicon with low metal impurity concentration by adding a measured amount of dopant before and/or during silicon crystal growth so as to nearly balance, or compensate, the p-type and n-type dopants in the crystal, thereby controlling the net doping concentration within an acceptable range for manufacturing high efficiency solar cells. | 09-11-2008 |
| 20080248600 | METHOD AND DEVICE FOR WAFER BACKSIDE ALIGNMENT OVERLAY ACCURACY - A method for wafer backside alignment overlay accuracy includes forming a buried layer on a front-side of a wafer; forming a conductive layer on the buried layer and patterning a first test structure and a second test structure therein; forming an etch stop layer on the conductive layer; etching through the wafer from the backside to perform an alignment process with the first test structure; and determining an overlay accuracy of the alignment process with the second test structure. The first test structure includes an optical vernier and the second test structure includes an electrical testing structure. | 10-09-2008 |
| 20090291510 | METHOD FOR CREATING WAFER TEST PATTERN - A method for creating a testing pattern for sampling the sheet resistance of a test wafer for tuning an annealing process includes establishing a center point for the wafer and determining a plurality of sample points having a radial displacement from the center point of the wafer and an angular displacement, the radial displacement of successive sample points decreasing in radial distance from one another as the distance from the center point increases and the angular displacement between each successive sample point being constant. | 11-26-2009 |
| 20090035881 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A burn-in input signal input to a burn-in circuit is delivered to an internal circuit through a selector. In response to a control signal from the burn-in circuit, the selector selects either the burn-in input signal or an input signal for operating the internal circuit. In the burn-in test process, a portion of an output signal is monitored to determine the degree of degradation of the internal circuit. | 02-05-2009 |
| 438012000 | And removal of defect | 1 |
| 20130115721 | EPITAXIAL FILM GROWTH IN RETROGRADE WELLS FOR SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device. A substrate is provided and includes a dielectric layer and a mask layer, which is patterned and developed. A plurality of trenches is created within the dielectric material by a retrograde etching process. The plurality of trenches is subsequently overfilled with a material by heteroepitaxial growth with aspect ratio trapping. The material includes at least one of germanium, a Group III-V compound, or a combination of two or more thereof. The overfilled plurality of trenches is then planarized. | 05-09-2013 |
| 438013000 | Altering electrical property by material removal | 4 |
| 20100068831 | Method for wafer trimming for increased device yield - According to an exemplary embodiment, a method for site-specific trimming of a wafer to provide a target parameter value for a plurality of devices on the wafer includes performing a first measurement of a parameter at a subset of the number of devices on the wafer. The method further includes forming a top layer over the wafer after performing the first measurement. The method further includes performing a second measurement of the parameter at the subset of the devices on the wafer after forming the top layer. The method further includes determining an amount of the top layer to remove across the wafer to provide the target parameter value for the devices by utilizing the first and second measurements of the parameter. The method can be utilized to, for example, achieve a more uniform characteristic frequency for bulk acoustic wave (BAW) filters. | 03-18-2010 |
| 20080268555 | SEMICONDUCTOR DEVICE AND ADJUSTING METHOD FOR SEMICONDUCTOR DEVICE - An object of the invention is to provide a semiconductor device and an adjusting method for a semiconductor device wherein power source noises and noises radiated as radio waves can be reduced and power source noises inside the semiconductor device can be cut. The open stub OS | 10-30-2008 |
| 20100167427 | PASSIVE DEVICE TRIMMING - The present invention relates to a method for trimming passive devices during fabrication to account for process variations. More particularly, the present invention relates to a method by which an adjustable device layer comprised within a passive device (e.g., resistor body, capacitor electrodes) can be measured and subsequently trimmed (e.g., etched to reduce size) during processing to correct for process variations. Essentially, an operational parameter is measured for a plurality of passive devices. The measurements are used to form an adjustment map for a region of a semiconductor body (e.g., wafer) comprising information pertaining to operational parameters as a function of spatial coordinates. The adjustment map is utilized by a DMD projector configured to pattern openings into a hardmask configured over the adjustable device layer. The adjustable device layer is then etched in regions not protected by the hardmask, thereby effectively trimming the passive device according to the adjustment map. | 07-01-2010 |
| 20110020958 | METHOD AND SEMICONDUCTOR STRUCTURE FOR MONITORING ETCH CHARACTERISTICS DURING FABRICATION OF VIAS OF INTERCONNECT STRUCTURES - By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective openings may be used for generating a corresponding variation of electrical characteristics of the test metal region. Consequently, by means of the electrical characteristics, respective variations of the etch process may be identified. | 01-27-2011 |
