Class / Patent application number | Description | Number of patent applications / Date published |
438006000 | Interconnecting plural devices on semiconductor substrate | 13 |
20080268553 | Electroless plating apparatus with non-liquid heating source - An electroless plating apparatus is provided. The electroless plating apparatus includes a wafer holder; a chemical dispensing nozzle over the wafer holder; a conduit connected to the chemical dispensing nozzle; and a radiation source over the wafer holder. | 10-30-2008 |
20090004762 | Stacking apparatus and method for stacking integrated circuit elements - A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages. | 01-01-2009 |
20090068766 | OPTICAL ELEMENT MOUNTING METHOD AND OPTICAL ELEMENT MOUNTING DEVICE - An optical element mounting method includes: illuminating ultraviolet light onto a polymer optical waveguide device; under the ultraviolet light illumination, capturing, by an image pickup device, the polymer optical waveguide device including a light incident/exiting position of a waveguide core; and judging, from a difference between bright and dark in a captured image, that a portion brighter than other portions or a portion darker than other portions is the light incident/exiting position of the waveguide core. | 03-12-2009 |
20090081812 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - The present invention is a production method for a semiconductor device equipped with a conductive film with predetermined film thickness on a sidewall of a concave portion formed in an insulating film, and comprises a step of forming the concave portion in the insulation film formed on a semiconductor substrate. Herein, the concave portion is a generic name of a via-hole and a trench. This production method comprises a step of forming a conductive film with film thickness, which is film thickness of a conductive film to be formed in the concave portion, and which is film thickness, calculated based upon the depth of the concave portion and a projected area of the sidewall of said concave portion when viewing the concave portion from the upper surface, and to be formed over the upper surface of the insulating film where the concave portion is formed. In other words, a film is formed taking the variation of configuration of these based upon a projected area of a via-hole or a trench into consideration. | 03-26-2009 |
20090130782 | METHOD AND LINE FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method is provided for manufacturing a semiconductor device that includes a multilayer wiring structure in which insulating layers and wiring layers each with a plurality of conductor lines are alternately stacked on each other. The method includes steps of forming a first wiring layer on a first insulating layer, detecting a defect in the first wiring layer on the first insulating layer, and determining whether or not the defect is to be irradiated with a focused ion beam, according to a detection result. If it is determined that the defect is to be irradiated, the defect is irradiated with a focused ion beam and then a second insulating layer is formed on the first wiring layer disposed on the first insulating layer. If it is determined that the defect is not to be irradiated with a focused ion beam, the second insulating layer is formed on the first wiring layer disposed on the first insulating layer without irradiating the defect. | 05-21-2009 |
20090170221 | Etch residue reduction by ash methodology - Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a second overash operation. The ashing operation is performed prior to etching of an etch stop layer. The operation removes residue from a cavity formed during formation of the interconnect structure and facilitates better CD control without altering the cavity profiles. | 07-02-2009 |
20120122248 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, there is provided a method of manufacturing a semiconductor device having a buffer circuit. In the method, a plurality of semiconductor elements is formed on a semiconductor substrate. The plurality of semiconductor elements are connected in parallel to each other in the buffer circuit. In the method, driving forces of the formed semiconductor elements is evaluated. In the method, one mask is selected from a plurality of masks based on the evaluating. The plurality of masks are formed in advance to have different wiring mask patterns to cause the numbers of semiconductor elements connected in parallel with each other among the plurality of semiconductor elements of the buffer circuit to be different from each other. In the method, a wiring pattern corresponding to the wiring mask pattern is formed by using the selected one mask. | 05-17-2012 |
20120164758 | IC HAVING VIABAR INTERCONNECTION AND RELATED METHOD - An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer. | 06-28-2012 |
20130164863 | SOLAR CELL MODULE MANUFACTURING DEVICE AND SOLAR CELL MODULE MANUFACTURING METHOD - A solar cell module manufacturing device is disclosed. The device includes a wire supply portion, a correction portion, and a cutting portion. The supply portion includes a bobbin and wiring material on the bobbin. The correction portion corrects curvature of the wiring material. The correction portion comprises a first pulley that comes in contact with the wiring material which is drawn from the bobbin. The first pulley comprises at a periphery thereof a first groove. The first groove comprises a first basal surface and a pair of first inclined surfaces which are arranged on both sides of the first basal surface. An inclination angle θ | 06-27-2013 |
20140073068 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition. | 03-13-2014 |
20160148840 | THROUGH SILICON VIAS AND THERMOCOMPRESSION BONDING USING INKJET-PRINTED NANOPARTICLES - Apparatus and method for filling and optionally bumping through-silicon vias (TSVs) in device circuits utilizing inkjet printheads for ejecting sufficiently small droplets of conductive nanoparticle inks into the TSVs. Ejected drops are accurately impinged along the length of each TSV within a substrate being heated to drive evaporation of the solvent carrying the metal nanoparticles into the trenches while not de-encapsulating the particles. Once all TSVs are filled, and optionally bumped, to a desired level while they are being heated then bonding and sintering can be performed, such as utilizing thermocompression bonding to another integrated circuit. | 05-26-2016 |
20160379877 | OPTIMIZED WIRES FOR RESISTANCE OR ELECTROMIGRATION - Optimized metal wires for resistance or electromigration, methods of manufacturing thereof and design methodologies are disclosed. The method includes depositing metal material within openings and on a surface of dielectric material resulting in metal filled openings and a topography of recessed areas aligned with the metal filled openings. The method further includes depositing an alloying material over the metal material, including within the recessed areas. The method further includes planarizing the metal material, leaving the alloying material within the recessed areas. The method further includes diffusing the alloying material into the metal material forming alloyed regions self-aligned with the metal filled openings. | 12-29-2016 |
20180027660 | ELECTRONIC COMPONENT EMBEDDED SUBSTRATE | 01-25-2018 |