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INCLUDING CONTROL RESPONSIVE TO SENSED CONDITION

Subclass of:

438 - Semiconductor device manufacturing: process

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
438007000 Optical characteristic sensed 199
438010000 Electrical characteristic sensed 48
438006000 Interconnecting plural devices on semiconductor substrate 9
Entries
DocumentTitleDate
20130045545TEST MAP CLASSIFICATION METHOD AND FABRICATION PROCESS CONDITION SETTING METHOD USING THE SAME - A test map classification method includes modifying test data by converting to a test map including a wafer identifier, a coordinate, and data on whether a predetermined failure item occurs; calculating similarities of wafer pairs in the test map; performing similarity filtering to reset all the similarities, except for at least one similarity, on the basis of a predetermined wafer; determining whether there are similar wafers by comparing the filtered similarities with a reference value; and classifying spatial patterns using a similar relationship between the wafer pairs when there are similar wafers.02-21-2013
20110177623Active Tribology Management of CMP Polishing Material - An arrangement and method for managing the tribology associated with a chemical mechanical planarization (CMP) process continuously monitors and modifies the properties of a polishing slurry in order to assist in controlling the removal rate associated with the CMP process. The viscosity of slurry as it leaves the CMP system (“spent slurry”) and the material removal rate associated with the semiconductor wafer are measured, and then the viscosity of the incoming slurry is adjusted if the measured material removal rate differs from a desired removal rate. If the removal rate is considered to be too fast, the viscosity of the fresh slurry being dispensed onto polishing pad is decreased; alternatively, if the removal rate is too slow, the viscosity is increased. As an alternative to modifying the viscosity of the slurry (or, perhaps in addition to modifying the viscosity), a lubricant may be added to the slurry to slow down the removal rate.07-21-2011
20110207241Formation method of metallic electrode of semiconductor device and metallic electrode formation apparatus - A formation method of a metallic electrode of a semiconductor device is disclosed. The method includes: acquiring data about surface shape of a surface part of a semiconductor substrate; and causing a deformation device to deform the semiconductor substrate based on the data so that a distance between a cutting plane and the surface part falls within a required accuracy in cutting amount. In deforming the semiconductor substrate, multiple actuators are used as the deformation device. A pitch of the multiple actuators is set to a value that is greater than one-half of wavelength of spatial frequency of a thickness distribution of the semiconductor substrate and that is less than or equal to the wavelength.08-25-2011
20090081810SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus has a fluid supply means 03-26-2009
20120184054MANUFACTURING APPARATUS AND METHOD FOR SEMICONDUCTOR DEVICE - Provided is a semiconductor manufacturing apparatus including: a reaction chamber including a gas supply inlet and a gas exhaust outlet, and into which a wafer is to be introduced; a process gas supply mechanism that supplies process gas into the reaction chamber from the gas supply inlet of the reaction chamber; a wafer retaining member that is arranged in the reaction chamber and that retains the wafer; a heater that heats the wafer retained by the wafer retaining member to a predetermined temperature; a rotation drive control mechanism that rotates the wafer retaining member together with the wafer; a gas exhaustion mechanism that exhausts gas in the reaction chamber from the gas exhaust outlet of the reaction chamber; and a drain that is disposed at a bottom portion near a wall surface in the reaction chamber and that collects and discharges oily silane that drips from the wall surface.07-19-2012
20120244644System and Method for Increasing Productivity of Organic Light Emitting Diode Material Screening - A system and method of increasing productivity of OLED material screening includes providing a substrate that includes an organic semiconductor, processing regions on the substrate by combinatorially varying parameters associated with the OLED device production on the substrate, performing a first characterization test on the processed regions on the substrate to generate first results, processing regions on the substrate in a combinatorial manner by varying parameters associated with the OLED device production on the substrate based on the first results of the first characterization test, performing a second characterization test on the processed regions on the substrate to generate second results, and determining whether the substrate meets a predetermined quality threshold based on the second results.09-27-2012
20130078744HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS OF THIN FILM - A semiconductor wafer, on the surface of which a silicon dioxide base material and an amorphous silicon thin film are formed in this order, is carried into a chamber. An insulated gate bipolar transistor (IGBT) is connected with a power supply circuit to a flash lamp, and the IGBT makes an energization period to the flash lamp to be 0.01 millisecond or more and 1 millisecond or less, consequently making a flash light irradiation time to be 0.01 millisecond or more and 1 millisecond or less. Since a flash heat treatment is performed with a remarkably short flash light irradiation time, the excessive heating of the thin film of amorphous silicon is suppressed and harmful influence such as the exfoliation of the film is prevented.03-28-2013
20130078743Method and Apparatus For Depositing A Layer On A Semiconductor Wafer by Vapor Deposition In A Process Chamber - A layer is deposited onto a semiconductor wafer by CVD in a process chamber having upper and lower covers, wherein the wafer front side temperature is measured; the wafer is heated to deposition temperature; the temperature of the upper process chamber cover is controlled to a target temperature by measuring the temperature of the center of the outer surface of the upper cover as the value of a controlled variable of an upper cover temperature control loop; a gas flow rate of process gas for depositing the layer is set; and a layer is deposited on the heated wafer front side during control of the upper cover temperature to the target temperature. A process chamber suitable therefor has a sensor for measuring the upper cover outer surface center temperature and a controller for controlling this temperature to a predetermined value.03-28-2013
20130084654COMBINED SILICON OXIDE ETCH AND CONTAMINATION REMOVAL PROCESS - A method of forming a semiconductor device. A substrate having first and second materials is provided, wherein the second material is occluded by the first material. The substrate is etched using a first non-plasma etch process that etches the first material at a higher rate relative to a rate of etching the second material. The first non-plasma etch process exposes the second material that is overlying at least a portion of the first material. The second material is then etched using a plasma containing a reactive gas, which exposes the at least a portion of the first material. The first material including the at least a portion of the first material that was exposed by etching the second material are etched using a second non-plasma etch process.04-04-2013
20100105153METHOD FOR MEASURING EXPANSION/CONTRACTION, METHOD FOR PROCESSING SUBSTRATE, METHOD FOR PRODUCING DEVICE, APPARATUS FOR MEASURING EXPANSION/CONTRACTION, AND APPARATUS FOR PROCESSING SUBSTRATE - An expansion/contraction measuring apparatus includes a transport section which transports a flexible substrate along a surface of the substrate; a detecting section detecting first and second marks which are formed on the substrate while being separated from each other by a predetermined spacing distance in a transport direction of the substrate and which are moved, in accordance with the transport of the substrate, to first and second detection areas disposed on a transport route for the substrate respectively; a substrate length setting section which sets a length of the substrate along the transport route between the first and second detection areas to a reference length; and a deriving section which derives information about expansion/contraction of the substrate in relation to the transport direction based on a detection result of the first and second marks. Accordingly, the expansion/contraction state of an expandable/contractible substrate is measured highly accurately.04-29-2010
20130029433PROCESS CONDITION MEASURING DEVICE - An instrument comprises a substrate, a plurality of sensors distributed at positions across the substrate's surface, at least one electronic processing component on the surface, electrical conductors extending across the surface and connected to the sensors and processing component, and a cover disposed over the sensors, processing component and conductors. The cover and substrate have similar material properties to a production substrate. The cover is configured to electromagnetically shield the sensors, conductors, or processing component. The instrument has approximately the same thickness and/or flatness as the production substrate. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.01-31-2013
20100136714Device for processing substrate and method of manufacturing semiconductor device - Provided is a substrate processing apparatus and a method of manufacturing a semiconductor device, which are hard to cause a defect in processing a substrate owing to that a pressure inside a process chamber is not kept constant, and which enable a better processing of a substrate. The substrate processing apparatus has: a process chamber for processing a substrate; a reactive gas-supplying module for supplying a reactive gas into the process chamber; a reactive gas-supplying line for supplying the reactive gas from the reactive gas-supplying module into the process chamber; an exhaust line for exhausting an inside of the process chamber; a pump provided in the exhaust line for vacuumizing the inside of the process chamber; a pressure-adjusting valve provided in the exhaust line for adjusting a pressure in the process chamber; a first pressure-measuring instrument for measuring an inside pressure of the process chamber; a second pressure-measuring instrument for measuring a differential pressure between the inside pressure of the process chamber and an outside pressure thereof; and a controller which controls the pressure-adjusting valve based on a value of the inside pressure of the process chamber measured by the first pressure-measuring instrument so as to keep the inside pressure of the process chamber constant, and controls the reactive gas-supplying module based on a value of the differential pressure measured by the second pressure-measuring instrument so as to allow supply of the reactive gas into the process chamber in a case of the inside pressure of the process chamber being smaller than the outside pressure thereof, and so as to preclude supply of the reactive gas into the process chamber in a case of the inside pressure of the process chamber being larger than the outside pressure thereof when processing the substrate.06-03-2010
20090042320METHODS FOR LIQUID TRANSFER COATING OF THREE-DIMENSIONAL SUBSTRATES - Methods here disclosed provide for selectively coating the top surfaces or ridges of a 3-D substrate while avoiding liquid coating material wicking into micro cavities on 3-D substrates. The substrate includes holes formed in a three-dimensional substrate by forming a sacrificial layer on a template. The template includes a template substrate with posts and trenches between the posts. The steps include subsequently depositing a semiconductor layer and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating the 3-D substrate using a liquid transfer coating step for applying a liquid coating material to a surface of the 3-D substrate. The method may further include coating the 3-D substrate by selectively coating the top ridges or surfaces of the substrate. Additional features may include filling the micro cavities of the substrate with a filling material, removing the filling material to expose only the substrate surfaces to be coated, coating the substrate with a layer of liquid coating material, and removing said filling material from the micro cavities of the substrate.02-12-2009
20130089935OVERLAY AND SEMICONDUCTOR PROCESS CONTROL USING A WAFER GEOMETRY METRIC - The present invention may include acquiring a wafer shape value at a plurality of points of a wafer surface at a first and second process level, generating a wafer shape change value at each of the points, generating a set of slope of shape change values at each of the points, calculating a set of process tool correctables utilizing the generated set of slope of shape change values, generating a set of slope shape change residuals (SSCRs) by calculating a slope of shape change residual value at each of the points utilizing the set of process tool correctables, defining a plurality of metric analysis regions distributed across the surface, and then generating one or more residual slope shape change metrics for each metric analysis region based on one or more SSCRs within each metric analysis region.04-11-2013
20130089934Material Delivery System and Method - A system and method for controlling saturated vapor pressure of a precursor material is provided. An embodiment comprises generating a calibration curve and utilizing the calibration curve to control a temperature of the precursor material in order to control its saturated vapor pressure. Alternatively, the calibration curve may be substituted for a real time sensor which can take readings in real time and adjust the temperature and saturated vapor pressure based upon the real time readings.04-11-2013
20090269861Device and method for manufacturing a semiconductor wafer - In order to manufacture an epitaxial wafer having satisfactory flatness over its entire surface, epitaxial layers are experimentally grown upon actual wafer samples under various different layer formation conditions, the thickness profiles are measured over the entire surfaces of these wafers before and after growth of the layers, and, from the differences thereof, layer thickness profiles over the entire areas of the epitaxial layers under the various different layer formation conditions are ascertained and stored. Thereafter, the thickness profile of a substrate wafer is measured over its entire area, this is added to each of the layer thickness profiles under the various different layer formation conditions which have been stored, and the planarities of the manufactured wafers which would be manufactured under these various different layer formation conditions are predicted. And one set of processing conditions is selected which is predicted to satisfy a required flatness specification, and an epitaxial layer is actually grown upon the substrate wafer under these processing conditions.10-29-2009
20120115256METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT - A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.05-10-2012
20120115255METHOD AND APPARATUS FOR DYNAMIC THIN-LAYER CHEMICAL PROCESSING OF SEMICONDUCTOR WAFERS - A semiconductor wafer processing and analysis apparatus (05-10-2012
20090011523Processing method and processing apparatus - A processing method of subjecting at least two stacked films, which comprise a first film and a second film of a target object to be processed, to a removing process by wet etching comprises bringing a first process liquid into contact with the first film of the target object, thereby etching the first film, determining whether the first film has been removed or not, switching the first process liquid to a second process liquid differing in a condition from the first process liquid when it has been determined that the first film has been removed, and bringing the second process liquid into contact with the second film, thereby etching the second film.01-08-2009
20080318344INDICATION OF THE END-POINT REACTION BETWEEN XeF2 AND MOLYBDENUM - Embodiments of the present invention relate to methods and systems for making a microelectromechanical system comprising supplying an etchant to etch one or more sacrificial structures of the system.12-25-2008
20120238040PLASMA ETCHING APPARATUS AND PLASMA ETCHING METHOD - Disclosed is a technology that can obtain high in-plane uniformity of etching while etching a substrate using plasma. A proper temperature of a focus ring capable of performing etching having high in-plane uniformity is identified in advance for each of the multilayers formed on a wafer, the temperature is reflected to a processing recipe as a set temperature, and a heating mechanism and a cooling mechanism are controlled such that the temperature of the focus ring is within an appropriate temperature range including the set temperature thereof for each of the layers to be successively etched. Heat of the focus ring is radiated using a laser and is discharged to a supporting table without using a heater, to independently separate the heating mechanism and the cooling mechanism from each other.09-20-2012
20110136268PROCESSES FOR FORMING ELECTRONIC DEVICES INCLUDING POLISHING METAL-CONTAINING LAYERS - A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed.06-09-2011
20110281376SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD AND STORAGE MEDIUM RECORDING PROGRAM - Disclosed is a substrate processing apparatus including: a substrate processing unit that performs substrate processing by supplying a processing liquid to a substrate to be processed; a positioning mechanism that contacts the sides of the substrate to determine the position of the substrate; a positioning driver that drives the positioning mechanism; a detector that detects the position of the positioning mechanism; a storage unit that stores the position of the positioning mechanism with respect to a reference substrate serving as a reference of the substrate as a reference position information; and an operator that calculates a difference between the reference position information and the position information of the positioning mechanism detected in the detector and calculates measurement information on the processed substrate based on the difference.11-17-2011
20120107968GROUP-III NITRIDE SEMICONDUCTOR LASER DEVICE, METHOD OF FABRICATING GROUP-III NITRIDE SEMICONDUCTOR LASER DEVICE, AND METHOD OF ESTIMATING DAMAGE FROM FORMATION OF SCRIBE GROOVE - A method of fabricating group-III nitride semiconductor laser device includes: preparing a substrate comprising a hexagonal group-III nitride semiconductor and having a semipolar principal surface; forming a substrate product having a laser structure, an anode electrode, and a cathode electrode, where the laser structure includes a semiconductor region and the substrate, where the semiconductor region is formed on the semipolar principal surface; scribing a first surface of the substrate product in a direction of an a-axis of the hexagonal group-III nitride semiconductor to form first and second scribed grooves; and carrying out breakup of the substrate product by press against a second surface of the substrate product, to form another substrate product and a laser bar.05-03-2012
20100112729CONTACT PATTERNING METHOD WITH TRANSITION ETCH FEEDBACK - A method for forming a contact hole in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including measuring a percentage of oxygen in an etching chamber, and controlling the percentage of oxygen in the etching chamber to enlarge a temporary inner diameter near a top of the contact hole.05-06-2010
20090148963Metal Wiring and Method of Manufacturing the Same, and Metal Wiring Substrate and Method of Manufacturing the Same - A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle α in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.06-11-2009
20090239313Integrated Circuit Chip Design Flow Methodology Including Insertion of On-Chip or Scribe Line Wireless Process Monitoring and Feedback Circuitry - Disclosed are embodiments of a design and manufacturing system and an associated method that allow for design analysis and for insertion, during wafer manufacture, of intra-process monitoring circuitry. These embodiments use a library of pre-qualified intra-process monitoring circuits and a cross-correlation table that links different monitoring circuits with different IC chip components. Specifically, these embodiments analyze integrated circuit chip design data to identify the components designed into the chip. Then, one or more intra-process monitoring circuits are selected from the library and the design data is modified to include the selected monitoring circuit(s).09-24-2009
20120202300DIE BONDER INCLUDING AUTOMATIC BOND LINE THICKNESS MEASUREMENT - A method for assembling integrated circuit (IC) devices includes dispensing a die attach adhesive onto a surface of a workpiece using a die bonding system, and placing an IC die on the die attach adhesive at surface of the workpiece to form an IC device. A pre-cure bond line thickness (pre-cure BLT) value is automatically optically measured for the die attach adhesive. The IC device is unloaded from the die bonding system after automatically optically measuring. The method can include comparing the pre-cure BLT value to a pre-cure BLT specification range, and if the pre-cure BLT value is outside the pre-cure BLT specification range, adjusting at least one die attach adhesive dispensing parameter based on the pre-cure BLT value for subsequent assembling. The adjusting can be automatic adjusting and the adjustment can be to the Z height parameter of the bond arm.08-09-2012
20090263919PLASMA OXIDATION PROCESSING METHOD - A plasma oxidation process is performed to form a silicon oxide film on the surface of a target object by use of plasma with an O(10-22-2009
20110201135Method of Reducing Contamination by Providing a Removable Polymer Protection Film During Microstructure Processing - By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process.08-18-2011
20110201134CAPACITIVELY COUPLED PLASMA REACTOR WITH MAGNETIC PLASMA CONTROL - A plasma reactor includes a vacuum enclosure including a side wall and a ceiling defining a vacuum chamber, and a workpiece support within the chamber and facing the ceiling for supporting a planar workpiece, the workpiece support and the ceiling together defining a processing region between the workpiece support and the ceiling. Process gas inlets furnish a process gas into the chamber. A plasma source power electrode is connected to an RF power generator for capacitively coupling plasma source power into the chamber for maintaining a plasma within the chamber. The reactor further includes at least a first overhead solenoidal electromagnet adjacent the ceiling, the overhead solenoidal electromagnet, the ceiling, the side wall and the workpiece support being located along a common axis of symmetry. A current source is connected to the first solenoidal electromagnet and furnishes a first electric current in the first solenoidal electromagnet whereby to generate within the chamber a magnetic field which is a function of the first electric current, the first electric current having a value such that the magnetic field increases uniformity of plasma ion density radial distribution about the axis of symmetry near a surface of the workpiece support.08-18-2011
20110171759Lithographic Apparatus and Device Manufacturing Method - Data from the piezo-electric sensors in the mounts for the projection system can be used in the control loops for other parts of the lithographic apparatus, for example the mask table, the substrate table or the air mounts for the frame bearing the projection system. Information from, for example, a geophone, which is used to measure the absolute velocity of the frame bearing the projection system, can be used in the control loop for the piezo-electric actuator in the mount for the projection system.07-14-2011
20090275149METHODS AND SYSTEMS FOR CONTROLLING CRITICAL DIMENSIONS IN TRACK LITHOGRAPHY TOOLS - A method of controlling wafer critical dimension (CD) uniformity on a track lithography tool includes obtaining a CD map for a wafer. The CD map includes a plurality of CD data points correlated with a multi-zone heater geometry map. The multi-zone heater includes a plurality of heater zones. The method also includes determining a CD value for a first heater zone of the plurality of heater zones based on one or more of the CD data points and computing a difference between the determined CD value for the first heater zone and a target CD value for the first heater zone. The method further includes determining a temperature variation for the first heater zone based, in part, on the computed difference and a temperature sensitivity of a photoresist deposited on the wafer and modifying a temperature of the first heater zone based, in part, on the temperature variation.11-05-2009
20090275150FILM FORMATION APPARATUS AND METHOD FOR SEMICONDUCTOR PROCESS - A film formation apparatus for a semiconductor process includes a source gas supply circuit to supply into a process container a source gas for depositing a thin film on target substrates, and a mixture gas supply circuit to supply into the process container a mixture gas containing a doping gas for doping the thin film with an impurity and a dilution gas for diluting the doping gas. The mixture gas supply circuit includes a gas mixture tank disposed outside the process container to mix the doping gas with the dilution gas to form the mixture gas, a mixture gas supply line to supply the mixture gas from the gas mixture tank into the process container, a doping gas supply circuit to supply the doping gas into the gas mixture tank, and a dilution gas supply circuit to supply the dilution gas into the gas mixture tank.11-05-2009
20090280579METHOD OF CONTROLLING EMBEDDED MATERIAL/GATE PROXIMITY - A method that includes forming a gate of a semiconductor device on a substrate and forming a recess for an embedded silicon-straining material in source and drain regions for the gate. In this method, a proximity value, which is defined as a distance between the gate and a closest edge of the recess, is controlled by controlling formation of an oxide layer provided beneath the gate. The method can also include feedforward control of process steps in the formation of the recess based upon values measured during the formation of the recess. The method can also apply feedback control to adjust a subsequent recess formation process performed on a subsequent semiconductor device based on the comparison between a measured proximity value and a target proximity value to decrease a difference between a proximity value of the subsequent semiconductor device and the target proximity value.11-12-2009
20110171758RECLAMATION OF SCRAP MATERIALS FOR LED MANUFACTURING - A method for reclamation of scrap materials during the formation of Group III-V materials by metal-organic chemical vapor deposition (MOCVD) processes and/or hydride vapor phase epitaxial (HVPE) processes is provided. More specifically, embodiments described herein generally relate to methods for repairing or replacing defective films or layers during the formation of devices formed by these materials. By periodic testing of the layers during the formation process, low-quality layers that may result in low-quality or defective devices may be detected prior to completion of the device. These low-quality layers may be partially or completely removed and redeposited to reclaim the substrate and any remaining high-quality layers that were previously deposited under the low-quality layer.07-14-2011
20110207242METHOD OF MANUFACTURE OF AN INTEGRATED CIRCUIT PACKAGE - A method of manufacturing an integrated circuit, IC, package comprising radio frequency, RF, components, the method comprising: 08-25-2011
20080241970Method and apparatus for performing a site-dependent dual damascene procedure - The present invention includes a method of performing a dual damascene procedure using Site-Dependent (S-D) procedures, the method including receiving a plurality of wafers and associated data by a S-D transfer subsystem coupled to a lithography-related subsystem, determining S-D wafer data for each wafer, establishing a first Dual Damascene processing sequence, determining a first set of S-D processing wafers to be processed, establishing real-time operational states for a plurality of first S-D processing elements in the lithography-related subsystem, transferring a first number of the first set of S-D processing wafers to a first number of the first S-D processing elements in the lithography-related subsystem and delaying other S-D wafers in the first set of S-D processing wafers for a first amount of time.10-02-2008
20080280379METHOD OF MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE AND MANUFACTURING SYSTEM USING THE SAME - Provided is a method of manufacturing a thin film transistor substrate and a manufacturing system using the same, wherein the production of corrosive substances is reduced during the process of manufacturing the thin film transistor substrate. The method includes providing an etching unit with an insulation substrate on which a thin metal film has been deposited, and dry-etching the insulation substrate so as to form a predetermined circuit pattern; providing a waiting unit with the insulation substrate waiting to be cleaned; performing a preliminary cleaning operation by a cleaning unit having a plurality of nozzles while the insulation substrate waits and checking the preliminary cleaning operation; and performing a main cleaning operation with regard to the insulation substrate based on the result of the check.11-13-2008
20080241969In-line lithography and etch system - The invention can provide a method of processing a wafer using Site-Dependent (S-D) processing sequences that can include S-D creation procedures, S-D evaluation procedures, and S-D transfer sequences. The S-D creation procedures can be performed using S-D processing elements, the S-D evaluation procedures can be performed using S-D evaluation elements, and S-D transfer sequences can be performed using site-dependent transfer subsystems. Site-dependent data can be stored in site-dependent libraries and/or databases.10-02-2008
20100297781METHOD FOR MANUFACTURING MEMS STRUCTURES - A method for manufacturing MEMS structures having at least one functional layer of silicon that contains structures that are exposed by removing a sacrificial layer, at least one sacrificial layer and at least one functional layer being deposited such that they grow in a monocrystalline manner, and the sacrificial layer is made up of a silicon-germanium mixed layer.11-25-2010
20090029488Soldering method for mounting semiconductor device on wiring board to ensure invariable gap therebetween, and soldering apparatus therefor - In a soldering method for mounting a semiconductor device on a wiring board, a plurality of solid-phase solders are provided between the semiconductor device and the wiring board, and are thermally melted to thereby produce a plurality of liquid-phase solders therebetween. A constant force is exerted on the liquid-phase solders by relatively moving the semiconductor device with respect to the wiring board so that an invariable gap is determined between the semiconductor device and the wiring board.01-29-2009
20090130780SEMICONDUCTOR PROCESSING SYSTEM AND METHOD OF PROCESSING A SEMICONDUCTOR WAFER - A method of processing semiconductor wafers includes applying reactive gas through a plurality of inlets to the semiconductor wafers. The method further includes removing exhaust gas resulting from the step of applying reactive gas. The removing of the exhaust gas is through a plurality of outlets coupled to a manifold. The manifold combines the exhaust gas from the plurality of outlets. The method further includes measuring a pressure in each outlet of the plurality of outlets during the step of removing.05-21-2009
20110207243PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - There is provided a means for uniformly controlling the in-plane temperature of a semiconductor wafer at high speed in a high heat input etching process. A refrigerant channel structure in a circular shape is formed in a sample stage. Due to a fact that a heat transfer coefficient of a refrigerant is largely changed from a refrigerant supply port to a refrigerant outlet port, the cross sections of the channel structure is structured so as to be increased from a first channel areas towards a second channel areas in order to make the heat transfer coefficient of the refrigerant constant in the refrigerant channel structure. Thereby, the heat transfer coefficient of the refrigerant is prevented from increasing by reducing the flow rate of the refrigerant at a dry degree area where the heat transfer coefficient of the refrigerant is increased. Further, the cross section of the channel structure is structured so as to be reduced from the second channel areas towards a third channel areas, and thereby the heat transfer coefficient of the refrigerant is prevented from decreasing. Accordingly, the heat transfer coefficient of the refrigerant can be uniformed in the channel structure.08-25-2011
20090186424PATTERN GENERATION METHOD, COMPUTER-READABLE RECORDING MEDIUM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A pattern generation method includes: acquiring a first design constraint for first patterns to be formed on a process target film by a first process, the first design constraint using, as indices, a pattern width of an arbitrary one of the first patterns, and a space between the arbitrary pattern and a pattern adjacent to the arbitrary pattern; correcting the first design constraint in accordance with pattern conversion by the second process, and thereby acquiring a second design constraint for the second pattern which uses, as indices, two patterns on both sides of a predetermined pattern space of the second pattern; judging whether the design pattern fulfils the second design constraint; and changing the design pattern so as to correspond to a value allowed by the second design constraint when the design constraint is not fulfilled.07-23-2009
20090162950DRY ETCHING EQUIPMENT AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A dry etching equipment includes a topography simulator and a control section. The topography simulator controls an amount of deposition species incident upon a sidewall to be processed in accordance with a wafer opening ratio and a solid angle of a local pattern, the deposition amount being represented by a product of a reaction product flux and the solid angle. The control section compares a database obtained by the topography simulator with an actual measured value detected from an etching condition during dry etching to calculate a correction value for etching process, and indicates the correction value to an etching chamber in the dry etching equipment. The dry etching equipment corrects in real time a parameter for the etching process conducted in the etching chamber.06-25-2009
20130217152SYSTEMS AND METHODS FOR FLEXIBLE COMPONENTS FOR POWERED CARDS AND DEVICES - Die may be thinned using a thinning and/or a polishing process. Such thinned die may be flexible and may change operational characteristics when flexed. The flexible die may be applied to a mechanical carrier (e.g., a PCB) of a card or device. Detection circuitry may also be provided on the PCB and may be used to detect changed operational characteristics. Such detection circuitry may cause a reaction to the changed characteristics by controlling other components on the card or device based upon the flex-induced changed characteristics. The thinned die may be stacked, interconnected, and encapsulated between sheets of laminate material to form a flexible card or device.08-22-2013
20110223693HEAT TREATMENT APPARATUS AND METHOD OF PROCESSING SUBSTRATE - There are provided a heat treatment apparatus and a method of processing a substrate, which can control uniformity in thickness of a film formed on a substrate. The heat treatment apparatus includes a processing chamber configured to process a substrate; a heating device configured to heat the substrate from a circumferential side of the substrate accommodated in the processing chamber; a cooling gas channel installed between the heating device and the processing chamber; a cooling device configured to flow a cooling gas into the cooling gas channel; a plurality of cooling gas inhalation passages configured to independently communicate with the cooling gas channel in regions into which the heating device is horizontally divided, and installed between the cooling device and the cooling gas channel; first pressure detectors installed respectively in the plurality of cooling gas inhalation passages; and a control unit configured to control the cooling device based on a first pressure value detected by the first pressure detectors.09-15-2011
20090142858Power-Measured Pulses for Thermal Trimming - A circuit for trimming a thermally-trimmable resistor, measuring a temperature coefficient of resistance of the thermally-trimmable resistor, and annealing a thermally-trimmable resistor post-trimming, the circuit comprising: a thermally-isolated area on a substrate housing the thermally-trimmable resistor; heating circuitry for applying a signal to a heating resistor; and a constant-power module adapted to maintain power dissipated in the heating resistor substantially constant over a duration of the signal by varying at least one parameter of the signal as a result of a change in resistance of the heating resistor during the signal.06-04-2009
20100248396HEAT TREATMENT APPARATUS AND CONTROL METHOD THEREFOR - A heat treatment apparatus includes a processing chamber having a gate valve at a sidewall and a cover at a ceiling via a sealing member; a gate valve heating unit provided at the gate valve; a processing chamber heating unit provided at a sidewall of the processing chamber; and a temperature controller that controls a set temperature for the sidewall of the processing chamber adjacent to the gate valve to be lower than a set temperature for an opposite sidewall of the processing chamber from the gate valve by controlling the processing chamber heating unit. The two set temperatures are set to be higher than a sublimation temperature of a reaction by-product, or higher than a condensation temperature of the gas, and the two set temperatures are also set to be lower than a temperature at which an amount of a gas permeating the sealing member increases.09-30-2010
20090081811DISTRIBUTED POWER ARRANGEMENTS FOR LOCALIZING POWER DELIVERY - A distributed power arrangement to provide local power delivery in a plasma processing system during substrate processing is provided. The distributed power arrangement includes a set of direct current (DC) power supply units. The distributed power arrangement also includes a plurality of power generators, which is configured to receive power from the set of DC power supply units. Each power generator of the plurality of power generators is coupled to a set of electrical elements, thereby enabling the each power generator of the plurality of power generators to control the local power delivery.03-26-2009
20100003769METHOD RELATING TO THE ACCURATE POSITIONING OF A SEMICONDUCTOR WAFER - Disclosed is a method involving repeatedly measuring a pressure within a flow of processing gas that is provided in a semiconductor processing apparatus for treatment of a semiconductor substrate, such as a semiconductor wafer. The flow of processing gas is made to extend between a surface of the substrate and a surface of a processing body. From the pressure measurements the occurrence of an event that is related to a variation in the position of the substrate's surface relative to the surface of the processing body is determined.01-07-2010
20110229987METHOD FOR LOW TEMPERATURE ION IMPLANTATION - Techniques for low temperature ion implantation are provided to improve throughput. Specifically, the pressure of the backside gas may temporarily, continually or continuously increase before the starting of the implant process, such that the wafer may be quickly cooled down from room temperature to be essentially equal to the prescribed implant temperature. Further, after the vacuum venting process, the wafer may wait an extra time in the load lock chamber before the wafer is moved out the ion implanter, in order to allow the wafer temperature to reach a higher temperature quickly for minimizing water condensation on the wafer surface. Furthermore, to accurately monitor the wafer temperature during a period of changing wafer temperature, a non-contact type temperature measuring device may be used to monitor wafer temperature in a real time manner with minimized condensation.09-22-2011
20090004761SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 01-01-2009
20120142122METHOD OF INSPECTING AND PROCESSING SEMICONDUCTOR WAFERS - A wafer inspection method comprises imaging a full surface of the wafer at an imaging resolution insufficient to resolve individual microstructures which are repetitively arranged on the wafer. A mask 06-07-2012
20090253221METHOD OF MEASURING NITROGEN CONTENT, METHOD OF FORMING SILICON OXYNITRIDE FILM AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - The total film thickness T1N of silicon oxynitride film and silicon oxide film remaining as its underlying layer is measured. A measurement target substrate is re-oxidized, and, after the re-oxidization, the total film thickness (T2N) of the silicon oxynitride film, silicon oxide film and silicon oxide film resulting from the re-oxidization on the target substrate is measured. Separately, a reference substrate provided with silicon oxide film is re-oxidized, and, after the re-oxidization, the total film thickness T2 of the silicon oxide film and silicon oxide film resulting from the re-oxidization on the reference substrate is measured. Re-oxidization rate reduction ratio RORR of the measurement target substrate is calculated by the following formula (1) from the values of total film thicknesses T1N, T2N and T2. The nitrogen concentration of the silicon oxynitride film of the target substrate is determined from the calculated re-oxidization rate reduction ratio RORR. RORR (%)={(T2−T2N)/(T2−T1N)}×100 (1).10-08-2009
20090258444APPARATUS AND METHODS FOR MANUFACTURING THIN-FILM SOLAR CELLS - Improved methods and apparatus for forming thin-film layers of semiconductor material absorber layers on a substrate web. According to the present teachings, a semiconductor layer may be formed in a multi-zone process whereby various layers are deposited sequentially onto a moving substrate web.10-15-2009
20110143461IN VACUUM OPTICAL WAFER HEATER FOR CRYOGENIC PROCESSING - A vacuum assembly used for warming processed substrates above the dew point to prevent unwanted moisture on the processed substrate surfaces as well as reducing negative impact on manufacturing throughput. The vacuum assembly includes a processing chamber, a substrate handling robot, and a heater which may be an optical heater. The processing chamber is configured to cryogenically process one or more substrates. The transfer chamber is connected to the processing chamber and houses the substrate handling robot. The substrate handling robot is configured to displace one or more substrates from the processing chamber to the transfer chamber. The heater is connected to the transfer chamber above the substrate handling robot such that the heater emits energy incident on the substrate when the substrate handling robot displaces the substrate in the transfer chamber.06-16-2011
20100015733METHOD AND DEVICE FOR MONITORING A HEAT TREATMENT OF A MICROTECHNOLOGICAL SUBSTRATE - A method of monitoring a heat treatment of a microtechnological substrate includes placement of the substrate to be treated in a heating zone and applying a heat treatment to the substrate, under predetermined temperature conditions, while monitoring the change over the course of time in the vibratory state of the substrate, and detecting a fracture in the substrate by detecting a peak characteristic in the vibratory state over the course of time.01-21-2010
20100197048METHOD OF PRODUCING SEMICONDUCTOR - In a conventional SGT production method, during dry etching for forming a pillar-shaped silicon layer and a gate electrode, an etching amount cannot be controlled using an end-point detection process, which causes difficulty in producing an SGT while stabilizing a height dimension of the pillar-shaped silicon layer, and a gate length. In an SGT production method of the present invention, a hard mask for use in dry etching for forming a pillar-shaped silicon layer is formed in a layered structure comprising a first hard mask and a second hard mask, to allow the end-point detection process to be used during the dry etching for the pillar-shaped silicon layer. In addition, a gate conductive film for use in dry etching for forming a gate electrode is formed in a layered structure comprising a first gate conductive film and a second gate conductive film, to allow the end-point detection process to be used during the dry etching for the gate electrode.08-05-2010
20100197047METHOD FOR MANUFACTURING SIMOX WAFER - At oxygen ion implanting steps in manufacture of a SIMOX wafer, a path is formed inside or on a back surface of wafer holding means, and oxygen ions are implanted while heating an outer peripheral portion of the wafer that is in contact with the wafer holding means by flowing a heated fluid through this path. An in-plane temperature of a wafer held at the time of ion implantation is prevented from becoming uneven, and in-plane film thicknesses of both an SOI layer and a BOX layer are uniformed.08-05-2010
20100240154TEMPERATURE CONTROL DEVICE, TEMPERATURE CONTROL METHOD, AND SUBSTRATE PROCESSING APPARATUS - Provided is a temperature control device for controlling a temperature of a member to be exposed to plasma in a substrate processing apparatus. The substrate processing apparatus includes a mounting electrode for mounting a target substrate and a facing electrode positioned to face the mounting electrode, excites a processing gas supplied between the mounting electrode and the facing electrode into plasma, and performs a plasma process on the target substrate with the plasma. The temperature control device includes a heating layer configured to heat a heating target member, a heat insulating layer positioned in contact with an opposite surface to a heating layer's surface facing the heating target member, and a cooling layer positioned in contact with an opposite surface to a heat insulating layer's surface facing the heating layer.09-23-2010
20090286331METHOD FOR SIMULATENOUSLY PRODUCING MULTIPLE WAFERS DURING A SINGLE EPITAXIAL GROWTH RUN AND SEMICONDUCTOR STRUCTURE GROWN THEREBY - HVPE method for simultaneously fabricating multiple Group III nitride semiconductor structures during a single reactor run. A HVPE reactor includes a reactor tube, a growth zone, a heating element and a plurality of gas blocks. A substrate holder is capable of holding multiple substrates and can be a single or multi-level substrate holder. The gas delivery blocks are independently controllable. Gas flows from the delivery blocks are mixed to provide a substantially uniform gas environment within the growth zone. The substrate holder can be controlled, e.g., rotated and/or tilted, for uniform material growth. Multiple Group III nitride semiconductor structures can be grown on each substrate during a single fabrication run of the HVPE reactor. Growth on different substrates is substantially uniform and can be performed on larger area substrates, such as 3-12″ substrates. 11-19-2009
20100035366Production of VDMOS-Transistors Having Optimized Gate Contact - The invention relates to a method for producing VDMOS transistors in which a specific layer arrangement and a specific method sequence allow setting up an improved gate contact when simultaneously producing source and gate contacts using a single contact hole mask (photo mask).02-11-2010
20100221849METHOD AND SYSTEM FOR CONTROLLING AN IMPLANTATION PROCESS - A method for implant uniformity is provided that includes determining a variation of critical dimensions (CD) of a semiconductor wafer, moving the semiconductor wafer in a two-dimensional mode during an implantation process, and controlling a velocity of the movement of the semiconductor wafer so that an implant dose to the semiconductor wafer is varied based on the variation of CD.09-02-2010
20110117679SACRIFICIAL OFFSET PROTECTION FILM FOR A FINFET DEVICE - A method for fabricating a semiconductor device is disclosed. An exemplary embodiment of the method includes providing a substrate; forming a fin structure over the substrate; forming a gate structure, wherein the gate structure overlies a portion of the fin structure; forming a sacrificial-offset-protection layer over another portion of the fin structure; and thereafter performing an implantation process.05-19-2011
20130130408MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED DEVICE - In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.05-23-2013
20130137193SYSTEMS AND METHODS FOR PREPARATION OF SAMPLES FOR SUB-SURFACE DEFECT REVIEW - One embodiment relates to a method of preparation of a sample of a substrate for sub-surface review using a scanning electron microscope apparatus. A defect at a location indicated in a first results file is re-detected, and the location of the defect is marked with at least one discrete marking point having predetermined positioning relative to the location of the defect. The location of the defect may be determined relative to the design for the device, and a cut location and a cut angle may be determined in at least a partly-automated manner using that information. Another embodiment relates to a system for preparing a sample for sub-surface review. Another embodiment relates to a method for marking a defect for review on a target substrate. Other embodiments, aspects and feature are also disclosed.05-30-2013
20090068765METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes performing positioning between a transfer position of a pattern forming surface of a transfer original plate on which a pattern to be transferred is formed and a transferred position of a transferred surface of a transferred substrate to which the pattern is to be transferred; contacting the pattern forming surface with the transferred surface; and partly correcting the positional deviation between the transfer position of the pattern forming surface and the transferred position of the transferred surface in the in-plane direction, after the positioning is performed.03-12-2009
20120270340MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED DEVICE - In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.10-25-2012
20110244602METHOD OF PRODUCING SEMICONDUCTOR - In a conventional SGT production method, during dry etching for forming a pillar-shaped silicon layer and a gate electrode, an etching amount cannot be controlled using an end-point detection process, which causes difficulty in producing an SGT while stabilizing a height dimension of the pillar-shaped silicon layer, and a gate length. In an SGT production method of the present invention, a hard mask for use in dry etching for forming a pillar-shaped silicon layer is formed in a layered structure comprising a first hard mask and a second hard mask, to allow the end-point detection process to be used during the dry etching for the pillar-shaped silicon layer. In addition, a gate conductive film for use in dry etching for forming a gate electrode is formed in a layered structure comprising a first gate conductive film and a second gate conductive film, to allow the end-point detection process to be used during the dry etching for the gate electrode.10-06-2011
20110244601METHOD FOR PRODUCING A SUBSTRATE INCLUDING A STEP OF THINNING WITH STOP WHEN A POROUS ZONE IS DETECTED - A method for producing a substrate including a step of thinning the thickness of the substrate is disclosed. The method is characterized in that it includes the following steps: the formation of a porous zone in an inner layer of the substrate; the progressive thinning of the thickness of the substrate towards the inner layer including a porous zone; the completion of the progressive thinning by polishing; and a controlled stoppage of polishing upon detection of the porous zone.10-06-2011
20090311807THERMAL PROCESSING APPARATUS AND THERMAL PROCESSING METHOD FOR OBJECT TO BE PROCESSED - The present invention is a thermal processing apparatus comprising: a processing vessel capable of being evacuated, the processing vessel also being capable of accommodating, in addition to a plurality of objects, an object for temperature measurement equipped with an elastic wave device; a holding unit configured to be loaded into and unloaded from the processing vessel, while the holding unit holding the plurality of objects to be processed and the object for temperature measurement; a gas introduction unit configured to introduce a gas into the processing vessel; a heating unit configured to heat the plurality of objects to be processed and the object for temperature measurement that are accommodated in the processing vessel; a first conductive member configured to function as a transmitter antenna connected to a transmitter through a radiofrequency line, for transmitting an electric wave for measurement toward the elastic wave device accommodated in the processing vessel; a second conductive member configured to function as a receiver antenna connected to a receiver through a radiofrequency line, for receiving an electric wave dependent on a temperature of the elastic wave device which is emitted from the elastic wave device accommodated in the processing vessel; a temperature analysis part configured to obtain a temperature of the object for temperature measurement based on the electric wave received by the receiver antenna; and a temperature control part configured to control the heating unit; wherein: the first conductive member is disposed as a part of a thermal processing part in the processing vessel; and the second conductive member is disposed as a part of a thermal processing part in the processing vessel.12-17-2009
20110250706METHOD OF FABRICATING MEMS, NEMS, PHOTONIC, MICRO- AND NANO-FABRICATED DEVICES AND SYSTEMS - An improved method for the fabrication of Micro-Electro-Mechanical Systems (MEMS), Nano-Electro-Mechanical Systems (NEMS), Photonics, Nanotechnology, 3-Dimensional Integration, Micro- and Nano-Fabricated Devices and Systems for both rapid prototyping development and manufacturing is disclosed. The method includes providing a plurality of different standardized and repeatable process modules usable in fabricating the devices and systems, defining a process sequence for fabricating a predefined one of the devices or systems, and identifying a series of the process modules that are usable in performing the defined process sequence and thus in fabricating the predefined device or system.10-13-2011
20100062547TECHNIQUE FOR MONITORING AND CONTROLLING A PLASMA PROCESS WITH AN ION MOBILITY SPECTROMETER - A plasma processing apparatus includes a process chamber, a platen positioned in the process chamber for supporting a workpiece, a source configured to generate a plasma in the process chamber, and a monitoring system including an ion mobility spectrometer configured to monitor a condition of the plasma. A monitoring method including generating a plasma in a process chamber of a plasma processing apparatus, supporting a workpiece on a platen in the process chamber, and monitoring a condition of the plasma with an ion mobility spectrometer is also provided.03-11-2010
20110177622APPARATUS AND METHODS OF MIXING AND DEPOSITING THIN FILM PHOTOVOLTAIC COMPOSITIONS - Improved methods and apparatus for forming thin-film layers of semiconductor material absorber layers on a substrate web. According to the present teachings, a semiconductor layer may be formed in a multi-zone process whereby various layers are deposited sequentially onto a moving substrate web. At least one layer is deposited from a mixed gallium indium source.07-21-2011
20110097823APPARATUS FOR FORMING THIN FILM AND METHOD OF MANUFACTURING SEMICONDUCTOR FILM - An apparatus including a vacuum chamber having a substrate holding unit that holds a substrate and a plasma electrode facing the substrate, a first gas supply unit that supplies a H04-28-2011
20100062546METHOD OF MANUFACTURING SOI SUBSTRATE - An object of the present invention is to improve use efficiency of a semiconductor substrate without lowering efficiency of a fabrication process. Another object of the present invention is to achieve cost reduction by effective use of a semiconductor substrate whose thickness is reduced due to repeated use in a process of manufacturing an SOI substrate. In a process of manufacturing an SOI substrate, a semiconductor substrate is used as a bond substrate a predetermined number of times, or as long as it meets predetermined conditions. In a case where a first single crystal semiconductor substrate cannot be used as a bond substrate, it is bonded to a second single crystal semiconductor substrate. Then, a stacked-layer substrate formed from the first single crystal semiconductor substrate and the second single crystal semiconductor substrate bonded to each other is used as a bond substrate in a process of manufacturing an SOI substrate.03-11-2010
20090215201METHOD FOR CONTROLLING SPATIAL TEMPERATURE DISTRIBUTION ACROSS A SEMICONDUCTOR WAFER - A chuck for a plasma processor comprises a temperature-controlled base, a thermal insulator, a flat support, and a heater. The temperature-controlled base is controlled in operation a temperature below the desired temperature of a workpiece. The thermal insulator is disposed over at least a portion of the temperature-controlled base. The flat support holds a workpiece and is disposed over the thermal insulator. A heater is embedded within the flat support and/or mounted to an underside of the flat support. The heater includes a plurality of heating elements that heat a plurality of corresponding heating zones. The power supplied and/or temperature of each heating element is controlled independently. The heater and flat support have a combined temperature rate change of at least 1° C. per second.08-27-2009
20110250707METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first group identifier allocated to a first group of semiconductor wafers is detected. The first group of semiconductor wafers includes a first semiconductor wafer to be processed first among the first group. A first processor of a plurality of processors, which process respective ones of the first group of semiconductor wafers, are determined based on the first group identifier. The first processor is used for processing the first semiconductor wafer. The first semiconductor wafer is supplied to the first processor.10-13-2011
20110097822FABRICATION METHOD OF SEMICONDUCTOR DEVICE WITH UNIFORM TOPOLOGY - A method of manufacturing a semiconductor device to have uniform topology includes forming an interlayer insulating layer on a semiconductor device, carrying out an ion implantation process by varying an amount of ion-implantation according to a height profile of the interlayer insulating layer, and planarizing the interlayer insulating layer.04-28-2011
20110076787Method and apparatus for uniform microwave treatment of semiconductor wafers - A microwave heating system comprises a microwave applicator cavity; a microwave power supply to deliver power to the applicator cavity; a dielectric support to support a generally planar workpiece; a dielectric gas manifold to supply a controlled flow of inert gas proximate to the periphery of the workpiece to provide differential cooling to the edge relative to the center; a first temperature measuring device configured to measure the temperature near the center of the workpiece; and, a second temperature measuring device configured to measure the temperature near the edge of the workpiece. The gas flow is controlled to minimize the temperature difference from center to edge, and may be recipe driven or controlled in real time, based on the two temperature measurements. The method is particularly useful for monolithic semiconductor wafers, various semiconducting films on substrates, and dielectric films on semiconducting wafers.03-31-2011
20110076786Method and apparatus for controlled thermal processing - A materials processing system comprises a thermal processing chamber including a heating source, a first noncontacting thermal measurement device positioned to measure temperature on a first area of the material being processed, and, a second noncontacting thermal measurement device positioned to measure temperature on a second area of the material being processed, the first device being relatively more sensitive to changes in surface emissivity than the second device. By comparing the outputs of the two devices, emissivity changes can be detected and used as a proxy for some physical change in the workpiece and thereby determine when the desired process has been completed. The system may be used to develop a process recipe, or it may be part of a system for real-time process control based on emissivity changes. Applicable processes include heating, annealing, dopant activation, silicide formation, carburization, nitridation, sintering, oxidation, vapor deposition, metallization, and plating.03-31-2011
20110045611 METHOD OF INITIATING MOLECULAR BONDING - The invention relates to a method of initiating molecular bonding, comprising bringing one face (02-24-2011
20100297783Plasma Processing Method - A method for performing a plasma process using a plasma processing apparatus which includes a vacuum process chamber, an exhaust device, a mass flow controller supplying a process gas, a stage electrode which receives and holds a workpiece by adsorption, a transfer device, and a high-frequency electrical source. The method includes a first step of performing the plasma process for the workpiece in the vacuum process chamber by a corresponding recipe of predetermined recipes, a second step of acquiring apparatus parameters showing the condition of the plasma processing apparatus when a specific recipe of the predetermined recipes is executed to diagnose whether the condition of the plasma processing apparatus is good or not based on the acquired apparatus parameters.11-25-2010
20100081217DEFECT INSPECTION APPARATUS, DEFECT INSPECTION METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A defect inspection method includes generating and applies a charged beam to a sample with patterns; controlling a shape of the charged beam so that a beam width in a first direction perpendicular to an optical axis differs from a beam width in a second direction perpendicular to the optical axis and the first direction, while substantially maintaining a cross-sectional area of the beam; scanning the sample with the charged beam having the controlled shape; and detecting charged particles from the sample by irradiation of the charged beam and detects a defect of the patterns. Assuming that the beam width of the charged beam in the first direction is smaller than that in the second direction, the first direction is set to a direction in which an interval between adjacent patterns becomes a minimum value and the sample is scanned in the second direction.04-01-2010
20090317924METHOD FOR OPTIMIZING THE ROUTING OF WAFERS/LOTS BASED ON YIELD - A method for increasing overall yield in semiconductor manufacturing including routing wafers or wafer lots based on process variation data obtained from the wafers or wafer lots and on process variation data obtained from tools processing the wafers or wafer lots. A system for increasing overall yield in semiconductor manufacturing includes a module for routing wafers or wafer lots based on process variation data obtained from the wafers or wafer lots and on process variation data obtained from the tools processing the wafers or wafer lots.12-24-2009
20090029486Substrate Processing Apparatus and Substrate Processing Method - A substrate processing apparatus has: a process chamber in which a substrate is processed; a heating device that optically heats the substrate accommodated in the process chamber from an outer periphery side of the substrate; a cooling device that cools the outer periphery side of the substrate by flowing a fluid in a vicinity of an outer periphery of the substrate optically heated by the heating device; a temperature detection portion that detects a temperature inside the process chamber; and a heating control portion that controls the heating device and the cooling device in such a manner so as to provide a temperature difference between a center portion of the substrate and an end portion of the substrate while maintaining a temperature at the center portion at a pre-determined temperature according to the temperature detected by the temperature detection portion.01-29-2009
20090029487SEMICONDUCTOR PRODUCTION METHOD AND SEMICONDUCTOR PRODUCTION DEVICE - The objective of the present invention is to prevent the variation in an ashing rate according to a temporal change within an ashing chamber. Then, in order to maintain the ashing rate, the decrease in the number of oxygen atoms in ashing gas within a process chamber 01-29-2009
20110053294UV IRRADIANCE MONITORING IN SEMICONDUCTOR PROCESSING USING A TEMPERATURE DEPENDENT SIGNAL - In a UV process tool for semiconductor processing, a temperature-dependent signal may be used as a monitor signal for determining the momentary irradiance of the UV radiation source. Consequently, a fast and reliable monitoring and/or controlling of the irradiance of UV process tools may be accomplished.03-03-2011
20100330709WAFER TEMPERATURE CORRECTION SYSTEM FOR ION IMPLANTATION DEVICE - To provide an ion implantation device capable of correcting the temperature of the wafer. The ion implantation device of the present invention has: an irradiation means that radiates ions; a retention means that includes a disk 12-30-2010
20100330710METHODS FOR CONSTRUCTING AN OPTIMAL ENDPOINT ALGORITHM - A method for automatically identifying an optimal endpoint algorithm for qualifying a process endpoint during substrate processing within a plasma processing system is provided. The method includes receiving sensor data from a plurality of sensors during substrate processing of at least one substrate within the plasma processing system, wherein the sensor data includes a plurality of signal streams from a plurality of sensor channels. The method also includes identifying an endpoint domain, wherein the endpoint domain is an approximate period within which the process endpoint is expected to occur. The method further includes analyzing the sensor data to generate a set of potential endpoint signatures. The method yet also includes converting the set of potential endpoint signatures into a set of optimal endpoint algorithms. The method yet further includes importing one optimal endpoint algorithm of the set of optimal endpoint algorithms into production environment.12-30-2010
20110033956SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD OF CONFIRMING OPERATION OF LIQUID FLOWRATE CONTROL DEVICE - A substrate processing apparatus, a method of manufacturing a semiconductor device, and a method of confirming an operation of a liquid flowrate control device are provided. The substrate processing apparatus comprises: a process chamber accommodating a substrate; a liquid source supply system supplying a liquid source into the process chamber; a solvent supply system supplying a solvent having a vapor pressure greater than that of the liquid source into the process chamber; a liquid flowrate control device controlling flowrates of the liquid source and the solvent; and a controller controlling the liquid source supply system, the solvent supply system, and the liquid flowrate control device so that the solvent is supplied into the liquid flowrate control device than the solvent supply system to confirm an operation of the liquid flowrate control device before the liquid source supply system supplies the liquid source into the process chamber.02-10-2011
20110136267METHOD OF CONTROLLING FILM THINNING OF SEMICONDUCTOR WAFER FOR SOLID-STATE IMAGE SENSING DEVICE - The thickness of a semiconductor wafer layer, extending from a mirror-finished surface thereof to a solid-state image sensing device, is measured. Based on the residual thickness data, plasma etching is performed from the mirror-finished surface until a predetermined thickness is reached by controlling the plasma etching amount. By doing this, it is possible to reduce variation in the thickness of the solid-state image sensing device at low cost without causing an increase in the number of processes.06-09-2011
20090197352Substrate processing method and film forming method - A substrate processing method in a processing chamber, has: accommodating a substrate into a processing chamber; and processing the substrate in the processing chamber on the basis of a correlation of a preset temperature of a heating device, a flow rate of fluid supplied by a cooling device and a temperature deviation between the center side of the substrate accommodated in the processing chamber and the outer peripheral side of the substrate while the substrate accommodated in the processing chamber is optically heated from an outer periphery side of the substrate at a corrected preset temperature by the heating device and the fluid is supplied to the outside of the processing chamber at the flow rate based on the correlation concerned to cool the outer peripheral side of the substrate by the cooling device.08-06-2009
20090197351LASER PROCESSING METHOD - In a laser beam processing method, when a laser beam is emitted along a second predetermined dividing line to form a second groove intersecting a first groove previously formed, the power output of the laser beam is allowed to be a first power output in a first interval, that is, until the second predetermined dividing line reaches a position immediately before the first groove. In a second interval from the position close to the first groove to the first groove reached by the second predetermined dividing line, the power output of the laser beam is set to a second power output lower than the first power output. Thus, overheat on the periphery of the second interval can be suppressed.08-06-2009
20120309116Substrate Analysis Using Surface Acoustic Wave Metrology - A system for imposing and analyzing surface acoustic waves in a substrate to determine characteristics of the substrate is disclosed. Optical elements and arrangements for imposing and analyzing surface acoustic waves in a substrate are also disclosed. NSOM's, gratings, and nanolight elements may be used to impose surface acoustic waves in a substrate and may also be used to measure transient changes in the substrate due to the passage of surface acoustic waves therethrough.12-06-2012
20120309115APPARATUS AND METHODS FOR SUPPORTING AND CONTROLLING A SUBSTRATE - Embodiments of the present invention provide apparatus and methods for supporting and controlling a substrate during thermal processing. One embodiment of the present invention provides an apparatus for processing a substrate. The apparatus includes a chamber body defining an inner volume, a substrate support disposed in the inner volume, and an auxiliary force assembly configured to apply an auxiliary force to the substrate. Another embodiment provides a gas delivery assembly configured to adjust a thermal mass of a fluid flow delivered to position, control and/or rotate a substrate.12-06-2012
20110070665DC and RF Hybrid Processing System - The invention can provide apparatus and methods for processing substrates and/or wafers in real-time using at least one Direct Current (DC)/Radio Frequency (RF) Hybrid (DC/RFH) processing system and associated Direct Current/Radio Frequency Hybrid (DC/RFH) procedures and DC/RFH process parameters and/or DC/RFH models.03-24-2011
20120156808METHOD FOR APPLYING LIQUID MATERIAL, AND APPARATUS AND PROGRAM FOR SAME - Provided are a method for filling a liquid material, and an apparatus and a program for the same, which make it possible, without changing a moving speed of an ejection device, to correct a change in ejection amount and to stabilize an application shape. Disclosed are: a method for filling a liquid material into a gap between a substrate and a work by using the capillary action; and an apparatus and a program for the same. The method comprises the steps of: generating an application pattern consisting of a plurality of application areas continuous to one another; assigning a plurality of ejection cycles, each obtained by combining the number of ejection pulses and the number of pause pulses at a predetermined ratio therebetween, to each of the application areas; and measuring an ejection amount at correction intervals and calculating a correction amount for the ejection amount. The method further comprises at least any one of the steps of: adjusting the numbers of ejection pulses and the numbers of pause pulses, which are included in the application pattern, based on the calculated correction amount; and adjusting the length of any application area continuous to at least one application area without changing ejection amounts per unit time in the respective application areas.06-21-2012
20120156807METHOD OF UPDATING CALIBRATION DATA AND A DEVICE MANUFACTURING METHOD - A method of updating calibration data of a first position detection system adapted to determine the position of an object, is presented. The first position detection system includes a target and a plurality of sensors one of which is mounted on an object and the calibration data including coefficients relating an apparent measured position to an actual position and which can be used to convert an apparent measured position to an actual position thereby to correct for physical imperfections in the first position detection system and enable determination of the actual position from the apparent measured position.06-21-2012
20120208300ETCH PROCESSING CHAMBER - A substrate etching method and apparatus are disclosed. In one embodiment, a method for etching is provided that includes, in a plasma processing chamber, etching a feature in a silicon layer using an etch recipe that includes cyclical etching and deposition substeps until an end point is reached, wherein an aspect ratio of the feature increases with a number of cyclical etching and deposition substeps performed over time until the end point is reached; and adjusting a recipe variable of the etch recipe in response to the current aspect ratio of the feature during etching to manage thickness of sidewall polymers when the feature becomes deeper to avoid closing the feature and preventing subsequent etching.08-16-2012
20100003770ELEMENTAL ANALYSIS METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Protons are entered into a substrate to be analyzed at a proton incident angle larger than 0° and smaller 90°. Excited by the entered protons and emitted from the substrate to be analyzed, the characteristic X-ray is measured by an energy dispersive X-ray detector and the like. Impurity elements present in the substrate to be analyzed are identified based on the measured characteristic X-ray. The in-plane distribution in the substrate can be obtained by scanning the proton beam. The in-depth distribution can be obtained by entering protons at different proton incident angles. The elemental analysis method can be applied to semiconductor device manufacturing processes to analyze metal contamination or quantify a conductivity determining impurity element on an inline basis and with a high degree of accuracy.01-07-2010
20120115254HEATING PLATE WITH PLANAR HEATER ZONES FOR SEMICONDUCTOR PROCESSING - A heating plate for a substrate support assembly in a semiconductor plasma processing apparatus, comprises multiple independently controllable planar heater zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar heater zone includes one or more heater elements made of an insulator-conductor composite. A substrate support assembly in which the heating plate is incorporated includes an electrostatic clamping electrode and a temperature controlled base plate. Methods for manufacturing the heating plate include bonding together ceramic sheets having planar heater zones, power supply lines, power return lines and vias.05-10-2012
20120058576Deposition System - A pumping and valve control device can be used in an atomic layer deposition system.03-08-2012
20120208301Methods and Systems for Creating or Performing a Dynamic Sampling Scheme for a Process During Which Measurements Are Performed on Wafers - Various methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers are provided. One method for creating a dynamic sampling scheme for a process during which measurements are performed on wafers includes performing the measurements on all of the wafers in at least one tot at all measurement spots on the wafers. The method also includes determining an optimal sampling scheme, an enhanced sampling scheme, a reduced sampling scheme, and thresholds for the dynamic sampling scheme for the process based on results of the measurements. The thresholds correspond to values of the measurements at which the optimal sampling scheme, the enhanced sampling scheme, and the reduced sampling scheme are to be used for the process.08-16-2012
20120070914TEMPERATURE CONTROL MODULE USING GAS PRESSURE TO CONTROL THERMAL CONDUCTANCE BETWEEN LIQUID COOLANT AND COMPONENT BODY - A temperature control module for a semiconductor processing chamber comprises a thermally conductive component body, one or more channels in the component body and one or more tubes concentric therewith, such that gas filled spaces surround the tubes. By flowing a heat transfer liquid in the tubes and adjusting the gas pressure in the spaces, localized temperature of the component body can be precisely controlled. One or more heating elements can be arranged in each zone and a heat transfer liquid can be passed through the tubes to effect heating or cooling of each zone by activating the heating elements and/or varying pressure of the gas in the spaces.03-22-2012
20100093111METHOD FOR MANUFACTURING ELECTRONIC DEVICE USING PLASMA REACTOR PROCESSING SYSTEM - To enable change of a concentration of atmosphere in a process chamber and realize a plasma reaction process required for manufacturing a liquid crystal device and a semiconductor device with a high yield at a low cost.04-15-2010
20120315709PROCESS AND APPARATUS FOR PRODUCING A SUBSTRATE - Process for producing a solar cell substrate, where metal particles are deposited on the surface of substrate. Metal particles are produced by liquid flame spraying method in such a way that the mean diameter of the particles to be between 30 nm and 150 nm and the deposition process is controlled in such a way that the average distance between particles is not more than four times the mean diameter of particles. Apparatus for carrying out such process.12-13-2012
20090130781METHOD FOR SIMULTANEOUSLY PRODUCING MULTIPLE WAFERS DURING A SINGLE EPITAXIAL GROWTH RUN AND SEMICONDUCTOR STRUCTURE GROWN THEREBY - HVPE method for simultaneously fabricating multiple Group III nitride semiconductor structures during a single reactor run. A HVPE reactor includes a reactor tube, a growth zone, a heating element and a plurality of gas blocks. A substrate holder is capable of holding multiple substrates and can be a single or multi-level substrate holder. The gas delivery blocks are independently controllable. Gas flows from the delivery blocks are mixed to provide a substantially uniform gas environment within the growth zone. The substrate holder can be controlled, e.g., rotated and/or tilted, for uniform material growth. Multiple Group III nitride semiconductor structures can be grown on each substrate during a single fabrication run of the HVPE reactor. Growth on different substrates is substantially uniform and can be performed on larger area substrates, such as 3-12″ substrates.05-21-2009
20110183443CONTACT PATTERNING METHOD WITH TRANSITION ETCH FEEDBACK - A method for forming a contact hole in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including measuring a percentage of oxygen in an etching chamber, and controlling the percentage of oxygen in the etching chamber to enlarge a temporary inner diameter near a top of the contact hole.07-28-2011
20120129275DUAL-BULB LAMPHEAD CONTROL METHODOLOGY - The present invention generally relates to methods of controlling UV lamp output to increase irradiance uniformity. The methods generally include determining a baseline irradiance within a chamber, determining the relative irradiance on a substrate corresponding to a first lamp and a second lamp, and determining correction or compensation factors based on the relative irradiances and the baseline irradiance. The lamps are then adjusted via closed loop control using the correction or compensation factors to individually adjust the lamps to the desired output. The lamps may optionally be adjusted to equal irradiances prior to adjusting the lamps to the desired output. The closed loop control ensures process uniformity from substrate to substrate. The irradiance measurement and the correction or compensation factors allow for adjustment of lamp set points due to chamber component degradation, chamber component replacement, or chamber cleaning.05-24-2012
20120231556ETCH TOOL PROCESS INDICATOR METHOD AND APPARATUS - A method for providing a process indicator for an etching chamber is provided. A wafer with a blanket etch layer is provided into the etching chamber. A blanket etch is performed on the blanket etch layer. A blanket deposition layer is deposited over the blanket etch layer after performing the blanket etch has been completed. A thickness of the blanket etch layer and a thickness of the blanket deposition layer is measured. The measured thicknesses are used to determine a process indicator.09-13-2012
20120231555ADAPTIVE ENDPOINT METHOD FOR PAD LIFE EFFECT ON CHEMICAL MECHANICAL POLISHING - The present disclosure provides a semiconductor manufacturing method. The method includes defining a plurality of time regions of pad life for a polishing pad in a chemical mechanical polishing (CMP) system; assigning a ladder coefficient to the polishing pad according to the plurality of time regions of pad life; defining a plurality of endpoint windows to the plurality of time regions, respectively, according to pad life effect; applying a CMP process to a wafer positioned on the polishing pad; determining a time region of a polishing signal of the wafer based on the ladder coefficient; associating one of the endpoint windows to the polishing signal according to the time region; and ending the CMP process at an endpoint determined by the endpoint window.09-13-2012
20120315710METHOD FOR PRODUCING RECONSTITUTED WAFERS AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICES - In order to provide a method for producing semiconductor devices that can use the highly productive W to W method, and achieve a high yield, a method for producing semiconductor devices comprises a step (S12-13-2012
20120315708METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a source electrode and a drain electrode on a front face of a semiconductor substrate which is transparent to visible light, forming a front-side gate electrode between the source electrode and the drain electrode on the front face of the semiconductor substrate; forming an aligning mark on a region of the front face of the semiconductor substrate other than a region between the source electrode and the drain electrode, aligning the semiconductor substrate based on the aligning mark that is seen through the semiconductor substrate, and forming a back-side gate electrode on a back face of the semiconductor substrate in a location opposite the front-side gate electrode.12-13-2012
20120214258Die Bonder and Semiconductor Manufacturing Method - The present invention provides a reliable die bonder that can accurately bond a die and a semiconductor manufacturing method. The present invention is provided with a bonding head that adsorbs a die from a wafer and bonds it to a substrate, a positioning mechanism that is provided with a first adjustment mechanism that positions a position of the die at predetermined accuracy, and positions the bonding head, a positioning controller that controls the positioning mechanism and a second adjustment mechanism that is provided to the bonding head, and adjusts a position of the die at higher accuracy than the first adjustment mechanism.08-23-2012
20120171786APPARATUS FOR MANUFACTURING SOLAR CELLS AND PROCESS FOR OPERATING SUCH APPARATUS - Apparatus (07-05-2012
20120077289APPARATUS AND METHOD OF TEMPERATURE CONTROL DURING CLEAVING PROCESSES OF THICK MATERIALS - A method for temperature control during a process of cleaving a plurality of free-standing thick films from a bulk material includes clamping a bulk material using a mechanical clamp device adapted to engage the bottom region of the bulk material through a seal with a planar surface of a stage to form a cavity with a height between the bottom region and the planar surface. The planar surface includes a plurality of gas passageways allowing a gas filled in the cavity with adjustable pressure. The method also includes maintaining the temperature of the surface region by processing at least input data and executing a control scheme utilizing at least one or more of; 03-29-2012
20100047932SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING PROGRAM, AND COMPUTER READABLE RECORDING MEDIUM HAVING SUBSTRATE PROCESSING PROGRAM THEREIN - Disclosed is a substrate processing apparatus to supply processing liquid having a predetermined flow rate and concentration to a substrate processing unit of the substrate processing apparatus with high accuracy. The substrate processing apparatus processes substrates in a plurality of substrate processing units by using the processing liquid supplied from a processing liquid supply part. If the flow rate of the processing liquid simultaneously used by the substrate processing units is less than a control flow rate that is controllable at the processing liquid supply part, the processing liquid is supplied from the processing liquid supply part such that the flow rate of the processing liquid is substantially identical to the control flow rate. If the flow rate of the processing liquid simultaneously used by the substrate processing units is substantially identical to the control flow rate that is controllable at the processing liquid supply part, the processing liquid having the flow rate simultaneously used by the substrate processing units is supplied from the processing liquid supply part.02-25-2010
20100279435TEMPERATURE CONTROL OF CHEMICAL MECHANICAL POLISHING - A chemical mechanical polishing apparatus including a platen for holding a pad having a polishing surface, a subsystem for holding a substrate and the polishing surface together during a polishing step, and a temperature sensor oriented to measure a temperature of the polishing surface, wherein the subsystem accepts the temperature measured by the sensor and is programmed to vary a polishing process parameter in response to the measured temperature. In an aspect, a chemical mechanical polishing apparatus having a platen for holding a pad having a polishing surface, a fluid delivery system for transporting a fluid from a source to the polishing surface, and a temperature controller which during operation controls the temperature of the fluid transported by the delivery system.11-04-2010
20100273277RAPID THERMAL PROCESSING SYSTEMS AND METHODS FOR TREATING MICROELECTRONIC SUBSTRATES - Rapid thermal processing systems and associated methods are disclosed herein. In one embodiment, a method for heating a microelectronic substrate include generating a plasma, applying the generated plasma to a surface of the microelectronic substrate, and raising a temperature of the microelectronic substrate with the generated plasma applied to the surface of the microelectronic substrate. The method further includes continuing to apply the generated plasma until the microelectronic substrate reaches a desired temperature.10-28-2010
20100009468METHOD OF MANUFACTURE FOR SEMICONDUCTOR PACKAGE WITH FLOW CONTROLLER - A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate or semiconductor package at one or more various locations. Flow controllers can control or direct the flow of the molding compound during the encapsulation process. Flow controllers can be sized, shaped, and positioned in order to smooth out the flow of the molding compound, such that the speed of the flow is substantially equivalent over areas of the substrate containing dies and over areas of the substrate without dies. In this manner, defects such as voids in the encapsulation, wire sweeping, and wire shorts can be substantially avoided during encapsulation.01-14-2010
20090061539Substrate holding structure and method of producing semiconductor device using the same - A substrate holding structure includes a wafer stage having a first main surface and a second main surface opposite to the first main surface. A substrate placing area is defined on the first main surface. The substrate holding structure further includes a static capacity measurement electrode having a center circular electrode and at least one circular ring electrode for measuring a combined capacity among a substrate to be placed in the substrate placing area, the center circular electrode, and the circular ring electrode; at least one temperature measurement unit; an electrode control unit connected to the center circular electrode and the circular ring electrode; a temperature control unit connected to the temperature measurement unit and the temperature adjustment unit; a storage unit; a calculation unit connected to the storage unit; and a control unit connected to the electrode control unit and the temperature control unit.03-05-2009
20100291713METHOD OF FORMING HIGHLY CONFORMAL AMORPHOUS CARBON LAYER - A method of forming a conformal amorphous hydrogenated carbon layer on an irregular surface of a semiconductor substrate includes: vaporizing a hydrocarbon-containing precursor; introducing the vaporized precursor and an argon gas into a CVD reaction chamber inside which the semiconductor substrate is placed; depositing a conformal amorphous hydrogenated carbon layer on the irregular surface of the semiconductor substrate by plasma CVD; and controlling the deposition of the conformal ratio of the depositing conformal amorphous hydrogenated carbon layer. The controlling includes (a) adjusting a step coverage of the conformal amorphous hydrogenated carbon layer to about 30% or higher as a function of substrate temperature, and (b) adjusting a conformal ratio of the conformal amorphous hydrogenated carbon layer to about 0.9 to about 1.1 as a function of RF power and/or argon gas flow rate,11-18-2010
20120083050DETECTING A DEPOSITION CONDITION - Apparatus and methods for detecting evaporation conditions in an evaporator for evaporating metal onto semiconductor wafers, such as GaAs wafers, are disclosed. One such apparatus can include a crystal monitor sensor configured to detect metal vapor associated with a metal source prior to metal deposition onto a semiconductor wafer. This apparatus can also include a shutter configured to remain in a closed position when the crystal monitor sensor detects an undesired condition, so as to prevent metal deposition onto the semiconductor wafer. In some implementations, the undesired condition can be indicative of a composition of a metal source, a deposition rate of a metal source, impurities of a metal source, position of a metal source, position of an electron beam, and/or intensity of an electron beam.04-05-2012
20120258555Multi-Frequency Hollow Cathode and Systems Implementing the Same - A hollow cathode system is provided for plasma generation in substrate plasma processing. The system includes an electrically conductive member shaped to circumscribe an interior cavity, and formed to have a process gas inlet in fluid communication with the interior cavity, and formed to have an opening that exposes the interior cavity to a substrate processing region. The system also includes a first radiofrequency (RF) power source in electrical communication with the electrically conductive member so as to enable transmission of a first RF power to the electrically conductive member. The system further includes a second RF power source in electrical communication with the electrically conductive member so as to enable transmission of a second RF power to the electrically conductive member. The first and second RF power sources are independently controllable with regard to frequency and amplitude.10-11-2012
20130171745ENERGY METER CALIBRATION AND MONITORING - A method of controlling a thermal treatment process for semiconductor substrates is described. A substrate is disposed in a thermal process chamber. A plurality of test locations are identified on the substrate surface, and the test locations are processed with different combinations of energy fluence and exposure duration. A physical property such as reflectivity is measured for each test process, and the data compared to a standard data set. The performance of the process is thus compared to a known physical quantity, and an adjustment applied to correct performance of the thermal processing apparatus.07-04-2013
20120322168CHEMICAL VAPOR DEPOSITION APPARATUS - System and method for forming one or more materials. The system includes a susceptor component configured to rotate around a central axis, and a showerhead component that is located above the susceptor component and not in direct contact with the susceptor component. Additionally, the system includes one or more substrate holders located on the susceptor component and configured to rotate around the central axis and also rotate around corresponding holder axes respectively, and a central component. Moreover, the system includes one or more first inlets formed within the central component, one or more second inlets, and one or more third inlets formed within the showerhead component and located farther away from the central component than the one or more second inlets.12-20-2012
20120276660SYSTEM FOR NON RADIAL TEMPERATURE CONTROL FOR ROTATING SUBSTRATES - Embodiments of the present invention provide apparatus and method for reducing non uniformity during thermal processing. One embodiment provides an apparatus for processing a substrate comprising a chamber body defining a processing volume, a substrate support disposed in the processing volume, wherein the substrate support is configured to rotate the substrate, a sensor assembly configured to measure temperature of the substrate at a plurality of locations, and one or more pulse heating elements configured to provide pulsed energy towards the processing volume.11-01-2012
20120329178NOVEL THERMAL PROCESSING APPARATUS - The present invention generally relates to an optical system that is able to reliably deliver a uniform amount of energy across an anneal region contained on a surface of a substrate. The optical system is adapted to deliver, or project, a uniform amount of energy having a desired two-dimensional shape on a desired region on the surface of the substrate. An energy source for the optical system is typically a plurality of lasers, which are combined to form the energy field.12-27-2012
20100167426PLASMA ETCHING APPARATUS AND PLASMA ETCHING METHOD - The invention provides a method for overcoming the drawbacks of deteriorated throughput, deteriorated reproducibility and plasma discharge instability when continuous discharge is performed during multiple steps of plasma etching. The present invention provides a gas switching method for switching from gas supply source 07-01-2010
20100167425METHOD OF PRODUCING BONDED SILICON WAFER - A bonded silicon wafer is produced by a method comprising a step of implanting oxygen ions from one surface of a silicon wafer for active layer to form an oxygen ion implanted layer, a step of bonding the one surface of the silicon wafer for active layer to one surface of a silicon wafer for support layer and then conducting a heat treatment for strengthening the bonding to form a silicon wafer composite, a step of polishing a silicon portion at a side of the silicon wafer for active layer in the silicon wafer composite on a rotating platen having a polishing means and stopping the polishing at a time of detecting change of physical properties on the rotating platen resulting from the exposure of at least a part of the oxygen ion implanted layer and a step of removing the oxygen ion implanted layer.07-01-2010
20100167424VARIABLE THICKNESS SINGLE MASK ETCH PROCESS - The present invention relates to a method of performing a variable film etch using a variable thickness photomask material. Essentially, a thickness of an adjustable film layer is measured and converted into a contour map of film thickness over a region of a semiconductor body (e.g., wafer). An etch mask layer (e.g., photoresist) is then formed above the adjustable film layer and is selectively patterned by a reticleless exposure system (e.g., DMD exposure system). The selective patterning subjects different regions of the etch mask layer to varying exposure times dependent upon the thickness of the underlying adjustable film. The more etching needed to provide the underlying film to a nominal thickness, the longer the exposure of the etch mask. Therefore, the resultant etch mask, after exposure, comprises a topology allowing for various degrees of selective etching of the underlying film resulting in a uniform film.07-01-2010
20130011937METHOD FOR WAFER BACK-GRINDING CONTROL - A method of reducing manufacturing defects of semiconductor wafers during a back-grinding process. The method includes receiving a semiconductor wafer on a chuck table, wherein said chuck table has a surface upon which a front side of the wafer is placed, and wherein said chuck table has one or more holes in surface and one or more sensors placed in said one or more holes. The method further includes grinding at least a portion of a back side of the semiconductor wafer. The method further includes monitoring a parameter, while grinding, measured by the one or more sensors and adjusting the grinding based at least on the monitored parameter.01-10-2013
20130011936SELECTIVE ETCHING BATH METHODS - An etching method. The method includes etching a first plurality of silicon wafers in a first enchant, each silicon wafer having SiO01-10-2013
20120149133MEMS PROCESS METHOD FOR HIGH ASPECT RATIO STRUCTURES - Methods for the controlled manufacture of high aspect ratio features. The method may include forming a layer stack on a top surface of a substrate and forming features in the layers of the layer stack. The high aspect ratio features may be defined using a resist layer that is patterned with a photolithographic condition. After removing at least one of the layers removed from the top of the layer stack, a feature dimension may be measured for features at different locations on the substrate. The method may further include changing the photolithographic condition based on the measured dimension and processing another substrate using the changed photolithographic condition.06-14-2012
20130023066SYSTEM AND METHOD FOR INCREASING PRODUCTIVITY OF ORGANIC LIGHT EMITTING DIODE MATERIAL SCREENING - A system and method of increasing productivity of OLED material screening includes providing a substrate that includes an organic semiconductor, processing regions on the substrate by combinatorially varying parameters associated with the OLED device production on the substrate, performing a first characterization test on the processed regions on the substrate to generate first results, processing regions on the substrate in a combinatorial manner by varying parameters associated with the OLED device production on the substrate based on the first results of the first characterization test, performing a second characterization test on the processed regions on the substrate to generate second results, and determining whether the substrate meets a predetermined quality threshold based on the second results.01-24-2013
20130023064Negative Ion Control for Dielectric Etch - Apparatus, methods, and computer programs for semiconductor processing in a capacitively-coupled plasma chamber are provided. A chamber includes a bottom radio frequency (RF) signal generator, a top RF signal generator, and an RF phase controller. The bottom RF signal generator is coupled to the bottom electrode in the chamber, and the top RF signal generator is coupled to the top electrode. Further, the bottom RF signal is set at a first phase, and the top RF signal is set at a second phase. The RF phase controller is operable to receive the bottom RF signal and operable to set the value of the second phase. Additionally, the RF phase controller is operable to track the first phase and the second phase to maintain a time difference between the maximum of the top RF signal and the minimum of the bottom RF signal at approximately a predetermined constant value, resulting in an increase of the negative ion flux to the surface of the wafer.01-24-2013
20130023065Apparatus and Methods for End Point Determination in Reactive Ion Etching - Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed.01-24-2013
20080248597Methods for determining a dose of an impurity implanted in a semiconductor substrate and an apparatus for same - Methods of determining a total impurity dose for a plasma doping process, and an apparatus configured to determine same. A total ion dose implanted in a semiconductor substrate is directly measured, such as by utilizing a Faraday cup. A ratio of impurity-based ion species to non-impurity-based ion species in a plasma generated by the plasma doping process and a ratio of each impurity-based ion species to a total impurity-based ion species in the plasma are directly measured. The ratios may be directly measured by ion mass spectroscopy. The total ion dose and the ratios are used to determine the total impurity dose. The apparatus includes an ion detector, an ion mass spectrometer, a dosimeter, and software.10-09-2008
20080241971Method and apparatus for performing a site-dependent dual patterning procedure - The present invention includes a method of performing a double-patterning (DP) processing sequence using a plurality of Site-Dependent (S-D) procedures, the method including receiving a first set of wafers by one or more subsystems in a processing system, creating one or more first patterned layers on a first set of patterned wafers, establishing first confidence data for the first set of patterned wafers, establishing a first set of high confidence wafers, creating one or more second patterned layers on a second set of patterned wafers, establishing second confidence data for the second set of patterned wafers and establishing a second set of high confidence wafers.10-02-2008
20120252141Adaptive Recipe Selector - The invention provides a method of processing a wafer using Ion Energy (IE)-related multilayer process sequences and Ion Energy Controlled Multi-Input/Multi-Output (IEC-MIMO) models and libraries that can include one or more measurement procedures, one or more IEC-etch sequences, and one or more Ion Energy Optimized (IEO) etch procedures. The IEC-MIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple IEC etch sequences. The multiple layers and/or the multiple IEC etch sequence can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using IEO etch procedures.10-04-2012
20130102091TEST SYSTEM SUPPORTING SIMPLIFIED CONFIGURATION FOR CONTROLLING TEST BLOCK CONCURRENCY - Techniques for configuring a test system that enable simple specification of a degree of concurrency in testing separate functional portions of a semiconductor device. For a test flow with multiple sub-flows; the pins accessed in connection with each sub-flow may define a flow domain. Site regions, each associated with a flow domain, may be defined. Tester sites may be associated with each of these flow domain specific site regions and independently operating resources may be assigned to these tester sites. A second portion of the defined site regions may be associated with tester sites, but resources assigned to these site regions may be accessed from multiple flow domains. Test blocks, even if not developed for concurrent execution, may be executed concurrently using resources in the flow domain specific site regions. Flexibility is provided to share resources through the use of the second portion of the site regions.04-25-2013
20130149799WAFER TEMPERATURE CORRECTION SYSTEM FOR ION IMPLANTATION DEVICE - To provide an ion implantation device capable of correcting the temperature of the wafer. The ion implantation device of the present invention has: an irradiation means that radiates ions; a retention means that includes a disk 06-13-2013
20110275166SYSTEMS AND METHODS FOR THIN-FILM DEPOSITION OF METAL OXIDES USING EXCITED NITROGEN-OXYGEN SPECIES - The present invention relates to a process and system for depositing a thin film onto a substrate. One aspect of the invention is depositing a thin film metal oxide layer using atomic layer deposition (ALD).11-10-2011
20100297782TECHNIQUES FOR PROCESSING A SUBSTRATE - Herein, an improved technique for processing a substrate is disclosed. In one particular exemplary embodiment, the technique may be realized with a system for processing one or more substrates. The system may comprise an ion source for generating ions of desired species, the ions generated from the ion source being directed toward the one or more substrates along an ion beam path; a substrate support for supporting the one or more substrates; a mask disposed between the ion source and the substrate support, the mask comprising a finger defining one or more apertures through which a portion of the ions traveling along the ion beam path pass; and a first detector for detecting ions, the first detector being fixedly positioned relative to the one or more substrates.11-25-2010
20130157387Multi-zone EPD Detectors - The present disclosure relates to a semiconductor body etching apparatus having a multi-zone end point detection system. In some embodiments, the multi-zone end point detection system has a processing chamber that houses a workpiece that is etched according to an etching process. A plurality of end point detector (EPD) probes are located within the processing chamber. Respective EPD probes are located within different zones in the processing chamber, thereby enabling the detection of end point signals from multiple zones within the processing chamber. The detected end point signals are provided from the plurality of EPD probes to an advanced process control (APC) unit. The APC unit is configured to make a tuning knob adjustment to etching process parameters based upon the detected end point signals and to thereby account for etching non-uniformities.06-20-2013
20110312106METHOD FOR PREPARING A LIGHT-EMITTING DEVICE USING GAS CLUSTER ION BEAM PROCESSING - A method of manufacturing semiconductor-based light-emitting devices, such as light-emitting diodes (LEDs), is described. The method comprises irradiating an interface region with a gas cluster ion beam (GCIB) to improve the interface region between a light-emitting device stack and the substrate, within the light-emitting device stack, and/or between the light-emitting device stack and a metal contact layer in an end-type contact.12-22-2011
20130189800PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - A plasma processing apparatus is provided which includes an inert gas supply route connected to a process gas supply piping which supplies a process gas into a processing chamber in a vacuum vessel, a valve which opens or closes the inert gas supply route, and an adjuster which adjusts a flow rate of the inert gas. When processing of a sample is complete, an inert gas is supplied into the process gas supply piping so that a pressure in the process gas supply piping is maintained at a pressure higher than a pressure at which a compound of the process gas and a material of an inner wall of the process gas supply piping vaporizes.07-25-2013
20120015454METHOD OF MANUFACTURING EPITAXIAL SILICON WAFER AND APPARATUS THEREFOR - A method of forming an epitaxial layer to increase flatness of an epitaxial silicon wafer is provided. In particular, a method of controlling the epitaxial layer thickness in a peripheral part of the wafer is provided. An apparatus for manufacturing an epitaxial wafer by growing an epitaxial layer with reaction of a semiconductor wafer and a source gas in a reaction furnace comprising: a pocket in which the semiconductor wafer is placed; a susceptor fixing the semiconductor; orientation-dependent control means dependent on a crystal orientation of the semiconductor wafer and/or orientation-independent control means independent from the crystal orientation of the semiconductor wafer, wherein the apparatus may improve flatness in a peripheral part of the epitaxial layer.01-19-2012
20120021538PLASMA PROCESSING METHOD AND STORAGE MEDIUM - There is provided a plasma processing method performing a plasma etching process on an oxide film of a target substrate through one or more steps by using a processing gas including a CF-based gas and a COS gas. The plasma processing method includes: performing a plasma etching process on the oxide film of the target substrate according to a processing recipe; measuring a concentration of sulfur (S) remaining on the target substrate (residual S concentration) after the plasma etching process is performed according to the processing recipe; adjusting a ratio of a COS gas flow rate with respect to a CF-based gas flow rate (COS/CF ratio) so as to allow the residual S concentration to become equal to or smaller than a predetermined value; and performing an actual plasma etching process according to a modified processing recipe storing the adjusted COS/CF ratio.01-26-2012
20120021537METHODS OF EVALUATING EPITAXIAL GROWTH AND METHODS OF FORMING AN EPITAXIAL LAYER - A method of evaluating an epitaxial growing process includes forming a mold layer on each of a plurality of substrates, forming a photoresist pattern on each mold layer, the photoresist pattern having opening portions, a total area of a bottom portion of the opening portions being different for each substrate, patterning each mold layer to expose a surface portion of the substrate to form an evaluation pattern on each substrate, evaluation patterns including opening portions corresponding to the opening portion in the photoresist pattern, determining substrate opening ratios for each substrate based on the opening portions in the evaluation pattern thereon, the substrate opening ratios being different for each substrate, performing a selective epitaxial process on each substrate to form an epitaxial layer, and evaluating characteristics of the epitaxial layer for each substrate to determine an optimal substrate opening ratio.01-26-2012
20120021536METHOD AND SYSTEM FOR APPLICATION OF AN INSULATING DIELECTRIC MATERIAL TO PHOTOVOLTAIC MODULE SUBSTRATES - A method and related system are provided for depositing a dielectric material into voids in one or more of the semiconductor material layers of a photovoltaic (PV) module substrate. A first side of the substrate is exposed to a light source such that light is transmitted through the substrate and any voids in the semiconductor material layers on the opposite side of the substrate. The light transmitted through the voids is detected and a printer is registered to the pattern of detected light to print a dielectric material and fill the voids.01-26-2012
20120028376Method of Controlling Critical Dimensions of Trenches in a Metallization System of a Semiconductor Device During Etch of an Etch Stop Layer - When forming metal lines and vias in complex metallization systems of semiconductor devices, an additional control mechanism for adjusting the final critical dimension may be implemented in the last etch process for etching through the etch stop layer after having patterned the low-k dielectric material. To this end, the concentration of a polymerizing gas may be controlled in accordance with the initial critical dimension obtained after the lithography process, thereby efficiently re-adjusting the final critical dimension so as to be close to the desired target value.02-02-2012
20130196453PRESUMABLY DEFECTIVE PORTION DECISION APPARATUS, PRESUMABLY DEFECTIVE PORTION DECISION METHOD, FABRICATION METHOD FOR SEMICONDUCTOR DEVICE AND PROGRAM - Disclosed herein is a presumably defective portion decision apparatus, including: an arithmetic operation section configured to divide a level difference included in level difference data which indicate a level difference distribution on the surface of a semiconductor device into two or more unit level differences in the depthwise direction of the level difference and determine, for each of the unit level differences obtained by the division, a relationship between the height of a contour line at a level difference position of an upper face and an area of an opening surrounded by the contour line to decide presence or absence of a presumably defective portion.08-01-2013
20130196454VAPOR DEPOSITION METHOD, VAPOR DEPOSITION DEVICE AND ORGANIC EL DISPLAY DEVICE - A coating film (08-01-2013
20120034713PROCESS, VOLTAGE, TEMPERATURE SENSOR - An integrated circuit includes a process sensor, a temperature sensor, and a voltage sensor. The process sensor is configured to sense a process parameter indicative of a semiconductor process by which the integrated circuit is formed and, based upon the sensed process parameter, to provide a characterization of the semiconductor process to the output of the process sensor. The temperature sensor is configured to provide an indication of a temperature of the integrated circuit to an output of the temperature sensor and the voltage sensor is configured to provide an indication of a power supply voltage level of the integrated circuit to an output of the voltage sensor. The output of the process sensor is coupled to at least one of the temperature sensor and the voltage sensor to compensate at least one of the indication of the temperature and the indication of the power supply voltage level.02-09-2012
20120088316SYSTEM AND METHOD FOR WAFER BACK-GRINDING CONTROL - In a system or method for controlling wafer back-grinding, a chuck table has a surface for supporting a semiconductor wafer during a back-grinding process, one or more holes in the surface, and one or more sensors disposed in the one or more holes for monitoring a parameter during back-grinding. A computer-implemented process control tool is coupled to receive one or mote outputs from the one or more sensors and control the back-grinding process based on the received one or more outputs.04-12-2012
20130210171METHOD FOR MOLECULAR ADHESION BONDING WITH COMPENSATION FOR RADIAL MISALIGNMENT - A method for bonding a first wafer on a second wafer by molecular adhesion, where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment.08-15-2013

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