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HAVING MAGNETIC OR FERROELECTRIC COMPONENT

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438 - Semiconductor device manufacturing: process

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DocumentTitleDate
20130040408METHOD OF FABRICATING RESISTANCE VARIABLE MEMORY DEVICE AND DEVICES AND SYSTEMS FORMED THEREBY - An exemplary method of forming a variable resistance memory may include forming first source/drain regions in a substrate, forming gate line structures and conductive isolation patterns buried in the substrate with the first source/drain regions interposed therebetween, and forming lower contact plugs on the first source/drain regions. The forming of lower contact plugs may include forming a first interlayer insulating layer, including a first recess region exposing the first source/drain regions adjacent to each other in a first direction, forming a conductive layer in the first recess region, patterning the conductive layer to form preliminary conductive patterns spaced apart from each other in the first direction, and patterning the preliminary conductive patterns to form conductive patterns spaced apart from each other in a second direction substantially orthogonal to the first direction.02-14-2013
20110183440SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, AND THIN FILM DEVICE - A manufacturing method of a semiconductor device is disclosed. The manufacturing method includes the steps of forming a contact plug in an insulation film so as to be connected to an element on a semiconductor substrate, applying PLA pretreatment to the insulation film in an NH07-28-2011
20120184053METHOD OF MANUFACTURING A MAGNETIC READ SENSOR HAVING A LOW RESISTANCE CAP STRUCTURE - A method for manufacturing a magnetic sensor that decreases area resistance and decreases MR ratio of the sensor by eliminating any oxide formation in the capping layer of the sensor. The method includes forming a sensor stack having a multi-layer capping structure formed there-over. The multi-layer capping structure can include first, second, third and fourth layers. The second layer is constructed of a material that is not easily oxidized and which is different from the first layer. The sensor can be formed using a mask that includes a carbon hard mask. After the sensor stack has been formed by ion milling, the hard mask can be removed by reactive ion etching. Then, a cleaning process is performed to remove the second, third and fourth layers of the capping layer structure using an end point detection method such as secondary ion mass spectrometry to detect the presence of the second layer.07-19-2012
20130078742ENHANCEMENT OF PROPERTIES OF THIN FILM FERROELECTRIC MATERIALS - Methods are provided for enhancing properties, including polarization, of thin-film ferroelectric materials in electronic devices. According to one embodiment, a process for enhancing properties of ferroelectric material in a device having completed wafer processing includes applying mechanical stress to the device, independently controlling the temperature of the device to cycle the temperature from room temperature to at or near the Curie temperature of the ferroelectric material and back to room temperature while the device is applied with the mechanical stress, and then removing the mechanical stress. Certain of the subject methods can be performed as part of a back end of line (BEOL) process, and may be performed during the testing phase at wafer or die level.03-28-2013
20130084653MEDIUM PATTERNING METHOD AND ASSOCIATED APPARATUS - According to one embodiment, a method for patterning a medium having a patterned hard mask applied thereon is disclosed herein. The patterned hard mark includes a plurality of apertures exposing portions of the medium. The method includes directing ions toward the medium, implanting a portion of the ions into the exposed portions of the medium, removing a layer of the patterned hard mask with another portion of the ions, and depositing hard mask material onto the patterned hard mask. Depositing hard mask material onto the exposed portions of the medium may follow implantation of the portion of the ions into the exposed portions of the medium.04-04-2013
20130034917METHOD FOR FABRICATING MAGNETIC TUNNEL JUNCTION DEVICE - A method for fabricating a semiconductor device includes forming a plurality of layers which are stacked as a bottom layer, an MTJ layer, and a top layer, patterning the top layer and the MTJ layer using an etch mask pattern to form a top layer pattern and an MTJ pattern, forming a carbon spacer on the sidewalls of the MTJ pattern and the top layer pattern to protect the MTJ pattern and the top layer pattern, and patterning the bottom layer using the carbon spacer and the etch mask pattern as an etch mask to form a bottom layer pattern.02-07-2013
20130210169MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING REDUCTION OF FERROELECTRIC FILM - A ferroelectric capacitor is formed on a semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode stacked in an order recited. A first capacitor protective film of aluminum oxide having a thickness equal to or thicker than 30 nm is formed covering the ferroelectric capacitor. A first insulating film of silicon oxide is formed on the first capacitor protective film by chemical vapor deposition using high density plasma.08-15-2013
20090155932METHOD OF MANUFACTURING MAGNETIC FIELD DETECTOR - Disclosed is a method of manufacturing a magnetic field detector having various structures that can be used as a high-density magnetic biosensor. An embodiment of the invention provides a method of manufacturing a magnetic field detector including a magnetoresistive element using a magnetic bead detecting thin film. The method includes: preparing a substrate; depositing the thin film on an upper surface of the substrate; and etching the thin film to form a ring-shaped magnetoresistive element.06-18-2009
20090155931FERROELECTRIC LAYER WITH DOMAINS STABILIZED BY STRAIN - The present invention describes a method including: providing a substrate; forming an underlying layer over the substrate; heating the substrate; forming a ferroelectric layer over the underlying layer, the ferroelectric layer having a thickness below a critical thickness, the underlying layer having a smaller lattice constant than the ferroelectric layer; cooling the substrate to room temperature; and inducing a compressive strain in the ferroelectric layer.06-18-2009
20100105152SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A lower electrode film is formed above a semiconductor substrate first, and then a ferroelectric film is formed on the lower electrode film. After that, an upper electrode film is formed on the ferroelectric film. When forming the upper electrode, an IrO04-29-2010
20100041168METHODS OF FABRICATING MAGNETIC MEMORY DEVICES WITH THIN CONDUCTIVE BRIDGES - A magnetic memory device includes a free layer and a guide layer on a substrate. An insulating layer is interposed between the free layer and the guide layer. At least one conductive bridge passes through the insulating layer and electrically connects the free layer and the guide layer. A diffusion barrier may be interposed between the guide layer and the insulating layer. The device may further include a reference layer having a fixed magnetization direction on a side of the free layer opposite the insulating layer and a tunnel barrier between the reference layer and the free layer. Related fabrication methods are also described.02-18-2010
20120107966MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION - A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, the method includes depositing a capping material on a free layer of a magnetic tunneling junction structure to form the capping layer and oxidizing a portion of the capping material to form a layer of oxidized material.05-03-2012
20130029432THIN-WAFER CURRENT SENSORS - Embodiments relate to IC current sensors fabricated using thin-wafer manufacturing technologies. Such technologies can include processing in which dicing before grinding (DBG) is utilized, which can improve reliability and minimize stress effects. While embodiments utilize face-up mounting, face-down mounting is made possible in other embodiments by via through-contacts. IC current sensor embodiments can present many advantages while minimizing drawbacks often associated with conventional IC current sensors.01-31-2013
20130029431METHOD FOR MANUFACTURING NONVOLATILE MEMORY DEVICE - According to one embodiment, a method for manufacturing a nonvolatile memory device including a plurality of memory cells is disclosed. Each of the plurality of memory cells includes a base layer including a first electrode, a magnetic tunnel junction device provided on the base layer, and a second electrode provided on the magnetic tunnel junction device. The magnetic tunnel junction device includes a first magnetic layer, a tunneling barrier layer provided on the first magnetic layer, and a second magnetic layer provided on the tunneling barrier layer. The method can include etching a portion of the second magnetic layer and a portion of the first magnetic layer by irradiating gas clusters onto a portion of a surface of the second magnetic layer or a portion of a surface of the first magnetic layer.01-31-2013
20130130405APPARATUS AND METHODS FOR SILICON OXIDE CVD RESIST PLANARIZATION - Embodiments of the present invention provide methods and apparatus for forming a patterned magnetic layer for use in magnetic media. According to embodiments of the present application, a silicon oxide layer formed by low temperature chemical vapor deposition is used to form a pattern in a hard mask layer, and the patterned hard mask is used to form a patterned magnetic layer by plasma ion implantation.05-23-2013
20100003767MAGNETIC TUNNEL JUNCTION DEVICE, MEMORY CELL HAVING THE SAME, AND METHOD FOR FABRICATING THE SAME - A method for fabricating a magnetic tunnel junction device includes forming an insulation layer having a plurality of openings, forming a first electrode over the bottom and the sidewall of an opening of the plurality of openings, forming a magnetic tunnel junction layer over the first electrode, and forming a second electrode over the magnetic tunnel junction layer to fill the remaining openings.01-07-2010
20130071954MAGNETIC RANDOM ACCESS MEMORY (MRAM) WITH ENHANCED MAGNETIC STIFFNESS AND METHOD OF MAKING SAME - A spin toque transfer magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B). Annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer. Cooling down of the STTMRAM element to a second temperature that is lower than the first temperature is performed and a third free sub-layer is directly deposited on top of the second free layer, with the third free sub-layer being made partially of boron (B), wherein the amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer.03-21-2013
20130059401METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device includes forming a depression in an upper portion of a semiconductor substrate, placing a sacrificial material in the depression, forming a plurality of fins extending in one direction and arranged periodically by selectively removing the semiconductor substrate and the sacrificial material, forming a device isolation insulating film in a lower portion of space between the fins, removing the sacrificial material, forming a gate insulating film on an exposed surface of the fin, and forming a gate electrode. The gate electrode extends in a direction crossing the one direction so as to straddle the fin on the device isolation insulating film.03-07-2013
20100068829MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING REDUCTION OF FERROELECTRIC FILM - A ferroelectric capacitor is formed on a semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode stacked in an order recited. A first capacitor protective film of aluminum oxide having a thickness equal to or thicker than 30 nm is formed covering the ferroelectric capacitor. A first insulating film of silicon oxide is formed on the first capacitor protective film by chemical vapor deposition using high density plasma.03-18-2010
20120225500TRANSPARENT NONVOLATILE MEMORY THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - Provided are a transparent nonvolatile memory thin film transistor (TFT) and a method of manufacturing the same. The memory TFT includes source and drain electrodes disposed on a transparent substrate. A transparent semiconductor thin layer is disposed on the source and drain electrodes and the transparent substrate interposed between the source and drain electrodes. An organic ferroelectric thin layer is disposed on the transparent semiconductor thin layer. A gate electrode is disposed on the organic ferroelectric thin layer in alignment with the transparent semiconductor thin layer. Thus, the transparent nonvolatile memory TFT employs the organic ferroelectric thin layer, the oxide semiconductor thin layer, and auxiliary insulating layers disposed above and below the organic ferroelectric thin layer, thereby enabling low-cost manufacture of a transparent nonvolatile memory device capable of a low-temperature process.09-06-2012
20120225499Method for Use in Making Electronic Devices Having Thin-Film Magnetic Components - Disclosed herein is a method of forming electronic device having thin-film components by using trenches. One or more of thin-film components is formed by depositing a thin-film in the trench followed by processing the deposited thin-film to have the desired thickness.09-06-2012
20120225498MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, a manufacturing method of semiconductor device includes forming plural elements on a substrate, forming a silicon compound film so as to bury between a plurality of elements, and modifying the silicon compound film to a silicon dioxide film by radiating microwaves.09-06-2012
20130065326METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a mask film on a partial region of a semiconductor substrate; forming a mask member above the semiconductor substrate in both the region where the mask film is formed and a region where the mask film is not formed; patterning the mask film and an upper portion of the semiconductor substrate by performing etching using the mask member as a mask. The method further includes removing part of the patterned upper portion of the semiconductor substrate by performing etching using the patterned mask film as a mask.03-14-2013
20090233382High Polarization Ferroelectric Capacitors for Integrated Circuits - One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectric cores during cooling.09-17-2009
20090233381Interconnect For a GMR Memory Cells And An Underlying Conductive Layer - A conductive plug located in a planar dielectric layer, under GMR memory cells, are used to directly connect the lower ferromagnetic layer of one of the GMR memory cell and a conductive layer under the planar dielectric layer.09-17-2009
20090047747Method of forming an amorphous ferroelectric memory device - This disclosure relates to amorphous ferroelectric memory devices and methods for forming them.02-19-2009
20120115251PROCESS FOR SELECTIVELY PATTERNING A MAGNETIC FILM STRUCTURE - Processes for selectively patterning a magnetic film structure generally include selectively etching an exposed portion of a freelayer disposed on a tunnel barrier layer by a wet process, which includes exposing the freelayer to an etchant solution comprising at least one acid and an organophosphorus acid inhibitor or salt thereof, stopping on the tunnel barrier layer.05-10-2012
20120115250CONCAVE-CONVEX PATTERN FORMING METHOD AND MAGNETIC TUNNEL JUNCTION ELEMENT FORMING METHOD - A method of forming a concave-convex pattern according to an embodiment includes: forming a guide pattern on a base material, the guide pattern having a convex portion; forming a formative layer on the guide pattern, the formative layer including a stacked structure formed by stacking a first layer and a second layer, the first layer including at least one element selected from a first metal element and a metalloid element, the second layer including a second metal element different from the first metal element; selectively leaving the formative layer only at side faces of the convex portions by performing etching on the formative layer; removing the guide pattern; and forming the concave-convex pattern in the base material by performing etching on the base material, with the remaining formative layer being used as a mask.05-10-2012
20110104829METHOD OF TRANSFER BY MEANS OF A FERROELECTRIC SUBSTRATE - A method of carrying out a transfer of one or more first components or of a first layer onto a second substrate including: a) application and maintaining, by electrostatic effect, of the one or more first components or of the first layer, on a first substrate, made of a ferroelectric material, electrically charged, b) placing in contact, direct or by molecular adhesion, and transfer of the components or the layer onto a second substrate, and c) dismantling of the first substrate, leaving at least one part of the components or the layer on the second substrate.05-05-2011
20090035877METHODS OF FORMING A FERROELECTRIC LAYER AND METHODS OF MANUFACTURING A FERROELECTRIC CAPACITOR INCLUDING THE SAME - A method of forming a ferroelectric layer is provided. A metal-organic source gas is provided into a chamber into which an oxidation gas is provided for a first time period to form ferroelectric grains on a substrate. A ferroelectric layer is formed by performing at least twice a step of providing a metal-organic source gas into the chamber during the first time period using a pulse method to grow the ferroelectric grains.02-05-2009
20110076785Process to fabricate bottom electrode for MRAM device - Formation of a bottom electrode for an MTJ device on a silicon nitride substrate is facilitated by including a protective coating that is partly consumed during etching of the alpha tantalum portion of said bottom electrode. Adhesion to SiN is enhanced by using a TaN/NiCr bilayer as “glue”.03-31-2011
20100129938SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate and a transistor formed on the semiconductor substrate. The semiconductor device also includes: a first interlayer insulation film formed on the semiconductor substrate including the upper portion of the transistor, a first contact formed to be connected through the first interlayer insulation film to the transistor, a ferroelectric capacitor formed to be connected to the first contact, a second interlayer insulation film formed on the first interlayer insulation film, and a second contact formed to connect the ferroelectric capacitor to a wiring through the second interlayer insulation film. The contact surfaces between the second contact and the ferroelectric capacitor have the same planar shape.05-27-2010
20100120175SENSOR DOUBLE PATTERNING METHODS - A method of making a memory cell or magnetic element by double patterning. The method includes providing a starting stack having a first area, masking a portion of the first area of the starting stack resulting in a first masked portion and a first unmasked portion. Then, removing the first unmasked portion of the starting stack to provide a second area. A portion of this second area is masked, resulting in a second masked portion and a second unmasked portion. The method also includes removing the second unmasked portion to provide a third area, with the finished cell or element being the third area.05-13-2010
20120288965SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Stable contact hole forming is attained even when an aluminum oxide film is present between layers provided with contact holes. The process comprises the steps of forming a first element layer on a semiconductor substrate; forming a first interlayer insulating film on the first element layer; forming a second element layer on the first interlayer insulating film; forming a second interlayer insulating film on the second element layer; forming a hole resist pattern on the second interlayer insulating film; conducting a first etching for forming of holes by etching the second interlayer insulating film; and conducting a second etching for extending of holes to the first element layer by etching the first interlayer insulating film.11-15-2012
20110281375MAGNETIC MICROELECTRONIC DEVICE ATTACHMENT - The present disclosure relates to the field of fabricating microelectronic packages, wherein microelectronic devices of the microelectronic packages may have magnetic attachment structures comprising a magnetic material formed on an attachment structure. The microelectronic device may be aligned on a substrate with a magnetic field and then held in place therewith while being attached to the substrate. The microelectronic device may also be aligned with an alignment plate which magnetically aligns and holds the component in place while being packaged.11-17-2011
20110143459SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A semiconductor substrate includes a wafer including an element area and a non-element area delineating the element area, a first layered structure situated in the element area, a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe, a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate, and a second layered structure situated in the non-element area, wherein the second layered structure includes at least a portion of the first layered structure.06-16-2011
20090093070CAPACITOR, METHOD OF MANUFACTURING THE SAME, METHOD OF MANUFACTURING FERROELECTRIC MEMORY DEVICE, METHOD OF MANUFACTURING ACTUATOR, AND METHOD OF MANUFACTURING LIQUID JET HEAD - A method of manufacturing a capacitor, including: forming a lower electrode on a substrate; forming a dielectric film of a ferroelectric or a piezoelectric on the lower electrode; forming an upper electrode on the dielectric film; and forming a silicon oxide film so that at least the dielectric film is covered with the silicon oxide film, the silicon oxide film being formed by using trimethoxysilane.04-09-2009
20090275147MITIGATION OF EDGE DEGRADATION IN FERROELECTRIC MEMORY DEVICES THROUGH PLASMA ETCH CLEAN - A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.11-05-2009
20100323458METHOD FOR MAKING P(VDF/TrFE) COPOLYMER LAYER SENSORS, AND CORRESPONDING SENSOR - The invention relates to the manufacture of a matrix sensor using a sensitive layer of a ferroelectric P(VDF/TrFE) copolymer, deposited on an integrated circuit. In order to simplify the manufacture and improve the yields, deposited first on the integrated circuit is a first layer of titanium and it is etched in order to form a matrix array of electrodes electrically connected to the integrated circuit; next, a P(VDF/TrFE) copolymer comprising a small proportion of around 1 to 10% of a second polymer that favors the adhesion of the P(VDF/TrFE) copolymer is deposited on the integrated circuit; the polymer is either underneath the P(VDF/TrFE) or blended therewith. The copolymer and its adhesion promoter are etched in a single step, and finally a second conductive layer is deposited and it is etched in order to form a counter electrode for the whole of the matrix array. For use in ultrasonic image sensors.12-23-2010
20110217792SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An FeRAM is produced by a method including the steps of forming a lower electrode layer (09-08-2011
20090098664FERROELECTRIC THIN FILM DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a method of manufacturing a ferroelectric thin film device, and, more particularly, to a method of manufacturing a ferroelectric thin film device having high crystallinity, good surface roughness and high deposition efficiency through on-axis type sputtering, and to a ferroelectric thin film device manufactured using the method. The method of manufacturing a ferroelectric thin film device includes: depositing an SrRuO04-16-2009
20080311683SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method of manufacturing a semiconductor device including forming a lower electrode over a substrate, increasing the temperature of the substrate with the lower electrode to a predetermined temperature under mixture gas atmosphere of inert gas and oxygen gas, forming a dielectric film on the lower electrode by using an organic metal raw material after the temperature reaches the predetermined temperature, and forming an upper electrode on the dielectric film.12-18-2008
20100112728METHODS FOR STRIPPING MATERIAL FOR WAFER RECLAMATION - Removal compositions and processes for removing at least one material layer from a rejected microelectronic device structure having same thereon. The removal composition includes hydrofluoric acid. The composition achieves substantial removal of the material(s) to be removed while not damaging the layers to be retained, for reclaiming, reworking, recycling and/or reuse of said structure.05-06-2010
20110269250GROWTH METHOD OF FE3N MATERIAL - A kind of growth method of Fe11-03-2011
20080311682MICROWAVE INTEGRATED CIRCUIT PACKAGE AND METHOD FOR FORMING SUCH PACKAGE - A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and placement of material on the dielectric layer to provide a predetermined magnetic or electric effect for the device, such effects being provided on the device from such patterned and placed material solely by electrical or magnetic waves coupled between such material and the device; and forming the material in the determined patterns and placement to provide the predetermined effects.12-18-2008
20090298201MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In a manufacturing method of a semiconductor device, a first insulating film covering a ferroelectric capacitor is formed, and a first opening that has a relatively large diameter and reaches an electrode of the ferroelectric capacitor is formed in the first insulating film, and then recovery annealing of the ferroelectric capacitor is performed, and thereby, a path for oxygen can be secured in performing the recovery annealing, and the sufficient recovery annealing can be performed without causing problems during a manufacturing process.12-03-2009
20110229986Magnetic Memory Devices and Methods of Forming the Same - Provided are a magnetic memory device and a method of forming the same. The method may include forming a pinning pattern on a substrate; forming a first interlayer insulating layer that exposes the pinning pattern on the substrate; forming a pinned layer, a tunneling barrier layer and a second magnetic conductive layer on the pinning pattern; and forming a pinned pattern, a tunnel barrier pattern and a second magnetic conductive pattern by performing a patterning process on the pinned layer, the tunnel barrier layer and the second magnetic conductive layer.09-22-2011
20120107965SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an insulating film provided over a semiconductor substrate, a conductive plug buried in the insulating film, an underlying conductive film which is provided on the conductive plug and on the insulating film and which has a flat upper surface, and a ferroelectric capacitor provided on the underlying conductive film. At least in a region on the conductive plug, the concentration of nitrogen in the underlying conductive film gradually decreases from the upper surface to the inside.05-03-2012
20120107964LOW-COST NON-VOLATILE FLASH-RAM MEMORY - A method of flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.05-03-2012
20120107963SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor device which is characterized as follows. The semiconductor device includes: an interlayer insulating film formed above a semiconductor substrate and provided with a hole above an impurity diffusion region; a conductive plug formed in the hole and electrically connected to the impurity diffusion region; a conductive oxygen barrier film formed on the conductive plug and the interlayer insulating film around the conductive plug; a conductive anti-diffusion film formed on the conductive oxygen barrier film; and a capacitor that has a lower electrode which is formed on the conductive anti-diffusion film and which exposes platinum or palladium on the upper surface, a capacitor dielectric film made of a ferroelectric material, and an upper electrode. The conductive anti-diffusion film is made of a non-oxide conductive material for preventing the diffusion of the constituent element of the capacitor dielectric film.05-03-2012
20120107962METHOD OF FABRICATING EPITAXIAL SEMICONDUCTOR DEVICES - A method of fabricating epitaxial semiconductor devices includes: (a) forming an etch limiting film that includes a sacrificial layer on an epitaxial substrate; (b) growing epitaxially layers of a semiconductor structure on the sacrificial layer; (c) forming on the semiconductor structure a layer of a device substrate that can be magnetized, and a patterned passage unit that extends from the device substrate to a depth as deep as the sacrificial layer such that a plurality of semiconductor units are defined in the semiconductor structure and the device substrate; and (d) separating the semiconductor units from the epitaxial substrate by etching laterally the sacrificial layer through the patterned passage unit while a magnetic attraction force is applied to the device substrate.05-03-2012
20100087014HEAT TREATMENT APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a heat treatment apparatus including a treatment chamber housing a silicon substrate, a heater being provided in the treatment chamber and heating the silicon substrate, and an atmosphere adjustment mechanism reducing a concentration of oxygen contained in an atmosphere inside the treatment chamber to less than an oxygen concentration in the air. The atmosphere adjustment mechanism is provided with an oxygen trap, for example.04-08-2010
20090263918METHODS AND APPARATUSES FOR DETERMINING THICKNESS OF A CONDUCTIVE LAYER - Methods and apparatuses are provided for calibrating eddy current sensors. A calibration curve is formed relating thickness of a conductive layer in a magnetic field to a value measured by the eddy current sensors or a value derived from such measurement, such as argument of impedance. The calibration curve may be an analytic function having infinite number terms, such as trigonometric, hyperbolic, and logarithmic, or a continuous plurality of functions, such as lines. Such curves can reduce the number of wafers used in the calibration of the sensors while providing higher accuracy over a larger thickness range. High accuracy allows the omission of optical sensors, and use of eddy current sensors for endpoint detection, transition call detection, and closed loop control in which a process parameter is changed based on the measured magnetic flux density change in one or more processing zones.10-22-2009
20090068762Methods of Processing a Substrate and Forming a Micromagnetic Device - A method of processing a substrate with a conductive film formed thereover and method of forming a micromagnetic device. In one embodiment, the method of processing the substrate includes reducing a temperature of the substrate to a stress-compensating temperature, and maintaining the temperature of the substrate at the stress-compensating temperature for a period of time. The method also includes increasing the temperature of the substrate above the stress-compensating temperature.03-12-2009
20110201133Method for forming polarization reversal - A method for forming a ferroelectric spontaneous polarization reversal, including the steps of forming a concave portion on a top face of a ferroelectric substrate or a bottom face of a ferroelectric substrate, and applying an electric field into the substrate, wherein a ferroelectric spontaneous polarization reversal is formed at least in one portion of a region of the substrate with the concave portion, and wherein the shape of the concave portion is configured such that the width of the concave portion gets narrower gradually toward the inside of the substrate. The method may further include the steps of, after the reversal, making into almost a flat-plane the top or bottom face having the concave portion, and then, forming a new concave portion in another region and applying an electric field to form another reversal in one portion of the region of the substrate having the new concave portion.08-18-2011
20090162948METHOD FOR ELIMINATING DEFECTS FROM SEMICONDUCTOR MATERIALS - Using a helium cryostat, the temperature for a substrate wafer(s) is reduced to 2.2 Kelvin over a period of twenty-four hours. Next, a soak segment will hold the temperature of the substrate wafer at 2.2 Kelvins for a period of ninety-six hours. At these low temperatures, alloys such as GaAs, InP, and GaP will form dipole molecular moments, which will re-align along lines of internal magnetic force as molecular bonds condense. Next the substrate wafer's temperature is ramped up to room temperature over a period of twenty-four hours. Next, the temperature of the substrate wafer is ramped up to assure that the temperature gradients made to occur within the wafer are kept low. Typically, a temper ramp up temperature will range between 300° F. to 1100° F. and depends upon the single crystal material used to construct the substrate wafer. Next, the substrate wafer undergoes a temper hold segment, which assures that the entire substrate wafer has had the benefit of the tempering temperature. A typical temper hold segment is around 3 hours and depends upon the material, thickness, and diameter size of the substrate wafer.06-25-2009
20110171755MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE HAVING MEMORY ELEMENT WITH PROTECTIVE FILM - To provide a manufacturing method of a semiconductor device capable of forming, as a protective film of an MTJ element, a silicon nitride film having good insulation properties without deteriorating the properties of the MTJ element. The method of the invention includes steps of forming a silicon nitride film over the entire surface including an MTJ element portion (MTJ element and an upper electrode) while using a parallel plate plasma CVD apparatus as a film forming apparatus and a film forming gas not containing NH07-14-2011
20090275148MITIGATION OF EDGE DEGRADATION IN FERROELECTRIC MEMORY DEVICES THROUGH PLASMA ETCH CLEAN - A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.11-05-2009
20090280578FERROELECTRIC MEMORY DEVICE AND FABRICATION PROCESS THEREOF, FABRICATION PROCESS OF A SEMICONDUCTOR DEVICE - A ferroelectric memory device includes a field effect transistor formed on a semiconductor substrate, an interlayer insulation film formed on the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug, wherein the ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below, the lower electrode being connected electrically to the conductive plug, a layer containing oxygen being interposed between the conductive plug and the lower electrode, a layer containing nitrogen being interposed between the layer containing oxygen and the lower electrode, a self-aligned layer being interposed between the layer containing nitrogen and the lower electrode.11-12-2009
20080274567METHOD OF FORMING INTEGRATED CIRCUIT HAVING A MAGNETIC TUNNEL JUNCTION DEVICE - A method for manufacturing an integrated circuit having a magnetic tunnel junction device is disclosed. The method includes depositing a bottom pinning structure above the bottom conductive structure. A first ferromagnetic structure is deposited above the bottom pinning structure in a chamber. A tunnel barrier structure is deposited above the first ferromagnetic layer structure in the chamber, and a second ferromagnetic structure is deposited above the tunnel barrier structure of the magnetic tunnel junction device in another chamber.11-06-2008
20090104718Method of magnetic tunneling layer processes for spin-transfer torque MRAM - A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps and two etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers by a third etch process. Optionally, the third etch may stop on the tunnel barrier or in the free layer. A second embodiment involves forming a first parallel line pattern on a hard mask layer and transferring the line pattern through the MTJ stack with a first etch step. A planar insulation layer is formed adjacent to the sidewalls in the line pattern and then a second parallel line pattern is formed which is transferred by a second etch through the MTJ stack to form a post pattern. Etch end point may be controlled independently for hard-axis and easy-axis dimensions.04-23-2009
20090275146METHOD AND APPARATUS FOR MANUFACTURING DEVICE - A method for manufacturing a device, includes: (A) forming a first electrode layer on a substrate; (B) forming a ferroelectric layer on the first electrode layer; (C) forming a second electrode layer on the ferroelectric layer; (D) forming a mask having a predetermined pattern on the second electrode layer; (E) forming a memory element by selectively removing the first electrode layer, the ferroelectric layer, and the second electrode layer using the mask; and (F) removing the mask, where at least, the processes (D) and (E), or the processes (E) and (F) are continuously performed under a reduced pressure.11-05-2009
20090280577Manufacturing method of a semiconductor device - There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.11-12-2009
20100136712COMPOUND AND METHOD FOR PRODUCING THE SAME - The invention provides a Ti doped lead barium zirconate dielectric material which could be applied to high frequency devices. The material comprises a compound with the chemical formula (Pb06-03-2010
20090130779Method of Forming a Magnetic Tunnel Junction Structure - In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction (MTJ) structure including a conductive layer on a substrate. The method also includes depositing a sacrificial layer on the conductive layer before depositing a patterning film layer.05-21-2009
20080286883Dry etching method and production method of magnetic memory device - Provision of a process capable of preferably etching particularly PtMn used for a pin layer of an MRAM is an object: a dry etching method for performing dry etching on a layer including platinum and/or manganese by using pulse plasma and a production method of an MRAM, wherein the dry etching method is applied to processing of the pin layer. The MRAM is configured to have a memory portion comprising a magnetic memory element composed of tunnel magnetoresistive effect element formed by stacking a magnetic fixed layer having a fixed magnetization direction, a tunnel barrier layer and a magnetic layer capable of changing the magnetization direction.11-20-2008
20080293165METHOD FOR MANUFACTURING NON-VOLATILE MAGNETIC MEMORY - In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic portions of the memory cell by forming an intermediate interlayer dielectric (ILD) layer, forming intermediate metal pillars embedded in the intermediate ILD layer, depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars, performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured, and performing back end on-line (BEOL) stage to make metal and contacts of the memory cell being manufactured.11-27-2008
20100144064SEMICONDUCTOR DEVICE HAVING A FERROELECTRIC CAPACITOR - An ultra-thin semiconductor chip of an FeRAM, which is miniaturized and highly integrated with characteristic degradation of a ferroelectric capacitor suppressed though a thin package structure is applied to the FeRAM is realized. The semiconductor chip is molded up by using a sealing resin with a filler content set at a value in a range of 90 weight % to 93 weight % to produce a package structure.06-10-2010
20100144062FABRICATING METHOD OF NONVOLATILE SEMICONDUCTOR STORAGE APPARATUS - A first electrode film, a ferroelectric film, and a second electrode film are accumulated above a semiconductor in this order, a hard mask is accumulated above the second electrode, scrub cleaning is performed on the surface of the hard mask with an surfactant, the hard mask on which the scrub cleaning is performed has been patterned according to a planar shape of a ferroelectric capacitor, and etching is performed by using as a hard mask the hard mask that has been patterned.06-10-2010
20090053833Method of Manufacturing Magnetic Multi-layered Film - A method of manufacturing a magnetic multi-layered film including: a first magnetic layer forming step of forming a first magnetic layer on a substrate; a non-magnetic layer forming step of forming a non-magnetic layer on the first magnetic layer; and a second magnetic layer forming step of forming a second magnetic layer on the non-magnetic layer, the method further including, before the non-magnetic layer forming step, a plasma treatment step of introducing the substrate into a plasma treatment apparatus and treating the substrate with inductive coupling-type plasma, with the substrate being electrically insulated from the plasma treatment apparatus.02-26-2009
20110207240Information storage devices using movement of magnetic domain walls and methods of manufacturing the same - An information storage device using movement of magnetic domain walls includes a writing magnetic layer having a magnetic domain wall. A stack structure is formed on the writing magnetic layer. The stack structure includes a connecting magnetic layer and an information storing magnetic layer stacked sequentially. The information storage device also includes a reader for reading information stored in the information storing magnetic layer.08-25-2011
20110269251Spin Transfer Torque Memory Device Having Common Source Line and Method for Manufacturing the Same - A spin transfer torque memory device and a method for manufacturing the same. The spin transfer torque memory device comprises a MRAM cell using a MTJ and a vertical transistor. A common source line is formed in the bottom of the vertical transistor, thereby obtaining the high-integrated and simplified memory device.11-03-2011
20090298204SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to the present invention, a method of fabricating a semiconductor device is provided including forming a first interlayer insulating film 12-03-2009
20090298202Techniques for Coupling in Semiconductor Devices - Techniques for exchange coupling of magnetic layers in semiconductor devices are provided. In one aspect, a semiconductor device is provided. The device comprises at least two magnetic layers, and a spacer layer formed between the magnetic layers, the spacer layer being configured to provide ferromagnetic exchange coupling between the layers, the magnetic layers experiencing anti-ferromagnetic dipole coupling, such that a net coupling of the magnetic layers is anti-ferromagnetic in a zero applied magnetic field. The semiconductor device may comprise magnetic random access memory (MRAM). In another aspect, a method for coupling magnetic layers in a semiconductor device comprising at least two magnetic layers and a spacer layer therebetween, the method comprises the following step. Ferromagnetic exchange coupling is provided of the magnetic layers, the magnetic layers experiencing anti-ferromagnetic dipole coupling, such that a net coupling of the magnetic layers is anti-ferromagnetic in a zero applied magnetic field.12-03-2009
20090298200Spin Transfer MRAM Device with Separated CPP Assisted Writing - A spin-transfer MRAM is described that has two sub-cells each having a conductive spacer between an upper CPP cell and a lower MTJ cell. The two conductive spacers in each bit cell are linked by a transistor which is controlled by a write word line. The two CPP cells in each bit cell have different resistance states and the MTJ cell and CPP cell in each sub-cell have different resistance states. The MTJ free layer rotates in response to switching in the CPP free layer because of a large demagnetization field exerted by the CPP free layer. An improved circuit design is disclosed that enables a faster and more reliable read process since the reference is a second MTJ within the same bit cell. When R12-03-2009
20090137065METHOD FOR MANUFACTURING MEMORY DEVICE - A method for manufacturing a memory device including a ferroelectric memory array region and a logic circuit region is provided. The method includes the steps of: forming, above a base substrate, a plurality of ferroelectric capacitors in the ferroelectric memory array region; forming a wiring layer above the base substrate in the logic circuit region; forming an interlayer dielectric layer that covers the ferroelectric capacitors and the wiring layer; etching the interlayer dielectric layer formed at least in the ferroelectric memory array region to form a concave section; polishing the interlayer dielectric layer by a CMP (chemical mechanical polishing) method; etching the interlayer dielectric layer above the ferroelectric capacitors and the wiring layer to form contact holes; and forming contact sections in the contact holes.05-28-2009
20090137066Sensor for a magnetic memory device and method of manufacturing the same - The invention encompasses fabrication methods including the steps of preparing a silicon substrate, forming an amorphous III-V material layer on the silicon substrate, heating the amorphous III-V material layer, and epitaxially growing III-V material on the amorphous III-V material layer.05-28-2009
20090142857Package design of small diameter sensor - A small sensor assembly is produced by encapsulating an inner package within an outer package. The inner assembly can have electrical components and sensors attached to a lead frame. The electrical components can be protected within inner packages that have alignment indentations. The alignment indentations are positioned over the outside edges of the lead frame and, preferably, no electrical components directly underlie the alignment indentations. The inner assembly is held in alignment by movable pins within a mold into which plastic is flowed. The mold is configured to cause some of the plastic to set earlier than the rest of the plastic and to hold the inner assembly in alignment within the mold. The movable pins can be retracted once enough plastic has set to hold the inner assembly. Unset plastic can then flow into the alignment indentations. A sealed sensor assembly is formed once all the plastic has set.06-04-2009
20090325319Novel capping layer for a magnetic tunnel junction device to enhance dR/R and a method of making the same - An MTJ in an MRAM array or TMR read head is disclosed in which a low magnetization capping layer is a composite having a NiFeHf inner layer formed on a NiFe or CoFeB/NiFe free layer, a Ta middle layer, and a Ru outer layer on the Ta layer. For example, a low magnetization NiFeHf layer is achieved by co-sputtering NiFe and Hf targets with a forward power of 400 W and 200 W, respectively. A higher Hf content increases the oxygen gettering power of the NiFeHf layer and the thickness is modified to change dR/R, RA, and magnetostriction values. A so-called dead layer between the free layer and capping layer is restored by incorporating a NiFeHf layer on the free layer to improve lattice matching. The Fe content in the NiFe target used to make the NiFeHf layer is preferably the same as in the NiFe free layer.12-31-2009
20110223692MICROWAVE INTEGRATED CIRCUIT PACKAGE AND METHOD FOR FORMING SUCH PACKAGE - A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and placement of material on the dielectric layer to provide a predetermined magnetic or electric effect for the device, such effects being provided on the device from such patterned and placed material solely by electrical or magnetic waves coupled between such material and the device; and forming the material in the determined patterns and placement to provide the predetermined effects.09-15-2011
20090298203MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - An aluminum oxide film covering a ferroelectric capacitor is formed. Next, an opening (12-03-2009
20100248395SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A ferroelectric capacitor provided with a ferroelectric film (09-30-2010
20090068764Semiconductor device and method of manufacturing the same - According to the present invention, contact plugs are formed by a CVD method without deteriorating the properties of the ferroelectric capacitor in a semiconductor device having a fine ferroelectric capacitor. Adhesive film is formed in a contact hole, which exposes an upper electrode of the ferroelectric capacitor after conducting heat treatment in an oxidizing atmosphere, and a W layer is deposited by the CVD method using such TiN adhesive film as a hydrogen barrier and the contact hole is filled.03-12-2009
20090068763METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A method for manufacturing a semiconductor device includes the steps of: forming a ferroelectric capacitor having a first electrode, a ferroelectric film and a second electrode successively laminated on a base substrate; forming a first interlayer dielectric film that covers the ferroelectric capacitor and the base substrate; forming a material film for a second interlayer dielectric film covering the first interlayer dielectric film; exposing the first interlayer dielectric film located on the ferroelectric capacitor by polishing an upper surface side of the material film for the second interlayer dielectric film by a CMP method; forming a contact hole that penetrates the first interlayer dielectric film and exposes the second electrode, after the step of exposing the first interlayer dielectric film; and forming in the contact hole a plug conductive section that conductively connects to the second electrode, wherein the first interlayer dielectric film has a lower polishing rate in the CMP method compared to the second interlayer dielectric film.03-12-2009
20090209051NONVOLATILE FERROELECTRIC PERPENDICULAR ELECTRODE CELL, FeRAM HAVING THE CELL AND METHOD FOR MANUFACTURING THE CELL - A nonvolatile ferroelectric perpendicular electrode cell comprises a ferroelectric capacitor and a serial PN diode switch. The ferroelectric capacitor includes a word line perpendicular electrode as a first electrode and a storage perpendicular electrode as a second electrode apart at a predetermined interval from the word line perpendicular electrode to have a column type, where a ferroelectric material is filled in a space where the first electrode are separated from the second electrode. The serial PN diode switch, which is connected between a bit line and the ferroelectric capacitor, selectively switches a current direction between the bit line and the ferroelectric capacitor depending on voltage change between the bit line and the ferroelectric capacitor.08-20-2009
20090117671METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING FERREOELECTRIC CAPACITOR - A method for manufacturing a semiconductor device includes the step of conducting an acceptance/rejection judgment about the semiconductor device. The acceptance/rejection judgment is conducted by using a hysteresis loop that indicates the relationship between the applied voltage and the polarization quantity of the ferroelectric capacitor.05-07-2009
20090004759Cobalt-doped indium-tin oxide films and methods - Methods of forming cobalt-doped indium-tin oxide structures are shown. Properties of structures include transparency, conductivity, and ferromagnetism. Monolayers that contain indium, monolayers that contain tin, and monolayers that contain cobalt are deposited onto a substrate and subsequently processed to form cobalt-doped indium-tin oxide. Devices that include oxide structures formed with these methods should have better step coverage over substrate topography and more robust film mechanical properties.01-01-2009
20090209050In-Situ Formed Capping Layer in MTJ Devices - A method of forming an integrated circuit includes forming magnetic tunnel junction (MTJ) layers; etching the MTJ layers to form a MTJ cell; and forming a dielectric capping layer on sidewalls of the MTJ cell, wherein the step of forming the dielectric capping layer is in-situ performed with the step of etching the MTJ layers.08-20-2009
20080261333Methods of forming a material film, methods of forming a capacitor, and methods of forming a semiconductor memory device using the same - A method of forming a material (e.g., ferroelectric) film, a method of manufacturing a capacitor, and a method of forming a semiconductor memory device using the method of forming the (e.g., ferroelectric) film are provided. Pursuant to an example embodiment of the present invention, a method of forming a ferroelectric film includes preparing a substrate, depositing an amorphous ferroelectric film on the substrate, and crystallizing the amorphous ferroelectric film by irradiating it with a laser beam. According to still another example embodiment of the present invention, a method of forming a ferroelectric film may reduce the thermal damage to other elements because the ferroelectric film may be formed at a temperature lower than about 500° C. to about 550° C.10-23-2008
20080261332METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides a method for manufacturing a semiconductor device, including the steps of: forming a ferroelectric film on a first conductive film by a sol-gel method; forming a first conductive metal oxide film on the ferroelectric film; carrying out a first annealing on the first conductive metal oxide film; forming a second conductive metal oxide film on the first conductive metal oxide film, so that the first and second conductive films serve as a second conductive film; and forming a capacitor by patterning the first conductive film, the ferroelectric film and the second conductive film. In the step of forming the first conductive metal oxide film, ferroelectric characteristics are adjusted with a flow rate ratio of oxygen by utilizing the fact that the ferroelectric characteristics of the ferroelectric film improve as the flow rate ratio of oxygen in a sputtering gas increases.10-23-2008
20080261331MRAM AND METHOD OF MANUFACTURING THE SAME - A magnetic memory device comprising, a magneto-resistance effect element that is provided at an intersection between a first write line and a second write line. And the magneto-resistance effect element having, an easy axis that extends in a direction of extension of the first write line, and a first conductive layer for electrical connection to the magneto-resistance effect element, the first conductive layer having sides which are in flush with sides of the magneto-resistance effect element.10-23-2008
20090258443Nonvolatile memory devices and methods of fabricating the same - Nonvolatile memory devices and methods of fabricating the same are provided. In some embodiments, a nonvolatile memory device includes a lower conductive member formed on an upper part of or inside a substrate, a ferroelectric organic layer formed on the lower conductive member, a protective layer formed on the ferroelectric organic layer, and an upper conductive member formed on the protective layer to cross the lower conductive member.10-15-2009
20100151595MAGNETIC RAM - A memory element for a magnetic RAM, having a first magnetic portion in a first recess of a first insulating layer; and a non-magnetic portion and a second magnetic portion in a second recess of a second insulating layer covering the first insulating layer, the second recess exposing the first magnetic portion and a portion of the first insulating layer around the first magnetic portion, the non-magnetic portion being interposed between the first and second magnetic portions.06-17-2010
20100178714Method of forming magnetic memory device - There are provided a magnetic memory device and a method of forming the magnetic memory device. The method of forming the magnetic memory device includes sequentially forming a first magnetic conductor, a tunnel barrier layer, and a second magnetic conductor on a substrate, forming a mask pattern on the second magnetic conductor, performing a primary etching of the second magnetic conductor by using the mask pattern as an etching mask, forming at least one spacer on sidewalls of the second magnetic conductor formed by the primary etching, and performing a secondary etching of the first magnetic conductor by using the mask pattern and the at least one spacers as an etching mask.07-15-2010
20090075399METHOD FOR MANUFACTURING FERROELECTRIC MEMORY DEVICE - A method for manufacturing a ferroelectric memory device includes the steps of: forming a ferroelectric capacitor on a substrate; forming a hydrogen barrier film that covers the ferroelectric capacitor; forming a dielectric film that covers the hydrogen barrier film; and forming a through hole that penetrates the dielectric film and the hydrogen barrier film by etching that uses a mixed gas containing perfluorocarbon gas and oxygen gas, wherein the flow quantity of the perfluorocarbon gas is 0.77 times or more but 3.8 times or less the flow quantity of the oxygen gas.03-19-2009
20130122609Zr-SUBSTITUTED BaTiO3 FILMS - The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition (ALD), to form a zirconium substituted layer of barium titanium oxide, produces a reliable ferroelectric structure for use in a variety of electronic devices such as a dielectric in nonvolatile random access memories (NVRAM), tunable dielectrics for multi layer ceramic capacitors (MLCC), infrared sensors and electro-optic modulators. In various embodiments, structures can be formed by depositing alternating layers of barium titanate and barium zirconate by ALD on a substrate surface using precursor chemicals, and repeating to form a sequentially deposited interleaved structure of desired thickness and composition. The properties of the dielectric may be tuned by adjusting the percentage of zirconium to titanium to optimize properties such as a dielectric constant, Curie point, film polarization, ferroelectric property and a desired relaxor response.05-16-2013
20100184239MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING MAGNETIC MEMORY - In the case where a laminated structure formed by laminating tunneling magnetoresistive films are processed by ion milling or the like, scattered substances of a material constituting the tunneling magnetoresistive film are deposited onto side walls of the laminated structure, or contaminate the inside of a device for processing. Accordingly, it has been difficult to manufacture a magnetic memory or a semiconductor device on which the magnetic memory is mounted, with stable characteristics.07-22-2010
20090269860MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a manufacturing method of a semiconductor device capable of forming, as a protective film of an MTJ element, a silicon nitride film having good insulation properties without deteriorating the properties of the MTJ element. The method of the invention includes steps of forming a silicon nitride film over the entire surface including an MTJ element portion (MTJ element and an upper electrode) while using a parallel plate plasma CVD apparatus as a film forming apparatus and a film forming gas not containing NH10-29-2009
20100261296SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is disclosed. The semiconductor device includes a ferroelectric capacitor formed on a substrate and a wiring structure formed on the ferroelectric capacitor. The wiring structure includes a dielectric inter layer and a Cu wiring section formed in the dielectric inter layer. In addition, an etching stopper layer including a hydrogen diffusion preventing layer is formed so as to face the dielectric inter layer.10-14-2010
20100261294MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - After a first via hole leading to a ferroelectric capacitor structure are formed in an interlayer insulating film by dry etching, a second via hole to expose part of the ferroelectric capacitor structure is formed in a hydrogen diffusion preventing film so as to be aligned with the first via hole by wet etching, and a via hole constructed by the first via hole and the second via hole communicating with each other is formed.10-14-2010
20100261295High performance MTJ element for STT-RAM and method for making the same - A method of forming a STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The device includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and, in one embodiment, a free layer that comprises an amorphous layer of Co10-14-2010
20100184240SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a method of manufacturing a semiconductor device, which comprises the steps of: forming a hydrogen diffusion preventing insulating film covering capacitors; forming a capacitor protecting insulating film on the hydrogen diffusion preventing insulating film; and forming a first insulating film on the capacitor protecting insulating film by a plasma CVD method where, while a high-frequency bias electric power is applied toward the semiconductor substrate, a plasma-generating high frequency electric power is applied to first deposition gas containing oxygen and silicon compound gas. In the method, a condition by which moisture content in the capacitor protecting insulating film becomes less than that in the first insulating film is adopted as a film deposition condition for the capacitor protecting insulating film.07-22-2010
20110059557METHOD OF MANUFACTURING NONVOLATILE MEMORY DEVICE - A method of manufacturing a nonvolatile memory device having a laminated structure in which a first magnetic material layer, a tunnel insulator film, and a second magnetic material layer are sequentially laminated, in which information is stored when an electric resistance value changes depending on a magnetization reversal state is disclosed. The method includes the steps of: sequentially forming the first magnetic material layer, the tunnel insulator film, and the second magnetic material layer; forming a mask layer on the second magnetic material layer; oxidizing a part uncovered by the mask layer of the second magnetic material layer; and reducing the oxidized part of the second magnetic material layer.03-10-2011
20100240151Method of double patterning and etching magnetic tunnel junction structures for spin-transfer torque MRAM devices - A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps each followed by two plasma etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers. The hard mask has an upper Ta layer with a thickness of 300 to 400 Angstroms and a lower NiCr layer less than 50 Angstroms thick. The upper Ta layer is etched with a fluorocarbon etch while lower NiCr layer and underlying MTJ layers are etched with a CH09-23-2010
20100240152Current-Confined Effect of Magnetic Nano-Current-Channel (NCC) for Magnetic Random Access Memory (MRAM) - One embodiment of the present invention includes a memory element having a composite free layer including a first free sub-layer formed on top of the bottom electrode, a nano-current-channel (NCC) layer formed on top of the first free sub-layer, and a second free sub-layer formed on top of the NCC layer, wherein when switching current is applied to the memory element, in a direction that is substantially perpendicular to the layers of the memory element, local magnetic moments of the NCC layer switch the state of the memory element.09-23-2010
20130217151METHOD FOR PRODUCING SPIN INJECTION ELECTRODE - A production method of the present disclosure includes: a first step of preparing a multi-layer graphene, and an iron oxide that is a ferromagnetic material contacting the graphene and containing Fe08-22-2013
20100144063Seminconductor device - The present invention provides a signal transmitting/receiving method comprising: disposing a ferromagnetic film between a semiconductor device having an inductor and an external device which includes an external inductor provided in a position corresponding to the inductor of the semiconductor device; disposing the inductor and the external inductor so as to face each other via the ferromagnetic film therebetween; and in a state in which the inductor and the external inductor face each other, transmitting and receiving the signals between the inductor and the external inductor by electromagnetic induction.06-10-2010
20100093110Ferroelectric passive memory cell, device and method of manufacture thereof - A first passive ferroelectric memory element comprising a first electrode system and a second electrode system, wherein said first electrode system is at least partly insulated from said second electrode system by an element system comprising at least one ferroelectric element, wherein said first electrode system is a conductive surface, or a conductive layer; wherein said second electrode system is an electrode pattern or a plurality of isolated conductive areas in contact with, for read-out or data-input purposes only, a plurality of conducting pins isolated from one another.04-15-2010
20090075401METHOD FOR MANUFACTURING FERROELECTRIC CAPACITOR AND METHOD FOR MANUFACTURING FERROELECTRIC MEMORY DEVICE - A method for manufacturing a ferroelectric capacitor having a ferroelectric film interposed between a first electrode and a second electrode is provided. The method includes the steps of: forming an electrode film above a substrate; thermally oxidizing a surface layer of the electrode film to form an oxidized electrode layer in an atmosphere of atmospheric-pressure with an oxygen partial pressure being 2% or grater; forming a ferroelectric film on the electrode layer by a MOCVD method thereby forming a first electrode composed of the electrode film including the oxidized electrode layer that serves as a base for the ferroelectric film; and forming a second electrode on the ferroelectric film.03-19-2009
20090075400METHOD FOR MANUFACTURING FERROELECTRIC MEMORY - A method for manufacturing a ferroelectric memory includes the steps of: forming an iridium film above a substrate; forming an iridium oxide layer on the iridium film; changing the iridium oxide layer into an amorphous iridium layer; oxidizing the amorphous iridium layer to form an iridium oxide portion; forming a ferroelectric film on the iridium oxide portion by a MOCVD method; and forming an electrode on the ferroelectric film.03-19-2009
20100120176METHOD FOR MANUFACTURING MAGNETIC MEMORY CHIP DEVICE - A method for manufacturing a magnetic memory chip device is provided with a step of writing information on a plurality of magnetic memory chips formed on a silicon wafer; a step of adhering a high permeability plate, which is composed of a material having permeability higher than that of silicon and has a thickness of 50 μm or more, on the rear surface of a silicon wafer after writing the information; and a step of dicing the silicon wafer into magnetic memory chips after adhering the high permeability plate.05-13-2010
20100197044METHOD OF MANUFACTURING A MAGNETIC RANDOM ACCESS MEMORY, METHOD OF MANUFACTURING AN EMBEDDED MEMORY, AND TEMPLATE - A magnetic material of a magnetoresistive element is formed on a lower electrode. An upper electrode is formed on the magnetic material. A resist for nano-imprint lithography is formed on the upper electrode. A first pattern or a second pattern is formed in the resist by setting a first template or a second template into contact with the resist and curing the resist. The first template has the first pattern that corresponds to the magnetoresistive element and the lower electrode. The second template has the second pattern that corresponds to the magnetoresistive element and the upper electrode. The magnetic material and the lower electrode are patterned at the same time by using the resist having the first pattern, or the magnetic material and the upper electrode are patterned at the same time by using the resist having the second pattern.08-05-2010
20100197043STRUCTURE AND METHOD FOR FABRICATING CLADDED CONDUCTIVE LINES IN MAGNETIC MEMORIES - A method of forming a magnetoelectronic device includes forming a dielectric material (08-05-2010
20100197045Power Semiconductor Devices Having Integrated Inductor - An electronic device (08-05-2010
20100197046SEMICONDUCTOR DEVICE - A silicide film is formed between a ferroelectric capacitor structure, which is formed by sandwiching a ferroelectric film between a lower electrode and an upper electrode, and a conductive plug (the conductive material constituting the plug is tungsten (W) for example). Here, an example is shown in which a base film of the conductive plug is the silicide film.08-05-2010
20100221848Embedded Magnetic Random Access Memory (MRAM) - A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.09-02-2010
20100267171MAGNETIC STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - In an MRAM, a curved region (10-21-2010
20090246890METHOD FOR MANUFACTURING A TUNNEL JUNCTION MAGNETORESISTIVE SENSOR WITH IMPROVED PERFORMANCE AND HAVING A CoFeB FREE LAYER - A method for manufacturing a magnetoresistive sensor that provides increased magnetoresistive performance. The method includes forming a series of sensor layers with at least one layer containing CoFeB, and having a first capping layer thereover. A high temperature annealing is performed to optimize the grains structure of the sensor layers. The first capping layer is then removed, such as by reactive ion etching (RIE). An antiferromagnetic layer is then deposited followed by a second capping layer. A second annealing is performed to set the magnetization of the pinned layer, the second annealing being performed at a lower temperature than the first annealing.10-01-2009
20080299679Low resistance tunneling magnetoresistive sensor with composite inner pinned layer - A high performance TMR sensor is fabricated by employing a composite inner pinned (AP12-04-2008
20090148962SUBSTRATE STRUCTURE AND METHOD FOR WIDEBAND POWER DECOUPLING - A substrate structure and method of wideband power decoupling comprising one or more embedded capacitors each comprising a ferroelectric material.06-11-2009
20130130406MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION - A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a free layer and a spin torque enhancing layer. The spin torque enhancing layer includes a nano-oxide layer.05-23-2013
20130130407SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a capacitor, the capacitor includes a lower electrode, which includes platinum, provided above a semiconductor substrate; a first ferroelectric film, which includes lead zirconate titanate added with La, provided on the lower electrode; a second ferroelectric film, which includes lead zirconate titanate added with La, Ca, and Sr, provided directly on the first ferroelectric film, the second ferroelectric film having a thickness smaller than that of the first ferroelectric film and includes amounts of Ca and Sr greater than amounts of Ca and Sr that may be present in the first ferroelectric film; and an upper electrode, which includes a conductive oxide, provided on the second ferroelectric film.05-23-2013
20110129946High density spin-transfer torque MRAM process - A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.06-02-2011
20130149794METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: forming a conductive film over a semiconductor substrate; forming a first ferroelectric film over the conductive film; forming an amorphous second ferroelectric film over the first ferroelectric film; forming a transition metal oxide material film containing ruthenium over the second ferroelectric film; forming a first conductive metal oxide film over the transition metal oxide material film without exposing the transition metal oxide material film to the air; annealing and crystallizing the second ferroelectric film; and patterning the first conductive metal oxide film, the first ferroelectric film, the second ferroelectric film, and the conductive film to form a ferroelectric capacitor.06-13-2013
20130149795ETCHING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In an etching method of an embodiment, a film to be etched, which includes a first metallic element, is formed on a semiconductor substrate. A carbide layer, which includes a second metallic element, is formed on the film to be etched. The carbide layer is etched. The film to be etched is etched by using the carbide layer as a mask.06-13-2013
20100178715MRAM with storage layer and super-paramagnetic sensing layer - An MRAM is disclosed that has a MTJ comprised of a ferromagnetic layer with a magnetization direction along a first axis, a super-paramagnetic (SP) free layer, and an insulating layer formed therebetween. The SP free layer has a remnant magnetization that is substantially zero in the absence of an external field, and in which magnetization is roughly proportional to an external field until reaching a saturation value. In one embodiment, a separate storage layer is formed above, below, or adjacent to the MTJ and has uniaxial anisotropy with a magnetization direction along its easy axis which parallels the first axis. In a second embodiment, the storage layer is formed on a non-magnetic conducting spacer layer within the MTJ and is patterned simultaneously with the MTJ. The SP free layer may be multiple layers or laminated layers of CoFeB. The storage layer may have a SyAP configuration and a laminated structure.07-15-2010
20110111532METHODS OF FORMING PATTERN STRUCTURES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME - Methods of forming pattern structures and methods of manufacturing memory devices using the same are provided, the methods of forming pattern structures include forming an etching object layer on a substrate and performing a plasma reactive etching process on the etching object layer using an etching gas including at least ammonia (NH05-12-2011
20110086440METHOD FOR MANUFACTURING AN EXTRAORDINARY MAGNETORESISTIVE (EMR) DEVICE WITH NOVEL LEAD STRUCTURE - A method for manufacturing an extraordinary magnetoresistive sensor (EMR sensor) having reduced size and increased resolution is described. The sensor includes a plurality of electrically conductive leads contacting a magnetically active layer and also includes an electrically conductive shunt structure. The electrically conductive leads of the sensor and the shunt structure can be formed in a common photolithographic masking and etching process so that they are self aligned with one another. This avoids the need to align multiple photolithographic processing steps, thereby allowing greatly increased resolution and reduced lead spacing. The EMR sensor can be formed with a magnetically active layer that can be close to or at the air bearing surface (ABS) for improved magnetic spacing with an adjacent magnetic medium of a data recording system.04-14-2011
20110244599PROCESS INTEGRATION OF A SINGLE CHIP THREE AXIS MAGNETIC FIELD SENSOR - A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.10-06-2011
20090068761Method of Forming a Micromagnetic Device - A method of forming a micromagnetic device on a substrate including forming a first insulating layer above the substrate, a first seed layer above the first insulating layer, a first conductive winding layer above the first seed layer, and a second insulating layer above the first conductive winding layer. The method also includes forming a first magnetic core layer above the second insulating layer, a third insulating layer above the first magnetic core layer, and a second magnetic core layer above the third insulating layer. The method still further includes forming a fourth insulating layer above the second magnetic core layer, a second seed layer above the fourth insulating layer, and a second conductive winding layer above the second seed layer and in vias to the first conductive winding layer. The first and second conductive winding layers form a winding for the micromagnetic device.03-12-2009
20100136713Hafnium doped cap and free layer for mram device - A high performance MTJ, and a process for manufacturing it, are described. A capping layer of NiFeHf is used to getter oxygen out of the free layer, thereby increasing the sharpness of the free layer-tunneling layer interface. The free layer comprises two NiFe layers whose magnetostriction constants are of opposite sign, thereby largely canceling one another.06-03-2010
20110212545Ferroelectric passive memory cell, device and method of manufacture thereof - A first passive ferroelectric memory element comprising a first electrode system and a second electrode system, wherein said first electrode system is at least partly insulated from said second electrode system by an element system comprising at least one ferroelectric element, wherein said first electrode system is a conductive surface, or a conductive layer; wherein said second electrode system is an electrode pattern or a plurality of isolated conductive areas in contact with, for read-out or data-input purposes only, a plurality of conducting pins isolated from one another.09-01-2011
20110143460METHOD OF MANUFACTURING MAGNETORESISTANCE ELEMENT AND STORAGE MEDIUM USED IN THE MANUFACTURING METHOD - An embodiment of the invention provides a method of manufacturing a magnetoresistance element with an MR ratio higher than that of the related art.06-16-2011
20110086439METHOD AND APPARATUS FOR MANUFACTURING MAGNETORESISTIVE ELEMENT - A method of manufacturing a magnetoresistive element includes a tunnel barrier forming step. The tunnel barrier forming step comprises a metal layer forming step of forming a metal layer to have a first thickness, a plasma processing step of performing a plasma treatment which exposes the metal layer to a plasma of an inert gas to etch the metal layer to have a second thickness smaller than the first thickness, and an oxidation step of oxidizing the metal layer having undergone the plasma treatment to form a metal oxide which forms a tunnel barrier.04-14-2011
20100015730Magnetic self-assembly for integrated circuit packages - An integrated circuit package may include a substrate and an integrated circuit. The substrate may include at least one region, and a first magnetic material associated with the at least one region. The integrated circuit may have a second magnetic material associated therewith. The second magnetic material may be attracted to the first magnetic material to coupled the integrated circuit to the at least one region of the substrate. The IC package may be utilized in an RFID tag of an RFID system. An associated method for assembling an integrated circuit to a substrate is also provided.01-21-2010
20120244642SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method for manufacturing a semiconductor device including a semiconductor substrate having transistors formed thereon, a first interlayer insulating film formed above the semiconductor substrate and the transistors, a ferroelectric capacitor formed above the first interlayer insulating film, a second interlayer insulating film formed above the first interlayer insulating film and the ferroelectric capacitor, a first metal wiring formed on the second interlayer insulating film, and a protection film formed on an upper surface of the wiring but not on a side surface of the wiring.09-27-2012
20120244641METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The device includes a magnetoresistance effect element using magnetic material containing at least one of cobalt, iron, and nickel. Forming the element includes forming a stacked body above a semiconductor substrate. The stacked body includes layers. The layers includes the magnetic material. Forming the element further includes processing the stacked body in a vacuum atmosphere by plasma etching using a first gas containing chlorine. Forming the element further includes subjecting the stacked body to a gas treatment using a second gas containing an amino group while holding the stacked body in the vacuum atmosphere.09-27-2012
20120244640METHOD OF MANUFACTURING MULTILAYER FILM - According to one embodiment, a method of manufacturing a multilayer film, the method includes forming a first layer, forming a second layer on the first layer, and transcribing a crystal information of one of the first and second layers to the other one of the first and second layers by executing a GCIB-irradiation to the second layer.09-27-2012
20120244639METHOD OF MANUFACTURING MAGNETIC MEMORY - According to one embodiment, a method of manufacturing a magnetic memory, the method includes forming a first magnetic layer having a variable magnetization, forming a tunnel barrier layer on the first magnetic layer, forming a second magnetic layer on the tunnel barrier layer, the second magnetic layer having an invariable magnetization, forming a hard mask layer as a mask on the second magnetic layer, patterning the second magnetic layer by using the mask of the hard mask layer, and executing a GCIB-irradiation by using the mask of the hard mask layer, after the patterning.09-27-2012
20100055804METHOD FOR PATTERNING SEMICONDUCTOR DEVICE HAVING MAGNETIC TUNNELING JUNCTION STRUCTURE - A method for patterning a semiconductor device includes forming a lower electrode conductive layer over a substrate, forming a stack structure including a lower electrode conductive layer, a first ferromagnetic layer, an insulation layer and a second ferromagnetic layer over a substrate, forming an upper electrode conductive layer used as a first hard mask over the stack structure, forming a second hard mask layer over the upper electrode conductive layer, selectively etching the second hard mask layer to form a second hard mask pattern, etching the upper electrode conductive layer using the second hard mask pattern as an etch barrier to form an upper electrode, and etching the stack structure including the lower electrode conductive layer, the first ferromagnetic layer, the insulation layer and the second ferromagnetic layer by at least using the upper electrode as an etch barrier.03-04-2010
20100068828METHOD OF FORMING A STRUCTURE HAVING A GIANT RESISTANCE ANISOTROPY OR LOW-K DIELECTRIC - A method is provided involving the growth of carbon nanotubes to provide giant resistance anisotropy or a low-k dielectric. The method comprises growing a plurality of one-dimensional nanostructures (03-18-2010
20100055805SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes forming a first film made of a first metal to an upper portion of a substrate, forming a second film made of an amorphous metal oxide or an microcrystalline metal oxide on the first film, subjecting the second film to a heat treatment, subjecting the second film after the heat treatment to a reduction treatment, forming a third film made of a ferroelectric material on the second film, and forming a fourth film made of a second metal on the third film.03-04-2010
20110081732Method of Manufacturing Magnetic Tunnel Junction Device and Apparatus for Manufacturing the Same - A method of manufacturing a magnetic tunnel junction device includes a barrier layer forming step of forming a tunnel barrier layer. The barrier layer forming step comprises a step of depositing a first metal layer, an oxygen surfactant layer forming step of forming an oxygen surfactant layer on the first metal layer, a step of deposing a second metal layer above the first oxygen surfactant layer, and an oxidation step of oxidizing the first metal layer and the second metal layer to form a metal oxide layer.04-07-2011
20110076784Fabrication of Magnetic Element Arrays - Techniques for fabricating an array of magnetic elements to form memory and other devices with a high areal density.03-31-2011
20110151587METHOD OF PRODUCING AN INTEGRATED MICROMAGNET SENSOR ASSEMBLY - A method of integrating a permanent bias magnet within a magnetoresistance sensor comprising depositing an alternating pattern of a metal material and a semiconductor material on or within a surface of an insulating substrate; depositing a mask on the surface of the insulating substrate to create an opening above the alternating pattern of metal material and semiconductor material; applying a magnetic paste within the opening above the alternating pattern of metal material and semiconductor material; curing the magnetic paste to form a hardened bias magnet; removing the mask; and magnetizing the hardened bias magnet by applying a strong magnetic field to the hardened bias magnet at a desired orientation.06-23-2011
20110033955NONVOLATILE FERROELECTRIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A nonvolatile ferroelectric memory device includes a plurality of unit cells. Each of the unit cells includes a cell capacitor and a cell transistor. The cell capacitor includes a storage node, a ferroelectric layer, and a plate line. The cell capacitors of more than one of the plurality of unit cells are provided in a trench.02-10-2011
20110045609METHOD FOR DETACHING LAYERS WITH LOW MAGNETIC PERMEABILITY - A method for detaching a first material layer from a second material layer includes following steps. Firstly, a high-magnetic-permeability material layer is formed on a first material layer. Secondly, a second material layer is formed on the high-magnetic-permeability material layer. Thirdly, the first and second material layers are cooled such that the first and second material layers shrink, wherein the first and second material layers are low-magnetic-permeability materials. Finally, the high-magnetic-permeability material layer is heated by applying a high-frequency radiofrequency electromagnetic wave thereto such that the high-magnetic-permeability material layer expands, thus detaching the first material layer from the second material layer.02-24-2011
20120034712SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method for manufacturing a semiconductor device including a ferroelectric capacitor formed over a semiconductor substrate, wherein the ferroelectric capacitor including a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film, and the upper electrode including a first conductive film formed of a first conductive noble metal oxide, and a second conductive film formed of a metal nitride compound formed on the first conductive film.02-09-2012
20100304504PROCESS AND APPARATUS FOR FABRICATING MAGNETIC DEVICE - Process and apparatus for fabricating a magnetic device is provided. Magnetic and/or nonmagnetic layers i n the device are etched by a mixed gas of a hydrogen gas and an inert gas such as N12-02-2010
20080248596Method of making a circuitized substrate having at least one capacitor therein - A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art. In still another embodiment, at least two spaced-apart conductors may be formed within a metal layer deposited on a dielectric layer, these conductors defining a channel there-between. The capacitive dielectric material may then be deposited (e.g., using lamination) within the channels.10-09-2008
20110151589PRODUCTION OF A DEVICE COMPRISING MAGNETIC STRUCTURES FORMED ON ONE AND THE SAME SUBSTRATE AND HAVING RESPECTIVE DIFFERENT MAGNETIZATION ORIENTATIONS - The invention relates to a method for producing a device comprising magnetic blocks magnetized in different directions, comprising steps of: 06-23-2011
20120171783FERROELECTRIC MEMORY AND MANUFACTURING METHOD THEREOF, AND MANUFACTURING METHOD OF FERROELECTRIC CAPACITOR - Provided is a ferroelectric memory including a silicon substrate, a transistor formed on the silicon substrate, and a ferroelectric capacitor formed above the transistor. The ferroelectric capacitor includes a lower electrode, a ferroelectric film formed on the lower electrode, an upper electrode formed on the ferroelectric film, and a metal film formed on the upper electrode.07-05-2012
20090317923SPIN-CURRENT SWITCHED MAGNETIC MEMORY ELEMENT SUITABLE FOR CIRCUIT INTEGRATION AND METHOD OF FABRICATING THE MEMORY ELEMENT - A magnetic memory element switchable by current injection includes a plurality of magnetic layers, at least one of the plurality of magnetic layers having a perpendicular magnetic anisotropy component and including a current-switchable magnetic moment, and at least one barrier layer formed adjacent to the plurality of magnetic layers (e.g., between two of the magnetic layers). The memory element has the switching threshold current and device impedance suitable for integration with complementary metal oxide semiconductor (CMOS) integrated circuits.12-24-2009
20110151588METHOD AND MAGNETIC TRANSFER STAMP FOR TRANSFERRING SEMICONDUCTOR DICE USING MAGNETIC TRANSFER PRINTING TECHNIQUES - Releasable semiconductor dice are deposited with a magnetic layer and held by magnetic forces to a magnetic or electromagnetic transfer stamp for the transfer of the dice from a host substrate directly or indirectly to a target substrate.06-23-2011
20090162947AERODYNAMIC SHAPES FOR WAFER STRUCTURES TO REDUCE DAMAGE CAUSED BY CLEANING PROCESSES - Wafer structures and associated methods of fabrication are described. The wafer structures are fabricated to have aerodynamic shapes. Even if the structures on the wafer are fragile, the aerodynamic shapes of the structures create less resistance to a fluid flow of a cleaning process, and are less likely to be damaged by the cleaning process. Also, the aerodynamic shape of the structures allows a fluid flow to be directed toward the wafer from a single angle to effectively clean the wafer.06-25-2009
20130196451MANUFACTURING METHOD OF MAGNETIC TUNNELING JUNCTION DEVICE - A method of manufacturing a magnetic tunneling junction device, includes: forming a magnetic pinned layer over a substrate; forming an insulating film over the magnetic pinned layer; forming a recess in the insulating film, the recess reaching a bottom of the insulating film; forming a tunneling insulating film over a bottom and side walls of the recess and over the insulating film; forming a magnetic free layer over the tunneling insulating film; forming an upper electrode conductive film on the magnetic free layer; and oxidizing a portion of the magnetic free layer along the side walls of the recess.08-01-2013
20110177621MAGNETIC MEMORY CELL CONSTRUCTION - A magnetic tunnel junction cell having a free layer, a ferromagnetic pinned layer, and a barrier layer therebetween. The free layer has a central ferromagnetic portion and a stabilizing portion radially proximate the central ferromagnetic portion. The construction can be used for both in-plane magnetic memory cells where the magnetization orientation of the magnetic layer is in the stack film plane and out-of-plane magnetic memory cells where the magnetization orientation of the magnetic layer is out of the stack film plane, e.g., perpendicular to the stack plane.07-21-2011
20090029485MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A capacitor in which a ferroelectric film (01-29-2009
20120276659SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An impurity-doped PZT film in an amorphous state doped with La, Ca, Sr, Si, Nb and/or the like is formed on a Pt film composing a bottom electrode film. Next, crystallization annealing for the impurity-doped PZT film is performed. Next, a PZT film is formed on the impurity-doped PZT film by an MOCVD method. Thereafter, an IrO11-01-2012
20120276658METHOD OF ETCHING A WORKPIECE - A workpiece is implanted to a first depth to form a first amorphized region. This amorphized region is then etched to the first depth. After etching, the workpiece is implanted to a second depth to form a second amorphized region below a location of the first amorphized region. The second amorphized region is then etched to the second depth. The implant and etch steps may be repeated until structure is formed to the desired depth. The workpiece may be, for example, a compound semiconductor, such as GaN, a magnetic material, silicon, or other materials.11-01-2012
20120276657METHOD OF PATTERNING OF MAGNETIC TUNNEL JUNCTIONS - Embodiments of the invention generally relate to methods for fabricating devices on semiconductor substrates. More specifically, embodiments of the invention relate to methods of patterning magnetic materials. Certain embodiments described herein use a reducing chemistry containing a hydrogen gas or hydrogen containing gas with an optional dilution gas at temperatures ranging from 20 to 300 degrees Celsius at a substrate bias less than 1,000 DC voltage to reduce the amount of sputtering and redeposition. Exemplary hydrogen containing gases which may be used with the embodiments described herein include NH11-01-2012
20110165702METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A ferroelectric capacitor is formed over a semiconductor substrate (07-07-2011
20110053293MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.03-03-2011
20100285613IN-PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE AND FABRICATION METHOD THEREOF - An in-plane switching mode liquid crystal display device includes a first substrate including a pixel electrode in a pixel region, a second substrate facing the first substrate and including a common electrode, a first alignment layer on the pixel electrode, a second alignment layer on the common electrode, a first ferroelectric liquid crystal layer on the first alignment layer and including a first spontaneous polarization, a second ferroelectric liquid crystal layer on the second alignment layer and including a second spontaneous polarization, a rotational direction of the first ferroelectric liquid crystal layer with respect to the first alignment layer being different from a rotational direction of the second ferroelectric liquid crystal layer with respect to the second alignment layer, and a twisted nematic liquid crystal layer between the first and second ferroelectric liquid crystal layers.11-11-2010
20120122246METHOD FOR MANUFACTURING MAGNETIC MEMORY CHIP DEVICE - A method for manufacturing a magnetic memory chip device comprises the steps of: writing information in each of a plurality of magnetic memory chips formed on a silicon wafer; adhering a high magnetic permeability plate on a back face of the silicon wafer after writing information, the high magnetic permeability plate having a higher magnetic permeability than silicon and having a thickness of 50 um or more; dicing the silicon wafer into respective magnetic memory chips after adhering the high magnetic permeability plate.05-17-2012
20100330708METHODS FOR MULTI-STAGE MOLDING OF INTEGRATED CIRCUIT PACKAGE - Methods for providing an integrated circuit using a multi-stage molding process to protect wirebonds. In one embodiment, a method includes attaching a die to a leadframe having a lead finger, attaching a wirebond between the die and the leadfinger, applying a first mold material over at least a portion of the wirebond and the die and the leadfinger to form an assembly, waiting for the first mold material to at least partially cure, and applying a second mold material over the assembly.12-30-2010
20100330707Robust Self-Aligned Process for Sub-65nm Current-Perpendicular Junction Pillars - A method for fabricating a device includes forming a first insulation layer to cover a removable mask and a device structure that has been defined by the mask. The device structure is below the mask. The mask is lifted off to expose a top portion of the device structure. A conductive island structure is formed over the first insulation layer and the exposed top portion of the device structure. The first insulation layer and the conductive island structure are covered with a second insulation layer. A contact is formed through the second insulation layer to the conductive island structure.12-30-2010
20110256642MANUFACTURING METHOD OF MAGNETO-RESISTANCE EFFECT ELEMENT - The present invention provides a manufacturing method of a magneto-resistance effect element, in which the step coverage of a formed film can be enlarged and also the film can be deposited in a low temperature range. In an embodiment of the present invention, an insulating protective layer is formed on a multilayered structure by a plasma CVD apparatus in which a plasma source and a film deposition chamber are separated from each other by a partition wall plate. According to the present method, it is possible to deposit the protective layer without inviting the degradation of a magnetic characteristic and also to perform low temperature film deposition even at a temperature lower than 150° C. Hence, it is possible to deposit the protective layer while leaving resist and also to reduce the number of steps in the manufacturing of the magneto-resistance effect element having a multilayered structure.10-20-2011
20110256643METHOD FOR DETACHING LAYERS WITH LOW MAGNETIC PERMEABILITY - A method for detaching a first material layer from a second material layer includes following steps: forming a high-magnetic-permeability material layer on a first material layer comprised of low-magnetic-permeability material; removing a portion of the high-magnetic-permeability material layer to expose a portion of the first material layer; epitaxially growing a second material layer comprised of low-magnetic-permeability material on the exposed portion of the first material layer and the high-magnetic-permeability material layer; cooling the first and second material layers; heating the high-magnetic-permeability material layer, thus detaching the first material layer from the second material layer.10-20-2011
20110183441METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device and a method of fabricating a semiconductor device that includes forming an interlayer insulating film on a semiconductor substrate; depositing a first soft magnetic thin film on the interlayer insulating film through sputtering using a target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N07-28-2011
20090197350MAGNETIC MEMORY DEVICE AND METHOD - An exemplary embodiment of a magnetic random access memory (MRAM) device includes a magnetic tunnel junction having a free layer, a first electrode (first magnetic field generating means) having a first portion that covers a surface of the free layer, and an electric power source connected to the first electrode via a connection that covers less than half of the first portion of the first electrode. Another exemplary embodiment of an MRAM device includes a magnetic tunnel junction, first and second electrodes (first and second magnetic field generating means) directly connected to the magnetic tunnel junction on opposite sides of the magnetic tunnel junction, and an electric power source having one pole connected to the first electrode via a first connection and having a second pole connected to the second electrode via a second connection, wherein the first and second connections are laterally offset from the connections between the first and second electrodes and the magnetic tunnel junction. Methods of operating and manufacturing these magnetic random access memories are also disclosed.08-06-2009
20120309113Quantum Tunneling Devices and Circuits with Lattice-Mismatched Semiconductor Structures - Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.12-06-2012
20120309112FERROELECTRIC MEMORY DEVICE AND FABRICATION PROCESS THEREOF, FABRICATION PROCESS OF A SEMICONDUCTOR DEVICE - A ferroelectric memory device includes a field effect transistor formed on a semiconductor substrate, an interlayer insulation film formed on the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug, wherein the ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below, the lower electrode being connected electrically to the conductive plug, a layer containing oxygen being interposed between the conductive plug and the lower electrode, a layer containing nitrogen being interposed between the layer containing oxygen and the lower electrode, a self-aligned layer being interposed between the layer containing nitrogen and the lower electrode.12-06-2012
20110189796Uniformity in the Performance of MTJ Cells - A method of forming an integrated circuit structure includes forming a bottom electrode layer over a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; patterning the MTJ layers to form a MTJ stack; forming a dielectric layer covering the MTJ stack; forming an opening in the dielectric layer to expose a portion of the MTJ stack; filling the opening with a top electrode material; and performing a planarization to the top electrode material. After the step of performing the planarization, the top electrode material and the dielectric layer are patterned, wherein a first portion of the top electrode material in the opening forms a top electrode, and a second portion of the top electrode material forms a metal strip over the dielectric layer and connected to the top electrode.08-04-2011
20100022032METHOD OF FORMING ORGANIC FERROELECTRIC FILM, METHOD OF MANUFACTURING MEMORY ELEMENT, MEMORY DEVICE, AND ELECTRONIC APPARATUS - A method of forming an organic ferroelectric film configured to include an organic ferroelectric material with a crystalline property as a principal material includes (a) forming a low crystallinity film having a crystallinity lower than a crystallinity of the organic ferroelectric film on one surface of a substrate, and (b) forming the organic ferroelectric film from the low crystallinity film. The step (a) includes applying a liquid material containing the organic ferroelectric material on the one surface of the substrate and then drying the liquid material, and the step (b) includes heating and pressurizing the low crystallinity film to enhancing the crystallinity in the low crystallinity film while fairing the low crystallinity film.01-28-2010
20100022031SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug and in the circumference thereof, a crystalline conductive film formed on the underlying conductive film, and a capacitor in which a lower electrode, a dielectric film made of a ferroelectric material, and an upper electrode are laminated in this order on the crystalline conductive film.01-28-2010
20100022030DRY ETCH STOP PROCESS FOR ELIMINATING ELECTRICAL SHORTING IN MRAM DEVICE STRUCTURES - The present invention relates generally to semiconductor fabrication and particularly to fabricating magnetic tunnel junction devices. In particular, this invention relates to a method for using the dielectric layer in tunnel junctions as an etch stop layer to eliminate electrical shorting that can result from the patterning process.01-28-2010
20110117677Spacer structure in MRAM cell and method of its fabrication - Methods are presented for fabricating an MTJ element having a uniform vertical distance between its free layer and a bit line and, in addition, having a protective spacer layer formed abutting the lateral sides of the MTJ element to eliminate leakage currents between MTJ layers and the bit line. Each method forms a dielectric spacer layer on the lateral sides of the MTJ element and, depending on the method, includes an additional layer that protects the spacer layer during etching processes used to form a Cu damascene bit line. At various stages in the process, a dielectric layer is also formed to act as a CMP stop layer so that the capping layer on the MTJ element is not thinned by the CMP process that planarizes the surrounding insulation. Subsequent to planarization, the stop layer is removed by an anisotropic etch of such precision that the MTJ element capping layer is not reduced in thickness and serves to maintain uniform vertical distance between the bit line and the MTJ free layer.05-19-2011
20090137067METHOD FOR FORMING AN INDUCTOR - A spiral inductor fabricated above a semiconductor substrate provides a large inductance while occupying only a small surface area. Including a layer of magnetic material above and below the inductor increases the inductance of the inductor. The magnetic material also acts as barrier that confines electronic noise generated in the spiral inductor to the area occupied by the spiral inductor. Inductance in a pair of stacked spiral inductors is increased by including a layer of magnetic material between the stacked spiral inductors.05-28-2009
20120301975SEMICONDUCTOR DEVICE INCLUDING A MAGNETIC TUNNEL JUNCTION DEVICE INCLUDING A LAMINATED STRUCTURE AND MANUFACTURING METHOD THEREFOR - A semiconductor device having a MTJ device excellent in operating characteristics and a manufacturing method therefor are provided. The MTJ device is formed of a laminated structure which is obtained by laminating a lower magnetic film, a tunnel insulating film, and an upper magnetic film in this order. The lower and upper magnetic films contain noncrystalline or microcrystalline ferrocobalt boron (CoFeB) as a constituent material. The tunnel insulating film contains aluminum oxide (AlO11-29-2012
20100009467Novel magnetic tunnel junction (MTJ) to reduce spin transfer magnetization switching current - A MTJ that minimizes spin-transfer magnetization switching current (Jc) in a Spin-RAM to <1×1001-14-2010
20120156806MAGNETIC RANDOM ACCESS MEMORY INTEGRATION HAVING IMPROVED SCALING - A conductive via for connecting between a digit line and one side of the magnetic device is positioned beneath, and aligned with, each magnetic device. Other contacts may satisfy the same design rules, using the same process step. An electrode formed on the conductive via is polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to at least a 45 nanometer node, a cell packing factor approaching 6F06-21-2012
20110318848FERROMAGNETIC PREFERRED GRAIN GROWTH PROMOTION SEED LAYER FOR AMORPHOUS OR MICROCRYSTALLINE MgO TUNNEL BARRIER - MgO-based magnetic tunnel junction (MTJ) device includes in essence a ferromagnetic reference layer, a MgO tunnel barrier and a ferromagnetic free layer. The microstructure of MgO tunnel barrier, which is prepared by the metallic Mg deposition followed by the oxidation process or reactive sputtering, is amorphous or microcrystalline with poor (001) out-of-plane texture. In the present invention at least only the ferromagnetic reference layer or both of the ferromagnetic reference and free layer is proposed to be bi-layer structure having a crystalline preferred grain growth promotion (PGGP) seed layer adjacent to the tunnel barrier. This crystalline PGGP seed layer induces the crystallization and the preferred grain growth of the MgO tunnel barrier upon post-deposition annealing.12-29-2011
20120003757HIGH CAPACITY LOW COST MULTI-STATE MAGNETIC MEMORY - A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.01-05-2012
20120009689Method of Forming a MEMS Power Inductor - A scalable MEMS inductor is formed on the top surface of a semiconductor die. The MEMS inductor includes a plurality of magnetic lower laminations, a circular trace that lies over and spaced apart from the magnetic lower laminations, and a plurality of upper laminations that lie over and spaced apart from the circular trace.01-12-2012
20120115253Semiconductor apparatus - A method for manufacturing a semiconductor apparatus includes forming a semiconductor device on a principal surface of a substrate, in which the semiconductor device includes an interconnect layer, forming a buffer film which covers the semiconductor device and prevents diffusion of a magnetic material, and forming a magnetic shielding film which covers the buffer film and includes the magnetic material.05-10-2012
20120115252SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug and in the circumference thereof, a crystalline conductive film formed on the underlying conductive film, and a capacitor in which a lower electrode, a dielectric film made of a ferroelectric material, and an upper electrode are laminated in this order on the crystalline conductive film.05-10-2012
20110081733Thin film photovoltaic device - The present invention provides a thin film photovoltaic device and a method of forming a thin film photovoltaic device. The thin film photovoltaic device has a substrate, a thin film layer formed on the substrate and first and second electrodes formed on one side of the thin film layer. By applying an electric field over the first and second electrodes, the thin film layer is polarized in a direction parallel to the surface plane of the film. Upon exposure to light, the thin film layer converts light energy into electricity. According to the method, a thin film layer is formed on a substrate. A first electrode and a second electrode are formed on one side of the thin film layer. By applying an electric field over the first and second electrodes, the thin film layer is polarized in a direction parallel to the surface plane of the film.04-07-2011
20120058575Low switching current dual spin filter (DSF) element for STT-RAM and a method for making the same - A dual spin filter that minimizes spin-transfer magnetization switching current (Jc) while achieving a high dR/R in STT-RAM devices is disclosed. The bottom spin valve has a MgO tunnel barrier layer formed with a natural oxidation process to achieve low RA, a CoFe/Ru/CoFeB—CoFe pinned layer, and a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel (NCC) layer to minimize Jc03-08-2012
20120058574MRAM with storage layer and super-paramagnetic sensing layer - An MRAM is disclosed that has a MTJ comprised of a ferromagnetic layer with a magnetization direction along a first axis, a super-paramagnetic (SP) free layer, and an insulating layer formed therebetween. The SP free layer has a remnant magnetization that is substantially zero in the absence of an external field, and in which magnetization is roughly proportional to an external field until reaching a saturation value. In one embodiment, a separate storage layer is formed above, below, or adjacent to the MTJ and has uniaxial anisotropy with a magnetization direction along its easy axis which parallels the first axis. In a second embodiment, the storage layer is formed on a non-magnetic conducting spacer layer within the MTJ and is patterned simultaneously with the MTJ. The SP free layer may be multiple layers or laminated layers of CoFeB. The storage layer may have a SyAP configuration and a laminated structure.03-08-2012
20120064640Spin transfer MRAM device with novel magnetic synthetic free layer - A method of forming a CPP MTJ MRAM element that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The device includes a tunneling barrier layer of MgO and a non-magnetic CPP layer of Cu or Cr and utilizes a novel synthetic free layer having three ferromagnetic layers mutually exchange coupled in pairwise configurations. The free layer comprises an inner ferromagnetic and two outer ferromagnetic layers, with the inner layer being ferromagnetically exchange coupled to one outer layer and anti-ferromagnetically exchange coupled to the other outer layer. The ferromagnetic coupling is very strong across an ultra-thin layer of Ta, Hf or Zr of thickness preferably less than 0.4 nm.03-15-2012
20110008915METHOD FOR USE IN MAKING ELECTRONIC DEVICES HAVING THIN-FILM MAGNETIC COMPONENTS - Disclosed herein is a method of forming electronic device having thin-film components by using trenches. One or more of thin-film components is formed by depositing a thin-film in the trench followed by processing the deposited thin-film to have the desired thickness.01-13-2011
20110091998SEMICONDUCTOR DEVICE INCLUDING FERROELECTRIC CAPACITOR - A semiconductor device includes a ferroelectric capacitor formed above the lower interlevel insulating film covering a MOS transistor formed on a semiconductor substrate, including lamination of a lower electrode, an oxide ferroelectric film, a first upper electrode made of conductive oxide having a stoichiometric composition AO04-21-2011
20110104828METHOD FOR MAKING MICROSTRUCTURES BY CONVERTING POROUS SILICON INTO POROUS METAL OR CERAMICS - A method for making a micro structure (05-05-2011
20110104827Template-Registered DiBlock Copolymer Mask for MRAM Device Formation - A method for fabricating a magnetoresistive random access memory (MRAM) includes forming a mask over a magnetic layer; forming a template on the mask; applying a diblock copolymer to the template; curing the diblock copolymer to form a first plurality of uniform shapes registered to the template; etching the mask to form a second plurality of uniform shapes; and etching the magnetic layer to form a third plurality of uniform shapes, the third plurality of uniform shapes comprising a plurality of magnetic tunnel junctions (MTJs). A diblock copolymer mask for fabricating a magnetoresistive random access memory (MRAM) includes a magnetic layer; a mask formed on the magnetic layer; a template formed on the mask; and a diblock copolymer mask comprising a plurality of uniform shapes formed on and registered to the template.05-05-2011
20120122247ELECTRONIC DEVICE INCLUDING A MAGNETO-RESISTIVE MEMORY DEVICE AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE - A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer.05-17-2012
20120164757Method for Junction Isolation to Reduce Junction Damage for a TMR Sensor - The present invention provides a method for manufacturing a TMR sensor that reduces damage to a sensor stack during intermediate stages of the manufacturing process. In an embodiment of the invention, after formation of a sensor stack, a protective layer is deposited on the sensor stack that provides protection from materials that may be used in subsequent steps of the manufacturing process. The protective layer is subsequently converted to an insulating layer and the thickness of the insulating layer is extended to an appropriate thickness. In converting the protective layer to an insulating layer, the sensor stack is not directly exposed to materials that may damage it. For example, in an embodiment of the invention, Mg is used as the protective layer that is subsequently converted to MgO with the introduction of oxygen. Although direct contact of oxygen with the sensor stack may cause damage to the sensor stack, direct contact is avoided by the present invention. Subsequently, the thickness of the insulating layer, in this example can be extended to an appropriate thickness without exposing the sensor stack to damage causing oxygen and inter-diffusion.06-28-2012
20120231553SUBSTRATE PROCESSING APPARATUS AND FABRICATION PROCESS OF A SEMICONDUCTOR DEVICE - A substrate processing apparatus includes a processing vessel evacuated by an evacuation system and including therein a stage for holding thereon a substrate to be processed, the processing vessel defining therein a processing space, a processing gas supply path that introduces an etching gas into the processing vessel, a plasma source that forms plasma in the processing space, and a high-frequency source connected to the stage. The processing vessel includes therein a shielding plate dividing the processing space into a first processing space part including a surface of the substrate to be processed and a second processing space part corresponding to a remaining part of the processing space, wherein the shielding plate is formed with an opening having a size larger than a size of the substrate to be processed.09-13-2012
20120315707MAGNETIC PATTERNS AND METHODS OF FORMING MAGNETIC PATTERNS - In a method of forming a magnetic pattern, a lower electrode layer is formed on a substrate. An insulating interlayer is formed on the lower electrode layer. The insulating interlayer is partially removed to form an opening. A first pinned layer pattern filling the opening is formed. A second pinned layer, a tunnel barrier layer, a free layer and an upper electrode layer are formed on the insulating interlayer and the first pinned layer pattern. The upper electrode layer, the free layer, the tunnel barrier layer and the second pinned layer are patterned to form a second pinned layer pattern, a tunnel barrier pattern, a free layer pattern and an upper electrode. The second pinned layer pattern covers an upper surface of the first pinned layer pattern.12-13-2012
20120220056MECHANICAL COUPLING IN A MULTI-CHIP MODULE USING MAGNETIC COMPONENTS - A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features mate with each other. In particular, a positive feature may mate with a given pair of negative features, which includes negative features on each of the substrates. Furthermore, at least one of the negative features in the given pair may include a hard magnetic material, and the positive feature and the other negative feature in the given pair may include a soft magnetic material that provide a flux-return path to the hard magnetic material. In this way, the hard magnetic material may facilitate the remateable mechanical coupling of the substrates.08-30-2012
20120135544Method of Fabricating Semiconductor Device and Apparatus for Fabricating the Same - Provided is a method of fabricating a semiconductor device. The method of fabricating a semiconductor device includes forming a plurality of magnetic memory patterns spaced apart from each other on a substrate, with each of the magnetic memory patterns including a free pattern, a tunnel barrier pattern, and a reference pattern which are stacked on the substrate, performing a magnetic thermal treatment process on the magnetic memory patterns, and forming a passivation layer on the magnetic memory patterns. The magnetic thermal treatment process and the forming of the passivation layer are simultaneously performed in one reactor.05-31-2012
20120135543Method For Forming Magnetic Tunnel Junction Structure And Method For Forming Magnetic Random Access Memory Using The Same - A method of fabricating a magnetic tunnel junction structure includes forming a magnetic tunnel junction layer on a substrate. A mask pattern is formed on a region of the second magnetic layer. A magnetic tunnel junction layer pattern and a sidewall dielectric layer pattern on at least one sidewall of the magnetic tunnel junction layer pattern are formed by performing at least one etch process and at least one oxidation process multiple times. The at least one etch process may include a first etch process to etch a portion of the magnetic tunnel junction layer using an inert gas and the mask pattern to form a first etch product. The at least one oxidation process may include a first oxidation process to oxidize the first etch product attached on an etched side of the magnetic tunnel junction layer.05-31-2012
20120220057SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Ferroelectric capacitors (08-30-2012
20120171785MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE - There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.07-05-2012
20120171784MAGNETRON-SPUTTERING FILM-FORMING APPARATUS AND MANUFACTURING METHOD FOR A SEMICONDUCTOR DEVICE - A magnetron-sputtering film-forming apparatus includes: a vacuum film-forming chamber (07-05-2012
20120077288SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to the present invention, a method of fabricating a semiconductor device is provided including forming a first interlayer insulating film 03-29-2012
20120077287DRAWN DUMMY FeCAP, VIA AND METAL STRUCTURES - A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components.03-29-2012
20100047930MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - A magnetic random access memory includes a first wiring, a second wiring formed above and spaced apart from the first wiring, a magnetoresistive effect element formed between the first wiring and the second wiring, formed in contact with an upper surface of the first wiring, and having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer, a metal layer formed on the magnetoresistive effect element and integrated with the magnetoresistive effect element to form stacked layers, a first side insulating film formed on side surfaces of the metal layer, the magnetoresistive effect element, and the first wiring, a first contact formed in contact with a side surface of the first side insulating film, and a third wiring formed on the metal layer and the first contact to electrically connect the magnetoresistive effect element and the first contact.02-25-2010
20100047931SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - When adopting a stack-type capacitor structure for a ferroelectric capacitor structure (02-25-2010
20100047929Novel underlayer for high performance magnetic tunneling junction MRAM - An MRAM structure is disclosed in which the bottom electrode has an amorphous TaN capping layer to consistently provide smooth and dense growth for AFM, pinned, tunnel barrier, and free layers in an overlying MTJ. Unlike a conventional Ta capping layer, TaN is oxidation resistant and has high resistivity to avoid shunting of a sense current caused by redeposition of the capping layer on the sidewalls of the tunnel barrier layer. Alternatively, the α-TaN layer is the seed layer in the MTJ. Furthermore, the seed layer may be a composite layer comprised of a NiCr, NiFe, or NiFeCr layer on the α-TaN layer. An α-TaN capping layer or seed layer can also be used in a TMR read head. An MTJ formed on an α-TaN capping layer has a high MR ratio, high Vb, and a RA similar to results obtained from MTJs based on an optimized Ta capping layer.02-25-2010
20100009466SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An interlayer insulating film (01-14-2010
20090061538Methods of forming ferroelectric capacitors and methods of manufacturing semiconductor devices using the same - In a method of forming a ferroelectric capacitor, a lower electrode layer is formed on a substrate. A first crystalline layer is formed on the lower electrode layer. A ferroelectric layer is formed on the first crystalline layer. The first crystalline layer one of prevents a component of the ferroelectric layer from diffusing into the lower electrode layer and mitigates fatigue of the ferroelectric layer. An upper electrode layer is formed on the ferroelectric layer.03-05-2009
20090061537METHOD OF MANUFACTURING OSCILLATOR DEVICE - A method of manufacturing oscillator devices each having an oscillator and a resilient supporting member for supporting the oscillator for oscillatory motion, includes a step of processing one and the same substrate to form oscillators and resilient supporting members of oscillator devices so that oscillators of adjacent oscillator devices are connected to each other, a step of forming or placing a magnetic material so that it extends across the connected oscillators of the adjacent oscillator devices, and a step of simultaneously cutting and separating the connected oscillators and the magnetic material formed or placed to extend across the connected oscillators, whereby oscillator devices such as oscillatory type actuators having good reliability and performance evenness can be manufactured with a good productivity.03-05-2009
20120264234MAGNETIC RANDOM ACCESS MEMORY (MRAM) WITH ENHANCED MAGNETIC STIFFNESS AND METHOD OF MAKING SAME - A spin toque transfer magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B). Annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer. Cooling down of the STTMRAM element to a second temperature that is lower than the first temperature is performed and a third free sub-layer is directly deposited on top of the second free layer, with the third free sub-layer being made partially of boron (B), wherein the amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer.10-18-2012
20110124133SPIN-CURRENT SWITCHABLE MAGNETIC MEMORY ELEMENT AND METHOD OF FABRICATING THE MEMORY ELEMENT - A method of fabricating a magnetic memory element includes forming a plurality of magnetic layers having a perpendicular magnetic anisotropy component, in which the plurality of magnetic layers includes a first magnetic layer having an alloy of a rare-earth metal and a transition metal, and a second magnetic layer.05-26-2011
20080299680METHODS OF FORMING MAGNETIC MEMORY DEVICES - Methods for creating a memory device can include depositing a sense layer, patterning the sense layer to form a plurality of magnetic data cells, depositing a separation layer over the plurality of data cells, depositing a reference layer over the separation layer, and patterning the reference layer to form an elongated magnetic reference cell wherein the elongated magnetic reference cell extends uninterrupted along more than one of the plurality of magnetic data cells.12-04-2008
20120329177SPIN-TORQUE MAGNETORESISTIVE STRUCTURES WITH BILAYER FREE LAYER - Magnetoresistive structures, devices, memories, and methods for forming the same are presented. For example, a magnetoresistive structure includes a ferromagnetic layer, a ferrimagnetic layer coupled to the ferromagnetic layer, a pinned layer and a nonmagnetic spacer layer. A free side of the magnetoresistive structure comprises the ferromagnetic layer and the ferrimagnetic layer. The nonmagnetic spacer layer is at least partly between the free side and the pinned layer. A saturation magnetization of the ferromagnetic layer opposes a saturation magnetization of the ferrimagnetic layer. The nonmagnetic spacer layer may include a tunnel barrier layer, such as one composed of magnesium oxide (MgO), or a nonmagnetic metal layer.12-27-2012
20120288964SPIN-TORQUE BASED MEMORY DEVICE WITH READ AND WRITE CURRENT PATHS MODULATED WITH A NON-LINEAR SHUNT RESISTOR - A fabrication method includes forming a spin-polarizing layer, a spin transport layer on the spin polarizing layer on a substrate, a free layer magnet on the spin transport layer, a non-magnetic layer on the spin polarizing layer, a reference layer on the non-magnetic layer, and a hard mask layer on the reference layer, etching the hard mask layer and forming a read portion including the reference layer, the nonmagnetic layer and the free layer magnet, forming a nonlinear resistor layer on surfaces of the spin transport layer, the spacers, and the hard mask layer, etching the nonlinear resistor layer, the spin transport layer, and the spin polarizing layer and forming a write portion including the spin transport layer and the spin polarizing layer, forming an interlevel dielectric layer, forming a trench, exposing an upper surface of the reference layer of the read and write portions.11-15-2012
20120288963MANUFACTURING METHOD OF MAGNETO-RESISTIVE ELEMENT - The present invention provides a manufacturing method of a magneto-resistive element capable of obtaining a higher MR ratio, in a method of forming a metal oxide layer (e.g., MgO layer) by oxidation treatment of a metal layer (e.g., Mg layer). An embodiment of the present invention includes the steps of; providing a substrate having a first ferromagnetic layer; fabricating a tunnel barrier layer on the first ferromagnetic layer; and forming a second ferromagnetic layer on the tunnel barrier layer. The step of fabricating the tunnel barrier layer includes; the steps of; depositing a first metal layer on the first ferromagnetic layer;11-15-2012
20100167423Semiconductor package and methods of manufacturing the same - A semiconductor package includes a semiconductor chip having first and second pads, a first insulation layer pattern formed on the semiconductor chip and having first and second openings that expose the first and the second pads, respectively, a first conductive layer pattern elongated along the first insulation layer pattern from the first pad, a first external terminal formed on the first conductive layer pattern, a second insulation layer pattern formed on the first conductive layer pattern and the first insulation layer pattern to expose the first external terminal and having a third opening in communication with the second opening, a second conductive layer pattern elongated along the second insulation layer pattern from the second pad, and a second external terminal formed on the second conductive layer pattern.07-01-2010
20130017625SEMICONDUCTOR FABRICATING DEVICE AND METHOD FOR DRIVING THE SAME, AND METHOD FOR FABRICATING MAGNETIC TUNNEL JUNCTION USING THE SAMEAANM CHOI; Won JoonAACI SeoulAACO KRAAGP CHOI; Won Joon Seoul KR - In a method for fabricating a magnetic tunnel junction, a first magnetic layer is formed on a substrate, and a tunnel insulating layer is formed on the first magnetic layer. Subsequently, a second magnetic layer is formed on the tunnel insulating layer. In the method, the first magnetic layer is formed by periodically sputtering a magnetic target while a metal target is continuously sputtered.01-17-2013
20130017627Embedded Magnetic Random Access Memory (MRAM) - A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.01-17-2013
20130017626ETCHING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICEAANM TOMIOKA; KazuhiroAACI Yokohama-shiAACO JPAAGP TOMIOKA; Kazuhiro Yokohama-shi JP - According to one embodiment, an etching apparatus includes a stage having an upper surface and a lower surface, and being capable of mounting a substrate on the upper surface, a chamber covering above the upper surface, a lower electrode having an opening portion, and provided under the lower surface, a gas supplying portion supplying an etching gas in the chamber, a high-frequency power source portion executing a plasma gasification of the etching gas by applying a high-frequency to the lower electrode, a micro wave generating portion setting a temperature of the substrate within an optimum range by applying a micro wave to the substrate through the opening portion, and a control portion controlling the gas supplying portion, the high-frequency power source portion and the micro wave generating portion.01-17-2013
20110159609METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: forming first conductive layer on semiconductor substrate; forming a magnetic film on the first conductive layer; forming second conductive layer on the magnetic film; forming a first mask layer on the second conductive layer; patterning the second conductive layer; patterning the magnetic film; forming a first insulating film on the first conductive layer to cover side surfaces of the patterned second conductive layer and the patterned magnetic film; forming a second mask layer on the first insulating film to cover the patterned second conductive layer, the patterned magnetic film, and the first insulating film; patterning the first insulating film; patterning the first conductive layer; forming a second insulating film on the semiconductor substrate to cover the patterned second conductive layer, the patterned magnetic film, and the patterned first conductive layer; and forming a third insulating film on the second insulating film.06-30-2011
20130023063METHOD FOR MANUFACTURING FERROELECTRIC DEVICE - A seed layer having a predetermined pattern is formed on a side of one surface of a second substrate, and a ferroelectric layer is formed on the side of the one surface of the second substrate. A lower electrode is formed on the ferroelectric layer, and the lower electrode and a first substrate are bonded via a bonding layer. A laser beam with a predetermined wavelength is irradiated from a side of other surface of the second substrate to transfer a ferroelectric film, which overlaps with the seed layer, of the ferroelectric layer and the seed layer onto the side of said one surface of the first substrate. The laser beam passes through the second substrate, is reflected by the seed layer, and is absorbed by a second portion of the ferroelectric layer. The second portion does not overlap with the seed layer.01-24-2013
20130023062THIN FILM MANUFACTURING APPARATUS, THIN FILM MANUFACTURING METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In an apparatus for manufacturing a ceramic thin film by employing a thermal CVD method, an internal jig, which is provided with a heat radiation material film on the surface, is provided at a position that faces a substrate (S) on which the film is to be formed. The thin film and a semiconductor device are manufactured using such apparatus.01-24-2013
20130171741METHOD FOR FABRICATING VARIABLE RESISTANCE MEMORY DEVICE - A method for fabricating a variable resistance memory device in accordance with an embodiment of the present invention includes: sequentially forming a first conductive layer and a variable resistance layer on a substrate; forming stacked structures in which first conductive lines and variable resistance lines are sequentially stacked by selectively etching the variable resistance layer and the first conductive layer; forming an insulating layer to fill a space between the stacked structures; forming a second conductive layer on the insulating layer and the stacked structures; and forming a second conductive line and a variable resistance pattern by etching the second conductive layer and the variable resistance line using mask patterns in a line type extending in a direction intersecting the stacked structures.07-04-2013
20130171742METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a miniaturized semiconductor device so as to form MTJ elements therein include the steps of depositing a magnetic tunnel junction (MTJ) precursor layer on a substrate and planarizing the precursor layer; forming a sacrificial and patternable dielectric layer on the MTJ precursor layer; patterning the sacrificial dielectric layer in accordance with predetermined placements and shapes of a to-be-formed hard mask, the patterning forming corresponding openings in the sacrificial dielectric layer; depositing an etch-resistant conductive material such as Cu in the openings for example by way of plating, and selectively removing the sacrificial dielectric layer so as to leave behind the etch-resistant conductive material in the form of a desired hard mask. Using the hard mask to etch and thus pattern the MTJ precursor layer so as to form MTJ elements having desired locations, sizes and shapes.07-04-2013
20130171743MAGNETIC DEVICE AND METHOD OF MANUFACTURING THE SAME - A magnetic device and a method of manufacturing the same. In the method, a lower magnetic layer, an insulation layer, and an upper magnetic layer are sequentially formed on a substrate. An upper magnetic layer pattern is formed by patterning the upper magnetic layer until an upper surface of the insulation layer is exposed. An isolation layer pattern is formed from portions of the insulation layer and the lower magnetic layer by performing an oxidation process on the exposed upper surface of the insulation layer, and an insulation layer pattern and a lower magnetic layer pattern are formed from portions of the insulation layer and the lower magnetic layer, where the isolation layer pattern is not formed.07-04-2013
20080248595Method for Manufacturing Semiconductor Device and Computer Storage Medium - A method for fabricating a semiconductor device includes the steps of forming a PbTiOx film having a predominantly (111) orientation on a lower electrode as a nucleation layer by an MOCVD process with a film thickness exceeding 2 nm, and forming a PZT film having a predominantly (111) orientation on the nucleation layer, wherein the step of forming the PbTiOx film is conducted under an oxygen partial pressure of less than 340 Pa.10-09-2008
20080220542LOW-FIRE FERROELECTRIC MATERIAL - A low-fire ferroelectric composition, includes a lead bismuth titanate compound having a formula represented by: (Bi09-11-2008
20130143333SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a substrate and a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode. The upper electrode includes a first layer formed of an oxide whose stoichiometric composition is expressed as AOx06-06-2013
20080213924Ferroelectric memory device and method of manufacturing the same - A method of manufacturing a ferroelectric memory device includes: forming a hydrogen barrier film which covers a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode, wherein a thickness of an area of the hydrogen barrier film provided on the upper electrode is made greater than a thickness of an area of the hydrogen barrier film provided on a sidewall of the ferroelectric capacitor by forming the area of the hydrogen barrier film provided on the upper electrode in a plurality of layers.09-04-2008
20130177997SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - An upper electrode of a ferroelectric capacitor has a first layer formed of a first oxide expressed by a chemical formula AO07-11-2013
20130115719METHOD FOR MANUFACTURING INTEGRATED CIRCUIT STRUCTURE WITH MAGNETORESISTANCE COMPONENT - A method or manufacturing an integrated circuit structure with a magnetoresistance component is provided. A substrate is provided. A circuit structure layer including a metal pad is formed on the substrate. A dielectric layer is formed on the circuit structure. A metal damascene structure is formed in the dielectric layer. An opening is formed in the dielectric layer so as to form a step-drop. A magnetoresistance material layer is formed on the dielectric layer after forming the metal damascene structure and the opening A photolithography process is applied to pattern the magnetoresistance material layer to form a magnetoresistance component electrically connected to the metal damascene structure.05-09-2013
20080206895MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - A magnetic random access memory includes, a lower electrode, a magnetoresistive element which is arranged above the lower electrode and has side surfaces, and a protective film which covers the side surfaces of the magnetoresistive element, has a same planar shape as the lower electrode, and is formed by one of sputtering, plasma CVD, and ALD.08-28-2008
20110217793Methods of Processing a Substrate and Forming a Micromagnetic Device - A method of processing a substrate with a conductive film formed thereover and method of forming a micromagnetic device. In one embodiment, the method of processing the substrate includes reducing a temperature of the substrate to a stress-compensating temperature, and maintaining the temperature of the substrate at the stress-compensating temperature for a period of time. The method also includes increasing the temperature of the substrate above the stress-compensating temperature.09-08-2011
20080199976METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING FERROELECTRIC CAPACITOR - A semiconductor device manufacturing method has a step forming a transistor layer portion on a semiconductor substrate, and a step forming a ferroelectric capacitor portion including a lower electrode, a ferroelectric substance and an upper electrode above the transistor layer portion, wherein the step forming the ferroelectric capacitor portion includes adjusting an area of the upper electrode on the basis of manufacturing parameters of the ferroelectric capacitor portion.08-21-2008
20080199975METHODS OF FORMING A METAL OXIDE LAYER PATTERN HAVING A DECREASED LINE WIDTH OF A PORTION THEREOF AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - Provided herein are methods of forming a metal oxide layer pattern on a substrate including providing a preliminary metal oxide layer on a substrate; etching the preliminary metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increases in a vertically downward direction; and etching the preliminary metal oxide layer pattern to form a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer. The present invention also provides methods of manufacturing a semiconductor device including forming a metal oxide layer and a first conductive layer on a substrate; etching the metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increase in a vertically downward direction; etching the first conductive layer to provide a first conductive layer pattern; and etching the preliminary metal oxide layer pattern to provide a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer pattern.08-21-2008
20110229985Fabrication of Magnetic Tunnel Junction (MTJ) Devices with Reduced Surface Roughness for Magnetic Random Access Memory (MRAM) - Reliability and yield of MTJ devices is improved by reducing surface roughness in the MTJ layers of the MTJ devices. Surface roughness is reduced by reducing surface roughness of layers below the MTJ layers such as the bottom electrode layer. Planarizing the bottom electrode layer through chemical mechanical polishing or etch back of spin-on material before depositing the MTJ layers decreases surface roughness of the bottom electrode layer and the MTJ layers. Alternatively, a capping layer may be planarized before deposition of the bottom electrode layer and MTJ layers to reduce surface roughness in the capping layer, the bottom electrode layer, and the MTJ layers.09-22-2011
20130149797Magnetic Random Access Memory (MRAM) Manufacturing Process for a Small Magnetic Tunnel Junction (MTJ) Design with a Low Programming Current Requirement - A method of making a magnetic random access memory cell includes forming a magnetic tunnel junction (MTJ) on top of a wafer, depositing oxide on top of the MTJ, depositing a photo-resist layer on top of the oxide layer, forming a trench in the photo-resist layer and oxide layer where the trench has a width that is substantially the same as that of the MTJ. Then, the photo-resist layer is removed and a hard mask layer is deposited on top of the oxide layer in the trench and the wafer is planarized to remove the portion of the hard mask layer that is not in the trench to substantially level the top of oxide layer and the hard layer on the wafer. The remaining oxide layer is etched and the MTJ is etched to remove the portion of the MTJ which is not covered by the hard mask layer.06-13-2013
20110275163Zr-SUBSTITUTED BaTiO3 FILMS - The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition (ALD), to form a zirconium substituted layer of barium titanium oxide (BaTiO11-10-2011
20130149796SEMICONDUCTOR DEVICE WITH FERRO-ELECTRIC CAPACITOR - A semiconductor device has a ferro-electric capacitor with small leak current and less process deterioration even upon miniaturization. The semiconductor device includes: a semiconductor element formed in a semiconductor substrate; lamination of an interlayer insulating film and a lower insulating shielding film having a hydrogen/moisture shielding function, the lamination being formed covering the semiconductor element; a conductive adhesion enhancing film formed above the lower insulating shielding film; and a ferro-electric capacitor including a lower electrode formed above the conductive adhesion enhancing film, a ferro-electric film formed on the lower electrode and being disposed within the lower electrode as viewed in plan, and an upper electrode formed on the ferro-electric film and being disposed within the ferro-electric film as viewed in plan, wherein the conductive adhesion enhancing film has a function of improving adhesion of the lower electrode and reducing leak current of the ferro-electric capacitor.06-13-2013
20130157382PROFILE METHOD IN MAGNETIC WRITE HEAD FABRICATION - A method according to one embodiment includes depositing a dielectric hard mask layer above a polymer mask under-layer; forming a photoresist mask above the hard mask layer; transferring the image of the photoresist mask onto the hard mask layer using reactive ion etching, thereby defining a hard mask; determining that a critical dimension bias of the hard mask is within or outside a specification; and changing a level of an input source power used during a subsequent reactive ion etching step to move the critical dimension bias towards a target critical dimension bias when the critical dimension bias of the hard mask is outside the specification. Additional embodiments are also disclosed.06-20-2013
20130157383METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a metal layer on a substrate, forming a plurality of layers of a magnetic tunnel junction (MTJ) element on the metal layer, forming a carbon layer including a hole, wherein the hole penetrates through the carbon layer, forming a metal pattern in the hole of the carbon layer, removing the carbon layer; and patterning the plurality of layers of the MTJ element using the metal pattern as an etching mask.06-20-2013
20130157384METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a first insulation layer over a bottom layer, selectively removing a portion the first insulation layer to form a first trench that exposes the bottom layer, forming spacers on inner sidewalls of the first trench; forming a pillar-shaped second insulation layer in the first trench between the spacers, removing the spacers to form a second trench between the pillar-shaped second insulation layer and the first insulation layer, and burying a conductive layer in the second trench.06-20-2013
20130157385METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a bottom-electrode metal layer over a substrate, planarizing the bottom-electrode metal layer by a first thickness through a chemical mechanical polishing (CMP) process, etching the bottom-electrode metal layer by a second thickness through a wet etching process, forming a plurality of layers of a magnetic tunneling junction (MTJ) element over the bottom-electrode metal layer, forming a top electrode over the plurality of layers, and forming the MTJ element and a bottom electrode by etching the plurality of layers and the bottom-electrode metal layer using the top electrode as an etch mask.06-20-2013
20120282711MAGNETIC TUNNEL JUNCTION (MTJ) FORMATION USING MULTIPLE ETCHING PROCESSES - A method of manufacturing a magnetic memory element includes the steps of forming a permanent magnetic layer on top a bottom electrode, forming a pinning layer on top the permanent magnetic layer, forming a magnetic tunnel junction (MTJ) including a barrier layer on top of the pinning layer, forming a top electrode on top of the MTJ, forming a hard mask on top of the top electrode, and using the hard mask to perform a series of etching processes to reduce the width of the MTJ and the top electrode to substantially a desired width, where one of these etching processes is stopped when a predetermined material in the pinning layer is detected thereby avoiding deposition of metal onto the barrier layer of the etching process thereby preventing shorting.11-08-2012
20130189799METHOD OF FABRICATING DUAL TRENCH ISOLATED EPITAXIAL DIODE ARRAY - The present invention discloses a method of fabricating dual trench isolated epitaxial diode array. This method starts with the formation of heavily-doped first conductivity type regions and heavily-doped second conductivity type regions on the substrate, followed by epitaxial growth, then the formation of the isolations between diode array word lines by deep trench etch and the formation of the isolations between bit lines vertical to deep trenches by shallow trench etch, and finally the formation of separate diode array cells in the regions enclosed by deep and shallow trench isolations by ion implantation. This invention also provides a method of preventing the crosstalk current between adjacent word lines and bit lines of epitaxial diode arrays isolated by foregoing dual shallow trenches. This invention can be used for diode-driven, high-density, large-capacity memory, such as phase change random access memory, resistive memory, magnetic memory and ferroelectric memory; the method thereof is completely compatible with conventional complementary metal-oxide semiconductor (CMOS) process, and because the diode arrays can be formed before the formation of peripheral circuits, no drift of peripheral circuits will be caused by the thermal process thereof, thereby solving the technical challenge of fabricating high-density, large-capacity embedded phase change random access memory.07-25-2013
20120015452Information storage devices using magnetic domain wall movement and methods of manufacturing the same - In an information storage device, a writing magnetic layer is formed on a substrate and has a magnetic domain wall. A connecting magnetic layer is formed on the writing magnetic layer, and an information storing magnetic layer is formed on an upper portion of side surfaces of the connecting magnetic layer. A reader reads information stored in the information storing magnetic layer.01-19-2012
20120021535MAGNETIC STACK WITH OXIDE TO REDUCE SWITCHING CURRENT - A magnetic stack having a ferromagnetic free layer, a metal oxide layer that is antiferromagnetic at a first temperature and non-magnetic at a second temperature higher than the first temperature, a ferromagnetic pinned reference layer, and a non-magnetic spacer layer between the free layer and the reference layer. During a writing process, the metal oxide layer is non-magnetic. For magnetic memory cells, such as magnetic tunnel junction cells, the metal oxide layer provides reduced switching currents.01-26-2012
20120028374SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A ferroelectric capacitor provided with a ferroelectric film (02-02-2012
20120028373Bi-layer hard mask for the patterning and etching of nanometer size MRAM devices - A composite hard mask is disclosed that prevents build up of metal etch residue in a MRAM device during etch processes that define an MTJ shape. As a result, MTJ shape integrity is substantially improved. The hard mask has a lower non-magnetic spacer, a middle conductive layer, and an upper sacrificial dielectric layer. The non-magnetic spacer serves as an etch stop during a pattern transfer with fluorocarbon plasma through the conductive layer. A photoresist pattern is transferred through the dielectric layer with a first fluorocarbon etch. Then the photoresist is removed and a second fluorocarbon etch transfers the pattern through the conductive layer. The dielectric layer protects the top surface of the conductive layer during the second fluorocarbon etch and during a substantial portion of a third RIE step with a gas comprised of C, H, and O that transfers the pattern through the underlying MTJ layers.02-02-2012
20100015729METHODS OF FORMING A THIN FERROELECTRIC LAYER AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THE SAME - In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic acid polymer, abrasive particles, and water to form a thin ferroelectric layer on the substrate. The slurry composition may reduce a polishing rate of the preliminary ferroelectric layer such that removal of a bulk portion of the preliminary ferroelectric layer may be suppressed and the surface roughness of the preliminary ferroelectric layer may be improved.01-21-2010
20120295370MAGNETIC RANDOM ACCESS MEMORY (MRAM) WITH ENHANCED MAGNETIC STIFFNESS AND METHOD OF MAKING SAME - A STTMRAM element has a free sub-layer with enhanced internal stiffness. A first free sub-layer is made partially of boron (B), annealing is performed of the STTMRAM element at a first temperature to reduce the B content at an interface between the first free sub-layer and the barrier layer, the annealing causing a second free sub-layer to be formed on top of the first free sub-layer and being made partially of B, with an amount greater than the amount of B in the first free sub-layer. The STTMRAM element is cooled to a second temperature that is lower than the first temperature and a third free sub-layer is deposited directly on top of the second free layer, with the third free sub-layer being made partially of boron B. The amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer.11-22-2012
20130203187SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The semiconductor device of this invention includes a semiconductor substrate having a main surface, and a magnetoresistive element located over the main surface of the semiconductor substrate. Further, it includes a protective layer, a wiring, a first upper electrode, and a second upper electrode. The protective layer is disposed so as to cover the side surface of the magnetoresistive element. The wiring is located over the top of the magnetoresistive element. The first upper electrode substantially the same in dimensions in plan view as the magnetoresistive element is disposed over the magnetoresistive element. The second upper electrode is electrically coupled with the first upper electrode over the first upper electrode, and larger in dimensions in plan view than the first upper electrode.08-08-2013
20130203186HEAT TREATMENT APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a heat treatment apparatus including a treatment chamber housing a silicon substrate, a heater being provided in the treatment chamber and heating the silicon substrate, and an atmosphere adjustment mechanism reducing a concentration of oxygen contained in an atmosphere inside the treatment chamber to less than an oxygen concentration in the air. The atmosphere adjustment mechanism is provided with an oxygen trap, for example.08-08-2013
20100055806Piezoelectrically Actuated Ultrananocrystalline Diamond Tip Array Integrated With Ferroelectric Or Phase Change Media For High-Density Memory - A compact large density memory piezoactuated storage device and process for its fabrication provides an integrated microelectromechanical (MEMS) and/or nanoelectromechanical (NEMS) system and structure that features an integrated large density array of nanotips made of wear-resistant conductive ultrananocrystalline diamond (UNCD) in which the tips are actuated via a piezoelectric thin film integrated with the UNCD tips. The tips of the special piezoactuated storage device effectively contact an underlying metal layer (top electrode) deposited on a polarizable ferroelectric layer that is grown on top of another metal layer (bottom electrode) to form a ferroelectric capacitor. Information is imprinted in the ferroelectric layer by the polarization induced by the application of a voltage pulse between the top and bottom electrodes through the conductive UNCD tips. This integrated microelectromechanical (MEMS) and/or nanoelectromechanical (NEMS) system and structure can be efficiently used to imprint data in the ferroelectric layer for memory storage with high density in the gigabit (Gb) to terabit (Tb) range. An alternative memory media to the ferroelectric layer can be a phase change material that exhibits two orders of magnitude difference in electrical resistance between amorphous and crystalline phases.03-04-2010
20130095576TRANSFORMER SIGNAL COUPLING FOR FLIP-CHIP INTEGRATION - Methods for transformer signal coupling and impedance matching for flip-chip circuit assemblies are presented. In one embodiment, a method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer. In another embodiment, a method for matching impedance in an RF circuit fabricated using flip-chip techniques may include passing an RF input signal through a first inductor formed using a passive process, inducing a time varying magnetic flux in proximity to a second inductor formed using an active process, and passing an RF signal induced by the time varying magnetic flux through the second inductor.04-18-2013
20120094398SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - In a semiconductor device manufacturing method, an amorphous or microcrystalline metal oxide film is formed over a first metal film which is preferentially oriented along a predetermined crystal plane. After that, a ferroelectric film is formed by a MOCVD method. When the ferroelectric film is formed, the metal oxide film formed over the first metal film is reduced to a second metal film and the ferroelectric film is formed over the second metal film. When the ferroelectric film is formed, the amorphous or microcrystalline metal oxide film is apt to be reduced uniformly. As a result, the second metal film the orientation of which is good is obtained and the ferroelectric film the orientation of which is good is formed over the second metal film. After the ferroelectric film is formed, an upper electrode is formed over the ferroelectric film.04-19-2012

Patent applications in class HAVING MAGNETIC OR FERROELECTRIC COMPONENT