| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 377118000 | PULSE COUNTING OR DIVIDING CHAINS | 9 |
| 20110200163 | Counter Circuit - A system includes a memory and a counter circuit associated with the memory and configured to receive a clock signal and a plurality of input bits, and configured to output a plurality of output bits to the memory. The counter circuit includes a first counter configured to receive a part of the plurality of input bits and to output a part of the plurality of output bits and a first signal, a control circuit configured to receive the clock signal and the first signal, and to output a second signal, and a second counter configured to receive another part of the plurality of input bits and the second signal, and to output another part of the plurality of output bits. | 08-18-2011 |
| 20110013741 | COUNTING CIRCUIT AND ADDRESS COUNTER USING THE SAME - A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal and outputs a signal according to a clock signal. The fifth FF is coupled to the output terminal of the fourth FF and is configured to output the output signal of the fourth FF synchronously with the clock signal. The logic operation unit logically combines the output signals of the second to fourth FFs and outputs first and second counting signals. | 01-20-2011 |
| 20120250817 | vMOS Multi-valued Counter Unit - The present invention discloses a νMOS based multi-valued counter unit. The counter unit includes a νMOS source follower and at least a control gate connected the νMOS source follower. The control gate includes a first dual-value D flip-flop, a second dual-value D flip-flop, an AND gate, and an OR gate. The present invention utilizes the νMOS to replace the complicated threshold value operations of the multi-value logic. The current invention implements the true multi-value logic and a multi-base multi-value counter by increasing the number of the dual-value D flip-flop, and connecting the dual-value D flip-flop to the input control gate of the νMOS follower. Comparing to the conventional multi-value counter, the present invention reduces the necessary components in constructing the counter, and it also reduces the cost and power consumption. The present invention applies the asynchronous carry-over concept to implement the multi-digit multi-value counter, and it also has been verified by the simulation of P Simulation Program with Integrated Circuit Emphasis (SPICE). | 10-04-2012 |
| 20120008733 | COUNTING CIRCUIT AND ADDRESS COUNTER USING THE SAME - A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a | 01-12-2012 |
| 20080226015 | PULSE EXTENSION CIRCUITS FOR EXTENDING PULSE SIGNALS - A pulse extension circuit for extending a pulse signal includes an input unit for receiving the pulse signal, an edge detection unit coupled to the input unit for generating a initiation signal, a pulse initiation unit coupled to the edge detection unit for outputting a control signal and adjusting a voltage level of the control signal, a pulse width control unit coupled to the pulse initiation unit for outputting a termination signal, a reset unit coupled to the edge detection unit, the pulse initiation unit and the pulse width control unit for outputting the first reset signal and the second reset signal to reset the pulse initiation unit and the pulse width control unit, and an output unit coupled to the input unit and the pulse initiation unit for extending a signal period of the pulse signal according to the pulse signal and the control signal. | 09-18-2008 |
| 377119000 | Using bistable regenerative trigger circuits | 4 |
| 20090290678 | COUNTING CIRCUIT AND ADDRESS COUNTER USING THE SAME - A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal and outputs a signal according to a clock signal. The fifth FF is coupled to the output terminal of the fourth FF and is configured to output the output signal of the fourth FF synchronously with the clock signal. The logic operation unit logically combines the output signals of the second to fourth FFs and outputs first and second counting signals. | 11-26-2009 |
| 20100296622 | Counter circuit - A counter circuit adding a first value indicated by a plurality of bits and a second value in response to a clock signal, a first part of the plurality of bits being lower order than a second part of the plurality of bits, the counter circuit including a first counter configured to add the first part of the plurality of bits and the second value in response to the clock signal to output a third value regarding a result of adding the first and the second values, a second counter configured to add the second part of the plurality of bits and a fourth value in response to the clock signal, and a clock transmission control circuit coupled to the first and second counters to receive the clock signal and the third value, and to control whether or not to supply the clock signal to the second counter in accordance with the received third value. | 11-25-2010 |
| 377124000 | Ring counter | 2 |
| 20110299651 | Shift frequency demultiplier with automatic reset function - A shift frequency demultiplier with automatic reset function is N-frequency demultiplication (N>2) and includes N-1 registers connected with each other and defined from a first register to an (N-1)th register. Each of the registers has an input end, an output end, a reset end and a clock end. For the registers from the first register to the (N-2)th register, the output end of every register is connected with the input end of a next register adjacent thereto, the output end of the (N-1)th register is connected with the input end of the first register by a reverser. The reset end of the (N-1)th register is connected with a system reset signal end. The system reset signal end logically multiplied by the output end of the (N-1)th register is connected with the reset ends of the registers from the first register to the (N-2)th register. | 12-08-2011 |
| 20110044424 | Frequency Divider and Method for Frequency Division - A frequency divider comprises a cascade of at least two triggered delay elements (FF | 02-24-2011 |
